drivers/usb/dwc3/dwc3-rockchip.c

   1 /**
   2  * dwc3-rockchip.c - Rockchip Specific Glue layer
   3  *
   4  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   5  *
   6  * Authors: William Wu <william.wu@rock-chips.com>
   7  *
   8  * This program is free software: you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2  of
  10  * the License as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/mutex.h>
  20 #include <linux/kernel.h>
  21 #include <linux/slab.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/clk.h>
  25 #include <linux/clk-provider.h>
  26 #include <linux/debugfs.h>
  27 #include <linux/of.h>
  28 #include <linux/of_platform.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/extcon.h>
  31 #include <linux/freezer.h>
  32 #include <linux/iopoll.h>
  33 #include <linux/reset.h>
  34 #include <linux/uaccess.h>
  35 #include <linux/usb.h>
  36 #include <linux/usb/hcd.h>
  37 #include <linux/usb/ch9.h>
  38
  39 #include "core.h"
  40 #include "io.h"
  41 #include "../host/xhci.h"
  42
  43 #define DWC3_ROCKCHIP_AUTOSUSPEND_DELAY 500 /* ms */
  44 #define PERIPHERAL_DISCONNECT_TIMEOUT   1000000 /* us */
  45 #define WAIT_FOR_HCD_READY_TIMEOUT      5000000 /* us */
  46 #define XHCI_TSTCTRL_MASK               (0xf << 28)
  47
  48 struct dwc3_rockchip {
  49         int                     num_clocks;
  50         bool                    connected;
  51         bool                    skip_suspend;
  52         bool                    suspended;
  53         struct device           *dev;
  54         struct clk              **clks;
  55         struct dwc3             *dwc;
  56         struct dentry           *root;
  57         struct reset_control    *otg_rst;
  58         struct extcon_dev       *edev;
  59         struct notifier_block   device_nb;
  60         struct notifier_block   host_nb;
  61         struct work_struct      otg_work;
  62         struct mutex            lock;
  63 };
  64
  65 static int dwc3_rockchip_force_mode_show(struct seq_file *s, void *unused)
  66 {
  67         struct dwc3_rockchip    *rockchip = s->private;
  68         struct dwc3             *dwc = rockchip->dwc;
  69
  70         switch (dwc->dr_mode) {
  71         case USB_DR_MODE_HOST:
  72                 seq_puts(s, "host\n");
  73                 break;
  74         case USB_DR_MODE_PERIPHERAL:
  75                 seq_puts(s, "peripheral\n");
  76                 break;
  77         case USB_DR_MODE_OTG:
  78                 seq_puts(s, "otg\n");
  79                 break;
  80         default:
  81                 seq_puts(s, "UNKNOWN\n");
  82         }
  83
  84         return 0;
  85 }
  86
  87 static int dwc3_rockchip_force_mode_open(struct inode *inode, struct file *file)
  88 {
  89         return single_open(file, dwc3_rockchip_force_mode_show,
  90                            inode->i_private);
  91 }
  92
  93 static ssize_t dwc3_rockchip_force_mode_write(struct file *file,
  94                                               const char __user *ubuf,
  95                                               size_t count, loff_t *ppos)
  96 {
  97         struct seq_file         *s = file->private_data;
  98         struct dwc3_rockchip    *rockchip = s->private;
  99         struct dwc3             *dwc = rockchip->dwc;
 100         enum usb_dr_mode        new_dr_mode;
 101         char                    buf[32];
 102
 103         if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
 104                 return -EFAULT;
 105
 106         if (!strncmp(buf, "0", 1) || !strncmp(buf, "otg", 3)) {
 107                 new_dr_mode = USB_DR_MODE_OTG;
 108         } else if (!strncmp(buf, "1", 1) || !strncmp(buf, "host", 4)) {
 109                 new_dr_mode = USB_DR_MODE_HOST;
 110         } else if (!strncmp(buf, "2", 1) || !strncmp(buf, "peripheral", 10)) {
 111                 new_dr_mode = USB_DR_MODE_PERIPHERAL;
 112         } else {
 113                 dev_info(rockchip->dev, "illegal dr_mode\n");
 114                 return count;
 115         }
 116
 117         if (dwc->dr_mode == new_dr_mode) {
 118                 dev_info(rockchip->dev, "Same with current dr_mode\n");
 119                 return count;
 120         }
 121
 122         /*
 123          * Disconnect vbus to trigger gadget disconnect process by setting
 124          * the mode of phy to invalid if the current dr_mode of controller
 125          * is peripheral, than schedule otg work to change connect status
 126          * and suspend the controller.
 127          */
 128         if (dwc->dr_mode == USB_DR_MODE_PERIPHERAL)
 129                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_INVALID);
 130         dwc->dr_mode = USB_DR_MODE_OTG;
 131         schedule_work(&rockchip->otg_work);
 132         flush_work(&rockchip->otg_work);
 133
 134         /*
 135          * Schedule otg work to change connect status and resume the
 136          * controller, than connect vbus to trigger connect interrupt
 137          * and connect gadget by setting the mode of phy to device if
 138          * the dr_mode is peripheral.
 139          */
 140         dwc->dr_mode = new_dr_mode;
 141         schedule_work(&rockchip->otg_work);
 142         flush_work(&rockchip->otg_work);
 143         if (dwc->dr_mode == USB_DR_MODE_PERIPHERAL)
 144                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
 145
 146         return count;
 147 }
 148
 149 static const struct file_operations dwc3_rockchip_force_mode_fops = {
 150         .open                   = dwc3_rockchip_force_mode_open,
 151         .write                  = dwc3_rockchip_force_mode_write,
 152         .read                   = seq_read,
 153         .llseek                 = seq_lseek,
 154         .release                = single_release,
 155 };
 156
 157 static int dwc3_rockchip_host_testmode_show(struct seq_file *s, void *unused)
 158 {
 159         struct dwc3_rockchip    *rockchip = s->private;
 160         struct dwc3             *dwc = rockchip->dwc;
 161         struct usb_hcd          *hcd  = dev_get_drvdata(&dwc->xhci->dev);
 162         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 163         __le32 __iomem          **port_array;
 164         u32                     reg;
 165
 166         if (rockchip->dwc->dr_mode == USB_DR_MODE_PERIPHERAL) {
 167                 dev_warn(rockchip->dev, "USB HOST not support!\n");
 168                 return 0;
 169         }
 170
 171         if (hcd->state == HC_STATE_HALT) {
 172                 dev_warn(rockchip->dev, "HOST is halted, set test mode first!\n");
 173                 return 0;
 174         }
 175
 176         port_array = xhci->usb2_ports;
 177         reg = readl(port_array[0] + PORTPMSC);
 178         reg &= XHCI_TSTCTRL_MASK;
 179         reg >>= 28;
 180
 181         switch (reg) {
 182         case 0:
 183                 seq_puts(s, "U2: no test\n");
 184                 break;
 185         case TEST_J:
 186                 seq_puts(s, "U2: test_j\n");
 187                 break;
 188         case TEST_K:
 189                 seq_puts(s, "U2: test_k\n");
 190                 break;
 191         case TEST_SE0_NAK:
 192                 seq_puts(s, "U2: test_se0_nak\n");
 193                 break;
 194         case TEST_PACKET:
 195                 seq_puts(s, "U2: test_packet\n");
 196                 break;
 197         case TEST_FORCE_EN:
 198                 seq_puts(s, "U2: test_force_enable\n");
 199                 break;
 200         default:
 201                 seq_printf(s, "U2: UNKNOWN %d\n", reg);
 202         }
 203
 204         port_array = xhci->usb3_ports;
 205         reg = readl(port_array[0]);
 206         reg &= PORT_PLS_MASK;
 207         if (reg == USB_SS_PORT_LS_COMP_MOD)
 208                 seq_puts(s, "U3: compliance mode\n");
 209         else
 210                 seq_printf(s, "U3: UNKNOWN %d\n", reg >> 5);
 211
 212         return 0;
 213 }
 214
 215 static int dwc3_rockchip_host_testmode_open(struct inode *inode,
 216                                             struct file *file)
 217 {
 218         return single_open(file, dwc3_rockchip_host_testmode_show,
 219                            inode->i_private);
 220 }
 221
 222 /**
 223  * dwc3_rockchip_set_test_mode - Enables USB2/USB3 HOST Test Modes
 224  * @rockchip: pointer to our context structure
 225  * @mode: the mode to set (U2: J, K SE0 NAK, Test_packet,
 226  * Force Enable; U3: Compliance mode)
 227  *
 228  * This function will return 0 on success or -EINVAL if wrong Test
 229  * Selector is passed.
 230  */
 231 static int dwc3_rockchip_set_test_mode(struct dwc3_rockchip *rockchip,
 232                                        u32 mode)
 233 {
 234         struct dwc3     *dwc = rockchip->dwc;
 235         struct usb_hcd  *hcd  = dev_get_drvdata(&dwc->xhci->dev);
 236         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 237         __le32 __iomem  **port_array;
 238         int             ret, val;
 239         u32             reg;
 240
 241         ret = readx_poll_timeout(readl, &hcd->state, val,
 242                                  val != HC_STATE_HALT, 1000,
 243                                  WAIT_FOR_HCD_READY_TIMEOUT);
 244         if (ret < 0) {
 245                 dev_err(rockchip->dev, "Wait for HCD ready timeout\n");
 246                 return -EINVAL;
 247         }
 248
 249         switch (mode) {
 250         case TEST_J:
 251         case TEST_K:
 252         case TEST_SE0_NAK:
 253         case TEST_PACKET:
 254         case TEST_FORCE_EN:
 255                 port_array = xhci->usb2_ports;
 256                 reg = readl(port_array[0] + PORTPMSC);
 257                 reg &= ~XHCI_TSTCTRL_MASK;
 258                 reg |= mode << 28;
 259                 writel(reg, port_array[0] + PORTPMSC);
 260                 break;
 261         case USB_SS_PORT_LS_COMP_MOD:
 262                 port_array = xhci->usb3_ports;
 263                 xhci_set_link_state(xhci, port_array, 0, mode);
 264                 break;
 265         default:
 266                 return -EINVAL;
 267         }
 268
 269         dev_info(rockchip->dev, "set USB HOST test mode successfully!\n");
 270
 271         return 0;
 272 }
 273
 274 static ssize_t dwc3_rockchip_host_testmode_write(struct file *file,
 275                                                  const char __user *ubuf,
 276                                                  size_t count, loff_t *ppos)
 277 {
 278         struct seq_file                 *s = file->private_data;
 279         struct dwc3_rockchip            *rockchip = s->private;
 280         struct extcon_dev               *edev = rockchip->edev;
 281         u32                             testmode = 0;
 282         bool                            flip = 0;
 283         char                            buf[32];
 284         union extcon_property_value     property;
 285
 286         if (rockchip->dwc->dr_mode == USB_DR_MODE_PERIPHERAL) {
 287                 dev_warn(rockchip->dev, "USB HOST not support!\n");
 288                 return -EINVAL;
 289         }
 290
 291         if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
 292                 return -EFAULT;
 293
 294         if (!strncmp(buf, "test_j", 6)) {
 295                 testmode = TEST_J;
 296         } else if (!strncmp(buf, "test_k", 6)) {
 297                 testmode = TEST_K;
 298         } else if (!strncmp(buf, "test_se0_nak", 12)) {
 299                 testmode = TEST_SE0_NAK;
 300         } else if (!strncmp(buf, "test_packet", 11)) {
 301                 testmode = TEST_PACKET;
 302         } else if (!strncmp(buf, "test_force_enable", 17)) {
 303                 testmode = TEST_FORCE_EN;
 304         } else if (!strncmp(buf, "test_u3", 7)) {
 305                 testmode = USB_SS_PORT_LS_COMP_MOD;
 306         } else if (!strncmp(buf, "test_flip_u3", 12)) {
 307                 testmode = USB_SS_PORT_LS_COMP_MOD;
 308                 flip = 1;
 309         } else {
 310                 dev_warn(rockchip->dev, "Test cmd not support!\n");
 311                 return -EINVAL;
 312         }
 313
 314         if (edev && !extcon_get_cable_state_(edev, EXTCON_USB_HOST)) {
 315                 if (extcon_get_cable_state_(edev, EXTCON_USB) > 0)
 316                         extcon_set_cable_state_(edev, EXTCON_USB, false);
 317
 318                 property.intval = flip;
 319                 extcon_set_property(edev, EXTCON_USB_HOST,
 320                                     EXTCON_PROP_USB_TYPEC_POLARITY, property);
 321                 extcon_set_cable_state_(edev, EXTCON_USB_HOST, true);
 322
 323                 /* Add a delay 1~1.5s to wait for XHCI HCD init */
 324                 usleep_range(1000000, 1500000);
 325         }
 326
 327         dwc3_rockchip_set_test_mode(rockchip, testmode);
 328
 329         return count;
 330 }
 331
 332 static const struct file_operations dwc3_host_testmode_fops = {
 333         .open                   = dwc3_rockchip_host_testmode_open,
 334         .write                  = dwc3_rockchip_host_testmode_write,
 335         .read                   = seq_read,
 336         .llseek                 = seq_lseek,
 337         .release                = single_release,
 338 };
 339
 340 static void dwc3_rockchip_debugfs_init(struct dwc3_rockchip *rockchip)
 341 {
 342         struct dentry   *root;
 343         struct dentry   *file;
 344
 345         root = debugfs_create_dir(dev_name(rockchip->dev), NULL);
 346         if (IS_ERR_OR_NULL(root)) {
 347                 if (!root)
 348                         dev_err(rockchip->dev, "Can't create debugfs root\n");
 349                 return;
 350         }
 351         rockchip->root = root;
 352
 353         if (IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) ||
 354             IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
 355                 file = debugfs_create_file("host_testmode", S_IRUSR | S_IWUSR,
 356                                            root, rockchip,
 357                                            &dwc3_host_testmode_fops);
 358                 if (!file)
 359                         dev_dbg(rockchip->dev, "Can't create debugfs host_testmode\n");
 360         }
 361
 362         if (IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) &&
 363             !rockchip->edev && (rockchip->dwc->dr_mode == USB_DR_MODE_OTG)) {
 364                 file = debugfs_create_file("rk_usb_force_mode",
 365                                            S_IRUSR | S_IWUSR,
 366                                            root, rockchip,
 367                                            &dwc3_rockchip_force_mode_fops);
 368                 if (!file)
 369                         dev_dbg(rockchip->dev,
 370                                 "Can't create debugfs rk_usb_force_mode\n");
 371         }
 372 }
 373
 374 static int dwc3_rockchip_device_notifier(struct notifier_block *nb,
 375                                          unsigned long event, void *ptr)
 376 {
 377         struct dwc3_rockchip *rockchip =
 378                 container_of(nb, struct dwc3_rockchip, device_nb);
 379
 380         if (!rockchip->suspended)
 381                 schedule_work(&rockchip->otg_work);
 382
 383         return NOTIFY_DONE;
 384 }
 385
 386 static int dwc3_rockchip_host_notifier(struct notifier_block *nb,
 387                                        unsigned long event, void *ptr)
 388 {
 389         struct dwc3_rockchip *rockchip =
 390                 container_of(nb, struct dwc3_rockchip, host_nb);
 391
 392         if (!rockchip->suspended)
 393                 schedule_work(&rockchip->otg_work);
 394
 395         return NOTIFY_DONE;
 396 }
 397
 398 static void dwc3_rockchip_otg_extcon_evt_work(struct work_struct *work)
 399 {
 400         struct dwc3_rockchip    *rockchip =
 401                 container_of(work, struct dwc3_rockchip, otg_work);
 402         struct dwc3             *dwc = rockchip->dwc;
 403         struct extcon_dev       *edev = rockchip->edev;
 404         struct usb_hcd          *hcd;
 405         struct xhci_hcd         *xhci;
 406         unsigned long           flags;
 407         int                     ret;
 408         int                     val;
 409         u32                     reg, count;
 410
 411         mutex_lock(&rockchip->lock);
 412
 413         if (rockchip->edev ? extcon_get_cable_state_(edev, EXTCON_USB) :
 414             (dwc->dr_mode == USB_DR_MODE_PERIPHERAL)) {
 415                 if (rockchip->connected)
 416                         goto out;
 417
 418                 /*
 419                  * If dr_mode is host only, never to set
 420                  * the mode to the peripheral mode.
 421                  */
 422                 if (dwc->dr_mode == USB_DR_MODE_HOST) {
 423                         dev_warn(rockchip->dev, "USB peripheral not support!\n");
 424                         goto out;
 425                 }
 426
 427                 /*
 428                  * Assert otg reset can put the dwc in P2 state, it's
 429                  * necessary operation prior to phy power on. However,
 430                  * asserting the otg reset may affect dwc chip operation.
 431                  * The reset will clear all of the dwc controller registers.
 432                  * So we need to reinit the dwc controller after deassert
 433                  * the reset. We use pm runtime to initialize dwc controller.
 434                  * Also, there are no synchronization primitives, meaning
 435                  * the dwc3 core code could at least in theory access chip
 436                  * registers while the reset is asserted, with unknown impact.
 437                  */
 438                 if (!rockchip->skip_suspend) {
 439                         reset_control_assert(rockchip->otg_rst);
 440                         usleep_range(1000, 1200);
 441                         reset_control_deassert(rockchip->otg_rst);
 442
 443                         pm_runtime_get_sync(rockchip->dev);
 444                         pm_runtime_get_sync(dwc->dev);
 445                 } else {
 446                         rockchip->skip_suspend = false;
 447                 }
 448
 449                 spin_lock_irqsave(&dwc->lock, flags);
 450                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 451                 spin_unlock_irqrestore(&dwc->lock, flags);
 452
 453                 rockchip->connected = true;
 454                 dev_info(rockchip->dev, "USB peripheral connected\n");
 455         } else if (rockchip->edev ?
 456                    extcon_get_cable_state_(edev, EXTCON_USB_HOST) :
 457                    (dwc->dr_mode == USB_DR_MODE_HOST)) {
 458                 if (rockchip->connected)
 459                         goto out;
 460
 461                 if (rockchip->skip_suspend) {
 462                         pm_runtime_put(dwc->dev);
 463                         pm_runtime_put(rockchip->dev);
 464                         rockchip->skip_suspend = false;
 465                 }
 466
 467                 /*
 468                  * If dr_mode is device only, never to
 469                  * set the mode to the host mode.
 470                  */
 471                 if (dwc->dr_mode == USB_DR_MODE_PERIPHERAL) {
 472                         dev_warn(rockchip->dev, "USB HOST not support!\n");
 473                         goto out;
 474                 }
 475
 476                 /*
 477                  * Assert otg reset can put the dwc in P2 state, it's
 478                  * necessary operation prior to phy power on. However,
 479                  * asserting the otg reset may affect dwc chip operation.
 480                  * The reset will clear all of the dwc controller registers.
 481                  * So we need to reinit the dwc controller after deassert
 482                  * the reset. We use pm runtime to initialize dwc controller.
 483                  * Also, there are no synchronization primitives, meaning
 484                  * the dwc3 core code could at least in theory access chip
 485                  * registers while the reset is asserted, with unknown impact.
 486                  */
 487                 reset_control_assert(rockchip->otg_rst);
 488                 usleep_range(1000, 1200);
 489                 reset_control_deassert(rockchip->otg_rst);
 490
 491                 /*
 492                  * In usb3 phy init, it will access usb3 module, so we need
 493                  * to resume rockchip dev before phy init to make sure usb3
 494                  * pd is enabled.
 495                  */
 496                 pm_runtime_get_sync(rockchip->dev);
 497
 498                 /*
 499                  * Don't abort on errors. If powering on a phy fails,
 500                  * we still need to init dwc controller and add the
 501                  * HCDs to avoid a crash when unloading the driver.
 502                  */
 503                 ret = phy_power_on(dwc->usb2_generic_phy);
 504                 if (ret < 0)
 505                         dev_err(dwc->dev, "Failed to power on usb2 phy\n");
 506
 507                 ret = phy_power_on(dwc->usb3_generic_phy);
 508                 if (ret < 0) {
 509                         phy_power_off(dwc->usb2_generic_phy);
 510                         dev_err(dwc->dev, "Failed to power on usb3 phy\n");
 511                 }
 512
 513                 pm_runtime_get_sync(dwc->dev);
 514
 515                 spin_lock_irqsave(&dwc->lock, flags);
 516                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 517                 spin_unlock_irqrestore(&dwc->lock, flags);
 518
 519                 /*
 520                  * The following sleep helps to ensure that inserted USB3
 521                  * Ethernet devices are discovered if already inserted
 522                  * when booting.
 523                  */
 524                 usleep_range(10000, 11000);
 525
 526                 hcd = dev_get_drvdata(&dwc->xhci->dev);
 527
 528                 if (hcd->state == HC_STATE_HALT) {
 529                         usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 530                         usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
 531                 }
 532
 533                 rockchip->connected = true;
 534                 dev_info(rockchip->dev, "USB HOST connected\n");
 535         } else {
 536                 if (!rockchip->connected)
 537                         goto out;
 538
 539                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 540
 541                 /*
 542                  * xhci does not support runtime pm. If HCDs are not removed
 543                  * here and and re-added after a cable is inserted, USB3
 544                  * connections will not work.
 545                  * A clean(er) solution would be to implement runtime pm
 546                  * support in xhci. After that is available, this code should
 547                  * be removed.
 548                  * HCDs have to be removed here to prevent attempts by the
 549                  * xhci code to access xhci registers after the call to
 550                  * pm_runtime_put_sync_suspend(). On rk3399, this can result
 551                  * in a crash under certain circumstances (this was observed
 552                  * on 3399 chromebook if the system is running on battery).
 553                  */
 554                 if (DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_HOST ||
 555                     DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_OTG) {
 556                         hcd = dev_get_drvdata(&dwc->xhci->dev);
 557                         xhci = hcd_to_xhci(hcd);
 558
 559                         if (hcd->state != HC_STATE_HALT) {
 560                                 xhci->xhc_state |= XHCI_STATE_REMOVING;
 561                                 count = 0;
 562
 563                                 /*
 564                                  * Wait until XHCI controller resume from
 565                                  * PM suspend, them we can remove hcd safely.
 566                                  */
 567                                 while (dwc->xhci->dev.power.is_suspended) {
 568                                         if (++count > 100) {
 569                                                 dev_err(rockchip->dev,
 570                                                         "wait for XHCI resume 10s timeout!\n");
 571                                                 goto out;
 572                                         }
 573                                         msleep(100);
 574                                 }
 575
 576 #ifdef CONFIG_FREEZER
 577                                 /*
 578                                  * usb_remove_hcd() may call usb_disconnect() to
 579                                  * remove a block device pluged in before.
 580                                  * Unfortunately, the block layer suspend/resume
 581                                  * path is fundamentally broken due to freezable
 582                                  * kthreads and workqueue and may deadlock if a
 583                                  * block device gets removed while resume is in
 584                                  * progress.
 585                                  *
 586                                  * We need to add a ugly hack to avoid removing
 587                                  * hcd and kicking off device removal while
 588                                  * freezer is active. This is a joke but does
 589                                  * avoid this particular deadlock when test with
 590                                  * USB-C HUB and USB2/3 flash drive.
 591                                  */
 592                                 while (pm_freezing)
 593                                         usleep_range(10000, 11000);
 594 #endif
 595
 596                                 usb_remove_hcd(hcd->shared_hcd);
 597                                 usb_remove_hcd(hcd);
 598                         }
 599
 600                         phy_power_off(dwc->usb2_generic_phy);
 601                         phy_power_off(dwc->usb3_generic_phy);
 602                 }
 603
 604                 if (DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_DEVICE) {
 605                         ret = readx_poll_timeout(atomic_read,
 606                                                  &dwc->dev->power.usage_count,
 607                                                  val,
 608                                                  val < 2 && !dwc->connected,
 609                                                  1000,
 610                                                  PERIPHERAL_DISCONNECT_TIMEOUT);
 611                         if (ret < 0) {
 612                                 rockchip->skip_suspend = true;
 613                                 dev_warn(rockchip->dev, "Peripheral disconnect timeout\n");
 614                         }
 615                 }
 616
 617                 if (!rockchip->skip_suspend) {
 618                         pm_runtime_put_sync_suspend(dwc->dev);
 619                         pm_runtime_put_sync_suspend(rockchip->dev);
 620                 }
 621
 622                 rockchip->connected = false;
 623                 dev_info(rockchip->dev, "USB unconnected\n");
 624         }
 625
 626 out:
 627         mutex_unlock(&rockchip->lock);
 628 }
 629
 630 static int dwc3_rockchip_extcon_register(struct dwc3_rockchip *rockchip)
 631 {
 632         int                     ret;
 633         struct device           *dev = rockchip->dev;
 634         struct extcon_dev       *edev;
 635
 636         if (device_property_read_bool(dev, "extcon")) {
 637                 edev = extcon_get_edev_by_phandle(dev, 0);
 638                 if (IS_ERR(edev)) {
 639                         if (PTR_ERR(edev) != -EPROBE_DEFER)
 640                                 dev_err(dev, "couldn't get extcon device\n");
 641                         return PTR_ERR(edev);
 642                 }
 643
 644                 rockchip->device_nb.notifier_call =
 645                                 dwc3_rockchip_device_notifier;
 646                 ret = extcon_register_notifier(edev, EXTCON_USB,
 647                                                &rockchip->device_nb);
 648                 if (ret < 0) {
 649                         dev_err(dev, "failed to register notifier for USB\n");
 650                         return ret;
 651                 }
 652
 653                 rockchip->host_nb.notifier_call =
 654                                 dwc3_rockchip_host_notifier;
 655                 ret = extcon_register_notifier(edev, EXTCON_USB_HOST,
 656                                                &rockchip->host_nb);
 657                 if (ret < 0) {
 658                         dev_err(dev, "failed to register notifier for USB HOST\n");
 659                         extcon_unregister_notifier(edev, EXTCON_USB,
 660                                                    &rockchip->device_nb);
 661                         return ret;
 662                 }
 663
 664                 rockchip->edev = edev;
 665         }
 666
 667         return 0;
 668 }
 669
 670 static void dwc3_rockchip_extcon_unregister(struct dwc3_rockchip *rockchip)
 671 {
 672         if (!rockchip->edev)
 673                 return;
 674
 675         extcon_unregister_notifier(rockchip->edev, EXTCON_USB,
 676                                    &rockchip->device_nb);
 677         extcon_unregister_notifier(rockchip->edev, EXTCON_USB_HOST,
 678                                    &rockchip->host_nb);
 679
 680         cancel_work_sync(&rockchip->otg_work);
 681 }
 682
 683 static int dwc3_rockchip_probe(struct platform_device *pdev)
 684 {
 685         struct dwc3_rockchip    *rockchip;
 686         struct device           *dev = &pdev->dev;
 687         struct device_node      *np = dev->of_node, *child;
 688         struct platform_device  *child_pdev;
 689         struct usb_hcd          *hcd = NULL;
 690
 691         unsigned int            count;
 692         int                     ret;
 693         int                     i;
 694
 695         rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
 696
 697         if (!rockchip)
 698                 return -ENOMEM;
 699
 700         count = of_clk_get_parent_count(np);
 701         if (!count)
 702                 return -ENOENT;
 703
 704         rockchip->num_clocks = count;
 705
 706         rockchip->clks = devm_kcalloc(dev, rockchip->num_clocks,
 707                                       sizeof(struct clk *), GFP_KERNEL);
 708         if (!rockchip->clks)
 709                 return -ENOMEM;
 710
 711         platform_set_drvdata(pdev, rockchip);
 712
 713         mutex_init(&rockchip->lock);
 714
 715         rockchip->dev = dev;
 716
 717         mutex_lock(&rockchip->lock);
 718
 719         for (i = 0; i < rockchip->num_clocks; i++) {
 720                 struct clk      *clk;
 721
 722                 clk = of_clk_get(np, i);
 723                 if (IS_ERR(clk)) {
 724                         ret = PTR_ERR(clk);
 725                         goto err0;
 726                 }
 727
 728                 ret = clk_prepare_enable(clk);
 729                 if (ret < 0) {
 730                         clk_put(clk);
 731                         goto err0;
 732                 }
 733
 734                 rockchip->clks[i] = clk;
 735         }
 736
 737         pm_runtime_set_active(dev);
 738         pm_runtime_enable(dev);
 739         ret = pm_runtime_get_sync(dev);
 740         if (ret < 0) {
 741                 dev_err(dev, "get_sync failed with err %d\n", ret);
 742                 goto err1;
 743         }
 744
 745         rockchip->otg_rst = devm_reset_control_get(dev, "usb3-otg");
 746         if (IS_ERR(rockchip->otg_rst)) {
 747                 dev_err(dev, "could not get reset controller\n");
 748                 ret = PTR_ERR(rockchip->otg_rst);
 749                 goto err1;
 750         }
 751
 752         child = of_get_child_by_name(np, "dwc3");
 753         if (!child) {
 754                 dev_err(dev, "failed to find dwc3 core node\n");
 755                 ret = -ENODEV;
 756                 goto err1;
 757         }
 758
 759         /* Allocate and initialize the core */
 760         ret = of_platform_populate(np, NULL, NULL, dev);
 761         if (ret) {
 762                 dev_err(dev, "failed to create dwc3 core\n");
 763                 goto err1;
 764         }
 765
 766         INIT_WORK(&rockchip->otg_work, dwc3_rockchip_otg_extcon_evt_work);
 767
 768         child_pdev = of_find_device_by_node(child);
 769         if (!child_pdev) {
 770                 dev_err(dev, "failed to find dwc3 core device\n");
 771                 ret = -ENODEV;
 772                 goto err2;
 773         }
 774
 775         rockchip->dwc = platform_get_drvdata(child_pdev);
 776         if (!rockchip->dwc) {
 777                 dev_err(dev, "failed to get drvdata dwc3\n");
 778                 ret = -EPROBE_DEFER;
 779                 goto err2;
 780         }
 781
 782         if (rockchip->dwc->dr_mode == USB_DR_MODE_HOST ||
 783             rockchip->dwc->dr_mode == USB_DR_MODE_OTG) {
 784                 hcd = dev_get_drvdata(&rockchip->dwc->xhci->dev);
 785                 if (!hcd) {
 786                         dev_err(dev, "fail to get drvdata hcd\n");
 787                         ret = -EPROBE_DEFER;
 788                         goto err2;
 789                 }
 790         }
 791
 792         ret = dwc3_rockchip_extcon_register(rockchip);
 793         if (ret < 0)
 794                 goto err2;
 795
 796         if (rockchip->edev || (rockchip->dwc->dr_mode == USB_DR_MODE_OTG)) {
 797                 if (hcd && hcd->state != HC_STATE_HALT) {
 798                         usb_remove_hcd(hcd->shared_hcd);
 799                         usb_remove_hcd(hcd);
 800                 }
 801
 802                 pm_runtime_set_autosuspend_delay(&child_pdev->dev,
 803                                                  DWC3_ROCKCHIP_AUTOSUSPEND_DELAY);
 804                 pm_runtime_allow(&child_pdev->dev);
 805                 pm_runtime_suspend(&child_pdev->dev);
 806                 pm_runtime_put_sync(dev);
 807
 808                 if ((extcon_get_cable_state_(rockchip->edev,
 809                                              EXTCON_USB) > 0) ||
 810                     (extcon_get_cable_state_(rockchip->edev,
 811                                              EXTCON_USB_HOST) > 0))
 812                         schedule_work(&rockchip->otg_work);
 813         }
 814
 815         dwc3_rockchip_debugfs_init(rockchip);
 816
 817         mutex_unlock(&rockchip->lock);
 818
 819         return ret;
 820
 821 err2:
 822         of_platform_depopulate(dev);
 823
 824 err1:
 825         pm_runtime_put_sync(dev);
 826         pm_runtime_disable(dev);
 827
 828 err0:
 829         for (i = 0; i < rockchip->num_clocks && rockchip->clks[i]; i++) {
 830                 if (!pm_runtime_status_suspended(dev))
 831                         clk_disable(rockchip->clks[i]);
 832                 clk_unprepare(rockchip->clks[i]);
 833                 clk_put(rockchip->clks[i]);
 834         }
 835
 836         mutex_unlock(&rockchip->lock);
 837
 838         return ret;
 839 }
 840
 841 static int dwc3_rockchip_remove(struct platform_device *pdev)
 842 {
 843         struct dwc3_rockchip    *rockchip = platform_get_drvdata(pdev);
 844         struct device           *dev = &pdev->dev;
 845         int                     i;
 846
 847         dwc3_rockchip_extcon_unregister(rockchip);
 848
 849         debugfs_remove_recursive(rockchip->root);
 850
 851         /* Restore hcd state before unregistering xhci */
 852         if (rockchip->edev && !rockchip->connected) {
 853                 struct usb_hcd *hcd =
 854                         dev_get_drvdata(&rockchip->dwc->xhci->dev);
 855
 856                 pm_runtime_get_sync(dev);
 857
 858                 /*
 859                  * The xhci code does not expect that HCDs have been removed.
 860                  * It will unconditionally call usb_remove_hcd() when the xhci
 861                  * driver is unloaded in of_platform_depopulate(). This results
 862                  * in a crash if the HCDs were already removed. To avoid this
 863                  * crash, add the HCDs here as dummy operation.
 864                  * This code should be removed after pm runtime support
 865                  * has been added to xhci.
 866                  */
 867                 if (hcd->state == HC_STATE_HALT) {
 868                         usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 869                         usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
 870                 }
 871         }
 872
 873         of_platform_depopulate(dev);
 874
 875         pm_runtime_put_sync(dev);
 876         pm_runtime_disable(dev);
 877
 878         for (i = 0; i < rockchip->num_clocks; i++) {
 879                 if (!pm_runtime_status_suspended(dev))
 880                         clk_disable(rockchip->clks[i]);
 881                 clk_unprepare(rockchip->clks[i]);
 882                 clk_put(rockchip->clks[i]);
 883         }
 884
 885         return 0;
 886 }
 887
 888 #ifdef CONFIG_PM
 889 static int dwc3_rockchip_runtime_suspend(struct device *dev)
 890 {
 891         struct dwc3_rockchip    *rockchip = dev_get_drvdata(dev);
 892         int                     i;
 893
 894         for (i = 0; i < rockchip->num_clocks; i++)
 895                 clk_disable(rockchip->clks[i]);
 896
 897         device_init_wakeup(dev, false);
 898
 899         return 0;
 900 }
 901
 902 static int dwc3_rockchip_runtime_resume(struct device *dev)
 903 {
 904         struct dwc3_rockchip    *rockchip = dev_get_drvdata(dev);
 905         int                     i;
 906
 907         for (i = 0; i < rockchip->num_clocks; i++)
 908                 clk_enable(rockchip->clks[i]);
 909
 910         device_init_wakeup(dev, true);
 911
 912         return 0;
 913 }
 914
 915 static int dwc3_rockchip_suspend(struct device *dev)
 916 {
 917         struct dwc3_rockchip *rockchip = dev_get_drvdata(dev);
 918         struct dwc3 *dwc = rockchip->dwc;
 919
 920         rockchip->suspended = true;
 921         cancel_work_sync(&rockchip->otg_work);
 922
 923         if (rockchip->edev && dwc->dr_mode != USB_DR_MODE_PERIPHERAL) {
 924                 /*
 925                  * If USB HOST connected, we will do phy power
 926                  * on in extcon evt work, so need to do phy
 927                  * power off in suspend. And we just power off
 928                  * USB2 PHY here because USB3 PHY power on operation
 929                  * need to be done while DWC3 controller is in P2
 930                  * state, but after resume DWC3 controller is in
 931                  * P0 state. So we put USB3 PHY in power on state.
 932                  */
 933                 if (extcon_get_cable_state_(rockchip->edev,
 934                                             EXTCON_USB_HOST) > 0)
 935                         phy_power_off(dwc->usb2_generic_phy);
 936         }
 937
 938         return 0;
 939 }
 940
 941 static int dwc3_rockchip_resume(struct device *dev)
 942 {
 943         struct dwc3_rockchip *rockchip = dev_get_drvdata(dev);
 944         struct dwc3 *dwc = rockchip->dwc;
 945
 946         rockchip->suspended = false;
 947
 948         if (rockchip->edev)
 949                 schedule_work(&rockchip->otg_work);
 950
 951         if (rockchip->edev && dwc->dr_mode != USB_DR_MODE_PERIPHERAL) {
 952                 if (extcon_get_cable_state_(rockchip->edev,
 953                                             EXTCON_USB_HOST) > 0)
 954                         phy_power_on(dwc->usb2_generic_phy);
 955         }
 956
 957         return 0;
 958 }
 959
 960 static const struct dev_pm_ops dwc3_rockchip_dev_pm_ops = {
 961         SET_SYSTEM_SLEEP_PM_OPS(dwc3_rockchip_suspend, dwc3_rockchip_resume)
 962         SET_RUNTIME_PM_OPS(dwc3_rockchip_runtime_suspend,
 963                            dwc3_rockchip_runtime_resume, NULL)
 964 };
 965
 966 #define DEV_PM_OPS      (&dwc3_rockchip_dev_pm_ops)
 967 #else
 968 #define DEV_PM_OPS      NULL
 969 #endif /* CONFIG_PM */
 970
 971 static const struct of_device_id rockchip_dwc3_match[] = {
 972         { .compatible = "rockchip,rk3399-dwc3" },
 973         { /* Sentinel */ }
 974 };
 975
 976 MODULE_DEVICE_TABLE(of, rockchip_dwc3_match);
 977
 978 static struct platform_driver dwc3_rockchip_driver = {
 979         .probe          = dwc3_rockchip_probe,
 980         .remove         = dwc3_rockchip_remove,
 981         .driver         = {
 982                 .name   = "rockchip-dwc3",
 983                 .of_match_table = rockchip_dwc3_match,
 984                 .pm     = DEV_PM_OPS,
 985         },
 986 };
 987
 988 module_platform_driver(dwc3_rockchip_driver);
 989
 990 MODULE_ALIAS("platform:rockchip-dwc3");
 991 MODULE_AUTHOR("William Wu <william.wu@rock-chips.com>");
 992 MODULE_LICENSE("GPL v2");
 993 MODULE_DESCRIPTION("DesignWare USB3 ROCKCHIP Glue Layer");