drivers/usb/dwc3/dwc3-rockchip.c

   1 /**
   2  * dwc3-rockchip.c - Rockchip Specific Glue layer
   3  *
   4  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   5  *
   6  * Authors: William Wu <william.wu@rock-chips.com>
   7  *
   8  * This program is free software: you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2  of
  10  * the License as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/mutex.h>
  20 #include <linux/kernel.h>
  21 #include <linux/slab.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/clk.h>
  25 #include <linux/clk-provider.h>
  26 #include <linux/of.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/extcon.h>
  30 #include <linux/reset.h>
  31 #include <linux/usb.h>
  32 #include <linux/usb/hcd.h>
  33
  34 #include "core.h"
  35 #include "io.h"
  36
  37 #define DWC3_ROCKCHIP_AUTOSUSPEND_DELAY  500 /* ms */
  38
  39 struct dwc3_rockchip {
  40         int                     num_clocks;
  41         bool                    connected;
  42         bool                    suspended;
  43         struct device           *dev;
  44         struct clk              **clks;
  45         struct dwc3             *dwc;
  46         struct reset_control    *otg_rst;
  47         struct extcon_dev       *edev;
  48         struct notifier_block   device_nb;
  49         struct notifier_block   host_nb;
  50         struct work_struct      otg_work;
  51         struct mutex            lock;
  52 };
  53
  54 static int dwc3_rockchip_device_notifier(struct notifier_block *nb,
  55                                          unsigned long event, void *ptr)
  56 {
  57         struct dwc3_rockchip *rockchip =
  58                 container_of(nb, struct dwc3_rockchip, device_nb);
  59
  60         if (!rockchip->suspended)
  61                 schedule_work(&rockchip->otg_work);
  62
  63         return NOTIFY_DONE;
  64 }
  65
  66 static int dwc3_rockchip_host_notifier(struct notifier_block *nb,
  67                                        unsigned long event, void *ptr)
  68 {
  69         struct dwc3_rockchip *rockchip =
  70                 container_of(nb, struct dwc3_rockchip, host_nb);
  71
  72         if (!rockchip->suspended)
  73                 schedule_work(&rockchip->otg_work);
  74
  75         return NOTIFY_DONE;
  76 }
  77
  78 static void dwc3_rockchip_otg_extcon_evt_work(struct work_struct *work)
  79 {
  80         struct dwc3_rockchip    *rockchip =
  81                 container_of(work, struct dwc3_rockchip, otg_work);
  82         struct dwc3             *dwc = rockchip->dwc;
  83         struct extcon_dev       *edev = rockchip->edev;
  84         struct usb_hcd          *hcd;
  85         unsigned long           flags;
  86         int                     ret;
  87         u32                     reg;
  88
  89         mutex_lock(&rockchip->lock);
  90
  91         if (extcon_get_cable_state_(edev, EXTCON_USB) > 0) {
  92                 if (rockchip->connected)
  93                         goto out;
  94
  95                 /*
  96                  * If dr_mode is host only, never to set
  97                  * the mode to the peripheral mode.
  98                  */
  99                 if (dwc->dr_mode == USB_DR_MODE_HOST) {
 100                         dev_warn(rockchip->dev, "USB peripheral not support!\n");
 101                         goto out;
 102                 }
 103
 104                 /*
 105                  * Assert otg reset can put the dwc in P2 state, it's
 106                  * necessary operation prior to phy power on. However,
 107                  * asserting the otg reset may affect dwc chip operation.
 108                  * The reset will clear all of the dwc controller registers.
 109                  * So we need to reinit the dwc controller after deassert
 110                  * the reset. We use pm runtime to initialize dwc controller.
 111                  * Also, there are no synchronization primitives, meaning
 112                  * the dwc3 core code could at least in theory access chip
 113                  * registers while the reset is asserted, with unknown impact.
 114                  */
 115                 reset_control_assert(rockchip->otg_rst);
 116                 usleep_range(1000, 1200);
 117                 reset_control_deassert(rockchip->otg_rst);
 118
 119                 pm_runtime_get_sync(rockchip->dev);
 120                 pm_runtime_get_sync(dwc->dev);
 121
 122                 spin_lock_irqsave(&dwc->lock, flags);
 123                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 124                 spin_unlock_irqrestore(&dwc->lock, flags);
 125
 126                 rockchip->connected = true;
 127                 dev_info(rockchip->dev, "USB peripheral connected\n");
 128         } else if (extcon_get_cable_state_(edev, EXTCON_USB_HOST) > 0) {
 129                 if (rockchip->connected)
 130                         goto out;
 131
 132                 /*
 133                  * If dr_mode is device only, never to
 134                  * set the mode to the host mode.
 135                  */
 136                 if (dwc->dr_mode == USB_DR_MODE_PERIPHERAL) {
 137                         dev_warn(rockchip->dev, "USB HOST not support!\n");
 138                         goto out;
 139                 }
 140
 141                 /*
 142                  * Assert otg reset can put the dwc in P2 state, it's
 143                  * necessary operation prior to phy power on. However,
 144                  * asserting the otg reset may affect dwc chip operation.
 145                  * The reset will clear all of the dwc controller registers.
 146                  * So we need to reinit the dwc controller after deassert
 147                  * the reset. We use pm runtime to initialize dwc controller.
 148                  * Also, there are no synchronization primitives, meaning
 149                  * the dwc3 core code could at least in theory access chip
 150                  * registers while the reset is asserted, with unknown impact.
 151                  */
 152                 reset_control_assert(rockchip->otg_rst);
 153                 usleep_range(1000, 1200);
 154                 reset_control_deassert(rockchip->otg_rst);
 155
 156                 /*
 157                  * In usb3 phy init, it will access usb3 module, so we need
 158                  * to resume rockchip dev before phy init to make sure usb3
 159                  * pd is enabled.
 160                  */
 161                 pm_runtime_get_sync(rockchip->dev);
 162
 163                 /*
 164                  * Don't abort on errors. If powering on a phy fails,
 165                  * we still need to init dwc controller and add the
 166                  * HCDs to avoid a crash when unloading the driver.
 167                  */
 168                 ret = phy_power_on(dwc->usb2_generic_phy);
 169                 if (ret < 0)
 170                         dev_err(dwc->dev, "Failed to power on usb2 phy\n");
 171
 172                 ret = phy_power_on(dwc->usb3_generic_phy);
 173                 if (ret < 0) {
 174                         phy_power_off(dwc->usb2_generic_phy);
 175                         dev_err(dwc->dev, "Failed to power on usb3 phy\n");
 176                 }
 177
 178                 pm_runtime_get_sync(dwc->dev);
 179
 180                 spin_lock_irqsave(&dwc->lock, flags);
 181                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 182                 spin_unlock_irqrestore(&dwc->lock, flags);
 183
 184                 /*
 185                  * The following sleep helps to ensure that inserted USB3
 186                  * Ethernet devices are discovered if already inserted
 187                  * when booting.
 188                  */
 189                 usleep_range(10000, 11000);
 190
 191                 hcd = dev_get_drvdata(&dwc->xhci->dev);
 192
 193                 if (hcd->state == HC_STATE_HALT) {
 194                         usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 195                         usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
 196                 }
 197
 198                 rockchip->connected = true;
 199                 dev_info(rockchip->dev, "USB HOST connected\n");
 200         } else {
 201                 if (!rockchip->connected)
 202                         goto out;
 203
 204                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 205
 206                 /*
 207                  * xhci does not support runtime pm. If HCDs are not removed
 208                  * here and and re-added after a cable is inserted, USB3
 209                  * connections will not work.
 210                  * A clean(er) solution would be to implement runtime pm
 211                  * support in xhci. After that is available, this code should
 212                  * be removed.
 213                  * HCDs have to be removed here to prevent attempts by the
 214                  * xhci code to access xhci registers after the call to
 215                  * pm_runtime_put_sync_suspend(). On rk3399, this can result
 216                  * in a crash under certain circumstances (this was observed
 217                  * on 3399 chromebook if the system is running on battery).
 218                  */
 219                 if (DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_HOST ||
 220                     DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_OTG) {
 221                         hcd = dev_get_drvdata(&dwc->xhci->dev);
 222
 223                         if (hcd->state != HC_STATE_HALT) {
 224                                 usb_remove_hcd(hcd->shared_hcd);
 225                                 usb_remove_hcd(hcd);
 226                         }
 227
 228                         phy_power_off(dwc->usb2_generic_phy);
 229                         phy_power_off(dwc->usb3_generic_phy);
 230                 }
 231
 232                 pm_runtime_put_sync(rockchip->dev);
 233                 pm_runtime_put_sync_suspend(dwc->dev);
 234
 235                 rockchip->connected = false;
 236                 dev_info(rockchip->dev, "USB unconnected\n");
 237         }
 238
 239 out:
 240         mutex_unlock(&rockchip->lock);
 241 }
 242
 243 static int dwc3_rockchip_extcon_register(struct dwc3_rockchip *rockchip)
 244 {
 245         int                     ret;
 246         struct device           *dev = rockchip->dev;
 247         struct extcon_dev       *edev;
 248
 249         if (device_property_read_bool(dev, "extcon")) {
 250                 edev = extcon_get_edev_by_phandle(dev, 0);
 251                 if (IS_ERR(edev)) {
 252                         if (PTR_ERR(edev) != -EPROBE_DEFER)
 253                                 dev_err(dev, "couldn't get extcon device\n");
 254                         return PTR_ERR(edev);
 255                 }
 256
 257                 INIT_WORK(&rockchip->otg_work,
 258                           dwc3_rockchip_otg_extcon_evt_work);
 259
 260                 rockchip->device_nb.notifier_call =
 261                                 dwc3_rockchip_device_notifier;
 262                 ret = extcon_register_notifier(edev, EXTCON_USB,
 263                                                &rockchip->device_nb);
 264                 if (ret < 0) {
 265                         dev_err(dev, "failed to register notifier for USB\n");
 266                         return ret;
 267                 }
 268
 269                 rockchip->host_nb.notifier_call =
 270                                 dwc3_rockchip_host_notifier;
 271                 ret = extcon_register_notifier(edev, EXTCON_USB_HOST,
 272                                                &rockchip->host_nb);
 273                 if (ret < 0) {
 274                         dev_err(dev, "failed to register notifier for USB HOST\n");
 275                         extcon_unregister_notifier(edev, EXTCON_USB,
 276                                                    &rockchip->device_nb);
 277                         return ret;
 278                 }
 279
 280                 rockchip->edev = edev;
 281         }
 282
 283         return 0;
 284 }
 285
 286 static void dwc3_rockchip_extcon_unregister(struct dwc3_rockchip *rockchip)
 287 {
 288         if (!rockchip->edev)
 289                 return;
 290
 291         extcon_unregister_notifier(rockchip->edev, EXTCON_USB,
 292                                    &rockchip->device_nb);
 293         extcon_unregister_notifier(rockchip->edev, EXTCON_USB_HOST,
 294                                    &rockchip->host_nb);
 295         cancel_work_sync(&rockchip->otg_work);
 296 }
 297
 298 static int dwc3_rockchip_probe(struct platform_device *pdev)
 299 {
 300         struct dwc3_rockchip    *rockchip;
 301         struct device           *dev = &pdev->dev;
 302         struct device_node      *np = dev->of_node, *child;
 303         struct platform_device  *child_pdev;
 304
 305         unsigned int            count;
 306         int                     ret;
 307         int                     i;
 308
 309         rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
 310
 311         if (!rockchip)
 312                 return -ENOMEM;
 313
 314         count = of_clk_get_parent_count(np);
 315         if (!count)
 316                 return -ENOENT;
 317
 318         rockchip->num_clocks = count;
 319
 320         rockchip->clks = devm_kcalloc(dev, rockchip->num_clocks,
 321                                       sizeof(struct clk *), GFP_KERNEL);
 322         if (!rockchip->clks)
 323                 return -ENOMEM;
 324
 325         platform_set_drvdata(pdev, rockchip);
 326
 327         mutex_init(&rockchip->lock);
 328
 329         rockchip->dev = dev;
 330
 331         mutex_lock(&rockchip->lock);
 332
 333         for (i = 0; i < rockchip->num_clocks; i++) {
 334                 struct clk      *clk;
 335
 336                 clk = of_clk_get(np, i);
 337                 if (IS_ERR(clk)) {
 338                         ret = PTR_ERR(clk);
 339                         goto err0;
 340                 }
 341
 342                 ret = clk_prepare_enable(clk);
 343                 if (ret < 0) {
 344                         clk_put(clk);
 345                         goto err0;
 346                 }
 347
 348                 rockchip->clks[i] = clk;
 349         }
 350
 351         pm_runtime_set_active(dev);
 352         pm_runtime_enable(dev);
 353         ret = pm_runtime_get_sync(dev);
 354         if (ret < 0) {
 355                 dev_err(dev, "get_sync failed with err %d\n", ret);
 356                 goto err1;
 357         }
 358
 359         rockchip->otg_rst = devm_reset_control_get(dev, "usb3-otg");
 360         if (IS_ERR(rockchip->otg_rst)) {
 361                 dev_err(dev, "could not get reset controller\n");
 362                 ret = PTR_ERR(rockchip->otg_rst);
 363                 goto err1;
 364         }
 365
 366         child = of_get_child_by_name(np, "dwc3");
 367         if (!child) {
 368                 dev_err(dev, "failed to find dwc3 core node\n");
 369                 ret = -ENODEV;
 370                 goto err1;
 371         }
 372
 373         /* Allocate and initialize the core */
 374         ret = of_platform_populate(np, NULL, NULL, dev);
 375         if (ret) {
 376                 dev_err(dev, "failed to create dwc3 core\n");
 377                 goto err1;
 378         }
 379
 380         child_pdev = of_find_device_by_node(child);
 381         if (!child_pdev) {
 382                 dev_err(dev, "failed to find dwc3 core device\n");
 383                 ret = -ENODEV;
 384                 goto err2;
 385         }
 386
 387         rockchip->dwc = platform_get_drvdata(child_pdev);
 388         if (!rockchip->dwc) {
 389                 dev_err(dev, "failed to get drvdata dwc3\n");
 390                 ret = -EPROBE_DEFER;
 391                 goto err2;
 392         }
 393
 394         ret = dwc3_rockchip_extcon_register(rockchip);
 395         if (ret < 0)
 396                 goto err2;
 397
 398         if (rockchip->edev) {
 399                 if (rockchip->dwc->dr_mode == USB_DR_MODE_HOST ||
 400                     rockchip->dwc->dr_mode == USB_DR_MODE_OTG) {
 401                         struct usb_hcd *hcd =
 402                                 dev_get_drvdata(&rockchip->dwc->xhci->dev);
 403                         if (!hcd) {
 404                                 dev_err(dev, "fail to get drvdata hcd\n");
 405                                 ret = -EPROBE_DEFER;
 406                                 goto err3;
 407                         }
 408                         if (hcd->state != HC_STATE_HALT) {
 409                                 usb_remove_hcd(hcd->shared_hcd);
 410                                 usb_remove_hcd(hcd);
 411                         }
 412                 }
 413
 414                 pm_runtime_set_autosuspend_delay(&child_pdev->dev,
 415                                                  DWC3_ROCKCHIP_AUTOSUSPEND_DELAY);
 416                 pm_runtime_allow(&child_pdev->dev);
 417                 pm_runtime_suspend(&child_pdev->dev);
 418                 pm_runtime_put_sync(dev);
 419
 420                 if ((extcon_get_cable_state_(rockchip->edev,
 421                                              EXTCON_USB) > 0) ||
 422                     (extcon_get_cable_state_(rockchip->edev,
 423                                              EXTCON_USB_HOST) > 0))
 424                         schedule_work(&rockchip->otg_work);
 425         }
 426
 427         mutex_unlock(&rockchip->lock);
 428
 429         return ret;
 430
 431 err3:
 432         dwc3_rockchip_extcon_unregister(rockchip);
 433
 434 err2:
 435         of_platform_depopulate(dev);
 436
 437 err1:
 438         pm_runtime_put_sync(dev);
 439         pm_runtime_disable(dev);
 440
 441 err0:
 442         for (i = 0; i < rockchip->num_clocks && rockchip->clks[i]; i++) {
 443                 if (!pm_runtime_status_suspended(dev))
 444                         clk_disable(rockchip->clks[i]);
 445                 clk_unprepare(rockchip->clks[i]);
 446                 clk_put(rockchip->clks[i]);
 447         }
 448
 449         mutex_unlock(&rockchip->lock);
 450
 451         return ret;
 452 }
 453
 454 static int dwc3_rockchip_remove(struct platform_device *pdev)
 455 {
 456         struct dwc3_rockchip    *rockchip = platform_get_drvdata(pdev);
 457         struct device           *dev = &pdev->dev;
 458         int                     i;
 459
 460         dwc3_rockchip_extcon_unregister(rockchip);
 461
 462         /* Restore hcd state before unregistering xhci */
 463         if (rockchip->edev && !rockchip->connected) {
 464                 struct usb_hcd *hcd =
 465                         dev_get_drvdata(&rockchip->dwc->xhci->dev);
 466
 467                 pm_runtime_get_sync(dev);
 468
 469                 /*
 470                  * The xhci code does not expect that HCDs have been removed.
 471                  * It will unconditionally call usb_remove_hcd() when the xhci
 472                  * driver is unloaded in of_platform_depopulate(). This results
 473                  * in a crash if the HCDs were already removed. To avoid this
 474                  * crash, add the HCDs here as dummy operation.
 475                  * This code should be removed after pm runtime support
 476                  * has been added to xhci.
 477                  */
 478                 if (hcd->state == HC_STATE_HALT) {
 479                         usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 480                         usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
 481                 }
 482         }
 483
 484         of_platform_depopulate(dev);
 485
 486         pm_runtime_put_sync(dev);
 487         pm_runtime_disable(dev);
 488
 489         for (i = 0; i < rockchip->num_clocks; i++) {
 490                 if (!pm_runtime_status_suspended(dev))
 491                         clk_disable(rockchip->clks[i]);
 492                 clk_unprepare(rockchip->clks[i]);
 493                 clk_put(rockchip->clks[i]);
 494         }
 495
 496         return 0;
 497 }
 498
 499 #ifdef CONFIG_PM
 500 static int dwc3_rockchip_runtime_suspend(struct device *dev)
 501 {
 502         struct dwc3_rockchip    *rockchip = dev_get_drvdata(dev);
 503         int                     i;
 504
 505         for (i = 0; i < rockchip->num_clocks; i++)
 506                 clk_disable(rockchip->clks[i]);
 507
 508         device_init_wakeup(dev, false);
 509
 510         return 0;
 511 }
 512
 513 static int dwc3_rockchip_runtime_resume(struct device *dev)
 514 {
 515         struct dwc3_rockchip    *rockchip = dev_get_drvdata(dev);
 516         int                     i;
 517
 518         for (i = 0; i < rockchip->num_clocks; i++)
 519                 clk_enable(rockchip->clks[i]);
 520
 521         device_init_wakeup(dev, true);
 522
 523         return 0;
 524 }
 525
 526 static int dwc3_rockchip_suspend(struct device *dev)
 527 {
 528         struct dwc3_rockchip *rockchip = dev_get_drvdata(dev);
 529
 530         rockchip->suspended = true;
 531         cancel_work_sync(&rockchip->otg_work);
 532
 533         return 0;
 534 }
 535
 536 static int dwc3_rockchip_resume(struct device *dev)
 537 {
 538         struct dwc3_rockchip *rockchip = dev_get_drvdata(dev);
 539
 540         rockchip->suspended = false;
 541
 542         return 0;
 543 }
 544
 545 static const struct dev_pm_ops dwc3_rockchip_dev_pm_ops = {
 546         SET_SYSTEM_SLEEP_PM_OPS(dwc3_rockchip_suspend, dwc3_rockchip_resume)
 547         SET_RUNTIME_PM_OPS(dwc3_rockchip_runtime_suspend,
 548                            dwc3_rockchip_runtime_resume, NULL)
 549 };
 550
 551 #define DEV_PM_OPS      (&dwc3_rockchip_dev_pm_ops)
 552 #else
 553 #define DEV_PM_OPS      NULL
 554 #endif /* CONFIG_PM */
 555
 556 static const struct of_device_id rockchip_dwc3_match[] = {
 557         { .compatible = "rockchip,rk3399-dwc3" },
 558         { /* Sentinel */ }
 559 };
 560
 561 MODULE_DEVICE_TABLE(of, rockchip_dwc3_match);
 562
 563 static struct platform_driver dwc3_rockchip_driver = {
 564         .probe          = dwc3_rockchip_probe,
 565         .remove         = dwc3_rockchip_remove,
 566         .driver         = {
 567                 .name   = "rockchip-dwc3",
 568                 .of_match_table = rockchip_dwc3_match,
 569                 .pm     = DEV_PM_OPS,
 570         },
 571 };
 572
 573 module_platform_driver(dwc3_rockchip_driver);
 574
 575 MODULE_ALIAS("platform:rockchip-dwc3");
 576 MODULE_AUTHOR("William Wu <william.wu@rock-chips.com>");
 577 MODULE_LICENSE("GPL v2");
 578 MODULE_DESCRIPTION("DesignWare USB3 ROCKCHIP Glue Layer");