drivers/usb/dwc3/dwc3-omap.c

   1 /**
   2  * dwc3-omap.c - OMAP Specific Glue layer
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/kernel.h>
  21 #include <linux/slab.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/platform_data/dwc3-omap.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/ioport.h>
  28 #include <linux/io.h>
  29 #include <linux/of.h>
  30 #include <linux/of_platform.h>
  31 #include <linux/extcon.h>
  32 #include <linux/regulator/consumer.h>
  33
  34 #include <linux/usb/otg.h>
  35
  36 /*
  37  * All these registers belong to OMAP's Wrapper around the
  38  * DesignWare USB3 Core.
  39  */
  40
  41 #define USBOTGSS_REVISION                       0x0000
  42 #define USBOTGSS_SYSCONFIG                      0x0010
  43 #define USBOTGSS_IRQ_EOI                        0x0020
  44 #define USBOTGSS_EOI_OFFSET                     0x0008
  45 #define USBOTGSS_IRQSTATUS_RAW_0                0x0024
  46 #define USBOTGSS_IRQSTATUS_0                    0x0028
  47 #define USBOTGSS_IRQENABLE_SET_0                0x002c
  48 #define USBOTGSS_IRQENABLE_CLR_0                0x0030
  49 #define USBOTGSS_IRQ0_OFFSET                    0x0004
  50 #define USBOTGSS_IRQSTATUS_RAW_1                0x0030
  51 #define USBOTGSS_IRQSTATUS_1                    0x0034
  52 #define USBOTGSS_IRQENABLE_SET_1                0x0038
  53 #define USBOTGSS_IRQENABLE_CLR_1                0x003c
  54 #define USBOTGSS_IRQSTATUS_RAW_2                0x0040
  55 #define USBOTGSS_IRQSTATUS_2                    0x0044
  56 #define USBOTGSS_IRQENABLE_SET_2                0x0048
  57 #define USBOTGSS_IRQENABLE_CLR_2                0x004c
  58 #define USBOTGSS_IRQSTATUS_RAW_3                0x0050
  59 #define USBOTGSS_IRQSTATUS_3                    0x0054
  60 #define USBOTGSS_IRQENABLE_SET_3                0x0058
  61 #define USBOTGSS_IRQENABLE_CLR_3                0x005c
  62 #define USBOTGSS_IRQSTATUS_EOI_MISC             0x0030
  63 #define USBOTGSS_IRQSTATUS_RAW_MISC             0x0034
  64 #define USBOTGSS_IRQSTATUS_MISC                 0x0038
  65 #define USBOTGSS_IRQENABLE_SET_MISC             0x003c
  66 #define USBOTGSS_IRQENABLE_CLR_MISC             0x0040
  67 #define USBOTGSS_IRQMISC_OFFSET                 0x03fc
  68 #define USBOTGSS_UTMI_OTG_STATUS                0x0080
  69 #define USBOTGSS_UTMI_OTG_CTRL                  0x0084
  70 #define USBOTGSS_UTMI_OTG_OFFSET                0x0480
  71 #define USBOTGSS_TXFIFO_DEPTH                   0x0508
  72 #define USBOTGSS_RXFIFO_DEPTH                   0x050c
  73 #define USBOTGSS_MMRAM_OFFSET                   0x0100
  74 #define USBOTGSS_FLADJ                          0x0104
  75 #define USBOTGSS_DEBUG_CFG                      0x0108
  76 #define USBOTGSS_DEBUG_DATA                     0x010c
  77 #define USBOTGSS_DEV_EBC_EN                     0x0110
  78 #define USBOTGSS_DEBUG_OFFSET                   0x0600
  79
  80 /* SYSCONFIG REGISTER */
  81 #define USBOTGSS_SYSCONFIG_DMADISABLE           (1 << 16)
  82
  83 /* IRQ_EOI REGISTER */
  84 #define USBOTGSS_IRQ_EOI_LINE_NUMBER            (1 << 0)
  85
  86 /* IRQS0 BITS */
  87 #define USBOTGSS_IRQO_COREIRQ_ST                (1 << 0)
  88
  89 /* IRQMISC BITS */
  90 #define USBOTGSS_IRQMISC_DMADISABLECLR          (1 << 17)
  91 #define USBOTGSS_IRQMISC_OEVT                   (1 << 16)
  92 #define USBOTGSS_IRQMISC_DRVVBUS_RISE           (1 << 13)
  93 #define USBOTGSS_IRQMISC_CHRGVBUS_RISE          (1 << 12)
  94 #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE       (1 << 11)
  95 #define USBOTGSS_IRQMISC_IDPULLUP_RISE          (1 << 8)
  96 #define USBOTGSS_IRQMISC_DRVVBUS_FALL           (1 << 5)
  97 #define USBOTGSS_IRQMISC_CHRGVBUS_FALL          (1 << 4)
  98 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL               (1 << 3)
  99 #define USBOTGSS_IRQMISC_IDPULLUP_FALL          (1 << 0)
 100
 101 /* UTMI_OTG_STATUS REGISTER */
 102 #define USBOTGSS_UTMI_OTG_STATUS_DRVVBUS        (1 << 5)
 103 #define USBOTGSS_UTMI_OTG_STATUS_CHRGVBUS       (1 << 4)
 104 #define USBOTGSS_UTMI_OTG_STATUS_DISCHRGVBUS    (1 << 3)
 105 #define USBOTGSS_UTMI_OTG_STATUS_IDPULLUP       (1 << 0)
 106
 107 /* UTMI_OTG_CTRL REGISTER */
 108 #define USBOTGSS_UTMI_OTG_CTRL_SW_MODE          (1 << 31)
 109 #define USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT     (1 << 9)
 110 #define USBOTGSS_UTMI_OTG_CTRL_TXBITSTUFFENABLE (1 << 8)
 111 #define USBOTGSS_UTMI_OTG_CTRL_IDDIG            (1 << 4)
 112 #define USBOTGSS_UTMI_OTG_CTRL_SESSEND          (1 << 3)
 113 #define USBOTGSS_UTMI_OTG_CTRL_SESSVALID        (1 << 2)
 114 #define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID        (1 << 1)
 115
 116 struct dwc3_omap {
 117         struct device           *dev;
 118
 119         int                     irq;
 120         void __iomem            *base;
 121
 122         u32                     utmi_otg_ctrl;
 123         u32                     utmi_otg_offset;
 124         u32                     irqmisc_offset;
 125         u32                     irq_eoi_offset;
 126         u32                     debug_offset;
 127         u32                     irq0_offset;
 128
 129         struct extcon_dev       *edev;
 130         struct notifier_block   vbus_nb;
 131         struct notifier_block   id_nb;
 132
 133         struct regulator        *vbus_reg;
 134 };
 135
 136 enum omap_dwc3_vbus_id_status {
 137         OMAP_DWC3_ID_FLOAT,
 138         OMAP_DWC3_ID_GROUND,
 139         OMAP_DWC3_VBUS_OFF,
 140         OMAP_DWC3_VBUS_VALID,
 141 };
 142
 143 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
 144 {
 145         return readl(base + offset);
 146 }
 147
 148 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
 149 {
 150         writel(value, base + offset);
 151 }
 152
 153 static u32 dwc3_omap_read_utmi_ctrl(struct dwc3_omap *omap)
 154 {
 155         return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL +
 156                                                         omap->utmi_otg_offset);
 157 }
 158
 159 static void dwc3_omap_write_utmi_ctrl(struct dwc3_omap *omap, u32 value)
 160 {
 161         dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL +
 162                                         omap->utmi_otg_offset, value);
 163
 164 }
 165
 166 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
 167 {
 168         return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_0 -
 169                                                 omap->irq0_offset);
 170 }
 171
 172 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
 173 {
 174         dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
 175                                                 omap->irq0_offset, value);
 176
 177 }
 178
 179 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
 180 {
 181         return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_MISC +
 182                                                 omap->irqmisc_offset);
 183 }
 184
 185 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
 186 {
 187         dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
 188                                         omap->irqmisc_offset, value);
 189
 190 }
 191
 192 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
 193 {
 194         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
 195                                                 omap->irqmisc_offset, value);
 196
 197 }
 198
 199 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
 200 {
 201         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
 202                                                 omap->irq0_offset, value);
 203 }
 204
 205 static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value)
 206 {
 207         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC +
 208                                                 omap->irqmisc_offset, value);
 209 }
 210
 211 static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value)
 212 {
 213         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 -
 214                                                 omap->irq0_offset, value);
 215 }
 216
 217 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
 218         enum omap_dwc3_vbus_id_status status)
 219 {
 220         int     ret;
 221         u32     val;
 222
 223         switch (status) {
 224         case OMAP_DWC3_ID_GROUND:
 225                 if (omap->vbus_reg) {
 226                         ret = regulator_enable(omap->vbus_reg);
 227                         if (ret) {
 228                                 dev_err(omap->dev, "regulator enable failed\n");
 229                                 return;
 230                         }
 231                 }
 232
 233                 val = dwc3_omap_read_utmi_ctrl(omap);
 234                 val &= ~(USBOTGSS_UTMI_OTG_CTRL_IDDIG
 235                                 | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
 236                                 | USBOTGSS_UTMI_OTG_CTRL_SESSEND);
 237                 val |= USBOTGSS_UTMI_OTG_CTRL_SESSVALID
 238                                 | USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT;
 239                 dwc3_omap_write_utmi_ctrl(omap, val);
 240                 break;
 241
 242         case OMAP_DWC3_VBUS_VALID:
 243                 val = dwc3_omap_read_utmi_ctrl(omap);
 244                 val &= ~USBOTGSS_UTMI_OTG_CTRL_SESSEND;
 245                 val |= USBOTGSS_UTMI_OTG_CTRL_IDDIG
 246                                 | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
 247                                 | USBOTGSS_UTMI_OTG_CTRL_SESSVALID
 248                                 | USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT;
 249                 dwc3_omap_write_utmi_ctrl(omap, val);
 250                 break;
 251
 252         case OMAP_DWC3_ID_FLOAT:
 253                 if (omap->vbus_reg)
 254                         regulator_disable(omap->vbus_reg);
 255
 256         case OMAP_DWC3_VBUS_OFF:
 257                 val = dwc3_omap_read_utmi_ctrl(omap);
 258                 val &= ~(USBOTGSS_UTMI_OTG_CTRL_SESSVALID
 259                                 | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
 260                                 | USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT);
 261                 val |= USBOTGSS_UTMI_OTG_CTRL_SESSEND
 262                                 | USBOTGSS_UTMI_OTG_CTRL_IDDIG;
 263                 dwc3_omap_write_utmi_ctrl(omap, val);
 264                 break;
 265
 266         default:
 267                 dev_WARN(omap->dev, "invalid state\n");
 268         }
 269 }
 270
 271 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap);
 272 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap);
 273
 274 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
 275 {
 276         struct dwc3_omap        *omap = _omap;
 277
 278         if (dwc3_omap_read_irqmisc_status(omap) ||
 279             dwc3_omap_read_irq0_status(omap)) {
 280                 /* mask irqs */
 281                 dwc3_omap_disable_irqs(omap);
 282                 return IRQ_WAKE_THREAD;
 283         }
 284
 285         return IRQ_NONE;
 286 }
 287
 288 static irqreturn_t dwc3_omap_interrupt_thread(int irq, void *_omap)
 289 {
 290         struct dwc3_omap        *omap = _omap;
 291         u32                     reg;
 292
 293         /* clear irq status flags */
 294         reg = dwc3_omap_read_irqmisc_status(omap);
 295         dwc3_omap_write_irqmisc_status(omap, reg);
 296
 297         reg = dwc3_omap_read_irq0_status(omap);
 298         dwc3_omap_write_irq0_status(omap, reg);
 299
 300         /* unmask irqs */
 301         dwc3_omap_enable_irqs(omap);
 302
 303         return IRQ_HANDLED;
 304 }
 305
 306 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
 307 {
 308         u32                     reg;
 309
 310         /* enable all IRQs */
 311         reg = USBOTGSS_IRQO_COREIRQ_ST;
 312         dwc3_omap_write_irq0_set(omap, reg);
 313
 314         reg = (USBOTGSS_IRQMISC_OEVT |
 315                         USBOTGSS_IRQMISC_DRVVBUS_RISE |
 316                         USBOTGSS_IRQMISC_CHRGVBUS_RISE |
 317                         USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
 318                         USBOTGSS_IRQMISC_IDPULLUP_RISE |
 319                         USBOTGSS_IRQMISC_DRVVBUS_FALL |
 320                         USBOTGSS_IRQMISC_CHRGVBUS_FALL |
 321                         USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
 322                         USBOTGSS_IRQMISC_IDPULLUP_FALL);
 323
 324         dwc3_omap_write_irqmisc_set(omap, reg);
 325 }
 326
 327 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
 328 {
 329         u32                     reg;
 330
 331         /* disable all IRQs */
 332         reg = USBOTGSS_IRQO_COREIRQ_ST;
 333         dwc3_omap_write_irq0_clr(omap, reg);
 334
 335         reg = (USBOTGSS_IRQMISC_OEVT |
 336                         USBOTGSS_IRQMISC_DRVVBUS_RISE |
 337                         USBOTGSS_IRQMISC_CHRGVBUS_RISE |
 338                         USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
 339                         USBOTGSS_IRQMISC_IDPULLUP_RISE |
 340                         USBOTGSS_IRQMISC_DRVVBUS_FALL |
 341                         USBOTGSS_IRQMISC_CHRGVBUS_FALL |
 342                         USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
 343                         USBOTGSS_IRQMISC_IDPULLUP_FALL);
 344
 345         dwc3_omap_write_irqmisc_clr(omap, reg);
 346 }
 347
 348 static int dwc3_omap_id_notifier(struct notifier_block *nb,
 349         unsigned long event, void *ptr)
 350 {
 351         struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb);
 352
 353         if (event)
 354                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
 355         else
 356                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
 357
 358         return NOTIFY_DONE;
 359 }
 360
 361 static int dwc3_omap_vbus_notifier(struct notifier_block *nb,
 362         unsigned long event, void *ptr)
 363 {
 364         struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb);
 365
 366         if (event)
 367                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
 368         else
 369                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
 370
 371         return NOTIFY_DONE;
 372 }
 373
 374 static void dwc3_omap_map_offset(struct dwc3_omap *omap)
 375 {
 376         struct device_node      *node = omap->dev->of_node;
 377
 378         /*
 379          * Differentiate between OMAP5 and AM437x.
 380          *
 381          * For OMAP5(ES2.0) and AM437x wrapper revision is same, even
 382          * though there are changes in wrapper register offsets.
 383          *
 384          * Using dt compatible to differentiate AM437x.
 385          */
 386         if (of_device_is_compatible(node, "ti,am437x-dwc3")) {
 387                 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
 388                 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
 389                 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
 390                 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
 391                 omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
 392         }
 393 }
 394
 395 static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap)
 396 {
 397         u32                     reg;
 398         struct device_node      *node = omap->dev->of_node;
 399         int                     utmi_mode = 0;
 400
 401         reg = dwc3_omap_read_utmi_ctrl(omap);
 402
 403         of_property_read_u32(node, "utmi-mode", &utmi_mode);
 404
 405         switch (utmi_mode) {
 406         case DWC3_OMAP_UTMI_MODE_SW:
 407                 reg |= USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
 408                 break;
 409         case DWC3_OMAP_UTMI_MODE_HW:
 410                 reg &= ~USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
 411                 break;
 412         default:
 413                 dev_WARN(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);
 414         }
 415
 416         dwc3_omap_write_utmi_ctrl(omap, reg);
 417 }
 418
 419 static int dwc3_omap_extcon_register(struct dwc3_omap *omap)
 420 {
 421         int                     ret;
 422         struct device_node      *node = omap->dev->of_node;
 423         struct extcon_dev       *edev;
 424
 425         if (of_property_read_bool(node, "extcon")) {
 426                 edev = extcon_get_edev_by_phandle(omap->dev, 0);
 427                 if (IS_ERR(edev)) {
 428                         dev_vdbg(omap->dev, "couldn't get extcon device\n");
 429                         return -EPROBE_DEFER;
 430                 }
 431
 432                 omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier;
 433                 ret = extcon_register_notifier(edev, EXTCON_USB,
 434                                                 &omap->vbus_nb);
 435                 if (ret < 0)
 436                         dev_vdbg(omap->dev, "failed to register notifier for USB\n");
 437
 438                 omap->id_nb.notifier_call = dwc3_omap_id_notifier;
 439                 ret = extcon_register_notifier(edev, EXTCON_USB_HOST,
 440                                                 &omap->id_nb);
 441                 if (ret < 0)
 442                         dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n");
 443
 444                 if (extcon_get_cable_state_(edev, EXTCON_USB) == true)
 445                         dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
 446                 if (extcon_get_cable_state_(edev, EXTCON_USB_HOST) == true)
 447                         dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
 448
 449                 omap->edev = edev;
 450         }
 451
 452         return 0;
 453 }
 454
 455 static int dwc3_omap_probe(struct platform_device *pdev)
 456 {
 457         struct device_node      *node = pdev->dev.of_node;
 458
 459         struct dwc3_omap        *omap;
 460         struct resource         *res;
 461         struct device           *dev = &pdev->dev;
 462         struct regulator        *vbus_reg = NULL;
 463
 464         int                     ret;
 465         int                     irq;
 466
 467         u32                     reg;
 468
 469         void __iomem            *base;
 470
 471         if (!node) {
 472                 dev_err(dev, "device node not found\n");
 473                 return -EINVAL;
 474         }
 475
 476         omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
 477         if (!omap)
 478                 return -ENOMEM;
 479
 480         platform_set_drvdata(pdev, omap);
 481
 482         irq = platform_get_irq(pdev, 0);
 483         if (irq < 0) {
 484                 dev_err(dev, "missing IRQ resource\n");
 485                 return -EINVAL;
 486         }
 487
 488         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 489         base = devm_ioremap_resource(dev, res);
 490         if (IS_ERR(base))
 491                 return PTR_ERR(base);
 492
 493         if (of_property_read_bool(node, "vbus-supply")) {
 494                 vbus_reg = devm_regulator_get(dev, "vbus");
 495                 if (IS_ERR(vbus_reg)) {
 496                         dev_err(dev, "vbus init failed\n");
 497                         return PTR_ERR(vbus_reg);
 498                 }
 499         }
 500
 501         omap->dev       = dev;
 502         omap->irq       = irq;
 503         omap->base      = base;
 504         omap->vbus_reg  = vbus_reg;
 505
 506         pm_runtime_enable(dev);
 507         ret = pm_runtime_get_sync(dev);
 508         if (ret < 0) {
 509                 dev_err(dev, "get_sync failed with err %d\n", ret);
 510                 goto err1;
 511         }
 512
 513         dwc3_omap_map_offset(omap);
 514         dwc3_omap_set_utmi_mode(omap);
 515
 516         /* check the DMA Status */
 517         reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
 518
 519         ret = devm_request_threaded_irq(dev, omap->irq, dwc3_omap_interrupt,
 520                                         dwc3_omap_interrupt_thread, IRQF_SHARED,
 521                                         "dwc3-omap", omap);
 522         if (ret) {
 523                 dev_err(dev, "failed to request IRQ #%d --> %d\n",
 524                                 omap->irq, ret);
 525                 goto err1;
 526         }
 527
 528         ret = dwc3_omap_extcon_register(omap);
 529         if (ret < 0)
 530                 goto err1;
 531
 532         ret = of_platform_populate(node, NULL, NULL, dev);
 533         if (ret) {
 534                 dev_err(&pdev->dev, "failed to create dwc3 core\n");
 535                 goto err2;
 536         }
 537
 538         dwc3_omap_enable_irqs(omap);
 539
 540         return 0;
 541
 542 err2:
 543         extcon_unregister_notifier(omap->edev, EXTCON_USB, &omap->vbus_nb);
 544         extcon_unregister_notifier(omap->edev, EXTCON_USB_HOST, &omap->id_nb);
 545
 546 err1:
 547         pm_runtime_put_sync(dev);
 548         pm_runtime_disable(dev);
 549
 550         return ret;
 551 }
 552
 553 static int dwc3_omap_remove(struct platform_device *pdev)
 554 {
 555         struct dwc3_omap        *omap = platform_get_drvdata(pdev);
 556
 557         extcon_unregister_notifier(omap->edev, EXTCON_USB, &omap->vbus_nb);
 558         extcon_unregister_notifier(omap->edev, EXTCON_USB_HOST, &omap->id_nb);
 559         dwc3_omap_disable_irqs(omap);
 560         of_platform_depopulate(omap->dev);
 561         pm_runtime_put_sync(&pdev->dev);
 562         pm_runtime_disable(&pdev->dev);
 563
 564         return 0;
 565 }
 566
 567 static const struct of_device_id of_dwc3_match[] = {
 568         {
 569                 .compatible =   "ti,dwc3"
 570         },
 571         {
 572                 .compatible =   "ti,am437x-dwc3"
 573         },
 574         { },
 575 };
 576 MODULE_DEVICE_TABLE(of, of_dwc3_match);
 577
 578 #ifdef CONFIG_PM_SLEEP
 579 static int dwc3_omap_suspend(struct device *dev)
 580 {
 581         struct dwc3_omap        *omap = dev_get_drvdata(dev);
 582
 583         omap->utmi_otg_ctrl = dwc3_omap_read_utmi_ctrl(omap);
 584         dwc3_omap_disable_irqs(omap);
 585
 586         return 0;
 587 }
 588
 589 static int dwc3_omap_resume(struct device *dev)
 590 {
 591         struct dwc3_omap        *omap = dev_get_drvdata(dev);
 592
 593         dwc3_omap_write_utmi_ctrl(omap, omap->utmi_otg_ctrl);
 594         dwc3_omap_enable_irqs(omap);
 595
 596         pm_runtime_disable(dev);
 597         pm_runtime_set_active(dev);
 598         pm_runtime_enable(dev);
 599
 600         return 0;
 601 }
 602
 603 static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {
 604
 605         SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
 606 };
 607
 608 #define DEV_PM_OPS      (&dwc3_omap_dev_pm_ops)
 609 #else
 610 #define DEV_PM_OPS      NULL
 611 #endif /* CONFIG_PM_SLEEP */
 612
 613 static struct platform_driver dwc3_omap_driver = {
 614         .probe          = dwc3_omap_probe,
 615         .remove         = dwc3_omap_remove,
 616         .driver         = {
 617                 .name   = "omap-dwc3",
 618                 .of_match_table = of_dwc3_match,
 619                 .pm     = DEV_PM_OPS,
 620         },
 621 };
 622
 623 module_platform_driver(dwc3_omap_driver);
 624
 625 MODULE_ALIAS("platform:omap-dwc3");
 626 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 627 MODULE_LICENSE("GPL v2");
 628 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");