2 * dwc3-omap.c - OMAP Specific Glue layer
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/slab.h>
22 #include <linux/interrupt.h>
23 #include <linux/platform_device.h>
24 #include <linux/platform_data/dwc3-omap.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/ioport.h>
30 #include <linux/of_platform.h>
31 #include <linux/extcon.h>
32 #include <linux/regulator/consumer.h>
34 #include <linux/usb/otg.h>
37 * All these registers belong to OMAP's Wrapper around the
38 * DesignWare USB3 Core.
41 #define USBOTGSS_REVISION 0x0000
42 #define USBOTGSS_SYSCONFIG 0x0010
43 #define USBOTGSS_IRQ_EOI 0x0020
44 #define USBOTGSS_EOI_OFFSET 0x0008
45 #define USBOTGSS_IRQSTATUS_RAW_0 0x0024
46 #define USBOTGSS_IRQSTATUS_0 0x0028
47 #define USBOTGSS_IRQENABLE_SET_0 0x002c
48 #define USBOTGSS_IRQENABLE_CLR_0 0x0030
49 #define USBOTGSS_IRQ0_OFFSET 0x0004
50 #define USBOTGSS_IRQSTATUS_RAW_1 0x0030
51 #define USBOTGSS_IRQSTATUS_1 0x0034
52 #define USBOTGSS_IRQENABLE_SET_1 0x0038
53 #define USBOTGSS_IRQENABLE_CLR_1 0x003c
54 #define USBOTGSS_IRQSTATUS_RAW_2 0x0040
55 #define USBOTGSS_IRQSTATUS_2 0x0044
56 #define USBOTGSS_IRQENABLE_SET_2 0x0048
57 #define USBOTGSS_IRQENABLE_CLR_2 0x004c
58 #define USBOTGSS_IRQSTATUS_RAW_3 0x0050
59 #define USBOTGSS_IRQSTATUS_3 0x0054
60 #define USBOTGSS_IRQENABLE_SET_3 0x0058
61 #define USBOTGSS_IRQENABLE_CLR_3 0x005c
62 #define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030
63 #define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034
64 #define USBOTGSS_IRQSTATUS_MISC 0x0038
65 #define USBOTGSS_IRQENABLE_SET_MISC 0x003c
66 #define USBOTGSS_IRQENABLE_CLR_MISC 0x0040
67 #define USBOTGSS_IRQMISC_OFFSET 0x03fc
68 #define USBOTGSS_UTMI_OTG_STATUS 0x0080
69 #define USBOTGSS_UTMI_OTG_CTRL 0x0084
70 #define USBOTGSS_UTMI_OTG_OFFSET 0x0480
71 #define USBOTGSS_TXFIFO_DEPTH 0x0508
72 #define USBOTGSS_RXFIFO_DEPTH 0x050c
73 #define USBOTGSS_MMRAM_OFFSET 0x0100
74 #define USBOTGSS_FLADJ 0x0104
75 #define USBOTGSS_DEBUG_CFG 0x0108
76 #define USBOTGSS_DEBUG_DATA 0x010c
77 #define USBOTGSS_DEV_EBC_EN 0x0110
78 #define USBOTGSS_DEBUG_OFFSET 0x0600
80 /* SYSCONFIG REGISTER */
81 #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16)
83 /* IRQ_EOI REGISTER */
84 #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0)
87 #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0)
90 #define USBOTGSS_IRQMISC_DMADISABLECLR (1 << 17)
91 #define USBOTGSS_IRQMISC_OEVT (1 << 16)
92 #define USBOTGSS_IRQMISC_DRVVBUS_RISE (1 << 13)
93 #define USBOTGSS_IRQMISC_CHRGVBUS_RISE (1 << 12)
94 #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE (1 << 11)
95 #define USBOTGSS_IRQMISC_IDPULLUP_RISE (1 << 8)
96 #define USBOTGSS_IRQMISC_DRVVBUS_FALL (1 << 5)
97 #define USBOTGSS_IRQMISC_CHRGVBUS_FALL (1 << 4)
98 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL (1 << 3)
99 #define USBOTGSS_IRQMISC_IDPULLUP_FALL (1 << 0)
101 /* UTMI_OTG_STATUS REGISTER */
102 #define USBOTGSS_UTMI_OTG_STATUS_DRVVBUS (1 << 5)
103 #define USBOTGSS_UTMI_OTG_STATUS_CHRGVBUS (1 << 4)
104 #define USBOTGSS_UTMI_OTG_STATUS_DISCHRGVBUS (1 << 3)
105 #define USBOTGSS_UTMI_OTG_STATUS_IDPULLUP (1 << 0)
107 /* UTMI_OTG_CTRL REGISTER */
108 #define USBOTGSS_UTMI_OTG_CTRL_SW_MODE (1 << 31)
109 #define USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT (1 << 9)
110 #define USBOTGSS_UTMI_OTG_CTRL_TXBITSTUFFENABLE (1 << 8)
111 #define USBOTGSS_UTMI_OTG_CTRL_IDDIG (1 << 4)
112 #define USBOTGSS_UTMI_OTG_CTRL_SESSEND (1 << 3)
113 #define USBOTGSS_UTMI_OTG_CTRL_SESSVALID (1 << 2)
114 #define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID (1 << 1)
129 struct extcon_dev *edev;
130 struct notifier_block vbus_nb;
131 struct notifier_block id_nb;
133 struct regulator *vbus_reg;
136 enum omap_dwc3_vbus_id_status {
140 OMAP_DWC3_VBUS_VALID,
143 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
145 return readl(base + offset);
148 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
150 writel(value, base + offset);
153 static u32 dwc3_omap_read_utmi_ctrl(struct dwc3_omap *omap)
155 return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL +
156 omap->utmi_otg_offset);
159 static void dwc3_omap_write_utmi_ctrl(struct dwc3_omap *omap, u32 value)
161 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL +
162 omap->utmi_otg_offset, value);
166 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
168 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_0 -
172 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
174 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
175 omap->irq0_offset, value);
179 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
181 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_MISC +
182 omap->irqmisc_offset);
185 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
187 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
188 omap->irqmisc_offset, value);
192 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
194 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
195 omap->irqmisc_offset, value);
199 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
201 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
202 omap->irq0_offset, value);
205 static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value)
207 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC +
208 omap->irqmisc_offset, value);
211 static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value)
213 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 -
214 omap->irq0_offset, value);
217 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
218 enum omap_dwc3_vbus_id_status status)
224 case OMAP_DWC3_ID_GROUND:
225 if (omap->vbus_reg) {
226 ret = regulator_enable(omap->vbus_reg);
228 dev_err(omap->dev, "regulator enable failed\n");
233 val = dwc3_omap_read_utmi_ctrl(omap);
234 val &= ~(USBOTGSS_UTMI_OTG_CTRL_IDDIG
235 | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
236 | USBOTGSS_UTMI_OTG_CTRL_SESSEND);
237 val |= USBOTGSS_UTMI_OTG_CTRL_SESSVALID;
238 dwc3_omap_write_utmi_ctrl(omap, val);
241 case OMAP_DWC3_VBUS_VALID:
242 val = dwc3_omap_read_utmi_ctrl(omap);
243 val &= ~USBOTGSS_UTMI_OTG_CTRL_SESSEND;
244 val |= USBOTGSS_UTMI_OTG_CTRL_IDDIG
245 | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
246 | USBOTGSS_UTMI_OTG_CTRL_SESSVALID;
247 dwc3_omap_write_utmi_ctrl(omap, val);
250 case OMAP_DWC3_ID_FLOAT:
252 regulator_disable(omap->vbus_reg);
254 case OMAP_DWC3_VBUS_OFF:
255 val = dwc3_omap_read_utmi_ctrl(omap);
256 val &= ~(USBOTGSS_UTMI_OTG_CTRL_SESSVALID
257 | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID);
258 val |= USBOTGSS_UTMI_OTG_CTRL_SESSEND
259 | USBOTGSS_UTMI_OTG_CTRL_IDDIG;
260 dwc3_omap_write_utmi_ctrl(omap, val);
264 dev_WARN(omap->dev, "invalid state\n");
268 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap);
269 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap);
271 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
273 struct dwc3_omap *omap = _omap;
275 if (dwc3_omap_read_irqmisc_status(omap) ||
276 dwc3_omap_read_irq0_status(omap)) {
278 dwc3_omap_disable_irqs(omap);
279 return IRQ_WAKE_THREAD;
285 static irqreturn_t dwc3_omap_interrupt_thread(int irq, void *_omap)
287 struct dwc3_omap *omap = _omap;
290 /* clear irq status flags */
291 reg = dwc3_omap_read_irqmisc_status(omap);
292 dwc3_omap_write_irqmisc_status(omap, reg);
294 reg = dwc3_omap_read_irq0_status(omap);
295 dwc3_omap_write_irq0_status(omap, reg);
298 dwc3_omap_enable_irqs(omap);
303 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
307 /* enable all IRQs */
308 reg = USBOTGSS_IRQO_COREIRQ_ST;
309 dwc3_omap_write_irq0_set(omap, reg);
311 reg = (USBOTGSS_IRQMISC_OEVT |
312 USBOTGSS_IRQMISC_DRVVBUS_RISE |
313 USBOTGSS_IRQMISC_CHRGVBUS_RISE |
314 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
315 USBOTGSS_IRQMISC_IDPULLUP_RISE |
316 USBOTGSS_IRQMISC_DRVVBUS_FALL |
317 USBOTGSS_IRQMISC_CHRGVBUS_FALL |
318 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
319 USBOTGSS_IRQMISC_IDPULLUP_FALL);
321 dwc3_omap_write_irqmisc_set(omap, reg);
324 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
328 /* disable all IRQs */
329 reg = USBOTGSS_IRQO_COREIRQ_ST;
330 dwc3_omap_write_irq0_clr(omap, reg);
332 reg = (USBOTGSS_IRQMISC_OEVT |
333 USBOTGSS_IRQMISC_DRVVBUS_RISE |
334 USBOTGSS_IRQMISC_CHRGVBUS_RISE |
335 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
336 USBOTGSS_IRQMISC_IDPULLUP_RISE |
337 USBOTGSS_IRQMISC_DRVVBUS_FALL |
338 USBOTGSS_IRQMISC_CHRGVBUS_FALL |
339 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
340 USBOTGSS_IRQMISC_IDPULLUP_FALL);
342 dwc3_omap_write_irqmisc_clr(omap, reg);
345 static int dwc3_omap_id_notifier(struct notifier_block *nb,
346 unsigned long event, void *ptr)
348 struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb);
351 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
353 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
358 static int dwc3_omap_vbus_notifier(struct notifier_block *nb,
359 unsigned long event, void *ptr)
361 struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb);
364 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
366 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
371 static void dwc3_omap_map_offset(struct dwc3_omap *omap)
373 struct device_node *node = omap->dev->of_node;
376 * Differentiate between OMAP5 and AM437x.
378 * For OMAP5(ES2.0) and AM437x wrapper revision is same, even
379 * though there are changes in wrapper register offsets.
381 * Using dt compatible to differentiate AM437x.
383 if (of_device_is_compatible(node, "ti,am437x-dwc3")) {
384 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
385 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
386 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
387 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
388 omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
392 static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap)
395 struct device_node *node = omap->dev->of_node;
398 reg = dwc3_omap_read_utmi_ctrl(omap);
400 of_property_read_u32(node, "utmi-mode", &utmi_mode);
403 case DWC3_OMAP_UTMI_MODE_SW:
404 reg |= USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
406 case DWC3_OMAP_UTMI_MODE_HW:
407 reg &= ~USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
410 dev_WARN(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);
413 dwc3_omap_write_utmi_ctrl(omap, reg);
416 static int dwc3_omap_extcon_register(struct dwc3_omap *omap)
419 struct device_node *node = omap->dev->of_node;
420 struct extcon_dev *edev;
422 if (of_property_read_bool(node, "extcon")) {
423 edev = extcon_get_edev_by_phandle(omap->dev, 0);
425 dev_vdbg(omap->dev, "couldn't get extcon device\n");
426 return -EPROBE_DEFER;
429 omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier;
430 ret = extcon_register_notifier(edev, EXTCON_USB,
433 dev_vdbg(omap->dev, "failed to register notifier for USB\n");
435 omap->id_nb.notifier_call = dwc3_omap_id_notifier;
436 ret = extcon_register_notifier(edev, EXTCON_USB_HOST,
439 dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n");
441 if (extcon_get_cable_state_(edev, EXTCON_USB) == true)
442 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
443 if (extcon_get_cable_state_(edev, EXTCON_USB_HOST) == true)
444 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
452 static int dwc3_omap_probe(struct platform_device *pdev)
454 struct device_node *node = pdev->dev.of_node;
456 struct dwc3_omap *omap;
457 struct resource *res;
458 struct device *dev = &pdev->dev;
459 struct regulator *vbus_reg = NULL;
469 dev_err(dev, "device node not found\n");
473 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
477 platform_set_drvdata(pdev, omap);
479 irq = platform_get_irq(pdev, 0);
481 dev_err(dev, "missing IRQ resource\n");
485 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
486 base = devm_ioremap_resource(dev, res);
488 return PTR_ERR(base);
490 if (of_property_read_bool(node, "vbus-supply")) {
491 vbus_reg = devm_regulator_get(dev, "vbus");
492 if (IS_ERR(vbus_reg)) {
493 dev_err(dev, "vbus init failed\n");
494 return PTR_ERR(vbus_reg);
501 omap->vbus_reg = vbus_reg;
503 pm_runtime_enable(dev);
504 ret = pm_runtime_get_sync(dev);
506 dev_err(dev, "get_sync failed with err %d\n", ret);
510 dwc3_omap_map_offset(omap);
511 dwc3_omap_set_utmi_mode(omap);
513 /* check the DMA Status */
514 reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
516 ret = devm_request_threaded_irq(dev, omap->irq, dwc3_omap_interrupt,
517 dwc3_omap_interrupt_thread, IRQF_SHARED,
520 dev_err(dev, "failed to request IRQ #%d --> %d\n",
525 ret = dwc3_omap_extcon_register(omap);
529 ret = of_platform_populate(node, NULL, NULL, dev);
531 dev_err(&pdev->dev, "failed to create dwc3 core\n");
535 dwc3_omap_enable_irqs(omap);
540 extcon_unregister_notifier(omap->edev, EXTCON_USB, &omap->vbus_nb);
541 extcon_unregister_notifier(omap->edev, EXTCON_USB_HOST, &omap->id_nb);
544 pm_runtime_put_sync(dev);
545 pm_runtime_disable(dev);
550 static int dwc3_omap_remove(struct platform_device *pdev)
552 struct dwc3_omap *omap = platform_get_drvdata(pdev);
554 extcon_unregister_notifier(omap->edev, EXTCON_USB, &omap->vbus_nb);
555 extcon_unregister_notifier(omap->edev, EXTCON_USB_HOST, &omap->id_nb);
556 dwc3_omap_disable_irqs(omap);
557 of_platform_depopulate(omap->dev);
558 pm_runtime_put_sync(&pdev->dev);
559 pm_runtime_disable(&pdev->dev);
564 static const struct of_device_id of_dwc3_match[] = {
566 .compatible = "ti,dwc3"
569 .compatible = "ti,am437x-dwc3"
573 MODULE_DEVICE_TABLE(of, of_dwc3_match);
575 #ifdef CONFIG_PM_SLEEP
576 static int dwc3_omap_suspend(struct device *dev)
578 struct dwc3_omap *omap = dev_get_drvdata(dev);
580 omap->utmi_otg_ctrl = dwc3_omap_read_utmi_ctrl(omap);
581 dwc3_omap_disable_irqs(omap);
586 static int dwc3_omap_resume(struct device *dev)
588 struct dwc3_omap *omap = dev_get_drvdata(dev);
590 dwc3_omap_write_utmi_ctrl(omap, omap->utmi_otg_ctrl);
591 dwc3_omap_enable_irqs(omap);
593 pm_runtime_disable(dev);
594 pm_runtime_set_active(dev);
595 pm_runtime_enable(dev);
600 static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {
602 SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
605 #define DEV_PM_OPS (&dwc3_omap_dev_pm_ops)
607 #define DEV_PM_OPS NULL
608 #endif /* CONFIG_PM_SLEEP */
610 static struct platform_driver dwc3_omap_driver = {
611 .probe = dwc3_omap_probe,
612 .remove = dwc3_omap_remove,
615 .of_match_table = of_dwc3_match,
620 module_platform_driver(dwc3_omap_driver);
622 MODULE_ALIAS("platform:omap-dwc3");
623 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
624 MODULE_LICENSE("GPL v2");
625 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");