drivers/usb/dwc3/core.c

   1 /**
   2  * core.c - DesignWare USB3 DRD Controller Core file
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/version.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/ioport.h>
  31 #include <linux/io.h>
  32 #include <linux/list.h>
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/of.h>
  36 #include <linux/acpi.h>
  37 #include <linux/pinctrl/consumer.h>
  38
  39 #include <linux/usb/ch9.h>
  40 #include <linux/usb/gadget.h>
  41 #include <linux/usb/of.h>
  42 #include <linux/usb/otg.h>
  43
  44 #include "core.h"
  45 #include "gadget.h"
  46 #include "io.h"
  47
  48 #include "debug.h"
  49
  50 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
  51
  52 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  53 {
  54         u32 reg;
  55
  56         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  57         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  58         reg |= DWC3_GCTL_PRTCAPDIR(mode);
  59         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  60 }
  61
  62 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
  63 {
  64         struct dwc3             *dwc = dep->dwc;
  65         u32                     reg;
  66
  67         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
  68                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
  69                         DWC3_GDBGFIFOSPACE_TYPE(type));
  70
  71         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
  72
  73         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
  74 }
  75
  76 /**
  77  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  78  * @dwc: pointer to our context structure
  79  */
  80 static int dwc3_core_soft_reset(struct dwc3 *dwc)
  81 {
  82         u32             reg;
  83         int             retries = 1000;
  84         int             ret;
  85
  86         usb_phy_init(dwc->usb2_phy);
  87         usb_phy_init(dwc->usb3_phy);
  88         ret = phy_init(dwc->usb2_generic_phy);
  89         if (ret < 0)
  90                 return ret;
  91
  92         ret = phy_init(dwc->usb3_generic_phy);
  93         if (ret < 0) {
  94                 phy_exit(dwc->usb2_generic_phy);
  95                 return ret;
  96         }
  97
  98         /*
  99          * We're resetting only the device side because, if we're in host mode,
 100          * XHCI driver will reset the host block. If dwc3 was configured for
 101          * host-only mode, then we can return early.
 102          */
 103         if (dwc->dr_mode == USB_DR_MODE_HOST)
 104                 return 0;
 105
 106         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 107         reg |= DWC3_DCTL_CSFTRST;
 108         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 109
 110         do {
 111                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 112                 if (!(reg & DWC3_DCTL_CSFTRST))
 113                         return 0;
 114
 115                 udelay(1);
 116         } while (--retries);
 117
 118         return -ETIMEDOUT;
 119 }
 120
 121 /**
 122  * dwc3_soft_reset - Issue soft reset
 123  * @dwc: Pointer to our controller context structure
 124  */
 125 static int dwc3_soft_reset(struct dwc3 *dwc)
 126 {
 127         unsigned long timeout;
 128         u32 reg;
 129
 130         timeout = jiffies + msecs_to_jiffies(500);
 131         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
 132         do {
 133                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 134                 if (!(reg & DWC3_DCTL_CSFTRST))
 135                         break;
 136
 137                 if (time_after(jiffies, timeout)) {
 138                         dev_err(dwc->dev, "Reset Timed Out\n");
 139                         return -ETIMEDOUT;
 140                 }
 141
 142                 cpu_relax();
 143         } while (true);
 144
 145         return 0;
 146 }
 147
 148 /*
 149  * dwc3_frame_length_adjustment - Adjusts frame length if required
 150  * @dwc3: Pointer to our controller context structure
 151  */
 152 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
 153 {
 154         u32 reg;
 155         u32 dft;
 156
 157         if (dwc->revision < DWC3_REVISION_250A)
 158                 return;
 159
 160         if (dwc->fladj == 0)
 161                 return;
 162
 163         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 164         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 165         if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
 166             "request value same as default, ignoring\n")) {
 167                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 168                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
 169                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 170         }
 171 }
 172
 173 /**
 174  * dwc3_free_one_event_buffer - Frees one event buffer
 175  * @dwc: Pointer to our controller context structure
 176  * @evt: Pointer to event buffer to be freed
 177  */
 178 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 179                 struct dwc3_event_buffer *evt)
 180 {
 181         dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
 182 }
 183
 184 /**
 185  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 186  * @dwc: Pointer to our controller context structure
 187  * @length: size of the event buffer
 188  *
 189  * Returns a pointer to the allocated event buffer structure on success
 190  * otherwise ERR_PTR(errno).
 191  */
 192 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 193                 unsigned length)
 194 {
 195         struct dwc3_event_buffer        *evt;
 196
 197         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 198         if (!evt)
 199                 return ERR_PTR(-ENOMEM);
 200
 201         evt->dwc        = dwc;
 202         evt->length     = length;
 203         evt->buf        = dma_alloc_coherent(dwc->dev, length,
 204                         &evt->dma, GFP_KERNEL);
 205         if (!evt->buf)
 206                 return ERR_PTR(-ENOMEM);
 207
 208         return evt;
 209 }
 210
 211 /**
 212  * dwc3_free_event_buffers - frees all allocated event buffers
 213  * @dwc: Pointer to our controller context structure
 214  */
 215 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 216 {
 217         struct dwc3_event_buffer        *evt;
 218
 219         evt = dwc->ev_buf;
 220         if (evt)
 221                 dwc3_free_one_event_buffer(dwc, evt);
 222 }
 223
 224 /**
 225  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 226  * @dwc: pointer to our controller context structure
 227  * @length: size of event buffer
 228  *
 229  * Returns 0 on success otherwise negative errno. In the error case, dwc
 230  * may contain some buffers allocated but not all which were requested.
 231  */
 232 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 233 {
 234         struct dwc3_event_buffer *evt;
 235
 236         evt = dwc3_alloc_one_event_buffer(dwc, length);
 237         if (IS_ERR(evt)) {
 238                 dev_err(dwc->dev, "can't allocate event buffer\n");
 239                 return PTR_ERR(evt);
 240         }
 241         dwc->ev_buf = evt;
 242
 243         return 0;
 244 }
 245
 246 /**
 247  * dwc3_event_buffers_setup - setup our allocated event buffers
 248  * @dwc: pointer to our controller context structure
 249  *
 250  * Returns 0 on success otherwise negative errno.
 251  */
 252 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
 253 {
 254         struct dwc3_event_buffer        *evt;
 255
 256         evt = dwc->ev_buf;
 257         dwc3_trace(trace_dwc3_core,
 258                         "Event buf %p dma %08llx length %d\n",
 259                         evt->buf, (unsigned long long) evt->dma,
 260                         evt->length);
 261
 262         evt->lpos = 0;
 263
 264         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
 265                         lower_32_bits(evt->dma));
 266         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
 267                         upper_32_bits(evt->dma));
 268         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
 269                         DWC3_GEVNTSIZ_SIZE(evt->length));
 270         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 271
 272         return 0;
 273 }
 274
 275 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 276 {
 277         struct dwc3_event_buffer        *evt;
 278
 279         evt = dwc->ev_buf;
 280
 281         evt->lpos = 0;
 282
 283         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
 284         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
 285         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
 286                         | DWC3_GEVNTSIZ_SIZE(0));
 287         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 288 }
 289
 290 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 291 {
 292         if (!dwc->has_hibernation)
 293                 return 0;
 294
 295         if (!dwc->nr_scratch)
 296                 return 0;
 297
 298         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 299                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 300         if (!dwc->scratchbuf)
 301                 return -ENOMEM;
 302
 303         return 0;
 304 }
 305
 306 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 307 {
 308         dma_addr_t scratch_addr;
 309         u32 param;
 310         int ret;
 311
 312         if (!dwc->has_hibernation)
 313                 return 0;
 314
 315         if (!dwc->nr_scratch)
 316                 return 0;
 317
 318          /* should never fall here */
 319         if (!WARN_ON(dwc->scratchbuf))
 320                 return 0;
 321
 322         scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
 323                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 324                         DMA_BIDIRECTIONAL);
 325         if (dma_mapping_error(dwc->dev, scratch_addr)) {
 326                 dev_err(dwc->dev, "failed to map scratch buffer\n");
 327                 ret = -EFAULT;
 328                 goto err0;
 329         }
 330
 331         dwc->scratch_addr = scratch_addr;
 332
 333         param = lower_32_bits(scratch_addr);
 334
 335         ret = dwc3_send_gadget_generic_command(dwc,
 336                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 337         if (ret < 0)
 338                 goto err1;
 339
 340         param = upper_32_bits(scratch_addr);
 341
 342         ret = dwc3_send_gadget_generic_command(dwc,
 343                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 344         if (ret < 0)
 345                 goto err1;
 346
 347         return 0;
 348
 349 err1:
 350         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 351                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 352
 353 err0:
 354         return ret;
 355 }
 356
 357 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 358 {
 359         if (!dwc->has_hibernation)
 360                 return;
 361
 362         if (!dwc->nr_scratch)
 363                 return;
 364
 365          /* should never fall here */
 366         if (!WARN_ON(dwc->scratchbuf))
 367                 return;
 368
 369         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 370                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 371         kfree(dwc->scratchbuf);
 372 }
 373
 374 static void dwc3_core_num_eps(struct dwc3 *dwc)
 375 {
 376         struct dwc3_hwparams    *parms = &dwc->hwparams;
 377
 378         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
 379         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
 380
 381         dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
 382                         dwc->num_in_eps, dwc->num_out_eps);
 383 }
 384
 385 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 386 {
 387         struct dwc3_hwparams    *parms = &dwc->hwparams;
 388
 389         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 390         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 391         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 392         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 393         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 394         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 395         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 396         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 397         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 398 }
 399
 400 /**
 401  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 402  * @dwc: Pointer to our controller context structure
 403  *
 404  * Returns 0 on success. The USB PHY interfaces are configured but not
 405  * initialized. The PHY interfaces and the PHYs get initialized together with
 406  * the core in dwc3_core_init.
 407  */
 408 int dwc3_phy_setup(struct dwc3 *dwc)
 409 {
 410         u32 reg;
 411         int ret;
 412
 413         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 414
 415         /*
 416          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 417          * to '0' during coreConsultant configuration. So default value
 418          * will be '0' when the core is reset. Application needs to set it
 419          * to '1' after the core initialization is completed.
 420          */
 421         if (dwc->revision > DWC3_REVISION_194A)
 422                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 423
 424         if (dwc->u2ss_inp3_quirk)
 425                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 426
 427         if (dwc->dis_rxdet_inp3_quirk)
 428                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
 429
 430         if (dwc->req_p1p2p3_quirk)
 431                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 432
 433         if (dwc->del_p1p2p3_quirk)
 434                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 435
 436         if (dwc->del_phy_power_chg_quirk)
 437                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 438
 439         if (dwc->lfps_filter_quirk)
 440                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 441
 442         if (dwc->rx_detect_poll_quirk)
 443                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 444
 445         if (dwc->tx_de_emphasis_quirk)
 446                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 447
 448         if (dwc->dis_u3_susphy_quirk)
 449                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 450
 451         if (dwc->dis_del_phy_power_chg_quirk)
 452                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 453
 454         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 455
 456         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 457
 458         /* Select the HS PHY interface */
 459         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 460         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 461                 if (dwc->hsphy_interface &&
 462                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 463                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 464                         break;
 465                 } else if (dwc->hsphy_interface &&
 466                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 467                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 468                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 469                 } else {
 470                         /* Relying on default value. */
 471                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 472                                 break;
 473                 }
 474                 /* FALLTHROUGH */
 475         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 476                 /* Making sure the interface and PHY are operational */
 477                 ret = dwc3_soft_reset(dwc);
 478                 if (ret)
 479                         return ret;
 480
 481                 udelay(1);
 482
 483                 ret = dwc3_ulpi_init(dwc);
 484                 if (ret)
 485                         return ret;
 486                 /* FALLTHROUGH */
 487         default:
 488                 break;
 489         }
 490
 491         switch (dwc->hsphy_mode) {
 492         case USBPHY_INTERFACE_MODE_UTMI:
 493                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 494                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 495                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 496                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 497                 break;
 498         case USBPHY_INTERFACE_MODE_UTMIW:
 499                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 500                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 501                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 502                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 503                 break;
 504         default:
 505                 break;
 506         }
 507
 508         /*
 509          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 510          * '0' during coreConsultant configuration. So default value will
 511          * be '0' when the core is reset. Application needs to set it to
 512          * '1' after the core initialization is completed.
 513          */
 514         if (dwc->revision > DWC3_REVISION_194A)
 515                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 516
 517         if (dwc->dis_u2_susphy_quirk)
 518                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 519
 520         if (dwc->dis_enblslpm_quirk)
 521                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 522
 523         if (dwc->dis_u2_freeclk_exists_quirk)
 524                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 525
 526         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 527
 528         return 0;
 529 }
 530
 531 static void dwc3_core_exit(struct dwc3 *dwc)
 532 {
 533         dwc3_event_buffers_cleanup(dwc);
 534
 535         usb_phy_shutdown(dwc->usb2_phy);
 536         usb_phy_shutdown(dwc->usb3_phy);
 537         phy_exit(dwc->usb2_generic_phy);
 538         phy_exit(dwc->usb3_generic_phy);
 539
 540         usb_phy_set_suspend(dwc->usb2_phy, 1);
 541         usb_phy_set_suspend(dwc->usb3_phy, 1);
 542         phy_power_off(dwc->usb2_generic_phy);
 543         phy_power_off(dwc->usb3_generic_phy);
 544 }
 545
 546 /**
 547  * dwc3_core_init - Low-level initialization of DWC3 Core
 548  * @dwc: Pointer to our controller context structure
 549  *
 550  * Returns 0 on success otherwise negative errno.
 551  */
 552 static int dwc3_core_init(struct dwc3 *dwc)
 553 {
 554         u32                     hwparams4 = dwc->hwparams.hwparams4;
 555         u32                     reg;
 556         int                     ret;
 557
 558         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 559         /* This should read as U3 followed by revision number */
 560         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
 561                 /* Detected DWC_usb3 IP */
 562                 dwc->revision = reg;
 563         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
 564                 /* Detected DWC_usb31 IP */
 565                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 566                 dwc->revision |= DWC3_REVISION_IS_DWC31;
 567         } else {
 568                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 569                 ret = -ENODEV;
 570                 goto err0;
 571         }
 572
 573         /*
 574          * Write Linux Version Code to our GUID register so it's easy to figure
 575          * out which kernel version a bug was found.
 576          */
 577         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 578
 579         /* Handle USB2.0-only core configuration */
 580         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 581                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 582                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 583                         dwc->maximum_speed = USB_SPEED_HIGH;
 584         }
 585
 586         /* issue device SoftReset too */
 587         ret = dwc3_soft_reset(dwc);
 588         if (ret)
 589                 goto err0;
 590
 591         ret = dwc3_core_soft_reset(dwc);
 592         if (ret)
 593                 goto err0;
 594
 595         ret = dwc3_phy_setup(dwc);
 596         if (ret)
 597                 goto err0;
 598
 599         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 600         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 601
 602         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 603         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 604                 /**
 605                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 606                  * issue which would cause xHCI compliance tests to fail.
 607                  *
 608                  * Because of that we cannot enable clock gating on such
 609                  * configurations.
 610                  *
 611                  * Refers to:
 612                  *
 613                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 614                  * SOF/ITP Mode Used
 615                  */
 616                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 617                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 618                                 (dwc->revision >= DWC3_REVISION_210A &&
 619                                 dwc->revision <= DWC3_REVISION_250A))
 620                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 621                 else
 622                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 623                 break;
 624         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 625                 /* enable hibernation here */
 626                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 627
 628                 /*
 629                  * REVISIT Enabling this bit so that host-mode hibernation
 630                  * will work. Device-mode hibernation is not yet implemented.
 631                  */
 632                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 633                 break;
 634         default:
 635                 dwc3_trace(trace_dwc3_core, "No power optimization available\n");
 636         }
 637
 638         /* check if current dwc3 is on simulation board */
 639         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 640                 dwc3_trace(trace_dwc3_core,
 641                                 "running on FPGA platform\n");
 642                 dwc->is_fpga = true;
 643         }
 644
 645         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 646                         "disable_scramble cannot be used on non-FPGA builds\n");
 647
 648         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 649                 reg |= DWC3_GCTL_DISSCRAMBLE;
 650         else
 651                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 652
 653         if (dwc->u2exit_lfps_quirk)
 654                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 655
 656         /*
 657          * WORKAROUND: DWC3 revisions <1.90a have a bug
 658          * where the device can fail to connect at SuperSpeed
 659          * and falls back to high-speed mode which causes
 660          * the device to enter a Connect/Disconnect loop
 661          */
 662         if (dwc->revision < DWC3_REVISION_190A)
 663                 reg |= DWC3_GCTL_U2RSTECN;
 664
 665         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 666
 667         dwc3_core_num_eps(dwc);
 668
 669         ret = dwc3_setup_scratch_buffers(dwc);
 670         if (ret)
 671                 goto err1;
 672
 673         /* Adjust Frame Length */
 674         dwc3_frame_length_adjustment(dwc);
 675
 676         usb_phy_set_suspend(dwc->usb2_phy, 0);
 677         usb_phy_set_suspend(dwc->usb3_phy, 0);
 678         ret = phy_power_on(dwc->usb2_generic_phy);
 679         if (ret < 0)
 680                 goto err2;
 681
 682         ret = phy_power_on(dwc->usb3_generic_phy);
 683         if (ret < 0)
 684                 goto err3;
 685
 686         ret = dwc3_event_buffers_setup(dwc);
 687         if (ret) {
 688                 dev_err(dwc->dev, "failed to setup event buffers\n");
 689                 goto err4;
 690         }
 691
 692         return 0;
 693
 694 err4:
 695         phy_power_off(dwc->usb2_generic_phy);
 696
 697 err3:
 698         phy_power_off(dwc->usb3_generic_phy);
 699
 700 err2:
 701         usb_phy_set_suspend(dwc->usb2_phy, 1);
 702         usb_phy_set_suspend(dwc->usb3_phy, 1);
 703         dwc3_core_exit(dwc);
 704
 705 err1:
 706         usb_phy_shutdown(dwc->usb2_phy);
 707         usb_phy_shutdown(dwc->usb3_phy);
 708         phy_exit(dwc->usb2_generic_phy);
 709         phy_exit(dwc->usb3_generic_phy);
 710
 711 err0:
 712         return ret;
 713 }
 714
 715 static int dwc3_core_get_phy(struct dwc3 *dwc)
 716 {
 717         struct device           *dev = dwc->dev;
 718         struct device_node      *node = dev->of_node;
 719         int ret;
 720
 721         if (node) {
 722                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
 723                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
 724         } else {
 725                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
 726                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
 727         }
 728
 729         if (IS_ERR(dwc->usb2_phy)) {
 730                 ret = PTR_ERR(dwc->usb2_phy);
 731                 if (ret == -ENXIO || ret == -ENODEV) {
 732                         dwc->usb2_phy = NULL;
 733                 } else if (ret == -EPROBE_DEFER) {
 734                         return ret;
 735                 } else {
 736                         dev_err(dev, "no usb2 phy configured\n");
 737                         return ret;
 738                 }
 739         }
 740
 741         if (IS_ERR(dwc->usb3_phy)) {
 742                 ret = PTR_ERR(dwc->usb3_phy);
 743                 if (ret == -ENXIO || ret == -ENODEV) {
 744                         dwc->usb3_phy = NULL;
 745                 } else if (ret == -EPROBE_DEFER) {
 746                         return ret;
 747                 } else {
 748                         dev_err(dev, "no usb3 phy configured\n");
 749                         return ret;
 750                 }
 751         }
 752
 753         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
 754         if (IS_ERR(dwc->usb2_generic_phy)) {
 755                 ret = PTR_ERR(dwc->usb2_generic_phy);
 756                 if (ret == -ENOSYS || ret == -ENODEV) {
 757                         dwc->usb2_generic_phy = NULL;
 758                 } else if (ret == -EPROBE_DEFER) {
 759                         return ret;
 760                 } else {
 761                         dev_err(dev, "no usb2 phy configured\n");
 762                         return ret;
 763                 }
 764         }
 765
 766         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
 767         if (IS_ERR(dwc->usb3_generic_phy)) {
 768                 ret = PTR_ERR(dwc->usb3_generic_phy);
 769                 if (ret == -ENOSYS || ret == -ENODEV) {
 770                         dwc->usb3_generic_phy = NULL;
 771                 } else if (ret == -EPROBE_DEFER) {
 772                         return ret;
 773                 } else {
 774                         dev_err(dev, "no usb3 phy configured\n");
 775                         return ret;
 776                 }
 777         }
 778
 779         return 0;
 780 }
 781
 782 static int dwc3_core_init_mode(struct dwc3 *dwc)
 783 {
 784         struct device *dev = dwc->dev;
 785         int ret;
 786
 787         switch (dwc->dr_mode) {
 788         case USB_DR_MODE_PERIPHERAL:
 789                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 790                 ret = dwc3_gadget_init(dwc);
 791                 if (ret) {
 792                         if (ret != -EPROBE_DEFER)
 793                                 dev_err(dev, "failed to initialize gadget\n");
 794                         return ret;
 795                 }
 796                 break;
 797         case USB_DR_MODE_HOST:
 798                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 799                 ret = dwc3_host_init(dwc);
 800                 if (ret) {
 801                         if (ret != -EPROBE_DEFER)
 802                                 dev_err(dev, "failed to initialize host\n");
 803                         return ret;
 804                 }
 805                 break;
 806         case USB_DR_MODE_OTG:
 807                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 808                 ret = dwc3_host_init(dwc);
 809                 if (ret) {
 810                         if (ret != -EPROBE_DEFER)
 811                                 dev_err(dev, "failed to initialize host\n");
 812                         return ret;
 813                 }
 814
 815                 ret = dwc3_gadget_init(dwc);
 816                 if (ret) {
 817                         if (ret != -EPROBE_DEFER)
 818                                 dev_err(dev, "failed to initialize gadget\n");
 819                         return ret;
 820                 }
 821                 break;
 822         default:
 823                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
 824                 return -EINVAL;
 825         }
 826
 827         return 0;
 828 }
 829
 830 static void dwc3_core_exit_mode(struct dwc3 *dwc)
 831 {
 832         switch (dwc->dr_mode) {
 833         case USB_DR_MODE_PERIPHERAL:
 834                 dwc3_gadget_exit(dwc);
 835                 break;
 836         case USB_DR_MODE_HOST:
 837                 dwc3_host_exit(dwc);
 838                 break;
 839         case USB_DR_MODE_OTG:
 840                 dwc3_host_exit(dwc);
 841                 dwc3_gadget_exit(dwc);
 842                 break;
 843         default:
 844                 /* do nothing */
 845                 break;
 846         }
 847 }
 848
 849 #define DWC3_ALIGN_MASK         (16 - 1)
 850
 851 static int dwc3_probe(struct platform_device *pdev)
 852 {
 853         struct device           *dev = &pdev->dev;
 854         struct resource         *res;
 855         struct dwc3             *dwc;
 856         u8                      lpm_nyet_threshold;
 857         u8                      tx_de_emphasis;
 858         u8                      hird_threshold;
 859
 860         int                     ret;
 861
 862         void __iomem            *regs;
 863         void                    *mem;
 864
 865         mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
 866         if (!mem)
 867                 return -ENOMEM;
 868
 869         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
 870         dwc->mem = mem;
 871         dwc->dev = dev;
 872
 873         /* Try to set 64-bit DMA first */
 874         if (!pdev->dev.dma_mask)
 875                 /* Platform did not initialize dma_mask */
 876                 ret = dma_coerce_mask_and_coherent(&pdev->dev,
 877                                                    DMA_BIT_MASK(64));
 878         else
 879                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
 880
 881         /* If seting 64-bit DMA mask fails, fall back to 32-bit DMA mask */
 882         if (ret) {
 883                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 884                 if (ret)
 885                         return ret;
 886         }
 887
 888         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 889         if (!res) {
 890                 dev_err(dev, "missing memory resource\n");
 891                 return -ENODEV;
 892         }
 893
 894         dwc->xhci_resources[0].start = res->start;
 895         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
 896                                         DWC3_XHCI_REGS_END;
 897         dwc->xhci_resources[0].flags = res->flags;
 898         dwc->xhci_resources[0].name = res->name;
 899
 900         res->start += DWC3_GLOBALS_REGS_START;
 901
 902         /*
 903          * Request memory region but exclude xHCI regs,
 904          * since it will be requested by the xhci-plat driver.
 905          */
 906         regs = devm_ioremap_resource(dev, res);
 907         if (IS_ERR(regs)) {
 908                 ret = PTR_ERR(regs);
 909                 goto err0;
 910         }
 911
 912         dwc->regs       = regs;
 913         dwc->regs_size  = resource_size(res);
 914
 915         /* default to highest possible threshold */
 916         lpm_nyet_threshold = 0xff;
 917
 918         /* default to -3.5dB de-emphasis */
 919         tx_de_emphasis = 1;
 920
 921         /*
 922          * default to assert utmi_sleep_n and use maximum allowed HIRD
 923          * threshold value of 0b1100
 924          */
 925         hird_threshold = 12;
 926
 927         dwc->maximum_speed = usb_get_maximum_speed(dev);
 928         dwc->dr_mode = usb_get_dr_mode(dev);
 929         dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
 930
 931         dwc->has_lpm_erratum = device_property_read_bool(dev,
 932                                 "snps,has-lpm-erratum");
 933         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
 934                                 &lpm_nyet_threshold);
 935         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
 936                                 "snps,is-utmi-l1-suspend");
 937         device_property_read_u8(dev, "snps,hird-threshold",
 938                                 &hird_threshold);
 939         dwc->usb3_lpm_capable = device_property_read_bool(dev,
 940                                 "snps,usb3_lpm_capable");
 941
 942         dwc->disable_scramble_quirk = device_property_read_bool(dev,
 943                                 "snps,disable_scramble_quirk");
 944         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
 945                                 "snps,u2exit_lfps_quirk");
 946         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
 947                                 "snps,u2ss_inp3_quirk");
 948         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
 949                                 "snps,req_p1p2p3_quirk");
 950         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
 951                                 "snps,del_p1p2p3_quirk");
 952         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
 953                                 "snps,del_phy_power_chg_quirk");
 954         dwc->lfps_filter_quirk = device_property_read_bool(dev,
 955                                 "snps,lfps_filter_quirk");
 956         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
 957                                 "snps,rx_detect_poll_quirk");
 958         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
 959                                 "snps,dis_u3_susphy_quirk");
 960         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
 961                                 "snps,dis_u2_susphy_quirk");
 962         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
 963                                 "snps,dis_enblslpm_quirk");
 964         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
 965                                 "snps,dis_rxdet_inp3_quirk");
 966         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
 967                                 "snps,dis-u2-freeclk-exists-quirk");
 968         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
 969                                 "snps,dis-del-phy-power-chg-quirk");
 970         dwc->xhci_slow_suspend_quirk = device_property_read_bool(dev,
 971                                 "snps,xhci-slow-suspend-quirk");
 972
 973         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
 974                                 "snps,tx_de_emphasis_quirk");
 975         device_property_read_u8(dev, "snps,tx_de_emphasis",
 976                                 &tx_de_emphasis);
 977         device_property_read_string(dev, "snps,hsphy_interface",
 978                                     &dwc->hsphy_interface);
 979         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
 980                                  &dwc->fladj);
 981
 982         /* default to superspeed if no maximum_speed passed */
 983         if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
 984                 dwc->maximum_speed = USB_SPEED_SUPER;
 985
 986         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
 987         dwc->tx_de_emphasis = tx_de_emphasis;
 988
 989         dwc->hird_threshold = hird_threshold
 990                 | (dwc->is_utmi_l1_suspend << 4);
 991
 992         platform_set_drvdata(pdev, dwc);
 993         dwc3_cache_hwparams(dwc);
 994
 995         ret = dwc3_core_get_phy(dwc);
 996         if (ret)
 997                 goto err0;
 998
 999         spin_lock_init(&dwc->lock);
1000
1001         if (!dev->dma_mask) {
1002                 dev->dma_mask = dev->parent->dma_mask;
1003                 dev->dma_parms = dev->parent->dma_parms;
1004                 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
1005         }
1006
1007         pm_runtime_set_active(dev);
1008         pm_runtime_use_autosuspend(dev);
1009         pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1010         pm_runtime_enable(dev);
1011         ret = pm_runtime_get_sync(dev);
1012         if (ret < 0)
1013                 goto err1;
1014
1015         pm_runtime_forbid(dev);
1016
1017         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1018         if (ret) {
1019                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1020                 ret = -ENOMEM;
1021                 goto err2;
1022         }
1023
1024         if (IS_ENABLED(CONFIG_USB_DWC3_HOST) &&
1025                         (dwc->dr_mode == USB_DR_MODE_OTG ||
1026                                         dwc->dr_mode == USB_DR_MODE_UNKNOWN))
1027                 dwc->dr_mode = USB_DR_MODE_HOST;
1028         else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET) &&
1029                         (dwc->dr_mode == USB_DR_MODE_OTG ||
1030                                         dwc->dr_mode == USB_DR_MODE_UNKNOWN))
1031                 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
1032
1033         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
1034                 dwc->dr_mode = USB_DR_MODE_OTG;
1035
1036         ret = dwc3_alloc_scratch_buffers(dwc);
1037         if (ret)
1038                 goto err3;
1039
1040         ret = dwc3_core_init(dwc);
1041         if (ret) {
1042                 dev_err(dev, "failed to initialize core\n");
1043                 goto err4;
1044         }
1045
1046         ret = dwc3_core_init_mode(dwc);
1047         if (ret)
1048                 goto err5;
1049
1050         dwc3_debugfs_init(dwc);
1051         pm_runtime_put(dev);
1052
1053         return 0;
1054
1055 err5:
1056         dwc3_event_buffers_cleanup(dwc);
1057
1058 err4:
1059         dwc3_free_scratch_buffers(dwc);
1060
1061 err3:
1062         dwc3_free_event_buffers(dwc);
1063         dwc3_ulpi_exit(dwc);
1064
1065 err2:
1066         pm_runtime_allow(&pdev->dev);
1067
1068 err1:
1069         pm_runtime_put_sync(&pdev->dev);
1070         pm_runtime_disable(&pdev->dev);
1071
1072 err0:
1073         /*
1074          * restore res->start back to its original value so that, in case the
1075          * probe is deferred, we don't end up getting error in request the
1076          * memory region the next time probe is called.
1077          */
1078         res->start -= DWC3_GLOBALS_REGS_START;
1079
1080         return ret;
1081 }
1082
1083 static int dwc3_remove(struct platform_device *pdev)
1084 {
1085         struct dwc3     *dwc = platform_get_drvdata(pdev);
1086         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1087
1088         pm_runtime_get_sync(&pdev->dev);
1089         /*
1090          * restore res->start back to its original value so that, in case the
1091          * probe is deferred, we don't end up getting error in request the
1092          * memory region the next time probe is called.
1093          */
1094         res->start -= DWC3_GLOBALS_REGS_START;
1095
1096         dwc3_debugfs_exit(dwc);
1097         dwc3_core_exit_mode(dwc);
1098
1099         dwc3_core_exit(dwc);
1100         dwc3_ulpi_exit(dwc);
1101
1102         pm_runtime_put_sync(&pdev->dev);
1103         pm_runtime_allow(&pdev->dev);
1104         pm_runtime_disable(&pdev->dev);
1105
1106         dwc3_free_event_buffers(dwc);
1107         dwc3_free_scratch_buffers(dwc);
1108
1109         return 0;
1110 }
1111
1112 #ifdef CONFIG_PM
1113 static int dwc3_suspend_common(struct dwc3 *dwc)
1114 {
1115         unsigned long   flags;
1116
1117         switch (dwc->dr_mode) {
1118         case USB_DR_MODE_PERIPHERAL:
1119         case USB_DR_MODE_OTG:
1120                 spin_lock_irqsave(&dwc->lock, flags);
1121                 dwc3_gadget_suspend(dwc);
1122                 spin_unlock_irqrestore(&dwc->lock, flags);
1123                 break;
1124         case USB_DR_MODE_HOST:
1125         default:
1126                 /* do nothing */
1127                 break;
1128         }
1129
1130         dwc3_core_exit(dwc);
1131
1132         return 0;
1133 }
1134
1135 static int dwc3_resume_common(struct dwc3 *dwc)
1136 {
1137         unsigned long   flags;
1138         int             ret;
1139
1140         ret = dwc3_core_init(dwc);
1141         if (ret)
1142                 return ret;
1143
1144         switch (dwc->dr_mode) {
1145         case USB_DR_MODE_PERIPHERAL:
1146         case USB_DR_MODE_OTG:
1147                 spin_lock_irqsave(&dwc->lock, flags);
1148                 dwc3_gadget_resume(dwc);
1149                 spin_unlock_irqrestore(&dwc->lock, flags);
1150                 /* FALLTHROUGH */
1151         case USB_DR_MODE_HOST:
1152         default:
1153                 /* do nothing */
1154                 break;
1155         }
1156
1157         return 0;
1158 }
1159
1160 static int dwc3_runtime_checks(struct dwc3 *dwc)
1161 {
1162         switch (dwc->dr_mode) {
1163         case USB_DR_MODE_PERIPHERAL:
1164         case USB_DR_MODE_OTG:
1165                 if (dwc->connected)
1166                         return -EBUSY;
1167                 break;
1168         case USB_DR_MODE_HOST:
1169         default:
1170                 /* do nothing */
1171                 break;
1172         }
1173
1174         return 0;
1175 }
1176
1177 static int dwc3_runtime_suspend(struct device *dev)
1178 {
1179         struct dwc3     *dwc = dev_get_drvdata(dev);
1180         int             ret;
1181
1182         if (dwc3_runtime_checks(dwc))
1183                 return -EBUSY;
1184
1185         ret = dwc3_suspend_common(dwc);
1186         if (ret)
1187                 return ret;
1188
1189         device_init_wakeup(dev, true);
1190
1191         return 0;
1192 }
1193
1194 static int dwc3_runtime_resume(struct device *dev)
1195 {
1196         struct dwc3     *dwc = dev_get_drvdata(dev);
1197         int             ret;
1198
1199         device_init_wakeup(dev, false);
1200
1201         ret = dwc3_resume_common(dwc);
1202         if (ret)
1203                 return ret;
1204
1205         switch (dwc->dr_mode) {
1206         case USB_DR_MODE_PERIPHERAL:
1207         case USB_DR_MODE_OTG:
1208                 dwc3_gadget_process_pending_events(dwc);
1209                 break;
1210         case USB_DR_MODE_HOST:
1211         default:
1212                 /* do nothing */
1213                 break;
1214         }
1215
1216         pm_runtime_mark_last_busy(dev);
1217
1218         return 0;
1219 }
1220
1221 static int dwc3_runtime_idle(struct device *dev)
1222 {
1223         struct dwc3     *dwc = dev_get_drvdata(dev);
1224
1225         switch (dwc->dr_mode) {
1226         case USB_DR_MODE_PERIPHERAL:
1227         case USB_DR_MODE_OTG:
1228                 if (dwc3_runtime_checks(dwc))
1229                         return -EBUSY;
1230                 break;
1231         case USB_DR_MODE_HOST:
1232         default:
1233                 /* do nothing */
1234                 break;
1235         }
1236
1237         pm_runtime_mark_last_busy(dev);
1238         pm_runtime_autosuspend(dev);
1239
1240         return 0;
1241 }
1242 #endif /* CONFIG_PM */
1243
1244 #ifdef CONFIG_PM_SLEEP
1245 static int dwc3_suspend(struct device *dev)
1246 {
1247         struct dwc3     *dwc = dev_get_drvdata(dev);
1248         int             ret;
1249
1250         if (pm_runtime_suspended(dwc->dev))
1251                 return 0;
1252
1253         ret = dwc3_suspend_common(dwc);
1254         if (ret)
1255                 return ret;
1256
1257         pinctrl_pm_select_sleep_state(dev);
1258
1259         return 0;
1260 }
1261
1262 static int dwc3_resume(struct device *dev)
1263 {
1264         struct dwc3     *dwc = dev_get_drvdata(dev);
1265         int             ret;
1266
1267         if (pm_runtime_suspended(dwc->dev))
1268                 return 0;
1269
1270         pinctrl_pm_select_default_state(dev);
1271
1272         ret = dwc3_resume_common(dwc);
1273         if (ret)
1274                 return ret;
1275
1276         pm_runtime_disable(dev);
1277         pm_runtime_set_active(dev);
1278         pm_runtime_enable(dev);
1279
1280         return 0;
1281 }
1282 #endif /* CONFIG_PM_SLEEP */
1283
1284 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1285         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1286         SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1287                         dwc3_runtime_idle)
1288 };
1289
1290 #ifdef CONFIG_OF
1291 static const struct of_device_id of_dwc3_match[] = {
1292         {
1293                 .compatible = "snps,dwc3"
1294         },
1295         {
1296                 .compatible = "synopsys,dwc3"
1297         },
1298         { },
1299 };
1300 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1301 #endif
1302
1303 #ifdef CONFIG_ACPI
1304
1305 #define ACPI_ID_INTEL_BSW       "808622B7"
1306
1307 static const struct acpi_device_id dwc3_acpi_match[] = {
1308         { ACPI_ID_INTEL_BSW, 0 },
1309         { },
1310 };
1311 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1312 #endif
1313
1314 static struct platform_driver dwc3_driver = {
1315         .probe          = dwc3_probe,
1316         .remove         = dwc3_remove,
1317         .driver         = {
1318                 .name   = "dwc3",
1319                 .of_match_table = of_match_ptr(of_dwc3_match),
1320                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1321                 .pm     = &dwc3_dev_pm_ops,
1322         },
1323 };
1324
1325 module_platform_driver(dwc3_driver);
1326
1327 MODULE_ALIAS("platform:dwc3");
1328 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1329 MODULE_LICENSE("GPL v2");
1330 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");