drivers/usb/dwc2/platform.c

   1 /*
   2  * platform.c - DesignWare HS OTG Controller platform driver
   3  *
   4  * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 #include <linux/kernel.h>
  38 #include <linux/module.h>
  39 #include <linux/slab.h>
  40 #include <linux/clk.h>
  41 #include <linux/device.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/of_device.h>
  44 #include <linux/mutex.h>
  45 #include <linux/platform_device.h>
  46 #include <linux/phy/phy.h>
  47 #include <linux/platform_data/s3c-hsotg.h>
  48
  49 #include <linux/usb/of.h>
  50
  51 #include "core.h"
  52 #include "hcd.h"
  53 #include "debug.h"
  54
  55 static const char dwc2_driver_name[] = "dwc2";
  56
  57 static const struct dwc2_core_params params_hi6220 = {
  58         .otg_cap                        = 2,    /* No HNP/SRP capable */
  59         .otg_ver                        = 0,    /* 1.3 */
  60         .dma_enable                     = 1,
  61         .dma_desc_enable                = 0,
  62         .dma_desc_fs_enable             = 0,
  63         .speed                          = 0,    /* High Speed */
  64         .enable_dynamic_fifo            = 1,
  65         .en_multiple_tx_fifo            = 1,
  66         .host_rx_fifo_size              = 512,
  67         .host_nperio_tx_fifo_size       = 512,
  68         .host_perio_tx_fifo_size        = 512,
  69         .max_transfer_size              = 65535,
  70         .max_packet_count               = 511,
  71         .host_channels                  = 16,
  72         .phy_type                       = 1,    /* UTMI */
  73         .phy_utmi_width                 = 8,
  74         .phy_ulpi_ddr                   = 0,    /* Single */
  75         .phy_ulpi_ext_vbus              = 0,
  76         .i2c_enable                     = 0,
  77         .ulpi_fs_ls                     = 0,
  78         .host_support_fs_ls_low_power   = 0,
  79         .host_ls_low_power_phy_clk      = 0,    /* 48 MHz */
  80         .ts_dline                       = 0,
  81         .reload_ctl                     = 0,
  82         .ahbcfg                         = GAHBCFG_HBSTLEN_INCR16 <<
  83                                           GAHBCFG_HBSTLEN_SHIFT,
  84         .uframe_sched                   = 0,
  85         .external_id_pin_ctl            = -1,
  86         .hibernation                    = -1,
  87 };
  88
  89 static const struct dwc2_core_params params_bcm2835 = {
  90         .otg_cap                        = 0,    /* HNP/SRP capable */
  91         .otg_ver                        = 0,    /* 1.3 */
  92         .dma_enable                     = 1,
  93         .dma_desc_enable                = 0,
  94         .dma_desc_fs_enable             = 0,
  95         .speed                          = 0,    /* High Speed */
  96         .enable_dynamic_fifo            = 1,
  97         .en_multiple_tx_fifo            = 1,
  98         .host_rx_fifo_size              = 774,  /* 774 DWORDs */
  99         .host_nperio_tx_fifo_size       = 256,  /* 256 DWORDs */
 100         .host_perio_tx_fifo_size        = 512,  /* 512 DWORDs */
 101         .max_transfer_size              = 65535,
 102         .max_packet_count               = 511,
 103         .host_channels                  = 8,
 104         .phy_type                       = 1,    /* UTMI */
 105         .phy_utmi_width                 = 8,    /* 8 bits */
 106         .phy_ulpi_ddr                   = 0,    /* Single */
 107         .phy_ulpi_ext_vbus              = 0,
 108         .i2c_enable                     = 0,
 109         .ulpi_fs_ls                     = 0,
 110         .host_support_fs_ls_low_power   = 0,
 111         .host_ls_low_power_phy_clk      = 0,    /* 48 MHz */
 112         .ts_dline                       = 0,
 113         .reload_ctl                     = 0,
 114         .ahbcfg                         = 0x10,
 115         .uframe_sched                   = 0,
 116         .external_id_pin_ctl            = -1,
 117         .hibernation                    = -1,
 118 };
 119
 120 static const struct dwc2_core_params params_rk3066 = {
 121         .otg_cap                        = 2,    /* non-HNP/non-SRP */
 122         .otg_ver                        = -1,
 123         .dma_enable                     = -1,
 124         .dma_desc_enable                = 0,
 125         .dma_desc_fs_enable             = 0,
 126         .speed                          = -1,
 127         .enable_dynamic_fifo            = 1,
 128         .en_multiple_tx_fifo            = -1,
 129         .host_rx_fifo_size              = 525,  /* 525 DWORDs */
 130         .host_nperio_tx_fifo_size       = 128,  /* 128 DWORDs */
 131         .host_perio_tx_fifo_size        = 256,  /* 256 DWORDs */
 132         .max_transfer_size              = -1,
 133         .max_packet_count               = -1,
 134         .host_channels                  = -1,
 135         .phy_type                       = -1,
 136         .phy_utmi_width                 = -1,
 137         .phy_ulpi_ddr                   = -1,
 138         .phy_ulpi_ext_vbus              = -1,
 139         .i2c_enable                     = -1,
 140         .ulpi_fs_ls                     = -1,
 141         .host_support_fs_ls_low_power   = -1,
 142         .host_ls_low_power_phy_clk      = -1,
 143         .ts_dline                       = -1,
 144         .reload_ctl                     = -1,
 145         .ahbcfg                         = GAHBCFG_HBSTLEN_INCR16 <<
 146                                           GAHBCFG_HBSTLEN_SHIFT,
 147         .uframe_sched                   = -1,
 148         .external_id_pin_ctl            = -1,
 149         .hibernation                    = -1,
 150 };
 151
 152 static const struct dwc2_core_params params_ltq = {
 153         .otg_cap                        = 2,    /* non-HNP/non-SRP */
 154         .otg_ver                        = -1,
 155         .dma_enable                     = -1,
 156         .dma_desc_enable                = -1,
 157         .dma_desc_fs_enable             = -1,
 158         .speed                          = -1,
 159         .enable_dynamic_fifo            = -1,
 160         .en_multiple_tx_fifo            = -1,
 161         .host_rx_fifo_size              = 288,  /* 288 DWORDs */
 162         .host_nperio_tx_fifo_size       = 128,  /* 128 DWORDs */
 163         .host_perio_tx_fifo_size        = 96,   /* 96 DWORDs */
 164         .max_transfer_size              = 65535,
 165         .max_packet_count               = 511,
 166         .host_channels                  = -1,
 167         .phy_type                       = -1,
 168         .phy_utmi_width                 = -1,
 169         .phy_ulpi_ddr                   = -1,
 170         .phy_ulpi_ext_vbus              = -1,
 171         .i2c_enable                     = -1,
 172         .ulpi_fs_ls                     = -1,
 173         .host_support_fs_ls_low_power   = -1,
 174         .host_ls_low_power_phy_clk      = -1,
 175         .ts_dline                       = -1,
 176         .reload_ctl                     = -1,
 177         .ahbcfg                         = GAHBCFG_HBSTLEN_INCR16 <<
 178                                           GAHBCFG_HBSTLEN_SHIFT,
 179         .uframe_sched                   = -1,
 180         .external_id_pin_ctl            = -1,
 181         .hibernation                    = -1,
 182 };
 183
 184 /*
 185  * Check the dr_mode against the module configuration and hardware
 186  * capabilities.
 187  *
 188  * The hardware, module, and dr_mode, can each be set to host, device,
 189  * or otg. Check that all these values are compatible and adjust the
 190  * value of dr_mode if possible.
 191  *
 192  *                      actual
 193  *    HW  MOD dr_mode   dr_mode
 194  *  ------------------------------
 195  *   HST  HST  any    :  HST
 196  *   HST  DEV  any    :  ---
 197  *   HST  OTG  any    :  HST
 198  *
 199  *   DEV  HST  any    :  ---
 200  *   DEV  DEV  any    :  DEV
 201  *   DEV  OTG  any    :  DEV
 202  *
 203  *   OTG  HST  any    :  HST
 204  *   OTG  DEV  any    :  DEV
 205  *   OTG  OTG  any    :  dr_mode
 206  */
 207 static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg)
 208 {
 209         enum usb_dr_mode mode;
 210
 211         hsotg->dr_mode = usb_get_dr_mode(hsotg->dev);
 212         if (hsotg->dr_mode == USB_DR_MODE_UNKNOWN)
 213                 hsotg->dr_mode = USB_DR_MODE_OTG;
 214
 215         mode = hsotg->dr_mode;
 216
 217         if (dwc2_hw_is_device(hsotg)) {
 218                 if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) {
 219                         dev_err(hsotg->dev,
 220                                 "Controller does not support host mode.\n");
 221                         return -EINVAL;
 222                 }
 223                 mode = USB_DR_MODE_PERIPHERAL;
 224         } else if (dwc2_hw_is_host(hsotg)) {
 225                 if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) {
 226                         dev_err(hsotg->dev,
 227                                 "Controller does not support device mode.\n");
 228                         return -EINVAL;
 229                 }
 230                 mode = USB_DR_MODE_HOST;
 231         } else {
 232                 if (IS_ENABLED(CONFIG_USB_DWC2_HOST))
 233                         mode = USB_DR_MODE_HOST;
 234                 else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL))
 235                         mode = USB_DR_MODE_PERIPHERAL;
 236         }
 237
 238         if (mode != hsotg->dr_mode) {
 239                 dev_warn(hsotg->dev,
 240                         "Configuration mismatch. dr_mode forced to %s\n",
 241                         mode == USB_DR_MODE_HOST ? "host" : "device");
 242
 243                 hsotg->dr_mode = mode;
 244         }
 245
 246         return 0;
 247 }
 248
 249 static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
 250 {
 251         struct platform_device *pdev = to_platform_device(hsotg->dev);
 252         int clk, ret;
 253
 254         ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
 255                                     hsotg->supplies);
 256         if (ret)
 257                 return ret;
 258
 259         for (clk = 0; clk < DWC2_MAX_CLKS && hsotg->clks[clk]; clk++) {
 260                 ret = clk_prepare_enable(hsotg->clks[clk]);
 261                 if (ret) {
 262                         while (--clk >= 0)
 263                                 clk_disable_unprepare(hsotg->clks[clk]);
 264                         return ret;
 265                 }
 266         }
 267
 268         if (hsotg->uphy)
 269                 ret = usb_phy_init(hsotg->uphy);
 270         else if (hsotg->plat && hsotg->plat->phy_init)
 271                 ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
 272         else {
 273                 ret = phy_power_on(hsotg->phy);
 274                 if (ret == 0)
 275                         ret = phy_init(hsotg->phy);
 276         }
 277
 278         return ret;
 279 }
 280
 281 /**
 282  * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
 283  * @hsotg: The driver state
 284  *
 285  * A wrapper for platform code responsible for controlling
 286  * low-level USB platform resources (phy, clock, regulators)
 287  */
 288 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
 289 {
 290         int ret = __dwc2_lowlevel_hw_enable(hsotg);
 291
 292         if (ret == 0)
 293                 hsotg->ll_hw_enabled = true;
 294         return ret;
 295 }
 296
 297 static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
 298 {
 299         struct platform_device *pdev = to_platform_device(hsotg->dev);
 300         int clk, ret = 0;
 301
 302         if (hsotg->uphy)
 303                 usb_phy_shutdown(hsotg->uphy);
 304         else if (hsotg->plat && hsotg->plat->phy_exit)
 305                 ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
 306         else {
 307                 ret = phy_exit(hsotg->phy);
 308                 if (ret == 0)
 309                         ret = phy_power_off(hsotg->phy);
 310         }
 311         if (ret)
 312                 return ret;
 313
 314         for (clk = DWC2_MAX_CLKS - 1; clk >= 0; clk--)
 315                 if (hsotg->clks[clk])
 316                         clk_disable_unprepare(hsotg->clks[clk]);
 317
 318         ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
 319                                      hsotg->supplies);
 320
 321         return ret;
 322 }
 323
 324 /**
 325  * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources
 326  * @hsotg: The driver state
 327  *
 328  * A wrapper for platform code responsible for controlling
 329  * low-level USB platform resources (phy, clock, regulators)
 330  */
 331 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
 332 {
 333         int ret = __dwc2_lowlevel_hw_disable(hsotg);
 334
 335         if (ret == 0)
 336                 hsotg->ll_hw_enabled = false;
 337         return ret;
 338 }
 339
 340 /* Only used to reset usb phy at interrupter runtime */
 341 static void dwc2_reset_phy_work(struct work_struct *data)
 342 {
 343         struct dwc2_hsotg *hsotg = container_of(data, struct dwc2_hsotg,
 344                         phy_rst_work);
 345         phy_reset(hsotg->phy);
 346 }
 347
 348 static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
 349 {
 350         int i, clk, ret;
 351
 352         /* Set default UTMI width */
 353         hsotg->phyif = GUSBCFG_PHYIF16;
 354
 355         /*
 356          * Attempt to find a generic PHY, then look for an old style
 357          * USB PHY and then fall back to pdata
 358          */
 359         hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy");
 360         if (IS_ERR(hsotg->phy)) {
 361                 ret = PTR_ERR(hsotg->phy);
 362                 switch (ret) {
 363                 case -ENODEV:
 364                 case -ENOSYS:
 365                         hsotg->phy = NULL;
 366                         break;
 367                 case -EPROBE_DEFER:
 368                         return ret;
 369                 default:
 370                         dev_err(hsotg->dev, "error getting phy %d\n", ret);
 371                         return ret;
 372                 }
 373         }
 374         INIT_WORK(&hsotg->phy_rst_work, dwc2_reset_phy_work);
 375
 376         if (!hsotg->phy) {
 377                 hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);
 378                 if (IS_ERR(hsotg->uphy)) {
 379                         ret = PTR_ERR(hsotg->uphy);
 380                         switch (ret) {
 381                         case -ENODEV:
 382                         case -ENXIO:
 383                                 hsotg->uphy = NULL;
 384                                 break;
 385                         case -EPROBE_DEFER:
 386                                 return ret;
 387                         default:
 388                                 dev_err(hsotg->dev, "error getting usb phy %d\n",
 389                                         ret);
 390                                 return ret;
 391                         }
 392                 }
 393         }
 394
 395         hsotg->plat = dev_get_platdata(hsotg->dev);
 396
 397         if (hsotg->phy) {
 398                 /*
 399                  * If using the generic PHY framework, check if the PHY bus
 400                  * width is 8-bit and set the phyif appropriately.
 401                  */
 402                 if (phy_get_bus_width(hsotg->phy) == 8)
 403                         hsotg->phyif = GUSBCFG_PHYIF8;
 404         }
 405
 406         for (clk = 0; clk < DWC2_MAX_CLKS; clk++) {
 407                 hsotg->clks[clk] = of_clk_get(hsotg->dev->of_node, clk);
 408                 if (IS_ERR(hsotg->clks[clk])) {
 409                         ret = PTR_ERR(hsotg->clks[clk]);
 410                         if (ret == -EPROBE_DEFER) {
 411                                 while (--clk >= 0)
 412                                         clk_put(hsotg->clks[clk]);
 413                                 return ret;
 414                         }
 415
 416                         hsotg->clks[clk] = NULL;
 417                         break;
 418                 }
 419         }
 420
 421         /* Regulators */
 422         for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
 423                 hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i];
 424
 425         ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies),
 426                                       hsotg->supplies);
 427         if (ret) {
 428                 dev_err(hsotg->dev, "failed to request supplies: %d\n", ret);
 429                 return ret;
 430         }
 431         return 0;
 432 }
 433
 434 /**
 435  * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
 436  * DWC_otg driver
 437  *
 438  * @dev: Platform device
 439  *
 440  * This routine is called, for example, when the rmmod command is executed. The
 441  * device may or may not be electrically present. If it is present, the driver
 442  * stops device processing. Any resources used on behalf of this device are
 443  * freed.
 444  */
 445 static int dwc2_driver_remove(struct platform_device *dev)
 446 {
 447         struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
 448
 449         dwc2_debugfs_exit(hsotg);
 450         if (hsotg->hcd_enabled)
 451                 dwc2_hcd_remove(hsotg);
 452         if (hsotg->gadget_enabled)
 453                 dwc2_hsotg_remove(hsotg);
 454
 455         if (hsotg->ll_hw_enabled)
 456                 dwc2_lowlevel_hw_disable(hsotg);
 457
 458         return 0;
 459 }
 460
 461 /**
 462  * dwc2_driver_shutdown() - Called on device shutdown
 463  *
 464  * @dev: Platform device
 465  *
 466  * In specific conditions (involving usb hubs) dwc2 devices can create a
 467  * lot of interrupts, even to the point of overwhelming devices running
 468  * at low frequencies. Some devices need to do special clock handling
 469  * at shutdown-time which may bring the system clock below the threshold
 470  * of being able to handle the dwc2 interrupts. Disabling dwc2-irqs
 471  * prevents reboots/poweroffs from getting stuck in such cases.
 472  */
 473 static void dwc2_driver_shutdown(struct platform_device *dev)
 474 {
 475         struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
 476
 477         disable_irq(hsotg->irq);
 478 }
 479
 480 static const struct of_device_id dwc2_of_match_table[] = {
 481         { .compatible = "brcm,bcm2835-usb", .data = &params_bcm2835 },
 482         { .compatible = "hisilicon,hi6220-usb", .data = &params_hi6220 },
 483         { .compatible = "rockchip,rk3066-usb", .data = &params_rk3066 },
 484         { .compatible = "lantiq,arx100-usb", .data = &params_ltq },
 485         { .compatible = "lantiq,xrx200-usb", .data = &params_ltq },
 486         { .compatible = "snps,dwc2", .data = NULL },
 487         { .compatible = "samsung,s3c6400-hsotg", .data = NULL},
 488         {},
 489 };
 490 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
 491
 492 /**
 493  * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
 494  * driver
 495  *
 496  * @dev: Platform device
 497  *
 498  * This routine creates the driver components required to control the device
 499  * (core, HCD, and PCD) and initializes the device. The driver components are
 500  * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved
 501  * in the device private data. This allows the driver to access the dwc2_hsotg
 502  * structure on subsequent calls to driver methods for this device.
 503  */
 504 static int dwc2_driver_probe(struct platform_device *dev)
 505 {
 506         const struct of_device_id *match;
 507         const struct dwc2_core_params *params;
 508         struct dwc2_core_params defparams;
 509         struct dwc2_hsotg *hsotg;
 510         struct resource *res;
 511         int retval;
 512
 513         match = of_match_device(dwc2_of_match_table, &dev->dev);
 514         if (match && match->data) {
 515                 params = match->data;
 516         } else {
 517                 /* Default all params to autodetect */
 518                 dwc2_set_all_params(&defparams, -1);
 519                 params = &defparams;
 520
 521                 /*
 522                  * Disable descriptor dma mode by default as the HW can support
 523                  * it, but does not support it for SPLIT transactions.
 524                  * Disable it for FS devices as well.
 525                  */
 526                 defparams.dma_desc_enable = 0;
 527                 defparams.dma_desc_fs_enable = 0;
 528         }
 529
 530         hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
 531         if (!hsotg)
 532                 return -ENOMEM;
 533
 534         hsotg->dev = &dev->dev;
 535
 536         /*
 537          * Use reasonable defaults so platforms don't have to provide these.
 538          */
 539         if (!dev->dev.dma_mask)
 540                 dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
 541         retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
 542         if (retval)
 543                 return retval;
 544
 545         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 546         hsotg->regs = devm_ioremap_resource(&dev->dev, res);
 547         if (IS_ERR(hsotg->regs))
 548                 return PTR_ERR(hsotg->regs);
 549
 550         dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
 551                 (unsigned long)res->start, hsotg->regs);
 552
 553         retval = dwc2_lowlevel_hw_init(hsotg);
 554         if (retval)
 555                 return retval;
 556
 557         spin_lock_init(&hsotg->lock);
 558
 559         hsotg->core_params = devm_kzalloc(&dev->dev,
 560                                 sizeof(*hsotg->core_params), GFP_KERNEL);
 561         if (!hsotg->core_params)
 562                 return -ENOMEM;
 563
 564         dwc2_set_all_params(hsotg->core_params, -1);
 565
 566         hsotg->irq = platform_get_irq(dev, 0);
 567         if (hsotg->irq < 0) {
 568                 dev_err(&dev->dev, "missing IRQ resource\n");
 569                 return hsotg->irq;
 570         }
 571
 572         dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
 573                 hsotg->irq);
 574         retval = devm_request_irq(hsotg->dev, hsotg->irq,
 575                                   dwc2_handle_common_intr, IRQF_SHARED,
 576                                   dev_name(hsotg->dev), hsotg);
 577         if (retval)
 578                 return retval;
 579
 580         retval = dwc2_lowlevel_hw_enable(hsotg);
 581         if (retval)
 582                 return retval;
 583
 584         retval = dwc2_get_dr_mode(hsotg);
 585         if (retval)
 586                 goto error;
 587
 588         /*
 589          * Reset before dwc2_get_hwparams() then it could get power-on real
 590          * reset value form registers.
 591          */
 592         dwc2_core_reset_and_force_dr_mode(hsotg);
 593
 594         /* Detect config values from hardware */
 595         retval = dwc2_get_hwparams(hsotg);
 596         if (retval)
 597                 goto error;
 598
 599         /* Validate parameter values */
 600         dwc2_set_parameters(hsotg, params);
 601
 602         dwc2_force_dr_mode(hsotg);
 603
 604         if (hsotg->dr_mode != USB_DR_MODE_HOST) {
 605                 retval = dwc2_gadget_init(hsotg, hsotg->irq);
 606                 if (retval)
 607                         goto error;
 608                 hsotg->gadget_enabled = 1;
 609         }
 610
 611         if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
 612                 retval = dwc2_hcd_init(hsotg, hsotg->irq);
 613                 if (retval) {
 614                         if (hsotg->gadget_enabled)
 615                                 dwc2_hsotg_remove(hsotg);
 616                         goto error;
 617                 }
 618                 hsotg->hcd_enabled = 1;
 619         }
 620
 621         platform_set_drvdata(dev, hsotg);
 622
 623         dwc2_debugfs_init(hsotg);
 624
 625         /* Gadget code manages lowlevel hw on its own */
 626         if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
 627                 dwc2_lowlevel_hw_disable(hsotg);
 628
 629         return 0;
 630
 631 error:
 632         dwc2_lowlevel_hw_disable(hsotg);
 633         return retval;
 634 }
 635
 636 static int __maybe_unused dwc2_suspend(struct device *dev)
 637 {
 638         struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
 639         int ret = 0;
 640
 641         if (dwc2_is_device_mode(dwc2))
 642                 dwc2_hsotg_suspend(dwc2);
 643
 644         if (dwc2->ll_hw_enabled)
 645                 ret = __dwc2_lowlevel_hw_disable(dwc2);
 646
 647         return ret;
 648 }
 649
 650 static int __maybe_unused dwc2_resume(struct device *dev)
 651 {
 652         struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
 653         int ret = 0;
 654
 655         if (dwc2->ll_hw_enabled) {
 656                 ret = __dwc2_lowlevel_hw_enable(dwc2);
 657                 if (ret)
 658                         return ret;
 659         }
 660
 661         if (dwc2_is_device_mode(dwc2))
 662                 ret = dwc2_hsotg_resume(dwc2);
 663
 664         return ret;
 665 }
 666
 667 static const struct dev_pm_ops dwc2_dev_pm_ops = {
 668         SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume)
 669 };
 670
 671 static struct platform_driver dwc2_platform_driver = {
 672         .driver = {
 673                 .name = dwc2_driver_name,
 674                 .of_match_table = dwc2_of_match_table,
 675                 .pm = &dwc2_dev_pm_ops,
 676         },
 677         .probe = dwc2_driver_probe,
 678         .remove = dwc2_driver_remove,
 679         .shutdown = dwc2_driver_shutdown,
 680 };
 681
 682 module_platform_driver(dwc2_platform_driver);
 683
 684 MODULE_DESCRIPTION("DESIGNWARE HS OTG Platform Glue");
 685 MODULE_AUTHOR("Matthijs Kooijman <matthijs@stdin.nl>");
 686 MODULE_LICENSE("Dual BSD/GPL");