2 * NXP (Philips) SCC+++(SCN+++) serial driver
4 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
6 * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/console.h>
21 #include <linux/serial_core.h>
22 #include <linux/serial.h>
24 #include <linux/tty.h>
25 #include <linux/tty_flip.h>
26 #include <linux/spinlock.h>
27 #include <linux/platform_device.h>
28 #include <linux/platform_data/serial-sccnxp.h>
30 #define SCCNXP_NAME "uart-sccnxp"
31 #define SCCNXP_MAJOR 204
32 #define SCCNXP_MINOR 205
34 #define SCCNXP_MR_REG (0x00)
35 # define MR0_BAUD_NORMAL (0 << 0)
36 # define MR0_BAUD_EXT1 (1 << 0)
37 # define MR0_BAUD_EXT2 (5 << 0)
38 # define MR0_FIFO (1 << 3)
39 # define MR0_TXLVL (1 << 4)
40 # define MR1_BITS_5 (0 << 0)
41 # define MR1_BITS_6 (1 << 0)
42 # define MR1_BITS_7 (2 << 0)
43 # define MR1_BITS_8 (3 << 0)
44 # define MR1_PAR_EVN (0 << 2)
45 # define MR1_PAR_ODD (1 << 2)
46 # define MR1_PAR_NO (4 << 2)
47 # define MR2_STOP1 (7 << 0)
48 # define MR2_STOP2 (0xf << 0)
49 #define SCCNXP_SR_REG (0x01)
50 #define SCCNXP_CSR_REG SCCNXP_SR_REG
51 # define SR_RXRDY (1 << 0)
52 # define SR_FULL (1 << 1)
53 # define SR_TXRDY (1 << 2)
54 # define SR_TXEMT (1 << 3)
55 # define SR_OVR (1 << 4)
56 # define SR_PE (1 << 5)
57 # define SR_FE (1 << 6)
58 # define SR_BRK (1 << 7)
59 #define SCCNXP_CR_REG (0x02)
60 # define CR_RX_ENABLE (1 << 0)
61 # define CR_RX_DISABLE (1 << 1)
62 # define CR_TX_ENABLE (1 << 2)
63 # define CR_TX_DISABLE (1 << 3)
64 # define CR_CMD_MRPTR1 (0x01 << 4)
65 # define CR_CMD_RX_RESET (0x02 << 4)
66 # define CR_CMD_TX_RESET (0x03 << 4)
67 # define CR_CMD_STATUS_RESET (0x04 << 4)
68 # define CR_CMD_BREAK_RESET (0x05 << 4)
69 # define CR_CMD_START_BREAK (0x06 << 4)
70 # define CR_CMD_STOP_BREAK (0x07 << 4)
71 # define CR_CMD_MRPTR0 (0x0b << 4)
72 #define SCCNXP_RHR_REG (0x03)
73 #define SCCNXP_THR_REG SCCNXP_RHR_REG
74 #define SCCNXP_IPCR_REG (0x04)
75 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
76 # define ACR_BAUD0 (0 << 7)
77 # define ACR_BAUD1 (1 << 7)
78 # define ACR_TIMER_MODE (6 << 4)
79 #define SCCNXP_ISR_REG (0x05)
80 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
81 # define IMR_TXRDY (1 << 0)
82 # define IMR_RXRDY (1 << 1)
83 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
84 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
85 #define SCCNXP_IPR_REG (0x0d)
86 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
87 #define SCCNXP_SOP_REG (0x0e)
88 #define SCCNXP_ROP_REG (0x0f)
91 #define MCTRL_MASK(sig) (0xf << (sig))
92 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
93 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
95 /* Supported chip types */
97 SCCNXP_TYPE_SC2681 = 2681,
98 SCCNXP_TYPE_SC2691 = 2691,
99 SCCNXP_TYPE_SC2692 = 2692,
100 SCCNXP_TYPE_SC2891 = 2891,
101 SCCNXP_TYPE_SC2892 = 2892,
102 SCCNXP_TYPE_SC28202 = 28202,
103 SCCNXP_TYPE_SC68681 = 68681,
104 SCCNXP_TYPE_SC68692 = 68692,
108 struct uart_driver uart;
109 struct uart_port port[SCCNXP_MAX_UARTS];
110 bool opened[SCCNXP_MAX_UARTS];
120 #define SCCNXP_HAVE_IO 0x00000001
121 #define SCCNXP_HAVE_MR0 0x00000002
123 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
124 struct console console;
130 struct timer_list timer;
132 struct sccnxp_pdata pdata;
135 static inline u8 sccnxp_raw_read(void __iomem *base, u8 reg, u8 shift)
137 return readb(base + (reg << shift));
140 static inline void sccnxp_raw_write(void __iomem *base, u8 reg, u8 shift, u8 v)
142 writeb(v, base + (reg << shift));
145 static inline u8 sccnxp_read(struct uart_port *port, u8 reg)
147 struct sccnxp_port *s = dev_get_drvdata(port->dev);
149 return sccnxp_raw_read(port->membase, reg & s->addr_mask,
153 static inline void sccnxp_write(struct uart_port *port, u8 reg, u8 v)
155 struct sccnxp_port *s = dev_get_drvdata(port->dev);
157 sccnxp_raw_write(port->membase, reg & s->addr_mask, port->regshift, v);
160 static inline u8 sccnxp_port_read(struct uart_port *port, u8 reg)
162 return sccnxp_read(port, (port->line << 3) + reg);
165 static inline void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v)
167 sccnxp_write(port, (port->line << 3) + reg, v);
170 static int sccnxp_update_best_err(int a, int b, int *besterr)
172 int err = abs(a - b);
174 if ((*besterr < 0) || (*besterr > err)) {
189 const struct baud_table baud_std[] = {
190 { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, },
191 { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, },
192 { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, },
193 { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, },
194 { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, },
195 { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, },
196 { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, },
197 { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, },
198 { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, },
199 { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, },
200 { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, },
201 { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, },
202 { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, },
203 { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, },
204 { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, },
205 { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, },
206 { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, },
207 { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, },
208 { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, },
209 { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, },
210 { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, },
211 { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, },
212 { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, },
213 { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, },
214 { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, },
215 { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, },
216 { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, },
217 { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, },
221 static int sccnxp_set_baud(struct uart_port *port, int baud)
223 struct sccnxp_port *s = dev_get_drvdata(port->dev);
224 int div_std, tmp_baud, bestbaud = baud, besterr = -1;
225 u8 i, acr = 0, csr = 0, mr0 = 0;
227 /* Find best baud from table */
228 for (i = 0; baud_std[i].baud && besterr; i++) {
229 if (baud_std[i].mr0 && !(s->flags & SCCNXP_HAVE_MR0))
231 div_std = DIV_ROUND_CLOSEST(s->freq_std, baud_std[i].baud);
232 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std);
233 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) {
234 acr = baud_std[i].acr;
235 csr = baud_std[i].csr;
236 mr0 = baud_std[i].mr0;
241 if (s->flags & SCCNXP_HAVE_MR0) {
242 /* Enable FIFO, set half level for TX */
243 mr0 |= MR0_FIFO | MR0_TXLVL;
245 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0);
246 sccnxp_port_write(port, SCCNXP_MR_REG, mr0);
249 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE);
250 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr);
252 if (baud != bestbaud)
253 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n",
259 static void sccnxp_enable_irq(struct uart_port *port, int mask)
261 struct sccnxp_port *s = dev_get_drvdata(port->dev);
263 s->imr |= mask << (port->line * 4);
264 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
267 static void sccnxp_disable_irq(struct uart_port *port, int mask)
269 struct sccnxp_port *s = dev_get_drvdata(port->dev);
271 s->imr &= ~(mask << (port->line * 4));
272 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
275 static void sccnxp_set_bit(struct uart_port *port, int sig, int state)
278 struct sccnxp_port *s = dev_get_drvdata(port->dev);
280 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) {
281 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig);
283 sccnxp_write(port, SCCNXP_SOP_REG, bitmask);
285 sccnxp_write(port, SCCNXP_ROP_REG, bitmask);
289 static void sccnxp_handle_rx(struct uart_port *port)
292 unsigned int ch, flag;
295 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
296 if (!(sr & SR_RXRDY))
298 sr &= SR_PE | SR_FE | SR_OVR | SR_BRK;
300 ch = sccnxp_port_read(port, SCCNXP_RHR_REG);
308 if (uart_handle_break(port))
310 } else if (sr & SR_PE)
311 port->icount.parity++;
313 port->icount.frame++;
314 else if (sr & SR_OVR)
315 port->icount.overrun++;
317 sr &= port->read_status_mask;
324 else if (sr & SR_OVR)
328 if (uart_handle_sysrq_char(port, ch))
331 if (sr & port->ignore_status_mask)
334 uart_insert_char(port, sr, SR_OVR, ch, flag);
337 tty_flip_buffer_push(&port->state->port);
340 static void sccnxp_handle_tx(struct uart_port *port)
343 struct circ_buf *xmit = &port->state->xmit;
344 struct sccnxp_port *s = dev_get_drvdata(port->dev);
346 if (unlikely(port->x_char)) {
347 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char);
353 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
354 /* Disable TX if FIFO is empty */
355 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) {
356 sccnxp_disable_irq(port, IMR_TXRDY);
358 /* Set direction to input */
359 if (s->flags & SCCNXP_HAVE_IO)
360 sccnxp_set_bit(port, DIR_OP, 0);
365 while (!uart_circ_empty(xmit)) {
366 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
367 if (!(sr & SR_TXRDY))
370 sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]);
371 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
375 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
376 uart_write_wakeup(port);
379 static void sccnxp_handle_events(struct sccnxp_port *s)
385 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG);
390 for (i = 0; i < s->uart.nr; i++) {
391 if (s->opened[i] && (isr & ISR_RXRDY(i)))
392 sccnxp_handle_rx(&s->port[i]);
393 if (s->opened[i] && (isr & ISR_TXRDY(i)))
394 sccnxp_handle_tx(&s->port[i]);
399 static void sccnxp_timer(unsigned long data)
401 struct sccnxp_port *s = (struct sccnxp_port *)data;
404 spin_lock_irqsave(&s->lock, flags);
405 sccnxp_handle_events(s);
406 spin_unlock_irqrestore(&s->lock, flags);
408 if (!timer_pending(&s->timer))
409 mod_timer(&s->timer, jiffies +
410 usecs_to_jiffies(s->pdata.poll_time_us));
413 static irqreturn_t sccnxp_ist(int irq, void *dev_id)
415 struct sccnxp_port *s = (struct sccnxp_port *)dev_id;
418 spin_lock_irqsave(&s->lock, flags);
419 sccnxp_handle_events(s);
420 spin_unlock_irqrestore(&s->lock, flags);
425 static void sccnxp_start_tx(struct uart_port *port)
427 struct sccnxp_port *s = dev_get_drvdata(port->dev);
430 spin_lock_irqsave(&s->lock, flags);
432 /* Set direction to output */
433 if (s->flags & SCCNXP_HAVE_IO)
434 sccnxp_set_bit(port, DIR_OP, 1);
436 sccnxp_enable_irq(port, IMR_TXRDY);
438 spin_unlock_irqrestore(&s->lock, flags);
441 static void sccnxp_stop_tx(struct uart_port *port)
446 static void sccnxp_stop_rx(struct uart_port *port)
448 struct sccnxp_port *s = dev_get_drvdata(port->dev);
451 spin_lock_irqsave(&s->lock, flags);
452 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE);
453 spin_unlock_irqrestore(&s->lock, flags);
456 static unsigned int sccnxp_tx_empty(struct uart_port *port)
460 struct sccnxp_port *s = dev_get_drvdata(port->dev);
462 spin_lock_irqsave(&s->lock, flags);
463 val = sccnxp_port_read(port, SCCNXP_SR_REG);
464 spin_unlock_irqrestore(&s->lock, flags);
466 return (val & SR_TXEMT) ? TIOCSER_TEMT : 0;
469 static void sccnxp_enable_ms(struct uart_port *port)
474 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)
476 struct sccnxp_port *s = dev_get_drvdata(port->dev);
479 if (!(s->flags & SCCNXP_HAVE_IO))
482 spin_lock_irqsave(&s->lock, flags);
484 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR);
485 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS);
487 spin_unlock_irqrestore(&s->lock, flags);
490 static unsigned int sccnxp_get_mctrl(struct uart_port *port)
494 struct sccnxp_port *s = dev_get_drvdata(port->dev);
495 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
497 if (!(s->flags & SCCNXP_HAVE_IO))
500 spin_lock_irqsave(&s->lock, flags);
502 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG);
504 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) {
505 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
508 mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0;
510 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) {
511 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
514 mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0;
516 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) {
517 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
520 mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0;
522 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) {
523 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
526 mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0;
529 spin_unlock_irqrestore(&s->lock, flags);
534 static void sccnxp_break_ctl(struct uart_port *port, int break_state)
536 struct sccnxp_port *s = dev_get_drvdata(port->dev);
539 spin_lock_irqsave(&s->lock, flags);
540 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ?
541 CR_CMD_START_BREAK : CR_CMD_STOP_BREAK);
542 spin_unlock_irqrestore(&s->lock, flags);
545 static void sccnxp_set_termios(struct uart_port *port,
546 struct ktermios *termios, struct ktermios *old)
548 struct sccnxp_port *s = dev_get_drvdata(port->dev);
553 spin_lock_irqsave(&s->lock, flags);
555 /* Mask termios capabilities we don't support */
556 termios->c_cflag &= ~CMSPAR;
558 /* Disable RX & TX, reset break condition, status and FIFOs */
559 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET |
560 CR_RX_DISABLE | CR_TX_DISABLE);
561 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
562 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
563 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
566 switch (termios->c_cflag & CSIZE) {
583 if (termios->c_cflag & PARENB) {
584 if (termios->c_cflag & PARODD)
590 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1;
592 /* Update desired format */
593 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1);
594 sccnxp_port_write(port, SCCNXP_MR_REG, mr1);
595 sccnxp_port_write(port, SCCNXP_MR_REG, mr2);
597 /* Set read status mask */
598 port->read_status_mask = SR_OVR;
599 if (termios->c_iflag & INPCK)
600 port->read_status_mask |= SR_PE | SR_FE;
601 if (termios->c_iflag & (BRKINT | PARMRK))
602 port->read_status_mask |= SR_BRK;
604 /* Set status ignore mask */
605 port->ignore_status_mask = 0;
606 if (termios->c_iflag & IGNBRK)
607 port->ignore_status_mask |= SR_BRK;
608 if (!(termios->c_cflag & CREAD))
609 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK;
612 baud = uart_get_baud_rate(port, termios, old, 50,
613 (s->flags & SCCNXP_HAVE_MR0) ?
615 baud = sccnxp_set_baud(port, baud);
617 /* Update timeout according to new baud rate */
618 uart_update_timeout(port, termios->c_cflag, baud);
620 /* Report actual baudrate back to core */
621 if (tty_termios_baud_rate(termios))
622 tty_termios_encode_baud_rate(termios, baud, baud);
625 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
627 spin_unlock_irqrestore(&s->lock, flags);
630 static int sccnxp_startup(struct uart_port *port)
632 struct sccnxp_port *s = dev_get_drvdata(port->dev);
635 spin_lock_irqsave(&s->lock, flags);
637 if (s->flags & SCCNXP_HAVE_IO) {
638 /* Outputs are controlled manually */
639 sccnxp_write(port, SCCNXP_OPCR_REG, 0);
642 /* Reset break condition, status and FIFOs */
643 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET);
644 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
645 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
646 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
649 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
651 /* Enable RX interrupt */
652 sccnxp_enable_irq(port, IMR_RXRDY);
654 s->opened[port->line] = 1;
656 spin_unlock_irqrestore(&s->lock, flags);
661 static void sccnxp_shutdown(struct uart_port *port)
663 struct sccnxp_port *s = dev_get_drvdata(port->dev);
666 spin_lock_irqsave(&s->lock, flags);
668 s->opened[port->line] = 0;
670 /* Disable interrupts */
671 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
673 /* Disable TX & RX */
674 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE);
676 /* Leave direction to input */
677 if (s->flags & SCCNXP_HAVE_IO)
678 sccnxp_set_bit(port, DIR_OP, 0);
680 spin_unlock_irqrestore(&s->lock, flags);
683 static const char *sccnxp_type(struct uart_port *port)
685 struct sccnxp_port *s = dev_get_drvdata(port->dev);
687 return (port->type == PORT_SC26XX) ? s->name : NULL;
690 static void sccnxp_release_port(struct uart_port *port)
695 static int sccnxp_request_port(struct uart_port *port)
701 static void sccnxp_config_port(struct uart_port *port, int flags)
703 if (flags & UART_CONFIG_TYPE)
704 port->type = PORT_SC26XX;
707 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)
709 if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX))
711 if (s->irq == port->irq)
717 static const struct uart_ops sccnxp_ops = {
718 .tx_empty = sccnxp_tx_empty,
719 .set_mctrl = sccnxp_set_mctrl,
720 .get_mctrl = sccnxp_get_mctrl,
721 .stop_tx = sccnxp_stop_tx,
722 .start_tx = sccnxp_start_tx,
723 .stop_rx = sccnxp_stop_rx,
724 .enable_ms = sccnxp_enable_ms,
725 .break_ctl = sccnxp_break_ctl,
726 .startup = sccnxp_startup,
727 .shutdown = sccnxp_shutdown,
728 .set_termios = sccnxp_set_termios,
730 .release_port = sccnxp_release_port,
731 .request_port = sccnxp_request_port,
732 .config_port = sccnxp_config_port,
733 .verify_port = sccnxp_verify_port,
736 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
737 static void sccnxp_console_putchar(struct uart_port *port, int c)
742 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) {
743 sccnxp_port_write(port, SCCNXP_THR_REG, c);
750 static void sccnxp_console_write(struct console *co, const char *c, unsigned n)
752 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
753 struct uart_port *port = &s->port[co->index];
756 spin_lock_irqsave(&s->lock, flags);
757 uart_console_write(port, c, n, sccnxp_console_putchar);
758 spin_unlock_irqrestore(&s->lock, flags);
761 static int sccnxp_console_setup(struct console *co, char *options)
763 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
764 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0];
765 int baud = 9600, bits = 8, parity = 'n', flow = 'n';
768 uart_parse_options(options, &baud, &parity, &bits, &flow);
770 return uart_set_options(port, co, baud, parity, bits, flow);
774 static int sccnxp_probe(struct platform_device *pdev)
776 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
777 int chiptype = pdev->id_entry->driver_data;
778 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev);
779 int i, ret, fifosize, freq_min, freq_max;
780 struct sccnxp_port *s;
781 void __iomem *membase;
784 dev_err(&pdev->dev, "Missing memory resource data\n");
785 return -EADDRNOTAVAIL;
788 dev_set_name(&pdev->dev, SCCNXP_NAME);
790 s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL);
792 dev_err(&pdev->dev, "Error allocating port structure\n");
795 platform_set_drvdata(pdev, s);
797 spin_lock_init(&s->lock);
799 /* Individual chip settings */
801 case SCCNXP_TYPE_SC2681:
804 s->freq_std = 3686400;
806 s->flags = SCCNXP_HAVE_IO;
811 case SCCNXP_TYPE_SC2691:
814 s->freq_std = 3686400;
821 case SCCNXP_TYPE_SC2692:
824 s->freq_std = 3686400;
826 s->flags = SCCNXP_HAVE_IO;
831 case SCCNXP_TYPE_SC2891:
834 s->freq_std = 3686400;
836 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0;
841 case SCCNXP_TYPE_SC2892:
844 s->freq_std = 3686400;
846 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0;
851 case SCCNXP_TYPE_SC28202:
854 s->freq_std = 14745600;
856 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0;
861 case SCCNXP_TYPE_SC68681:
864 s->freq_std = 3686400;
866 s->flags = SCCNXP_HAVE_IO;
871 case SCCNXP_TYPE_SC68692:
874 s->freq_std = 3686400;
876 s->flags = SCCNXP_HAVE_IO;
882 dev_err(&pdev->dev, "Unsupported chip type %i\n", chiptype);
889 "No platform data supplied, using defaults\n");
890 s->pdata.frequency = s->freq_std;
892 memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata));
894 if (pdata->poll_time_us) {
895 dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n",
896 pdata->poll_time_us);
901 s->irq = platform_get_irq(pdev, 0);
903 dev_err(&pdev->dev, "Missing irq resource data\n");
909 /* Check input frequency */
910 if ((s->pdata.frequency < freq_min) ||
911 (s->pdata.frequency > freq_max)) {
912 dev_err(&pdev->dev, "Frequency out of bounds\n");
917 membase = devm_request_and_ioremap(&pdev->dev, res);
919 dev_err(&pdev->dev, "Failed to ioremap\n");
924 s->uart.owner = THIS_MODULE;
925 s->uart.dev_name = "ttySC";
926 s->uart.major = SCCNXP_MAJOR;
927 s->uart.minor = SCCNXP_MINOR;
928 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
929 s->uart.cons = &s->console;
930 s->uart.cons->device = uart_console_device;
931 s->uart.cons->write = sccnxp_console_write;
932 s->uart.cons->setup = sccnxp_console_setup;
933 s->uart.cons->flags = CON_PRINTBUFFER;
934 s->uart.cons->index = -1;
935 s->uart.cons->data = s;
936 strcpy(s->uart.cons->name, "ttySC");
938 ret = uart_register_driver(&s->uart);
940 dev_err(&pdev->dev, "Registering UART driver failed\n");
944 for (i = 0; i < s->uart.nr; i++) {
946 s->port[i].dev = &pdev->dev;
947 s->port[i].irq = s->irq;
948 s->port[i].type = PORT_SC26XX;
949 s->port[i].fifosize = fifosize;
950 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;
951 s->port[i].iotype = UPIO_MEM;
952 s->port[i].mapbase = res->start;
953 s->port[i].membase = membase;
954 s->port[i].regshift = s->pdata.reg_shift;
955 s->port[i].uartclk = s->pdata.frequency;
956 s->port[i].ops = &sccnxp_ops;
957 uart_add_one_port(&s->uart, &s->port[i]);
958 /* Set direction to input */
959 if (s->flags & SCCNXP_HAVE_IO)
960 sccnxp_set_bit(&s->port[i], DIR_OP, 0);
963 /* Disable interrupts */
965 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0);
967 /* Board specific configure */
972 ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL,
974 IRQF_TRIGGER_FALLING |
976 dev_name(&pdev->dev), s);
980 dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq);
982 init_timer(&s->timer);
983 setup_timer(&s->timer, sccnxp_timer, (unsigned long)s);
984 mod_timer(&s->timer, jiffies +
985 usecs_to_jiffies(s->pdata.poll_time_us));
990 platform_set_drvdata(pdev, NULL);
995 static int sccnxp_remove(struct platform_device *pdev)
998 struct sccnxp_port *s = platform_get_drvdata(pdev);
1001 devm_free_irq(&pdev->dev, s->irq, s);
1003 del_timer_sync(&s->timer);
1005 for (i = 0; i < s->uart.nr; i++)
1006 uart_remove_one_port(&s->uart, &s->port[i]);
1008 uart_unregister_driver(&s->uart);
1009 platform_set_drvdata(pdev, NULL);
1017 static const struct platform_device_id sccnxp_id_table[] = {
1018 { "sc2681", SCCNXP_TYPE_SC2681 },
1019 { "sc2691", SCCNXP_TYPE_SC2691 },
1020 { "sc2692", SCCNXP_TYPE_SC2692 },
1021 { "sc2891", SCCNXP_TYPE_SC2891 },
1022 { "sc2892", SCCNXP_TYPE_SC2892 },
1023 { "sc28202", SCCNXP_TYPE_SC28202 },
1024 { "sc68681", SCCNXP_TYPE_SC68681 },
1025 { "sc68692", SCCNXP_TYPE_SC68692 },
1028 MODULE_DEVICE_TABLE(platform, sccnxp_id_table);
1030 static struct platform_driver sccnxp_uart_driver = {
1032 .name = SCCNXP_NAME,
1033 .owner = THIS_MODULE,
1035 .probe = sccnxp_probe,
1036 .remove = sccnxp_remove,
1037 .id_table = sccnxp_id_table,
1039 module_platform_driver(sccnxp_uart_driver);
1041 MODULE_LICENSE("GPL v2");
1042 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1043 MODULE_DESCRIPTION("SCCNXP serial driver");