drivers/tty/serial/pch_uart.c

   1 /*
   2  *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   3  *
   4  *This program is free software; you can redistribute it and/or modify
   5  *it under the terms of the GNU General Public License as published by
   6  *the Free Software Foundation; version 2 of the License.
   7  *
   8  *This program is distributed in the hope that it will be useful,
   9  *but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  *GNU General Public License for more details.
  12  *
  13  *You should have received a copy of the GNU General Public License
  14  *along with this program; if not, write to the Free Software
  15  *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17 #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  18 #define SUPPORT_SYSRQ
  19 #endif
  20 #include <linux/kernel.h>
  21 #include <linux/serial_reg.h>
  22 #include <linux/slab.h>
  23 #include <linux/module.h>
  24 #include <linux/pci.h>
  25 #include <linux/console.h>
  26 #include <linux/serial_core.h>
  27 #include <linux/tty.h>
  28 #include <linux/tty_flip.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/dmi.h>
  32 #include <linux/nmi.h>
  33 #include <linux/delay.h>
  34
  35 #include <linux/debugfs.h>
  36 #include <linux/dmaengine.h>
  37 #include <linux/pch_dma.h>
  38
  39 enum {
  40         PCH_UART_HANDLED_RX_INT_SHIFT,
  41         PCH_UART_HANDLED_TX_INT_SHIFT,
  42         PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
  43         PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
  44         PCH_UART_HANDLED_MS_INT_SHIFT,
  45         PCH_UART_HANDLED_LS_INT_SHIFT,
  46 };
  47
  48 enum {
  49         PCH_UART_8LINE,
  50         PCH_UART_2LINE,
  51 };
  52
  53 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
  54
  55 /* Set the max number of UART port
  56  * Intel EG20T PCH: 4 port
  57  * LAPIS Semiconductor ML7213 IOH: 3 port
  58  * LAPIS Semiconductor ML7223 IOH: 2 port
  59 */
  60 #define PCH_UART_NR     4
  61
  62 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
  63 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
  64 #define PCH_UART_HANDLED_RX_ERR_INT     (1<<((\
  65                                         PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
  66 #define PCH_UART_HANDLED_RX_TRG_INT     (1<<((\
  67                                         PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
  68 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
  69
  70 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
  71
  72 #define PCH_UART_RBR            0x00
  73 #define PCH_UART_THR            0x00
  74
  75 #define PCH_UART_IER_MASK       (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
  76                                 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
  77 #define PCH_UART_IER_ERBFI      0x00000001
  78 #define PCH_UART_IER_ETBEI      0x00000002
  79 #define PCH_UART_IER_ELSI       0x00000004
  80 #define PCH_UART_IER_EDSSI      0x00000008
  81
  82 #define PCH_UART_IIR_IP                 0x00000001
  83 #define PCH_UART_IIR_IID                0x00000006
  84 #define PCH_UART_IIR_MSI                0x00000000
  85 #define PCH_UART_IIR_TRI                0x00000002
  86 #define PCH_UART_IIR_RRI                0x00000004
  87 #define PCH_UART_IIR_REI                0x00000006
  88 #define PCH_UART_IIR_TOI                0x00000008
  89 #define PCH_UART_IIR_FIFO256            0x00000020
  90 #define PCH_UART_IIR_FIFO64             PCH_UART_IIR_FIFO256
  91 #define PCH_UART_IIR_FE                 0x000000C0
  92
  93 #define PCH_UART_FCR_FIFOE              0x00000001
  94 #define PCH_UART_FCR_RFR                0x00000002
  95 #define PCH_UART_FCR_TFR                0x00000004
  96 #define PCH_UART_FCR_DMS                0x00000008
  97 #define PCH_UART_FCR_FIFO256            0x00000020
  98 #define PCH_UART_FCR_RFTL               0x000000C0
  99
 100 #define PCH_UART_FCR_RFTL1              0x00000000
 101 #define PCH_UART_FCR_RFTL64             0x00000040
 102 #define PCH_UART_FCR_RFTL128            0x00000080
 103 #define PCH_UART_FCR_RFTL224            0x000000C0
 104 #define PCH_UART_FCR_RFTL16             PCH_UART_FCR_RFTL64
 105 #define PCH_UART_FCR_RFTL32             PCH_UART_FCR_RFTL128
 106 #define PCH_UART_FCR_RFTL56             PCH_UART_FCR_RFTL224
 107 #define PCH_UART_FCR_RFTL4              PCH_UART_FCR_RFTL64
 108 #define PCH_UART_FCR_RFTL8              PCH_UART_FCR_RFTL128
 109 #define PCH_UART_FCR_RFTL14             PCH_UART_FCR_RFTL224
 110 #define PCH_UART_FCR_RFTL_SHIFT         6
 111
 112 #define PCH_UART_LCR_WLS        0x00000003
 113 #define PCH_UART_LCR_STB        0x00000004
 114 #define PCH_UART_LCR_PEN        0x00000008
 115 #define PCH_UART_LCR_EPS        0x00000010
 116 #define PCH_UART_LCR_SP         0x00000020
 117 #define PCH_UART_LCR_SB         0x00000040
 118 #define PCH_UART_LCR_DLAB       0x00000080
 119 #define PCH_UART_LCR_NP         0x00000000
 120 #define PCH_UART_LCR_OP         PCH_UART_LCR_PEN
 121 #define PCH_UART_LCR_EP         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
 122 #define PCH_UART_LCR_1P         (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
 123 #define PCH_UART_LCR_0P         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
 124                                 PCH_UART_LCR_SP)
 125
 126 #define PCH_UART_LCR_5BIT       0x00000000
 127 #define PCH_UART_LCR_6BIT       0x00000001
 128 #define PCH_UART_LCR_7BIT       0x00000002
 129 #define PCH_UART_LCR_8BIT       0x00000003
 130
 131 #define PCH_UART_MCR_DTR        0x00000001
 132 #define PCH_UART_MCR_RTS        0x00000002
 133 #define PCH_UART_MCR_OUT        0x0000000C
 134 #define PCH_UART_MCR_LOOP       0x00000010
 135 #define PCH_UART_MCR_AFE        0x00000020
 136
 137 #define PCH_UART_LSR_DR         0x00000001
 138 #define PCH_UART_LSR_ERR        (1<<7)
 139
 140 #define PCH_UART_MSR_DCTS       0x00000001
 141 #define PCH_UART_MSR_DDSR       0x00000002
 142 #define PCH_UART_MSR_TERI       0x00000004
 143 #define PCH_UART_MSR_DDCD       0x00000008
 144 #define PCH_UART_MSR_CTS        0x00000010
 145 #define PCH_UART_MSR_DSR        0x00000020
 146 #define PCH_UART_MSR_RI         0x00000040
 147 #define PCH_UART_MSR_DCD        0x00000080
 148 #define PCH_UART_MSR_DELTA      (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
 149                                 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
 150
 151 #define PCH_UART_DLL            0x00
 152 #define PCH_UART_DLM            0x01
 153
 154 #define PCH_UART_BRCSR          0x0E
 155
 156 #define PCH_UART_IID_RLS        (PCH_UART_IIR_REI)
 157 #define PCH_UART_IID_RDR        (PCH_UART_IIR_RRI)
 158 #define PCH_UART_IID_RDR_TO     (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
 159 #define PCH_UART_IID_THRE       (PCH_UART_IIR_TRI)
 160 #define PCH_UART_IID_MS         (PCH_UART_IIR_MSI)
 161
 162 #define PCH_UART_HAL_PARITY_NONE        (PCH_UART_LCR_NP)
 163 #define PCH_UART_HAL_PARITY_ODD         (PCH_UART_LCR_OP)
 164 #define PCH_UART_HAL_PARITY_EVEN        (PCH_UART_LCR_EP)
 165 #define PCH_UART_HAL_PARITY_FIX1        (PCH_UART_LCR_1P)
 166 #define PCH_UART_HAL_PARITY_FIX0        (PCH_UART_LCR_0P)
 167 #define PCH_UART_HAL_5BIT               (PCH_UART_LCR_5BIT)
 168 #define PCH_UART_HAL_6BIT               (PCH_UART_LCR_6BIT)
 169 #define PCH_UART_HAL_7BIT               (PCH_UART_LCR_7BIT)
 170 #define PCH_UART_HAL_8BIT               (PCH_UART_LCR_8BIT)
 171 #define PCH_UART_HAL_STB1               0
 172 #define PCH_UART_HAL_STB2               (PCH_UART_LCR_STB)
 173
 174 #define PCH_UART_HAL_CLR_TX_FIFO        (PCH_UART_FCR_TFR)
 175 #define PCH_UART_HAL_CLR_RX_FIFO        (PCH_UART_FCR_RFR)
 176 #define PCH_UART_HAL_CLR_ALL_FIFO       (PCH_UART_HAL_CLR_TX_FIFO | \
 177                                         PCH_UART_HAL_CLR_RX_FIFO)
 178
 179 #define PCH_UART_HAL_DMA_MODE0          0
 180 #define PCH_UART_HAL_FIFO_DIS           0
 181 #define PCH_UART_HAL_FIFO16             (PCH_UART_FCR_FIFOE)
 182 #define PCH_UART_HAL_FIFO256            (PCH_UART_FCR_FIFOE | \
 183                                         PCH_UART_FCR_FIFO256)
 184 #define PCH_UART_HAL_FIFO64             (PCH_UART_HAL_FIFO256)
 185 #define PCH_UART_HAL_TRIGGER1           (PCH_UART_FCR_RFTL1)
 186 #define PCH_UART_HAL_TRIGGER64          (PCH_UART_FCR_RFTL64)
 187 #define PCH_UART_HAL_TRIGGER128         (PCH_UART_FCR_RFTL128)
 188 #define PCH_UART_HAL_TRIGGER224         (PCH_UART_FCR_RFTL224)
 189 #define PCH_UART_HAL_TRIGGER16          (PCH_UART_FCR_RFTL16)
 190 #define PCH_UART_HAL_TRIGGER32          (PCH_UART_FCR_RFTL32)
 191 #define PCH_UART_HAL_TRIGGER56          (PCH_UART_FCR_RFTL56)
 192 #define PCH_UART_HAL_TRIGGER4           (PCH_UART_FCR_RFTL4)
 193 #define PCH_UART_HAL_TRIGGER8           (PCH_UART_FCR_RFTL8)
 194 #define PCH_UART_HAL_TRIGGER14          (PCH_UART_FCR_RFTL14)
 195 #define PCH_UART_HAL_TRIGGER_L          (PCH_UART_FCR_RFTL64)
 196 #define PCH_UART_HAL_TRIGGER_M          (PCH_UART_FCR_RFTL128)
 197 #define PCH_UART_HAL_TRIGGER_H          (PCH_UART_FCR_RFTL224)
 198
 199 #define PCH_UART_HAL_RX_INT             (PCH_UART_IER_ERBFI)
 200 #define PCH_UART_HAL_TX_INT             (PCH_UART_IER_ETBEI)
 201 #define PCH_UART_HAL_RX_ERR_INT         (PCH_UART_IER_ELSI)
 202 #define PCH_UART_HAL_MS_INT             (PCH_UART_IER_EDSSI)
 203 #define PCH_UART_HAL_ALL_INT            (PCH_UART_IER_MASK)
 204
 205 #define PCH_UART_HAL_DTR                (PCH_UART_MCR_DTR)
 206 #define PCH_UART_HAL_RTS                (PCH_UART_MCR_RTS)
 207 #define PCH_UART_HAL_OUT                (PCH_UART_MCR_OUT)
 208 #define PCH_UART_HAL_LOOP               (PCH_UART_MCR_LOOP)
 209 #define PCH_UART_HAL_AFE                (PCH_UART_MCR_AFE)
 210
 211 #define PCI_VENDOR_ID_ROHM              0x10DB
 212
 213 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 214
 215 #define DEFAULT_UARTCLK   1843200 /*   1.8432 MHz */
 216 #define CMITC_UARTCLK   192000000 /* 192.0000 MHz */
 217 #define FRI2_64_UARTCLK  64000000 /*  64.0000 MHz */
 218 #define FRI2_48_UARTCLK  48000000 /*  48.0000 MHz */
 219 #define NTC1_UARTCLK     64000000 /*  64.0000 MHz */
 220
 221 struct pch_uart_buffer {
 222         unsigned char *buf;
 223         int size;
 224 };
 225
 226 struct eg20t_port {
 227         struct uart_port port;
 228         int port_type;
 229         void __iomem *membase;
 230         resource_size_t mapbase;
 231         unsigned int iobase;
 232         struct pci_dev *pdev;
 233         int fifo_size;
 234         int uartclk;
 235         int start_tx;
 236         int start_rx;
 237         int tx_empty;
 238         int trigger;
 239         int trigger_level;
 240         struct pch_uart_buffer rxbuf;
 241         unsigned int dmsr;
 242         unsigned int fcr;
 243         unsigned int mcr;
 244         unsigned int use_dma;
 245         struct dma_async_tx_descriptor  *desc_tx;
 246         struct dma_async_tx_descriptor  *desc_rx;
 247         struct pch_dma_slave            param_tx;
 248         struct pch_dma_slave            param_rx;
 249         struct dma_chan                 *chan_tx;
 250         struct dma_chan                 *chan_rx;
 251         struct scatterlist              *sg_tx_p;
 252         int                             nent;
 253         struct scatterlist              sg_rx;
 254         int                             tx_dma_use;
 255         void                            *rx_buf_virt;
 256         dma_addr_t                      rx_buf_dma;
 257
 258         struct dentry   *debugfs;
 259
 260         /* protect the eg20t_port private structure and io access to membase */
 261         spinlock_t lock;
 262 };
 263
 264 /**
 265  * struct pch_uart_driver_data - private data structure for UART-DMA
 266  * @port_type:                  The number of DMA channel
 267  * @line_no:                    UART port line number (0, 1, 2...)
 268  */
 269 struct pch_uart_driver_data {
 270         int port_type;
 271         int line_no;
 272 };
 273
 274 enum pch_uart_num_t {
 275         pch_et20t_uart0 = 0,
 276         pch_et20t_uart1,
 277         pch_et20t_uart2,
 278         pch_et20t_uart3,
 279         pch_ml7213_uart0,
 280         pch_ml7213_uart1,
 281         pch_ml7213_uart2,
 282         pch_ml7223_uart0,
 283         pch_ml7223_uart1,
 284         pch_ml7831_uart0,
 285         pch_ml7831_uart1,
 286 };
 287
 288 static struct pch_uart_driver_data drv_dat[] = {
 289         [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
 290         [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
 291         [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
 292         [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
 293         [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
 294         [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
 295         [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
 296         [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
 297         [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
 298         [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
 299         [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
 300 };
 301
 302 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
 303 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
 304 #endif
 305 static unsigned int default_baud = 9600;
 306 static unsigned int user_uartclk = 0;
 307 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
 308 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
 309 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
 310 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
 311
 312 #ifdef CONFIG_DEBUG_FS
 313
 314 #define PCH_REGS_BUFSIZE        1024
 315
 316
 317 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
 318                                 size_t count, loff_t *ppos)
 319 {
 320         struct eg20t_port *priv = file->private_data;
 321         char *buf;
 322         u32 len = 0;
 323         ssize_t ret;
 324         unsigned char lcr;
 325
 326         buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
 327         if (!buf)
 328                 return 0;
 329
 330         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 331                         "PCH EG20T port[%d] regs:\n", priv->port.line);
 332
 333         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 334                         "=================================\n");
 335         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 336                         "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
 337         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 338                         "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
 339         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 340                         "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
 341         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 342                         "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
 343         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 344                         "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
 345         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 346                         "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
 347         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 348                         "BRCSR: \t0x%02x\n",
 349                         ioread8(priv->membase + PCH_UART_BRCSR));
 350
 351         lcr = ioread8(priv->membase + UART_LCR);
 352         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 353         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 354                         "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
 355         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 356                         "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
 357         iowrite8(lcr, priv->membase + UART_LCR);
 358
 359         if (len > PCH_REGS_BUFSIZE)
 360                 len = PCH_REGS_BUFSIZE;
 361
 362         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 363         kfree(buf);
 364         return ret;
 365 }
 366
 367 static const struct file_operations port_regs_ops = {
 368         .owner          = THIS_MODULE,
 369         .open           = simple_open,
 370         .read           = port_show_regs,
 371         .llseek         = default_llseek,
 372 };
 373 #endif  /* CONFIG_DEBUG_FS */
 374
 375 /* Return UART clock, checking for board specific clocks. */
 376 static int pch_uart_get_uartclk(void)
 377 {
 378         const char *cmp;
 379
 380         if (user_uartclk)
 381                 return user_uartclk;
 382
 383         cmp = dmi_get_system_info(DMI_BOARD_NAME);
 384         if (cmp && strstr(cmp, "CM-iTC"))
 385                 return CMITC_UARTCLK;
 386
 387         cmp = dmi_get_system_info(DMI_BIOS_VERSION);
 388         if (cmp && strnstr(cmp, "FRI2", 4))
 389                 return FRI2_64_UARTCLK;
 390
 391         cmp = dmi_get_system_info(DMI_PRODUCT_NAME);
 392         if (cmp && strstr(cmp, "Fish River Island II"))
 393                 return FRI2_48_UARTCLK;
 394
 395         /* Kontron COMe-mTT10 (nanoETXexpress-TT) */
 396         cmp = dmi_get_system_info(DMI_BOARD_NAME);
 397         if (cmp && (strstr(cmp, "COMe-mTT") ||
 398                     strstr(cmp, "nanoETXexpress-TT")))
 399                 return NTC1_UARTCLK;
 400
 401         return DEFAULT_UARTCLK;
 402 }
 403
 404 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
 405                                           unsigned int flag)
 406 {
 407         u8 ier = ioread8(priv->membase + UART_IER);
 408         ier |= flag & PCH_UART_IER_MASK;
 409         iowrite8(ier, priv->membase + UART_IER);
 410 }
 411
 412 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
 413                                            unsigned int flag)
 414 {
 415         u8 ier = ioread8(priv->membase + UART_IER);
 416         ier &= ~(flag & PCH_UART_IER_MASK);
 417         iowrite8(ier, priv->membase + UART_IER);
 418 }
 419
 420 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
 421                                  unsigned int parity, unsigned int bits,
 422                                  unsigned int stb)
 423 {
 424         unsigned int dll, dlm, lcr;
 425         int div;
 426
 427         div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
 428         if (div < 0 || USHRT_MAX <= div) {
 429                 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
 430                 return -EINVAL;
 431         }
 432
 433         dll = (unsigned int)div & 0x00FFU;
 434         dlm = ((unsigned int)div >> 8) & 0x00FFU;
 435
 436         if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
 437                 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
 438                 return -EINVAL;
 439         }
 440
 441         if (bits & ~PCH_UART_LCR_WLS) {
 442                 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
 443                 return -EINVAL;
 444         }
 445
 446         if (stb & ~PCH_UART_LCR_STB) {
 447                 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
 448                 return -EINVAL;
 449         }
 450
 451         lcr = parity;
 452         lcr |= bits;
 453         lcr |= stb;
 454
 455         dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
 456                  __func__, baud, div, lcr, jiffies);
 457         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 458         iowrite8(dll, priv->membase + PCH_UART_DLL);
 459         iowrite8(dlm, priv->membase + PCH_UART_DLM);
 460         iowrite8(lcr, priv->membase + UART_LCR);
 461
 462         return 0;
 463 }
 464
 465 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
 466                                     unsigned int flag)
 467 {
 468         if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
 469                 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
 470                         __func__, flag);
 471                 return -EINVAL;
 472         }
 473
 474         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
 475         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
 476                  priv->membase + UART_FCR);
 477         iowrite8(priv->fcr, priv->membase + UART_FCR);
 478
 479         return 0;
 480 }
 481
 482 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
 483                                  unsigned int dmamode,
 484                                  unsigned int fifo_size, unsigned int trigger)
 485 {
 486         u8 fcr;
 487
 488         if (dmamode & ~PCH_UART_FCR_DMS) {
 489                 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
 490                         __func__, dmamode);
 491                 return -EINVAL;
 492         }
 493
 494         if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
 495                 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
 496                         __func__, fifo_size);
 497                 return -EINVAL;
 498         }
 499
 500         if (trigger & ~PCH_UART_FCR_RFTL) {
 501                 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
 502                         __func__, trigger);
 503                 return -EINVAL;
 504         }
 505
 506         switch (priv->fifo_size) {
 507         case 256:
 508                 priv->trigger_level =
 509                     trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 510                 break;
 511         case 64:
 512                 priv->trigger_level =
 513                     trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 514                 break;
 515         case 16:
 516                 priv->trigger_level =
 517                     trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 518                 break;
 519         default:
 520                 priv->trigger_level =
 521                     trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 522                 break;
 523         }
 524         fcr =
 525             dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
 526         iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
 527         iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
 528                  priv->membase + UART_FCR);
 529         iowrite8(fcr, priv->membase + UART_FCR);
 530         priv->fcr = fcr;
 531
 532         return 0;
 533 }
 534
 535 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
 536 {
 537         unsigned int msr = ioread8(priv->membase + UART_MSR);
 538         priv->dmsr = msr & PCH_UART_MSR_DELTA;
 539         return (u8)msr;
 540 }
 541
 542 static void pch_uart_hal_write(struct eg20t_port *priv,
 543                               const unsigned char *buf, int tx_size)
 544 {
 545         int i;
 546         unsigned int thr;
 547
 548         for (i = 0; i < tx_size;) {
 549                 thr = buf[i++];
 550                 iowrite8(thr, priv->membase + PCH_UART_THR);
 551         }
 552 }
 553
 554 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
 555                              int rx_size)
 556 {
 557         int i;
 558         u8 rbr, lsr;
 559         struct uart_port *port = &priv->port;
 560
 561         lsr = ioread8(priv->membase + UART_LSR);
 562         for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
 563              i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
 564              lsr = ioread8(priv->membase + UART_LSR)) {
 565                 rbr = ioread8(priv->membase + PCH_UART_RBR);
 566
 567                 if (lsr & UART_LSR_BI) {
 568                         port->icount.brk++;
 569                         if (uart_handle_break(port))
 570                                 continue;
 571                 }
 572 #ifdef SUPPORT_SYSRQ
 573                 if (port->sysrq) {
 574                         if (uart_handle_sysrq_char(port, rbr))
 575                                 continue;
 576                 }
 577 #endif
 578
 579                 buf[i++] = rbr;
 580         }
 581         return i;
 582 }
 583
 584 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
 585 {
 586         return ioread8(priv->membase + UART_IIR) &\
 587                       (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
 588 }
 589
 590 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
 591 {
 592         return ioread8(priv->membase + UART_LSR);
 593 }
 594
 595 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
 596 {
 597         unsigned int lcr;
 598
 599         lcr = ioread8(priv->membase + UART_LCR);
 600         if (on)
 601                 lcr |= PCH_UART_LCR_SB;
 602         else
 603                 lcr &= ~PCH_UART_LCR_SB;
 604
 605         iowrite8(lcr, priv->membase + UART_LCR);
 606 }
 607
 608 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
 609                    int size)
 610 {
 611         struct uart_port *port = &priv->port;
 612         struct tty_port *tport = &port->state->port;
 613
 614         tty_insert_flip_string(tport, buf, size);
 615         tty_flip_buffer_push(tport);
 616
 617         return 0;
 618 }
 619
 620 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
 621 {
 622         int ret = 0;
 623         struct uart_port *port = &priv->port;
 624
 625         if (port->x_char) {
 626                 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
 627                         __func__, port->x_char, jiffies);
 628                 buf[0] = port->x_char;
 629                 port->x_char = 0;
 630                 ret = 1;
 631         }
 632
 633         return ret;
 634 }
 635
 636 static int dma_push_rx(struct eg20t_port *priv, int size)
 637 {
 638         struct tty_struct *tty;
 639         int room;
 640         struct uart_port *port = &priv->port;
 641         struct tty_port *tport = &port->state->port;
 642
 643         port = &priv->port;
 644         tty = tty_port_tty_get(tport);
 645         if (!tty) {
 646                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 647                 return 0;
 648         }
 649
 650         room = tty_buffer_request_room(tport, size);
 651
 652         if (room < size)
 653                 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
 654                          size - room);
 655         if (!room)
 656                 return room;
 657
 658         tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
 659
 660         port->icount.rx += room;
 661         tty_kref_put(tty);
 662
 663         return room;
 664 }
 665
 666 static void pch_free_dma(struct uart_port *port)
 667 {
 668         struct eg20t_port *priv;
 669         priv = container_of(port, struct eg20t_port, port);
 670
 671         if (priv->chan_tx) {
 672                 dma_release_channel(priv->chan_tx);
 673                 priv->chan_tx = NULL;
 674         }
 675         if (priv->chan_rx) {
 676                 dma_release_channel(priv->chan_rx);
 677                 priv->chan_rx = NULL;
 678         }
 679
 680         if (priv->rx_buf_dma) {
 681                 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
 682                                   priv->rx_buf_dma);
 683                 priv->rx_buf_virt = NULL;
 684                 priv->rx_buf_dma = 0;
 685         }
 686
 687         return;
 688 }
 689
 690 static bool filter(struct dma_chan *chan, void *slave)
 691 {
 692         struct pch_dma_slave *param = slave;
 693
 694         if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
 695                                                   chan->device->dev)) {
 696                 chan->private = param;
 697                 return true;
 698         } else {
 699                 return false;
 700         }
 701 }
 702
 703 static void pch_request_dma(struct uart_port *port)
 704 {
 705         dma_cap_mask_t mask;
 706         struct dma_chan *chan;
 707         struct pci_dev *dma_dev;
 708         struct pch_dma_slave *param;
 709         struct eg20t_port *priv =
 710                                 container_of(port, struct eg20t_port, port);
 711         dma_cap_zero(mask);
 712         dma_cap_set(DMA_SLAVE, mask);
 713
 714         dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number,
 715                                        PCI_DEVFN(0xa, 0)); /* Get DMA's dev
 716                                                                 information */
 717         /* Set Tx DMA */
 718         param = &priv->param_tx;
 719         param->dma_dev = &dma_dev->dev;
 720         param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
 721
 722         param->tx_reg = port->mapbase + UART_TX;
 723         chan = dma_request_channel(mask, filter, param);
 724         if (!chan) {
 725                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
 726                         __func__);
 727                 return;
 728         }
 729         priv->chan_tx = chan;
 730
 731         /* Set Rx DMA */
 732         param = &priv->param_rx;
 733         param->dma_dev = &dma_dev->dev;
 734         param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
 735
 736         param->rx_reg = port->mapbase + UART_RX;
 737         chan = dma_request_channel(mask, filter, param);
 738         if (!chan) {
 739                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
 740                         __func__);
 741                 dma_release_channel(priv->chan_tx);
 742                 priv->chan_tx = NULL;
 743                 return;
 744         }
 745
 746         /* Get Consistent memory for DMA */
 747         priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
 748                                     &priv->rx_buf_dma, GFP_KERNEL);
 749         priv->chan_rx = chan;
 750 }
 751
 752 static void pch_dma_rx_complete(void *arg)
 753 {
 754         struct eg20t_port *priv = arg;
 755         struct uart_port *port = &priv->port;
 756         int count;
 757
 758         dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
 759         count = dma_push_rx(priv, priv->trigger_level);
 760         if (count)
 761                 tty_flip_buffer_push(&port->state->port);
 762         async_tx_ack(priv->desc_rx);
 763         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
 764                                             PCH_UART_HAL_RX_ERR_INT);
 765 }
 766
 767 static void pch_dma_tx_complete(void *arg)
 768 {
 769         struct eg20t_port *priv = arg;
 770         struct uart_port *port = &priv->port;
 771         struct circ_buf *xmit = &port->state->xmit;
 772         struct scatterlist *sg = priv->sg_tx_p;
 773         int i;
 774
 775         for (i = 0; i < priv->nent; i++, sg++) {
 776                 xmit->tail += sg_dma_len(sg);
 777                 port->icount.tx += sg_dma_len(sg);
 778         }
 779         xmit->tail &= UART_XMIT_SIZE - 1;
 780         async_tx_ack(priv->desc_tx);
 781         dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
 782         priv->tx_dma_use = 0;
 783         priv->nent = 0;
 784         kfree(priv->sg_tx_p);
 785         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
 786 }
 787
 788 static int pop_tx(struct eg20t_port *priv, int size)
 789 {
 790         int count = 0;
 791         struct uart_port *port = &priv->port;
 792         struct circ_buf *xmit = &port->state->xmit;
 793
 794         if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
 795                 goto pop_tx_end;
 796
 797         do {
 798                 int cnt_to_end =
 799                     CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 800                 int sz = min(size - count, cnt_to_end);
 801                 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
 802                 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
 803                 count += sz;
 804         } while (!uart_circ_empty(xmit) && count < size);
 805
 806 pop_tx_end:
 807         dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
 808                  count, size - count, jiffies);
 809
 810         return count;
 811 }
 812
 813 static int handle_rx_to(struct eg20t_port *priv)
 814 {
 815         struct pch_uart_buffer *buf;
 816         int rx_size;
 817         int ret;
 818         if (!priv->start_rx) {
 819                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
 820                                                      PCH_UART_HAL_RX_ERR_INT);
 821                 return 0;
 822         }
 823         buf = &priv->rxbuf;
 824         do {
 825                 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
 826                 ret = push_rx(priv, buf->buf, rx_size);
 827                 if (ret)
 828                         return 0;
 829         } while (rx_size == buf->size);
 830
 831         return PCH_UART_HANDLED_RX_INT;
 832 }
 833
 834 static int handle_rx(struct eg20t_port *priv)
 835 {
 836         return handle_rx_to(priv);
 837 }
 838
 839 static int dma_handle_rx(struct eg20t_port *priv)
 840 {
 841         struct uart_port *port = &priv->port;
 842         struct dma_async_tx_descriptor *desc;
 843         struct scatterlist *sg;
 844
 845         priv = container_of(port, struct eg20t_port, port);
 846         sg = &priv->sg_rx;
 847
 848         sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
 849
 850         sg_dma_len(sg) = priv->trigger_level;
 851
 852         sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
 853                      sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
 854                      ~PAGE_MASK);
 855
 856         sg_dma_address(sg) = priv->rx_buf_dma;
 857
 858         desc = dmaengine_prep_slave_sg(priv->chan_rx,
 859                         sg, 1, DMA_DEV_TO_MEM,
 860                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 861
 862         if (!desc)
 863                 return 0;
 864
 865         priv->desc_rx = desc;
 866         desc->callback = pch_dma_rx_complete;
 867         desc->callback_param = priv;
 868         desc->tx_submit(desc);
 869         dma_async_issue_pending(priv->chan_rx);
 870
 871         return PCH_UART_HANDLED_RX_INT;
 872 }
 873
 874 static unsigned int handle_tx(struct eg20t_port *priv)
 875 {
 876         struct uart_port *port = &priv->port;
 877         struct circ_buf *xmit = &port->state->xmit;
 878         int fifo_size;
 879         int tx_size;
 880         int size;
 881         int tx_empty;
 882
 883         if (!priv->start_tx) {
 884                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 885                         __func__, jiffies);
 886                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 887                 priv->tx_empty = 1;
 888                 return 0;
 889         }
 890
 891         fifo_size = max(priv->fifo_size, 1);
 892         tx_empty = 1;
 893         if (pop_tx_x(priv, xmit->buf)) {
 894                 pch_uart_hal_write(priv, xmit->buf, 1);
 895                 port->icount.tx++;
 896                 tx_empty = 0;
 897                 fifo_size--;
 898         }
 899         size = min(xmit->head - xmit->tail, fifo_size);
 900         if (size < 0)
 901                 size = fifo_size;
 902
 903         tx_size = pop_tx(priv, size);
 904         if (tx_size > 0) {
 905                 port->icount.tx += tx_size;
 906                 tx_empty = 0;
 907         }
 908
 909         priv->tx_empty = tx_empty;
 910
 911         if (tx_empty) {
 912                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 913                 uart_write_wakeup(port);
 914         }
 915
 916         return PCH_UART_HANDLED_TX_INT;
 917 }
 918
 919 static unsigned int dma_handle_tx(struct eg20t_port *priv)
 920 {
 921         struct uart_port *port = &priv->port;
 922         struct circ_buf *xmit = &port->state->xmit;
 923         struct scatterlist *sg;
 924         int nent;
 925         int fifo_size;
 926         int tx_empty;
 927         struct dma_async_tx_descriptor *desc;
 928         int num;
 929         int i;
 930         int bytes;
 931         int size;
 932         int rem;
 933
 934         if (!priv->start_tx) {
 935                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 936                         __func__, jiffies);
 937                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 938                 priv->tx_empty = 1;
 939                 return 0;
 940         }
 941
 942         if (priv->tx_dma_use) {
 943                 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
 944                         __func__, jiffies);
 945                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 946                 priv->tx_empty = 1;
 947                 return 0;
 948         }
 949
 950         fifo_size = max(priv->fifo_size, 1);
 951         tx_empty = 1;
 952         if (pop_tx_x(priv, xmit->buf)) {
 953                 pch_uart_hal_write(priv, xmit->buf, 1);
 954                 port->icount.tx++;
 955                 tx_empty = 0;
 956                 fifo_size--;
 957         }
 958
 959         bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
 960                              UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
 961                              xmit->tail, UART_XMIT_SIZE));
 962         if (!bytes) {
 963                 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
 964                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 965                 uart_write_wakeup(port);
 966                 return 0;
 967         }
 968
 969         if (bytes > fifo_size) {
 970                 num = bytes / fifo_size + 1;
 971                 size = fifo_size;
 972                 rem = bytes % fifo_size;
 973         } else {
 974                 num = 1;
 975                 size = bytes;
 976                 rem = bytes;
 977         }
 978
 979         dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
 980                 __func__, num, size, rem);
 981
 982         priv->tx_dma_use = 1;
 983
 984         priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
 985         if (!priv->sg_tx_p) {
 986                 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
 987                 return 0;
 988         }
 989
 990         sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
 991         sg = priv->sg_tx_p;
 992
 993         for (i = 0; i < num; i++, sg++) {
 994                 if (i == (num - 1))
 995                         sg_set_page(sg, virt_to_page(xmit->buf),
 996                                     rem, fifo_size * i);
 997                 else
 998                         sg_set_page(sg, virt_to_page(xmit->buf),
 999                                     size, fifo_size * i);
1000         }
1001
1002         sg = priv->sg_tx_p;
1003         nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
1004         if (!nent) {
1005                 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
1006                 return 0;
1007         }
1008         priv->nent = nent;
1009
1010         for (i = 0; i < nent; i++, sg++) {
1011                 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1012                               fifo_size * i;
1013                 sg_dma_address(sg) = (sg_dma_address(sg) &
1014                                     ~(UART_XMIT_SIZE - 1)) + sg->offset;
1015                 if (i == (nent - 1))
1016                         sg_dma_len(sg) = rem;
1017                 else
1018                         sg_dma_len(sg) = size;
1019         }
1020
1021         desc = dmaengine_prep_slave_sg(priv->chan_tx,
1022                                         priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1023                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1024         if (!desc) {
1025                 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
1026                         __func__);
1027                 return 0;
1028         }
1029         dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1030         priv->desc_tx = desc;
1031         desc->callback = pch_dma_tx_complete;
1032         desc->callback_param = priv;
1033
1034         desc->tx_submit(desc);
1035
1036         dma_async_issue_pending(priv->chan_tx);
1037
1038         return PCH_UART_HANDLED_TX_INT;
1039 }
1040
1041 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1042 {
1043         struct uart_port *port = &priv->port;
1044         struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1045         char   *error_msg[5] = {};
1046         int    i = 0;
1047
1048         if (lsr & PCH_UART_LSR_ERR)
1049                 error_msg[i++] = "Error data in FIFO\n";
1050
1051         if (lsr & UART_LSR_FE) {
1052                 port->icount.frame++;
1053                 error_msg[i++] = "  Framing Error\n";
1054         }
1055
1056         if (lsr & UART_LSR_PE) {
1057                 port->icount.parity++;
1058                 error_msg[i++] = "  Parity Error\n";
1059         }
1060
1061         if (lsr & UART_LSR_OE) {
1062                 port->icount.overrun++;
1063                 error_msg[i++] = "  Overrun Error\n";
1064         }
1065
1066         if (tty == NULL) {
1067                 for (i = 0; error_msg[i] != NULL; i++)
1068                         dev_err(&priv->pdev->dev, error_msg[i]);
1069         }
1070 }
1071
1072 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1073 {
1074         struct eg20t_port *priv = dev_id;
1075         unsigned int handled;
1076         u8 lsr;
1077         int ret = 0;
1078         unsigned char iid;
1079         unsigned long flags;
1080         int next = 1;
1081         u8 msr;
1082
1083         spin_lock_irqsave(&priv->lock, flags);
1084         handled = 0;
1085         while (next) {
1086                 iid = pch_uart_hal_get_iid(priv);
1087                 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1088                         break;
1089                 switch (iid) {
1090                 case PCH_UART_IID_RLS:  /* Receiver Line Status */
1091                         lsr = pch_uart_hal_get_line_status(priv);
1092                         if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1093                                                 UART_LSR_PE | UART_LSR_OE)) {
1094                                 pch_uart_err_ir(priv, lsr);
1095                                 ret = PCH_UART_HANDLED_RX_ERR_INT;
1096                         } else {
1097                                 ret = PCH_UART_HANDLED_LS_INT;
1098                         }
1099                         break;
1100                 case PCH_UART_IID_RDR:  /* Received Data Ready */
1101                         if (priv->use_dma) {
1102                                 pch_uart_hal_disable_interrupt(priv,
1103                                                 PCH_UART_HAL_RX_INT |
1104                                                 PCH_UART_HAL_RX_ERR_INT);
1105                                 ret = dma_handle_rx(priv);
1106                                 if (!ret)
1107                                         pch_uart_hal_enable_interrupt(priv,
1108                                                 PCH_UART_HAL_RX_INT |
1109                                                 PCH_UART_HAL_RX_ERR_INT);
1110                         } else {
1111                                 ret = handle_rx(priv);
1112                         }
1113                         break;
1114                 case PCH_UART_IID_RDR_TO:       /* Received Data Ready
1115                                                    (FIFO Timeout) */
1116                         ret = handle_rx_to(priv);
1117                         break;
1118                 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1119                                                    Empty */
1120                         if (priv->use_dma)
1121                                 ret = dma_handle_tx(priv);
1122                         else
1123                                 ret = handle_tx(priv);
1124                         break;
1125                 case PCH_UART_IID_MS:   /* Modem Status */
1126                         msr = pch_uart_hal_get_modem(priv);
1127                         next = 0; /* MS ir prioirty is the lowest. So, MS ir
1128                                      means final interrupt */
1129                         if ((msr & UART_MSR_ANY_DELTA) == 0)
1130                                 break;
1131                         ret |= PCH_UART_HANDLED_MS_INT;
1132                         break;
1133                 default:        /* Never junp to this label */
1134                         dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1135                                 iid, jiffies);
1136                         ret = -1;
1137                         next = 0;
1138                         break;
1139                 }
1140                 handled |= (unsigned int)ret;
1141         }
1142
1143         spin_unlock_irqrestore(&priv->lock, flags);
1144         return IRQ_RETVAL(handled);
1145 }
1146
1147 /* This function tests whether the transmitter fifo and shifter for the port
1148                                                 described by 'port' is empty. */
1149 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1150 {
1151         struct eg20t_port *priv;
1152
1153         priv = container_of(port, struct eg20t_port, port);
1154         if (priv->tx_empty)
1155                 return TIOCSER_TEMT;
1156         else
1157                 return 0;
1158 }
1159
1160 /* Returns the current state of modem control inputs. */
1161 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1162 {
1163         struct eg20t_port *priv;
1164         u8 modem;
1165         unsigned int ret = 0;
1166
1167         priv = container_of(port, struct eg20t_port, port);
1168         modem = pch_uart_hal_get_modem(priv);
1169
1170         if (modem & UART_MSR_DCD)
1171                 ret |= TIOCM_CAR;
1172
1173         if (modem & UART_MSR_RI)
1174                 ret |= TIOCM_RNG;
1175
1176         if (modem & UART_MSR_DSR)
1177                 ret |= TIOCM_DSR;
1178
1179         if (modem & UART_MSR_CTS)
1180                 ret |= TIOCM_CTS;
1181
1182         return ret;
1183 }
1184
1185 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1186 {
1187         u32 mcr = 0;
1188         struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1189
1190         if (mctrl & TIOCM_DTR)
1191                 mcr |= UART_MCR_DTR;
1192         if (mctrl & TIOCM_RTS)
1193                 mcr |= UART_MCR_RTS;
1194         if (mctrl & TIOCM_LOOP)
1195                 mcr |= UART_MCR_LOOP;
1196
1197         if (priv->mcr & UART_MCR_AFE)
1198                 mcr |= UART_MCR_AFE;
1199
1200         if (mctrl)
1201                 iowrite8(mcr, priv->membase + UART_MCR);
1202 }
1203
1204 static void pch_uart_stop_tx(struct uart_port *port)
1205 {
1206         struct eg20t_port *priv;
1207         priv = container_of(port, struct eg20t_port, port);
1208         priv->start_tx = 0;
1209         priv->tx_dma_use = 0;
1210 }
1211
1212 static void pch_uart_start_tx(struct uart_port *port)
1213 {
1214         struct eg20t_port *priv;
1215
1216         priv = container_of(port, struct eg20t_port, port);
1217
1218         if (priv->use_dma) {
1219                 if (priv->tx_dma_use) {
1220                         dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1221                                 __func__);
1222                         return;
1223                 }
1224         }
1225
1226         priv->start_tx = 1;
1227         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1228 }
1229
1230 static void pch_uart_stop_rx(struct uart_port *port)
1231 {
1232         struct eg20t_port *priv;
1233         priv = container_of(port, struct eg20t_port, port);
1234         priv->start_rx = 0;
1235         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1236                                              PCH_UART_HAL_RX_ERR_INT);
1237 }
1238
1239 /* Enable the modem status interrupts. */
1240 static void pch_uart_enable_ms(struct uart_port *port)
1241 {
1242         struct eg20t_port *priv;
1243         priv = container_of(port, struct eg20t_port, port);
1244         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1245 }
1246
1247 /* Control the transmission of a break signal. */
1248 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1249 {
1250         struct eg20t_port *priv;
1251         unsigned long flags;
1252
1253         priv = container_of(port, struct eg20t_port, port);
1254         spin_lock_irqsave(&priv->lock, flags);
1255         pch_uart_hal_set_break(priv, ctl);
1256         spin_unlock_irqrestore(&priv->lock, flags);
1257 }
1258
1259 /* Grab any interrupt resources and initialise any low level driver state. */
1260 static int pch_uart_startup(struct uart_port *port)
1261 {
1262         struct eg20t_port *priv;
1263         int ret;
1264         int fifo_size;
1265         int trigger_level;
1266
1267         priv = container_of(port, struct eg20t_port, port);
1268         priv->tx_empty = 1;
1269
1270         if (port->uartclk)
1271                 priv->uartclk = port->uartclk;
1272         else
1273                 port->uartclk = priv->uartclk;
1274
1275         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1276         ret = pch_uart_hal_set_line(priv, default_baud,
1277                               PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1278                               PCH_UART_HAL_STB1);
1279         if (ret)
1280                 return ret;
1281
1282         switch (priv->fifo_size) {
1283         case 256:
1284                 fifo_size = PCH_UART_HAL_FIFO256;
1285                 break;
1286         case 64:
1287                 fifo_size = PCH_UART_HAL_FIFO64;
1288                 break;
1289         case 16:
1290                 fifo_size = PCH_UART_HAL_FIFO16;
1291                 break;
1292         case 1:
1293         default:
1294                 fifo_size = PCH_UART_HAL_FIFO_DIS;
1295                 break;
1296         }
1297
1298         switch (priv->trigger) {
1299         case PCH_UART_HAL_TRIGGER1:
1300                 trigger_level = 1;
1301                 break;
1302         case PCH_UART_HAL_TRIGGER_L:
1303                 trigger_level = priv->fifo_size / 4;
1304                 break;
1305         case PCH_UART_HAL_TRIGGER_M:
1306                 trigger_level = priv->fifo_size / 2;
1307                 break;
1308         case PCH_UART_HAL_TRIGGER_H:
1309         default:
1310                 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1311                 break;
1312         }
1313
1314         priv->trigger_level = trigger_level;
1315         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1316                                     fifo_size, priv->trigger);
1317         if (ret < 0)
1318                 return ret;
1319
1320         ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1321                         KBUILD_MODNAME, priv);
1322         if (ret < 0)
1323                 return ret;
1324
1325         if (priv->use_dma)
1326                 pch_request_dma(port);
1327
1328         priv->start_rx = 1;
1329         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1330                                             PCH_UART_HAL_RX_ERR_INT);
1331         uart_update_timeout(port, CS8, default_baud);
1332
1333         return 0;
1334 }
1335
1336 static void pch_uart_shutdown(struct uart_port *port)
1337 {
1338         struct eg20t_port *priv;
1339         int ret;
1340
1341         priv = container_of(port, struct eg20t_port, port);
1342         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1343         pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1344         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1345                               PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1346         if (ret)
1347                 dev_err(priv->port.dev,
1348                         "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1349
1350         pch_free_dma(port);
1351
1352         free_irq(priv->port.irq, priv);
1353 }
1354
1355 /* Change the port parameters, including word length, parity, stop
1356  *bits.  Update read_status_mask and ignore_status_mask to indicate
1357  *the types of events we are interested in receiving.  */
1358 static void pch_uart_set_termios(struct uart_port *port,
1359                                  struct ktermios *termios, struct ktermios *old)
1360 {
1361         int baud;
1362         int rtn;
1363         unsigned int parity, bits, stb;
1364         struct eg20t_port *priv;
1365         unsigned long flags;
1366
1367         priv = container_of(port, struct eg20t_port, port);
1368         switch (termios->c_cflag & CSIZE) {
1369         case CS5:
1370                 bits = PCH_UART_HAL_5BIT;
1371                 break;
1372         case CS6:
1373                 bits = PCH_UART_HAL_6BIT;
1374                 break;
1375         case CS7:
1376                 bits = PCH_UART_HAL_7BIT;
1377                 break;
1378         default:                /* CS8 */
1379                 bits = PCH_UART_HAL_8BIT;
1380                 break;
1381         }
1382         if (termios->c_cflag & CSTOPB)
1383                 stb = PCH_UART_HAL_STB2;
1384         else
1385                 stb = PCH_UART_HAL_STB1;
1386
1387         if (termios->c_cflag & PARENB) {
1388                 if (termios->c_cflag & PARODD)
1389                         parity = PCH_UART_HAL_PARITY_ODD;
1390                 else
1391                         parity = PCH_UART_HAL_PARITY_EVEN;
1392
1393         } else
1394                 parity = PCH_UART_HAL_PARITY_NONE;
1395
1396         /* Only UART0 has auto hardware flow function */
1397         if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1398                 priv->mcr |= UART_MCR_AFE;
1399         else
1400                 priv->mcr &= ~UART_MCR_AFE;
1401
1402         termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1403
1404         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1405
1406         spin_lock_irqsave(&priv->lock, flags);
1407         spin_lock(&port->lock);
1408
1409         uart_update_timeout(port, termios->c_cflag, baud);
1410         rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1411         if (rtn)
1412                 goto out;
1413
1414         pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1415         /* Don't rewrite B0 */
1416         if (tty_termios_baud_rate(termios))
1417                 tty_termios_encode_baud_rate(termios, baud, baud);
1418
1419 out:
1420         spin_unlock(&port->lock);
1421         spin_unlock_irqrestore(&priv->lock, flags);
1422 }
1423
1424 static const char *pch_uart_type(struct uart_port *port)
1425 {
1426         return KBUILD_MODNAME;
1427 }
1428
1429 static void pch_uart_release_port(struct uart_port *port)
1430 {
1431         struct eg20t_port *priv;
1432
1433         priv = container_of(port, struct eg20t_port, port);
1434         pci_iounmap(priv->pdev, priv->membase);
1435         pci_release_regions(priv->pdev);
1436 }
1437
1438 static int pch_uart_request_port(struct uart_port *port)
1439 {
1440         struct eg20t_port *priv;
1441         int ret;
1442         void __iomem *membase;
1443
1444         priv = container_of(port, struct eg20t_port, port);
1445         ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1446         if (ret < 0)
1447                 return -EBUSY;
1448
1449         membase = pci_iomap(priv->pdev, 1, 0);
1450         if (!membase) {
1451                 pci_release_regions(priv->pdev);
1452                 return -EBUSY;
1453         }
1454         priv->membase = port->membase = membase;
1455
1456         return 0;
1457 }
1458
1459 static void pch_uart_config_port(struct uart_port *port, int type)
1460 {
1461         struct eg20t_port *priv;
1462
1463         priv = container_of(port, struct eg20t_port, port);
1464         if (type & UART_CONFIG_TYPE) {
1465                 port->type = priv->port_type;
1466                 pch_uart_request_port(port);
1467         }
1468 }
1469
1470 static int pch_uart_verify_port(struct uart_port *port,
1471                                 struct serial_struct *serinfo)
1472 {
1473         struct eg20t_port *priv;
1474
1475         priv = container_of(port, struct eg20t_port, port);
1476         if (serinfo->flags & UPF_LOW_LATENCY) {
1477                 dev_info(priv->port.dev,
1478                         "PCH UART : Use PIO Mode (without DMA)\n");
1479                 priv->use_dma = 0;
1480                 serinfo->flags &= ~UPF_LOW_LATENCY;
1481         } else {
1482 #ifndef CONFIG_PCH_DMA
1483                 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1484                         __func__);
1485                 return -EOPNOTSUPP;
1486 #endif
1487                 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1488                 if (!priv->use_dma)
1489                         pch_request_dma(port);
1490                 priv->use_dma = 1;
1491         }
1492
1493         return 0;
1494 }
1495
1496 /*
1497  *      Wait for transmitter & holding register to empty
1498  */
1499 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1500 {
1501         unsigned int status, tmout = 10000;
1502
1503         /* Wait up to 10ms for the character(s) to be sent. */
1504         for (;;) {
1505                 status = ioread8(up->membase + UART_LSR);
1506
1507                 if ((status & bits) == bits)
1508                         break;
1509                 if (--tmout == 0)
1510                         break;
1511                 udelay(1);
1512         }
1513
1514         /* Wait up to 1s for flow control if necessary */
1515         if (up->port.flags & UPF_CONS_FLOW) {
1516                 unsigned int tmout;
1517                 for (tmout = 1000000; tmout; tmout--) {
1518                         unsigned int msr = ioread8(up->membase + UART_MSR);
1519                         if (msr & UART_MSR_CTS)
1520                                 break;
1521                         udelay(1);
1522                         touch_nmi_watchdog();
1523                 }
1524         }
1525 }
1526
1527 #ifdef CONFIG_CONSOLE_POLL
1528 /*
1529  * Console polling routines for communicate via uart while
1530  * in an interrupt or debug context.
1531  */
1532 static int pch_uart_get_poll_char(struct uart_port *port)
1533 {
1534         struct eg20t_port *priv =
1535                 container_of(port, struct eg20t_port, port);
1536         u8 lsr = ioread8(priv->membase + UART_LSR);
1537
1538         if (!(lsr & UART_LSR_DR))
1539                 return NO_POLL_CHAR;
1540
1541         return ioread8(priv->membase + PCH_UART_RBR);
1542 }
1543
1544
1545 static void pch_uart_put_poll_char(struct uart_port *port,
1546                          unsigned char c)
1547 {
1548         unsigned int ier;
1549         struct eg20t_port *priv =
1550                 container_of(port, struct eg20t_port, port);
1551
1552         /*
1553          * First save the IER then disable the interrupts
1554          */
1555         ier = ioread8(priv->membase + UART_IER);
1556         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1557
1558         wait_for_xmitr(priv, UART_LSR_THRE);
1559         /*
1560          * Send the character out.
1561          * If a LF, also do CR...
1562          */
1563         iowrite8(c, priv->membase + PCH_UART_THR);
1564         if (c == 10) {
1565                 wait_for_xmitr(priv, UART_LSR_THRE);
1566                 iowrite8(13, priv->membase + PCH_UART_THR);
1567         }
1568
1569         /*
1570          * Finally, wait for transmitter to become empty
1571          * and restore the IER
1572          */
1573         wait_for_xmitr(priv, BOTH_EMPTY);
1574         iowrite8(ier, priv->membase + UART_IER);
1575 }
1576 #endif /* CONFIG_CONSOLE_POLL */
1577
1578 static struct uart_ops pch_uart_ops = {
1579         .tx_empty = pch_uart_tx_empty,
1580         .set_mctrl = pch_uart_set_mctrl,
1581         .get_mctrl = pch_uart_get_mctrl,
1582         .stop_tx = pch_uart_stop_tx,
1583         .start_tx = pch_uart_start_tx,
1584         .stop_rx = pch_uart_stop_rx,
1585         .enable_ms = pch_uart_enable_ms,
1586         .break_ctl = pch_uart_break_ctl,
1587         .startup = pch_uart_startup,
1588         .shutdown = pch_uart_shutdown,
1589         .set_termios = pch_uart_set_termios,
1590 /*      .pm             = pch_uart_pm,          Not supported yet */
1591 /*      .set_wake       = pch_uart_set_wake,    Not supported yet */
1592         .type = pch_uart_type,
1593         .release_port = pch_uart_release_port,
1594         .request_port = pch_uart_request_port,
1595         .config_port = pch_uart_config_port,
1596         .verify_port = pch_uart_verify_port,
1597 #ifdef CONFIG_CONSOLE_POLL
1598         .poll_get_char = pch_uart_get_poll_char,
1599         .poll_put_char = pch_uart_put_poll_char,
1600 #endif
1601 };
1602
1603 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1604
1605 static void pch_console_putchar(struct uart_port *port, int ch)
1606 {
1607         struct eg20t_port *priv =
1608                 container_of(port, struct eg20t_port, port);
1609
1610         wait_for_xmitr(priv, UART_LSR_THRE);
1611         iowrite8(ch, priv->membase + PCH_UART_THR);
1612 }
1613
1614 /*
1615  *      Print a string to the serial port trying not to disturb
1616  *      any possible real use of the port...
1617  *
1618  *      The console_lock must be held when we get here.
1619  */
1620 static void
1621 pch_console_write(struct console *co, const char *s, unsigned int count)
1622 {
1623         struct eg20t_port *priv;
1624         unsigned long flags;
1625         int priv_locked = 1;
1626         int port_locked = 1;
1627         u8 ier;
1628
1629         priv = pch_uart_ports[co->index];
1630
1631         touch_nmi_watchdog();
1632
1633         local_irq_save(flags);
1634         if (priv->port.sysrq) {
1635                 /* call to uart_handle_sysrq_char already took the priv lock */
1636                 priv_locked = 0;
1637                 /* serial8250_handle_port() already took the port lock */
1638                 port_locked = 0;
1639         } else if (oops_in_progress) {
1640                 priv_locked = spin_trylock(&priv->lock);
1641                 port_locked = spin_trylock(&priv->port.lock);
1642         } else {
1643                 spin_lock(&priv->lock);
1644                 spin_lock(&priv->port.lock);
1645         }
1646
1647         /*
1648          *      First save the IER then disable the interrupts
1649          */
1650         ier = ioread8(priv->membase + UART_IER);
1651
1652         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1653
1654         uart_console_write(&priv->port, s, count, pch_console_putchar);
1655
1656         /*
1657          *      Finally, wait for transmitter to become empty
1658          *      and restore the IER
1659          */
1660         wait_for_xmitr(priv, BOTH_EMPTY);
1661         iowrite8(ier, priv->membase + UART_IER);
1662
1663         if (port_locked)
1664                 spin_unlock(&priv->port.lock);
1665         if (priv_locked)
1666                 spin_unlock(&priv->lock);
1667         local_irq_restore(flags);
1668 }
1669
1670 static int __init pch_console_setup(struct console *co, char *options)
1671 {
1672         struct uart_port *port;
1673         int baud = default_baud;
1674         int bits = 8;
1675         int parity = 'n';
1676         int flow = 'n';
1677
1678         /*
1679          * Check whether an invalid uart number has been specified, and
1680          * if so, search for the first available port that does have
1681          * console support.
1682          */
1683         if (co->index >= PCH_UART_NR)
1684                 co->index = 0;
1685         port = &pch_uart_ports[co->index]->port;
1686
1687         if (!port || (!port->iobase && !port->membase))
1688                 return -ENODEV;
1689
1690         port->uartclk = pch_uart_get_uartclk();
1691
1692         if (options)
1693                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1694
1695         return uart_set_options(port, co, baud, parity, bits, flow);
1696 }
1697
1698 static struct uart_driver pch_uart_driver;
1699
1700 static struct console pch_console = {
1701         .name           = PCH_UART_DRIVER_DEVICE,
1702         .write          = pch_console_write,
1703         .device         = uart_console_device,
1704         .setup          = pch_console_setup,
1705         .flags          = CON_PRINTBUFFER | CON_ANYTIME,
1706         .index          = -1,
1707         .data           = &pch_uart_driver,
1708 };
1709
1710 #define PCH_CONSOLE     (&pch_console)
1711 #else
1712 #define PCH_CONSOLE     NULL
1713 #endif  /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1714
1715 static struct uart_driver pch_uart_driver = {
1716         .owner = THIS_MODULE,
1717         .driver_name = KBUILD_MODNAME,
1718         .dev_name = PCH_UART_DRIVER_DEVICE,
1719         .major = 0,
1720         .minor = 0,
1721         .nr = PCH_UART_NR,
1722         .cons = PCH_CONSOLE,
1723 };
1724
1725 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1726                                              const struct pci_device_id *id)
1727 {
1728         struct eg20t_port *priv;
1729         int ret;
1730         unsigned int iobase;
1731         unsigned int mapbase;
1732         unsigned char *rxbuf;
1733         int fifosize;
1734         int port_type;
1735         struct pch_uart_driver_data *board;
1736         char name[32];  /* for debugfs file name */
1737
1738         board = &drv_dat[id->driver_data];
1739         port_type = board->port_type;
1740
1741         priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1742         if (priv == NULL)
1743                 goto init_port_alloc_err;
1744
1745         rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1746         if (!rxbuf)
1747                 goto init_port_free_txbuf;
1748
1749         switch (port_type) {
1750         case PORT_UNKNOWN:
1751                 fifosize = 256; /* EG20T/ML7213: UART0 */
1752                 break;
1753         case PORT_8250:
1754                 fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1755                 break;
1756         default:
1757                 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1758                 goto init_port_hal_free;
1759         }
1760
1761         pci_enable_msi(pdev);
1762         pci_set_master(pdev);
1763
1764         spin_lock_init(&priv->lock);
1765
1766         iobase = pci_resource_start(pdev, 0);
1767         mapbase = pci_resource_start(pdev, 1);
1768         priv->mapbase = mapbase;
1769         priv->iobase = iobase;
1770         priv->pdev = pdev;
1771         priv->tx_empty = 1;
1772         priv->rxbuf.buf = rxbuf;
1773         priv->rxbuf.size = PAGE_SIZE;
1774
1775         priv->fifo_size = fifosize;
1776         priv->uartclk = pch_uart_get_uartclk();
1777         priv->port_type = PORT_MAX_8250 + port_type + 1;
1778         priv->port.dev = &pdev->dev;
1779         priv->port.iobase = iobase;
1780         priv->port.membase = NULL;
1781         priv->port.mapbase = mapbase;
1782         priv->port.irq = pdev->irq;
1783         priv->port.iotype = UPIO_PORT;
1784         priv->port.ops = &pch_uart_ops;
1785         priv->port.flags = UPF_BOOT_AUTOCONF;
1786         priv->port.fifosize = fifosize;
1787         priv->port.line = board->line_no;
1788         priv->trigger = PCH_UART_HAL_TRIGGER_M;
1789
1790         spin_lock_init(&priv->port.lock);
1791
1792         pci_set_drvdata(pdev, priv);
1793         priv->trigger_level = 1;
1794         priv->fcr = 0;
1795
1796 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1797         pch_uart_ports[board->line_no] = priv;
1798 #endif
1799         ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1800         if (ret < 0)
1801                 goto init_port_hal_free;
1802
1803 #ifdef CONFIG_DEBUG_FS
1804         snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1805         priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1806                                 NULL, priv, &port_regs_ops);
1807 #endif
1808
1809         return priv;
1810
1811 init_port_hal_free:
1812 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1813         pch_uart_ports[board->line_no] = NULL;
1814 #endif
1815         free_page((unsigned long)rxbuf);
1816 init_port_free_txbuf:
1817         kfree(priv);
1818 init_port_alloc_err:
1819
1820         return NULL;
1821 }
1822
1823 static void pch_uart_exit_port(struct eg20t_port *priv)
1824 {
1825
1826 #ifdef CONFIG_DEBUG_FS
1827         if (priv->debugfs)
1828                 debugfs_remove(priv->debugfs);
1829 #endif
1830         uart_remove_one_port(&pch_uart_driver, &priv->port);
1831         pci_set_drvdata(priv->pdev, NULL);
1832         free_page((unsigned long)priv->rxbuf.buf);
1833 }
1834
1835 static void pch_uart_pci_remove(struct pci_dev *pdev)
1836 {
1837         struct eg20t_port *priv = pci_get_drvdata(pdev);
1838
1839         pci_disable_msi(pdev);
1840
1841 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1842         pch_uart_ports[priv->port.line] = NULL;
1843 #endif
1844         pch_uart_exit_port(priv);
1845         pci_disable_device(pdev);
1846         kfree(priv);
1847         return;
1848 }
1849 #ifdef CONFIG_PM
1850 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1851 {
1852         struct eg20t_port *priv = pci_get_drvdata(pdev);
1853
1854         uart_suspend_port(&pch_uart_driver, &priv->port);
1855
1856         pci_save_state(pdev);
1857         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1858         return 0;
1859 }
1860
1861 static int pch_uart_pci_resume(struct pci_dev *pdev)
1862 {
1863         struct eg20t_port *priv = pci_get_drvdata(pdev);
1864         int ret;
1865
1866         pci_set_power_state(pdev, PCI_D0);
1867         pci_restore_state(pdev);
1868
1869         ret = pci_enable_device(pdev);
1870         if (ret) {
1871                 dev_err(&pdev->dev,
1872                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1873                 return ret;
1874         }
1875
1876         uart_resume_port(&pch_uart_driver, &priv->port);
1877
1878         return 0;
1879 }
1880 #else
1881 #define pch_uart_pci_suspend NULL
1882 #define pch_uart_pci_resume NULL
1883 #endif
1884
1885 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1886         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1887          .driver_data = pch_et20t_uart0},
1888         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1889          .driver_data = pch_et20t_uart1},
1890         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1891          .driver_data = pch_et20t_uart2},
1892         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1893          .driver_data = pch_et20t_uart3},
1894         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1895          .driver_data = pch_ml7213_uart0},
1896         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1897          .driver_data = pch_ml7213_uart1},
1898         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1899          .driver_data = pch_ml7213_uart2},
1900         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1901          .driver_data = pch_ml7223_uart0},
1902         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1903          .driver_data = pch_ml7223_uart1},
1904         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1905          .driver_data = pch_ml7831_uart0},
1906         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1907          .driver_data = pch_ml7831_uart1},
1908         {0,},
1909 };
1910
1911 static int pch_uart_pci_probe(struct pci_dev *pdev,
1912                                         const struct pci_device_id *id)
1913 {
1914         int ret;
1915         struct eg20t_port *priv;
1916
1917         ret = pci_enable_device(pdev);
1918         if (ret < 0)
1919                 goto probe_error;
1920
1921         priv = pch_uart_init_port(pdev, id);
1922         if (!priv) {
1923                 ret = -EBUSY;
1924                 goto probe_disable_device;
1925         }
1926         pci_set_drvdata(pdev, priv);
1927
1928         return ret;
1929
1930 probe_disable_device:
1931         pci_disable_msi(pdev);
1932         pci_disable_device(pdev);
1933 probe_error:
1934         return ret;
1935 }
1936
1937 static struct pci_driver pch_uart_pci_driver = {
1938         .name = "pch_uart",
1939         .id_table = pch_uart_pci_id,
1940         .probe = pch_uart_pci_probe,
1941         .remove = pch_uart_pci_remove,
1942         .suspend = pch_uart_pci_suspend,
1943         .resume = pch_uart_pci_resume,
1944 };
1945
1946 static int __init pch_uart_module_init(void)
1947 {
1948         int ret;
1949
1950         /* register as UART driver */
1951         ret = uart_register_driver(&pch_uart_driver);
1952         if (ret < 0)
1953                 return ret;
1954
1955         /* register as PCI driver */
1956         ret = pci_register_driver(&pch_uart_pci_driver);
1957         if (ret < 0)
1958                 uart_unregister_driver(&pch_uart_driver);
1959
1960         return ret;
1961 }
1962 module_init(pch_uart_module_init);
1963
1964 static void __exit pch_uart_module_exit(void)
1965 {
1966         pci_unregister_driver(&pch_uart_pci_driver);
1967         uart_unregister_driver(&pch_uart_driver);
1968 }
1969 module_exit(pch_uart_module_exit);
1970
1971 MODULE_LICENSE("GPL v2");
1972 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1973 module_param(default_baud, uint, S_IRUGO);
1974 MODULE_PARM_DESC(default_baud,
1975                  "Default BAUD for initial driver state and console (default 9600)");
1976 module_param(user_uartclk, uint, S_IRUGO);
1977 MODULE_PARM_DESC(user_uartclk,
1978                  "Override UART default or board specific UART clock");