2 * Copyright (C) 2012 Invensense, Inc.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
16 * @brief Hardware drivers.
19 * @file inv_mpu_misc.c
20 * @brief A sysfs device driver for Invensense mpu.
21 * @details This file is part of invensense mpu driver code
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26 #include <linux/module.h>
27 #include <linux/init.h>
28 #include <linux/slab.h>
29 #include <linux/i2c.h>
30 #include <linux/err.h>
31 #include <linux/delay.h>
32 #include <linux/sysfs.h>
33 #include <linux/jiffies.h>
34 #include <linux/irq.h>
35 #include <linux/interrupt.h>
36 #include <linux/kfifo.h>
37 #include <linux/poll.h>
38 #include <linux/miscdevice.h>
39 #include <linux/crc32.h>
41 #include "inv_mpu_iio.h"
42 #include "inv_counters.h"
45 #define DMP_ORIENTATION_TIME 500
46 #define DMP_ORIENTATION_ANGLE 60
47 #define DMP_DEFAULT_FIFO_RATE 200
48 #define DMP_TAP_SCALE (767603923 / 5)
49 #define DMP_MULTI_SHIFT 30
50 #define DMP_MULTI_TAP_TIME 500
51 #define DMP_SHAKE_REJECT_THRESH 100
52 #define DMP_SHAKE_REJECT_TIME 10
53 #define DMP_SHAKE_REJECT_TIMEOUT 10
54 #define DMP_ANGLE_SCALE 15
55 #define DMP_PRECISION 1000
56 #define DMP_MAX_DIVIDER 4
57 #define DMP_MAX_MIN_TAPS 4
58 #define DMP_IMAGE_CRC_VALUE 0x665f5a73
59 #define DMP_IMAGE_SIZE 2913
61 /*--- Test parameters defaults --- */
62 #define DEF_OLDEST_SUPP_PROD_REV 8
63 #define DEF_OLDEST_SUPP_SW_REV 2
66 #define DEF_SELFTEST_SAMPLE_RATE 0
67 /* full scale setting dps */
68 #define DEF_SELFTEST_GYRO_FS (0 << 3)
69 #define DEF_SELFTEST_ACCEL_FS (2 << 3)
70 #define DEF_SELFTEST_GYRO_SENS (32768 / 250)
71 /* wait time before collecting data */
72 #define DEF_GYRO_WAIT_TIME 10
73 #define DEF_ST_STABLE_TIME 200
74 #define DEF_ST_6500_STABLE_TIME 20
75 #define DEF_GYRO_SCALE 131
76 #define DEF_ST_PRECISION 1000
77 #define DEF_ST_ACCEL_FS_MG 8000UL
78 #define DEF_ST_SCALE (1L << 15)
79 #define DEF_ST_TRY_TIMES 2
80 #define DEF_ST_COMPASS_RESULT_SHIFT 2
81 #define DEF_ST_ACCEL_RESULT_SHIFT 1
82 #define DEF_ST_OTP0_THRESH 60
83 #define DEF_ST_ABS_THRESH 20
86 #define DEF_ST_COMPASS_WAIT_MIN (10 * 1000)
87 #define DEF_ST_COMPASS_WAIT_MAX (15 * 1000)
88 #define DEF_ST_COMPASS_TRY_TIMES 10
89 #define DEF_ST_COMPASS_8963_SHIFT 2
94 /*---- MPU6050 notable product revisions ----*/
95 #define MPU_PRODUCT_KEY_B1_E1_5 105
96 #define MPU_PRODUCT_KEY_B2_F1 431
97 /* accelerometer Hw self test min and max bias shift (mg) */
98 #define DEF_ACCEL_ST_SHIFT_MIN 300
99 #define DEF_ACCEL_ST_SHIFT_MAX 950
101 #define DEF_ACCEL_ST_SHIFT_DELTA 140
102 #define DEF_GYRO_CT_SHIFT_DELTA 140
103 /* gyroscope Coriolis self test min and max bias shift (dps) */
104 #define DEF_GYRO_CT_SHIFT_MIN 10
105 #define DEF_GYRO_CT_SHIFT_MAX 105
107 /*---- MPU6500 Self Test Pass/Fail Criteria ----*/
108 /* Gyro Offset Max Value (dps) */
109 #define DEF_GYRO_OFFSET_MAX 20
110 /* Gyro Self Test Absolute Limits ST_AL (dps) */
111 #define DEF_GYRO_ST_AL 60
112 /* Accel Self Test Absolute Limits ST_AL (mg) */
113 #define DEF_ACCEL_ST_AL_MIN 225
114 #define DEF_ACCEL_ST_AL_MAX 675
115 #define DEF_6500_ACCEL_ST_SHIFT_DELTA 500
116 #define DEF_6500_GYRO_CT_SHIFT_DELTA 500
117 #define DEF_ST_MPU6500_ACCEL_LPF 2
118 #define DEF_ST_6500_ACCEL_FS_MG 2000UL
119 #define DEF_SELFTEST_6500_ACCEL_FS (0 << 3)
121 /* Note: The ST_AL values are only used when ST_OTP = 0,
122 * i.e no factory self test values for reference
125 /* NOTE: product entries are in chronological order */
126 static const struct prod_rev_map_t prod_rev_map[] = {
128 {MPL_PROD_KEY(0, 1), MPU_SILICON_REV_A2, 131, 16384},
129 {MPL_PROD_KEY(0, 2), MPU_SILICON_REV_A2, 131, 16384},
130 {MPL_PROD_KEY(0, 3), MPU_SILICON_REV_A2, 131, 16384},
131 {MPL_PROD_KEY(0, 4), MPU_SILICON_REV_A2, 131, 16384},
132 {MPL_PROD_KEY(0, 5), MPU_SILICON_REV_A2, 131, 16384},
133 {MPL_PROD_KEY(0, 6), MPU_SILICON_REV_A2, 131, 16384},
135 {MPL_PROD_KEY(0, 7), MPU_SILICON_REV_A2, 131, 16384},
136 {MPL_PROD_KEY(0, 8), MPU_SILICON_REV_A2, 131, 16384},
137 {MPL_PROD_KEY(0, 9), MPU_SILICON_REV_A2, 131, 16384},
138 {MPL_PROD_KEY(0, 10), MPU_SILICON_REV_A2, 131, 16384},
139 {MPL_PROD_KEY(0, 11), MPU_SILICON_REV_A2, 131, 16384},
140 {MPL_PROD_KEY(0, 12), MPU_SILICON_REV_A2, 131, 16384},
141 {MPL_PROD_KEY(0, 13), MPU_SILICON_REV_A2, 131, 16384},
142 {MPL_PROD_KEY(0, 14), MPU_SILICON_REV_A2, 131, 16384},
143 {MPL_PROD_KEY(0, 15), MPU_SILICON_REV_A2, 131, 16384},
144 {MPL_PROD_KEY(0, 27), MPU_SILICON_REV_A2, 131, 16384},
146 {MPL_PROD_KEY(1, 16), MPU_SILICON_REV_B1, 131, 16384},
147 {MPL_PROD_KEY(1, 17), MPU_SILICON_REV_B1, 131, 16384},
148 {MPL_PROD_KEY(1, 18), MPU_SILICON_REV_B1, 131, 16384},
149 {MPL_PROD_KEY(1, 19), MPU_SILICON_REV_B1, 131, 16384},
150 {MPL_PROD_KEY(1, 20), MPU_SILICON_REV_B1, 131, 16384},
151 {MPL_PROD_KEY(1, 28), MPU_SILICON_REV_B1, 131, 16384},
152 {MPL_PROD_KEY(1, 1), MPU_SILICON_REV_B1, 131, 16384},
153 {MPL_PROD_KEY(1, 2), MPU_SILICON_REV_B1, 131, 16384},
154 {MPL_PROD_KEY(1, 3), MPU_SILICON_REV_B1, 131, 16384},
155 {MPL_PROD_KEY(1, 4), MPU_SILICON_REV_B1, 131, 16384},
156 {MPL_PROD_KEY(1, 5), MPU_SILICON_REV_B1, 131, 16384},
157 {MPL_PROD_KEY(1, 6), MPU_SILICON_REV_B1, 131, 16384},
159 {MPL_PROD_KEY(2, 7), MPU_SILICON_REV_B1, 131, 16384},
160 {MPL_PROD_KEY(2, 8), MPU_SILICON_REV_B1, 131, 16384},
161 {MPL_PROD_KEY(2, 9), MPU_SILICON_REV_B1, 131, 16384},
162 {MPL_PROD_KEY(2, 10), MPU_SILICON_REV_B1, 131, 16384},
163 {MPL_PROD_KEY(2, 11), MPU_SILICON_REV_B1, 131, 16384},
164 {MPL_PROD_KEY(2, 12), MPU_SILICON_REV_B1, 131, 16384},
165 {MPL_PROD_KEY(2, 29), MPU_SILICON_REV_B1, 131, 16384},
167 {MPL_PROD_KEY(3, 30), MPU_SILICON_REV_B1, 131, 16384},
169 {MPL_PROD_KEY(4, 31), MPU_SILICON_REV_B1, 131, 8192},
170 {MPL_PROD_KEY(4, 1), MPU_SILICON_REV_B1, 131, 8192},
171 {MPL_PROD_KEY(4, 3), MPU_SILICON_REV_B1, 131, 8192},
173 {MPL_PROD_KEY(5, 3), MPU_SILICON_REV_B1, 131, 16384},
175 {MPL_PROD_KEY(6, 19), MPU_SILICON_REV_B1, 131, 16384},
177 {MPL_PROD_KEY(7, 19), MPU_SILICON_REV_B1, 131, 16384},
179 {MPL_PROD_KEY(8, 19), MPU_SILICON_REV_B1, 131, 16384},
181 {MPL_PROD_KEY(9, 19), MPU_SILICON_REV_B1, 131, 16384},
183 {MPL_PROD_KEY(10, 19), MPU_SILICON_REV_B1, 131, 16384}
187 * List of product software revisions
190 * software revision 0 falls back to the old detection method
191 * based off the product version and product revision per the
194 static const struct prod_rev_map_t sw_rev_map[] = {
196 {1, MPU_SILICON_REV_B1, 131, 8192}, /* rev C */
197 {2, MPU_SILICON_REV_B1, 131, 16384} /* rev D */
200 static const u16 mpu_6500_st_tb[256] = {
201 2620, 2646, 2672, 2699, 2726, 2753, 2781, 2808,
202 2837, 2865, 2894, 2923, 2952, 2981, 3011, 3041,
203 3072, 3102, 3133, 3165, 3196, 3228, 3261, 3293,
204 3326, 3359, 3393, 3427, 3461, 3496, 3531, 3566,
205 3602, 3638, 3674, 3711, 3748, 3786, 3823, 3862,
206 3900, 3939, 3979, 4019, 4059, 4099, 4140, 4182,
207 4224, 4266, 4308, 4352, 4395, 4439, 4483, 4528,
208 4574, 4619, 4665, 4712, 4759, 4807, 4855, 4903,
209 4953, 5002, 5052, 5103, 5154, 5205, 5257, 5310,
210 5363, 5417, 5471, 5525, 5581, 5636, 5693, 5750,
211 5807, 5865, 5924, 5983, 6043, 6104, 6165, 6226,
212 6289, 6351, 6415, 6479, 6544, 6609, 6675, 6742,
213 6810, 6878, 6946, 7016, 7086, 7157, 7229, 7301,
214 7374, 7448, 7522, 7597, 7673, 7750, 7828, 7906,
215 7985, 8065, 8145, 8227, 8309, 8392, 8476, 8561,
216 8647, 8733, 8820, 8909, 8998, 9088, 9178, 9270,
217 9363, 9457, 9551, 9647, 9743, 9841, 9939, 10038,
218 10139, 10240, 10343, 10446, 10550, 10656, 10763, 10870,
219 10979, 11089, 11200, 11312, 11425, 11539, 11654, 11771,
220 11889, 12008, 12128, 12249, 12371, 12495, 12620, 12746,
221 12874, 13002, 13132, 13264, 13396, 13530, 13666, 13802,
222 13940, 14080, 14221, 14363, 14506, 14652, 14798, 14946,
223 15096, 15247, 15399, 15553, 15709, 15866, 16024, 16184,
224 16346, 16510, 16675, 16842, 17010, 17180, 17352, 17526,
225 17701, 17878, 18057, 18237, 18420, 18604, 18790, 18978,
226 19167, 19359, 19553, 19748, 19946, 20145, 20347, 20550,
227 20756, 20963, 21173, 21385, 21598, 21814, 22033, 22253,
228 22475, 22700, 22927, 23156, 23388, 23622, 23858, 24097,
229 24338, 24581, 24827, 25075, 25326, 25579, 25835, 26093,
230 26354, 26618, 26884, 27153, 27424, 27699, 27976, 28255,
231 28538, 28823, 29112, 29403, 29697, 29994, 30294, 30597,
232 30903, 31212, 31524, 31839, 32157, 32479, 32804
235 static const int accl_st_tb[31] = {
236 340, 351, 363, 375, 388, 401, 414, 428,
237 443, 458, 473, 489, 506, 523, 541, 559,
238 578, 597, 617, 638, 660, 682, 705, 729,
239 753, 779, 805, 832, 860, 889, 919};
241 static const int gyro_6050_st_tb[31] = {
242 3275, 3425, 3583, 3748, 3920, 4100, 4289, 4486,
243 4693, 4909, 5134, 5371, 5618, 5876, 6146, 6429,
244 6725, 7034, 7358, 7696, 8050, 8421, 8808, 9213,
245 9637, 10080, 10544, 11029, 11537, 12067, 12622};
246 static const int gyro_3500_st_tb[255] = {
247 2620, 2646, 2672, 2699, 2726, 2753, 2781, 2808,
248 2837, 2865, 2894, 2923, 2952, 2981, 3011, 3041,
249 3072, 3102, 3133, 3165, 3196, 3228, 3261, 3293,
250 3326, 3359, 3393, 3427, 3461, 3496, 3531, 3566,
251 3602, 3638, 3674, 3711, 3748, 3786, 3823, 3862,
252 3900, 3939, 3979, 4019, 4059, 4099, 4140, 4182,
253 4224, 4266, 4308, 4352, 4395, 4439, 4483, 4528,
254 4574, 4619, 4665, 4712, 4759, 4807, 4855, 4903,
255 4953, 5002, 5052, 5103, 5154, 5205, 5257, 5310,
256 5363, 5417, 5471, 5525, 5581, 5636, 5693, 5750,
257 5807, 5865, 5924, 5983, 6043, 6104, 6165, 6226,
258 6289, 6351, 6415, 6479, 6544, 6609, 6675, 6742,
259 6810, 6878, 6946, 7016, 7086, 7157, 7229, 7301,
260 7374, 7448, 7522, 7597, 7673, 7750, 7828, 7906,
261 7985, 8065, 8145, 8227, 8309, 8392, 8476, 8561,
262 8647, 8733, 8820, 8909, 8998, 9088, 9178, 9270,
263 9363, 9457, 9551, 9647, 9743, 9841, 9939, 10038,
264 10139, 10240, 10343, 10446, 10550, 10656, 10763, 10870,
265 10979, 11089, 11200, 11312, 11425, 11539, 11654, 11771,
266 11889, 12008, 12128, 12249, 12371, 12495, 12620, 12746,
267 12874, 13002, 13132, 13264, 13396, 13530, 13666, 13802,
268 13940, 14080, 14221, 14363, 14506, 14652, 14798, 14946,
269 15096, 15247, 15399, 15553, 15709, 15866, 16024, 16184,
270 16346, 16510, 16675, 16842, 17010, 17180, 17352, 17526,
271 17701, 17878, 18057, 18237, 18420, 18604, 18790, 18978,
272 19167, 19359, 19553, 19748, 19946, 20145, 20347, 20550,
273 20756, 20963, 21173, 21385, 21598, 21814, 22033, 22253,
274 22475, 22700, 22927, 23156, 23388, 23622, 23858, 24097,
275 24338, 24581, 24827, 25075, 25326, 25579, 25835, 26093,
276 26354, 26618, 26884, 27153, 27424, 27699, 27976, 28255,
277 28538, 28823, 29112, 29403, 29697, 29994, 30294, 30597,
278 30903, 31212, 31524, 31839, 32157, 32479, 32804};
280 char *wr_pr_debug_begin(u8 const *data, u32 len, char *string)
283 string = kmalloc(len * 2 + 1, GFP_KERNEL);
284 for (ii = 0; ii < len; ii++)
285 sprintf(&string[ii * 2], "%02X", data[ii]);
290 char *wr_pr_debug_end(char *string)
296 int mpu_memory_write(struct inv_mpu_iio_s *st, u8 mpu_addr, u16 mem_addr,
297 u32 len, u8 const *data)
309 if (len >= (sizeof(buf) - 1))
312 bank[0] = REG_BANK_SEL;
313 bank[1] = mem_addr >> 8;
315 addr[0] = REG_MEM_START_ADDR;
316 addr[1] = mem_addr & 0xFF;
319 memcpy(buf + 1, data, len);
325 msg.len = sizeof(bank);
326 /* msg.scl_rate = 200*1000; */
327 INV_I2C_INC_MPUWRITE(3);
328 res = i2c_transfer(st->sl_handle, &msg, 1);
338 msg.len = sizeof(addr);
339 /* msg.scl_rate = 200*1000; */
340 INV_I2C_INC_MPUWRITE(3);
341 res = i2c_transfer(st->sl_handle, &msg, 1);
352 /* msg.scl_rate = 200*1000; */
353 INV_I2C_INC_MPUWRITE(2+len);
354 res = i2c_transfer(st->sl_handle, &msg, 1);
363 pr_debug("%s WM%02X%02X%02X%s%s - %d\n", st->hw->name,
364 mpu_addr, bank[1], addr[1],
365 wr_pr_debug_begin(data, len, write),
366 wr_pr_debug_end(write),
372 int mpu_memory_read(struct inv_mpu_iio_s *st, u8 mpu_addr, u16 mem_addr,
385 bank[0] = REG_BANK_SEL;
386 bank[1] = mem_addr >> 8;
388 addr[0] = REG_MEM_START_ADDR;
389 addr[1] = mem_addr & 0xFF;
397 msg.len = sizeof(bank);
398 /* msg.scl_rate = 200*1000; */
399 INV_I2C_INC_MPUWRITE(3);
400 res = i2c_transfer(st->sl_handle, &msg, 1);
410 msg.len = sizeof(addr);
411 /* msg.scl_rate = 200*1000; */
412 INV_I2C_INC_MPUWRITE(3);
413 res = i2c_transfer(st->sl_handle, &msg, 1);
424 /* msg.scl_rate = 200*1000; */
425 INV_I2C_INC_MPUWRITE(3);
426 res = i2c_transfer(st->sl_handle, &msg, 1);
434 msg.flags = I2C_M_RD;
437 /* msg.scl_rate = 200*1000; */
438 INV_I2C_INC_MPUREAD(len);
439 res = i2c_transfer(st->sl_handle, &msg, 1);
447 pr_debug("%s RM%02X%02X%02X%02X - %s%s\n", st->hw->name,
448 mpu_addr, bank[1], addr[1], len,
449 wr_pr_debug_begin(data, len, read),
450 wr_pr_debug_end(read));
456 int mpu_memory_write_unaligned(struct inv_mpu_iio_s *st, u16 key, int len,
463 if (len > MPU_MEM_BANK_SIZE)
465 addr = inv_dmp_get_address(key);
466 if (addr > MPU6XXX_MAX_MPU_MEM)
469 end = ((addr + len - 1) >> 8);
471 result = mpu_memory_write(st, st->i2c_addr, addr, len, d);
476 result = mpu_memory_write(st, st->i2c_addr, addr, len1, d);
477 result |= mpu_memory_write(st, st->i2c_addr, end, len2,
485 * index_of_key()- Inverse lookup of the index of an MPL product key .
486 * @key: the MPL product indentifier also referred to as 'key'.
488 static short index_of_key(u16 key)
491 for (i = 0; i < NUM_OF_PROD_REVS; i++)
492 if (prod_rev_map[i].mpl_product_key == key)
497 int inv_get_silicon_rev_mpu6500(struct inv_mpu_iio_s *st)
499 struct inv_chip_info_s *chip_info = &st->chip_info;
503 result = inv_i2c_read(st, REG_WHOAMI, 1, &whoami);
506 if (whoami != MPU6500_ID && whoami != MPU9250_ID &&
507 whoami != MPU6515_ID)
510 /*memory read need more time after power up */
511 msleep(POWER_UP_TIME);
512 result = mpu_memory_read(st, st->i2c_addr,
513 MPU6500_MEM_REV_ADDR, 1, &sw_rev);
514 sw_rev &= INV_MPU_REV_MASK;
520 /* these values are place holders and not real values */
521 chip_info->product_id = MPU6500_PRODUCT_REVISION;
522 chip_info->product_revision = MPU6500_PRODUCT_REVISION;
523 chip_info->silicon_revision = MPU6500_PRODUCT_REVISION;
524 chip_info->software_revision = sw_rev;
525 chip_info->gyro_sens_trim = DEFAULT_GYRO_TRIM;
526 chip_info->accl_sens_trim = DEFAULT_ACCL_TRIM;
527 chip_info->multi = 1;
532 int inv_get_silicon_rev_mpu6050(struct inv_mpu_iio_s *st)
535 struct inv_reg_map_s *reg;
536 u8 prod_ver = 0x00, prod_rev = 0x00;
537 struct prod_rev_map_t *p_rev;
539 (BIT_PRFTCH_EN | BIT_CFG_USER_BANK | MPU_MEM_OTP_BANK_0);
540 u16 mem_addr = ((bank << 8) | MEM_ADDR_PROD_REV);
545 struct inv_chip_info_s *chip_info = &st->chip_info;
548 result = inv_i2c_read(st, REG_PRODUCT_ID, 1, &prod_ver);
552 /*memory read need more time after power up */
553 msleep(POWER_UP_TIME);
554 result = mpu_memory_read(st, st->i2c_addr, mem_addr,
559 /* clean the prefetch and cfg user bank bits */
560 result = inv_i2c_single_write(st, reg->bank_sel, 0);
563 /* get the software-product version, read from XA_OFFS_L */
564 result = inv_i2c_read(st, REG_XA_OFFS_L_TC,
565 SOFT_PROD_VER_BYTES, regs);
569 sw_rev = (regs[4] & 0x01) << 2 | /* 0x0b, bit 0 */
570 (regs[2] & 0x01) << 1 | /* 0x09, bit 0 */
571 (regs[0] & 0x01); /* 0x07, bit 0 */
572 /* if 0, use the product key to determine the type of part */
574 key = MPL_PROD_KEY(prod_ver, prod_rev);
577 index = index_of_key(key);
578 if (index < 0 || index >= NUM_OF_PROD_REVS)
580 /* check MPL is compiled for this device */
581 if (prod_rev_map[index].silicon_rev != MPU_SILICON_REV_B1)
583 p_rev = (struct prod_rev_map_t *)&prod_rev_map[index];
584 /* if valid, use the software product key */
585 } else if (sw_rev < ARRAY_SIZE(sw_rev_map)) {
586 p_rev = (struct prod_rev_map_t *)&sw_rev_map[sw_rev];
590 chip_info->product_id = prod_ver;
591 chip_info->product_revision = prod_rev;
592 chip_info->silicon_revision = p_rev->silicon_rev;
593 chip_info->software_revision = sw_rev;
594 chip_info->gyro_sens_trim = p_rev->gyro_trim;
595 chip_info->accl_sens_trim = p_rev->accel_trim;
596 if (chip_info->accl_sens_trim == 0)
597 chip_info->accl_sens_trim = DEFAULT_ACCL_TRIM;
598 chip_info->multi = DEFAULT_ACCL_TRIM / chip_info->accl_sens_trim;
599 if (chip_info->multi != 1)
600 pr_info("multi is %d\n", chip_info->multi);
605 * read_accel_hw_self_test_prod_shift()- read the accelerometer hardware
606 * self-test bias shift calculated
607 * during final production test and
608 * stored in chip non-volatile memory.
609 * @st: main data structure.
610 * @st_prod: A pointer to an array of 3 elements to hold the values
611 * for production hardware self-test bias shifts returned to the
613 * @accl_sens: accel sensitivity.
615 static int read_accel_hw_self_test_prod_shift(struct inv_mpu_iio_s *st,
616 int *st_prod, int *accl_sens)
622 for (i = 0; i < 3; i++)
625 result = inv_i2c_read(st, REG_ST_GCT_X, ARRAY_SIZE(regs), regs);
629 if ((0 == regs[0]) && (0 == regs[1]) &&
630 (0 == regs[2]) && (0 == regs[3]))
632 shift_code[X] = ((regs[0] & 0xE0) >> 3) | ((regs[3] & 0x30) >> 4);
633 shift_code[Y] = ((regs[1] & 0xE0) >> 3) | ((regs[3] & 0x0C) >> 2);
634 shift_code[Z] = ((regs[2] & 0xE0) >> 3) | (regs[3] & 0x03);
635 for (i = 0; i < 3; i++) {
636 if (shift_code[i] != 0)
637 st_prod[i] = accl_sens[i] *
638 accl_st_tb[shift_code[i] - 1];
645 * inv_check_accl_self_test()- check accel self test. this function returns
646 * zero as success. A non-zero return value
647 * indicates failure in self test.
648 * @*st: main data structure.
649 * @*reg_avg: average value of normal test.
650 * @*st_avg: average value of self test
652 static int inv_check_accl_self_test(struct inv_mpu_iio_s *st,
653 int *reg_avg, int *st_avg){
654 int gravity, reg_z_avg, g_z_sign, j, ret_val;
656 int st_shift_prod[THREE_AXIS], st_shift_cust[THREE_AXIS];
657 int st_shift_ratio[THREE_AXIS];
658 int accel_sens[THREE_AXIS];
660 if (st->chip_info.software_revision < DEF_OLDEST_SUPP_SW_REV &&
661 st->chip_info.product_revision < DEF_OLDEST_SUPP_PROD_REV)
665 tmp = DEF_ST_SCALE * DEF_ST_PRECISION / DEF_ST_ACCEL_FS_MG;
666 for (j = 0; j < 3; j++)
669 if (MPL_PROD_KEY(st->chip_info.product_id,
670 st->chip_info.product_revision) ==
671 MPU_PRODUCT_KEY_B1_E1_5) {
672 /* half sensitivity Z accelerometer parts */
675 /* half sensitivity X, Y, Z accelerometer parts */
676 accel_sens[X] /= st->chip_info.multi;
677 accel_sens[Y] /= st->chip_info.multi;
678 accel_sens[Z] /= st->chip_info.multi;
680 gravity = accel_sens[Z];
681 reg_z_avg = reg_avg[Z] - g_z_sign * gravity * DEF_ST_PRECISION;
682 ret_val = read_accel_hw_self_test_prod_shift(st, st_shift_prod,
687 for (j = 0; j < 3; j++) {
688 st_shift_cust[j] = abs(reg_avg[j] - st_avg[j]);
689 if (st_shift_prod[j]) {
690 tmp = st_shift_prod[j] / DEF_ST_PRECISION;
691 st_shift_ratio[j] = abs(st_shift_cust[j] / tmp
693 if (st_shift_ratio[j] > DEF_ACCEL_ST_SHIFT_DELTA)
696 if (st_shift_cust[j] <
697 DEF_ACCEL_ST_SHIFT_MIN * gravity)
699 if (st_shift_cust[j] >
700 DEF_ACCEL_ST_SHIFT_MAX * gravity)
709 * inv_check_3500_gyro_self_test() check gyro self test. this function returns
710 * zero as success. A non-zero return value
711 * indicates failure in self test.
712 * @*st: main data structure.
713 * @*reg_avg: average value of normal test.
714 * @*st_avg: average value of self test
717 static int inv_check_3500_gyro_self_test(struct inv_mpu_iio_s *st,
718 int *reg_avg, int *st_avg){
722 u8 st_code[THREE_AXIS];
725 for (i = 0; i < 3; i++)
726 gst[i] = st_avg[i] - reg_avg[i];
727 result = inv_i2c_read(st, REG_3500_OTP, THREE_AXIS, st_code);
733 for (i = 0; i < 3; i++) {
735 gst_otp[i] = gyro_3500_st_tb[st_code[i] - 1];
737 /* check self test value passing criterion. Using the DEF_ST_TOR
738 * for certain degree of tolerance */
739 for (i = 0; i < 3; i++) {
740 if (gst_otp[i] == 0) {
741 if (abs(gst[i]) * DEF_ST_TOR < DEF_ST_OTP0_THRESH *
746 if (abs(gst[i]/gst_otp[i] - DEF_ST_PRECISION) >
747 DEF_GYRO_CT_SHIFT_DELTA)
751 /* check for absolute value passing criterion. Using DEF_ST_TOR
752 * for certain degree of tolerance */
753 for (i = 0; i < 3; i++) {
754 if (abs(reg_avg[i]) > DEF_ST_TOR * DEF_ST_ABS_THRESH *
755 DEF_ST_PRECISION * DEF_GYRO_SCALE)
763 * inv_check_6050_gyro_self_test() - check 6050 gyro self test. this function
764 * returns zero as success. A non-zero return
765 * value indicates failure in self test.
766 * @*st: main data structure.
767 * @*reg_avg: average value of normal test.
768 * @*st_avg: average value of self test
770 static int inv_check_6050_gyro_self_test(struct inv_mpu_iio_s *st,
771 int *reg_avg, int *st_avg){
774 int st_shift_prod[3], st_shift_cust[3], st_shift_ratio[3], i;
777 if (st->chip_info.software_revision < DEF_OLDEST_SUPP_SW_REV &&
778 st->chip_info.product_revision < DEF_OLDEST_SUPP_PROD_REV)
782 result = inv_i2c_read(st, REG_ST_GCT_X, 3, regs);
788 for (i = 0; i < 3; i++) {
790 st_shift_prod[i] = gyro_6050_st_tb[regs[i] - 1];
792 st_shift_prod[i] = 0;
794 st_shift_prod[1] = -st_shift_prod[1];
796 for (i = 0; i < 3; i++) {
797 st_shift_cust[i] = st_avg[i] - reg_avg[i];
798 if (st_shift_prod[i]) {
799 st_shift_ratio[i] = abs(st_shift_cust[i] /
800 st_shift_prod[i] - DEF_ST_PRECISION);
801 if (st_shift_ratio[i] > DEF_GYRO_CT_SHIFT_DELTA)
804 if (st_shift_cust[i] < DEF_ST_PRECISION *
805 DEF_GYRO_CT_SHIFT_MIN * DEF_SELFTEST_GYRO_SENS)
807 if (st_shift_cust[i] > DEF_ST_PRECISION *
808 DEF_GYRO_CT_SHIFT_MAX * DEF_SELFTEST_GYRO_SENS)
812 /* check for absolute value passing criterion. Using DEF_ST_TOR
813 * for certain degree of tolerance */
814 for (i = 0; i < 3; i++)
815 if (abs(reg_avg[i]) > DEF_ST_TOR * DEF_ST_ABS_THRESH *
816 DEF_ST_PRECISION * DEF_GYRO_SCALE)
823 * inv_check_6500_gyro_self_test() - check 6500 gyro self test. this function
824 * returns zero as success. A non-zero return
825 * value indicates failure in self test.
826 * @*st: main data structure.
827 * @*reg_avg: average value of normal test.
828 * @*st_avg: average value of self test
830 static int inv_check_6500_gyro_self_test(struct inv_mpu_iio_s *st,
831 int *reg_avg, int *st_avg)
835 int otp_value_zero = 0;
836 int st_shift_prod[3], st_shift_cust[3], i;
839 result = inv_i2c_read(st, REG_6500_XG_ST_DATA, 3, regs);
842 pr_debug("%s self_test gyro shift_code - %02x %02x %02x\n",
843 st->hw->name, regs[0], regs[1], regs[2]);
845 for (i = 0; i < 3; i++) {
847 st_shift_prod[i] = mpu_6500_st_tb[regs[i] - 1];
849 st_shift_prod[i] = 0;
853 pr_debug("%s self_test gyro st_shift_prod - %+d %+d %+d\n",
854 st->hw->name, st_shift_prod[0], st_shift_prod[1],
857 for (i = 0; i < 3; i++) {
858 st_shift_cust[i] = st_avg[i] - reg_avg[i];
859 if (!otp_value_zero) {
860 /* Self Test Pass/Fail Criteria A */
861 if (st_shift_cust[i] < DEF_6500_GYRO_CT_SHIFT_DELTA
865 /* Self Test Pass/Fail Criteria B */
866 if (st_shift_cust[i] < DEF_GYRO_ST_AL *
867 DEF_SELFTEST_GYRO_SENS *
872 pr_debug("%s self_test gyro st_shift_cust - %+d %+d %+d\n",
873 st->hw->name, st_shift_cust[0], st_shift_cust[1],
877 /* Self Test Pass/Fail Criteria C */
878 for (i = 0; i < 3; i++)
879 if (abs(reg_avg[i]) > DEF_GYRO_OFFSET_MAX *
880 DEF_SELFTEST_GYRO_SENS *
889 * inv_check_6500_accel_self_test() - check 6500 accel self test. this function
890 * returns zero as success. A non-zero return
891 * value indicates failure in self test.
892 * @*st: main data structure.
893 * @*reg_avg: average value of normal test.
894 * @*st_avg: average value of self test
896 static int inv_check_6500_accel_self_test(struct inv_mpu_iio_s *st,
897 int *reg_avg, int *st_avg) {
899 int st_shift_prod[3], st_shift_cust[3], st_shift_ratio[3], i;
901 int otp_value_zero = 0;
903 #define ACCEL_ST_AL_MIN ((DEF_ACCEL_ST_AL_MIN * DEF_ST_SCALE \
904 / DEF_ST_6500_ACCEL_FS_MG) * DEF_ST_PRECISION)
905 #define ACCEL_ST_AL_MAX ((DEF_ACCEL_ST_AL_MAX * DEF_ST_SCALE \
906 / DEF_ST_6500_ACCEL_FS_MG) * DEF_ST_PRECISION)
909 result = inv_i2c_read(st, REG_6500_XA_ST_DATA, 3, regs);
912 pr_debug("%s self_test accel shift_code - %02x %02x %02x\n",
913 st->hw->name, regs[0], regs[1], regs[2]);
915 for (i = 0; i < 3; i++) {
917 st_shift_prod[i] = mpu_6500_st_tb[regs[i] - 1];
919 st_shift_prod[i] = 0;
923 pr_debug("%s self_test accel st_shift_prod - %+d %+d %+d\n",
924 st->hw->name, st_shift_prod[0], st_shift_prod[1],
927 if (!otp_value_zero) {
928 /* Self Test Pass/Fail Criteria A */
929 for (i = 0; i < 3; i++) {
930 st_shift_cust[i] = st_avg[i] - reg_avg[i];
931 st_shift_ratio[i] = abs(st_shift_cust[i] /
932 st_shift_prod[i] - DEF_ST_PRECISION);
933 if (st_shift_ratio[i] > DEF_6500_ACCEL_ST_SHIFT_DELTA)
937 /* Self Test Pass/Fail Criteria B */
938 for (i = 0; i < 3; i++) {
939 st_shift_cust[i] = abs(st_avg[i] - reg_avg[i]);
940 if (st_shift_cust[i] < ACCEL_ST_AL_MIN ||
941 st_shift_cust[i] > ACCEL_ST_AL_MAX)
945 pr_debug("%s self_test accel st_shift_cust - %+d %+d %+d\n",
946 st->hw->name, st_shift_cust[0], st_shift_cust[1],
953 * inv_do_test() - do the actual test of self testing
955 int inv_do_test(struct inv_mpu_iio_s *st, int self_test_flag,
956 int *gyro_result, int *accl_result)
958 struct inv_reg_map_s *reg;
959 int result, i, j, packet_size;
960 u8 data[BYTES_PER_SENSOR * 2], d;
962 int fifo_count, packet_count, ind, s;
965 has_accl = (st->chip_type != INV_ITG3500);
967 packet_size = BYTES_PER_SENSOR * 2;
969 packet_size = BYTES_PER_SENSOR;
971 result = inv_i2c_single_write(st, reg->int_enable, 0);
974 /* disable the sensor output to FIFO */
975 result = inv_i2c_single_write(st, reg->fifo_en, 0);
978 /* disable fifo reading */
979 result = inv_i2c_single_write(st, reg->user_ctrl, 0);
983 result = inv_i2c_single_write(st, reg->user_ctrl, BIT_FIFO_RST);
986 /* setup parameters */
987 result = inv_i2c_single_write(st, reg->lpf, INV_FILTER_98HZ);
991 if (INV_MPU6500 == st->chip_type) {
992 /* config accel LPF register for MPU6500 */
993 result = inv_i2c_single_write(st, REG_6500_ACCEL_CONFIG2,
994 DEF_ST_MPU6500_ACCEL_LPF |
1000 result = inv_i2c_single_write(st, reg->sample_rate_div,
1001 DEF_SELFTEST_SAMPLE_RATE);
1004 /* wait for the sampling rate change to stabilize */
1005 mdelay(INV_MPU_SAMPLE_RATE_CHANGE_STABLE);
1006 result = inv_i2c_single_write(st, reg->gyro_config,
1007 self_test_flag | DEF_SELFTEST_GYRO_FS);
1011 if (INV_MPU6500 == st->chip_type)
1012 d = DEF_SELFTEST_6500_ACCEL_FS;
1014 d = DEF_SELFTEST_ACCEL_FS;
1015 d |= self_test_flag;
1016 result = inv_i2c_single_write(st, reg->accl_config, d);
1020 /* wait for the output to get stable */
1021 if (self_test_flag) {
1022 if (INV_MPU6500 == st->chip_type)
1023 msleep(DEF_ST_6500_STABLE_TIME);
1025 msleep(DEF_ST_STABLE_TIME);
1028 /* enable FIFO reading */
1029 result = inv_i2c_single_write(st, reg->user_ctrl, BIT_FIFO_EN);
1032 /* enable sensor output to FIFO */
1034 d = BITS_GYRO_OUT | BIT_ACCEL_OUT;
1037 for (i = 0; i < THREE_AXIS; i++) {
1042 while (s < st->self_test.samples) {
1043 result = inv_i2c_single_write(st, reg->fifo_en, d);
1046 mdelay(DEF_GYRO_WAIT_TIME);
1047 result = inv_i2c_single_write(st, reg->fifo_en, 0);
1051 result = inv_i2c_read(st, reg->fifo_count_h,
1052 FIFO_COUNT_BYTE, data);
1055 fifo_count = be16_to_cpup((__be16 *)(&data[0]));
1056 pr_debug("%s self_test fifo_count - %d\n",
1057 st->hw->name, fifo_count);
1058 packet_count = fifo_count / packet_size;
1060 while ((i < packet_count) && (s < st->self_test.samples)) {
1062 result = inv_i2c_read(st, reg->fifo_r_w,
1068 for (j = 0; j < THREE_AXIS; j++) {
1069 vals[j] = (short)be16_to_cpup(
1070 (__be16 *)(&data[ind + 2 * j]));
1071 accl_result[j] += vals[j];
1073 ind += BYTES_PER_SENSOR;
1075 "%s self_test accel data - %d %+d %+d %+d",
1076 st->hw->name, s, vals[0], vals[1], vals[2]);
1079 for (j = 0; j < THREE_AXIS; j++) {
1080 vals[j] = (short)be16_to_cpup(
1081 (__be16 *)(&data[ind + 2 * j]));
1082 gyro_result[j] += vals[j];
1084 pr_debug("%s self_test gyro data - %d %+d %+d %+d",
1085 st->hw->name, s, vals[0], vals[1], vals[2]);
1093 for (j = 0; j < THREE_AXIS; j++) {
1094 accl_result[j] = accl_result[j] / s;
1095 accl_result[j] *= DEF_ST_PRECISION;
1098 for (j = 0; j < THREE_AXIS; j++) {
1099 gyro_result[j] = gyro_result[j] / s;
1100 gyro_result[j] *= DEF_ST_PRECISION;
1107 * inv_recover_setting() recover the old settings after everything is done
1109 void inv_recover_setting(struct inv_mpu_iio_s *st)
1111 struct inv_reg_map_s *reg;
1115 inv_i2c_single_write(st, reg->gyro_config,
1116 st->chip_config.fsr << GYRO_CONFIG_FSR_SHIFT);
1117 inv_i2c_single_write(st, reg->lpf, st->chip_config.lpf);
1118 data = ONE_K_HZ/st->chip_config.new_fifo_rate - 1;
1119 inv_i2c_single_write(st, reg->sample_rate_div, data);
1120 if (INV_ITG3500 != st->chip_type) {
1121 inv_i2c_single_write(st, reg->accl_config,
1122 (st->chip_config.accl_fs <<
1123 ACCL_CONFIG_FSR_SHIFT));
1125 st->switch_gyro_engine(st, false);
1126 st->switch_accl_engine(st, false);
1127 st->set_power_state(st, false);
1130 static int inv_check_compass_self_test(struct inv_mpu_iio_s *st)
1137 sens = st->chip_info.compass_sens;
1139 /* set to bypass mode */
1140 result = inv_i2c_single_write(st, REG_INT_PIN_CFG,
1141 st->plat_data.int_config | BIT_BYPASS_EN);
1143 result = inv_i2c_single_write(st, REG_INT_PIN_CFG,
1144 st->plat_data.int_config);
1147 /* set to power down mode */
1148 result = inv_secondary_write(REG_AKM_MODE, DATA_AKM_MODE_PD);
1152 /* write 1 to ASTC register */
1153 result = inv_secondary_write(REG_AKM_ST_CTRL, DATA_AKM_SELF_TEST);
1156 /* set self test mode */
1157 result = inv_secondary_write(REG_AKM_MODE, DATA_AKM_MODE_ST);
1160 counter = DEF_ST_COMPASS_TRY_TIMES;
1161 while (counter > 0) {
1162 usleep_range(DEF_ST_COMPASS_WAIT_MIN, DEF_ST_COMPASS_WAIT_MAX);
1163 result = inv_secondary_read(REG_AKM_STATUS, 1, data);
1166 if ((data[0] & DATA_AKM_DRDY) == 0)
1171 if ((data[0] & DATA_AKM_DRDY) == 0) {
1175 result = inv_secondary_read(REG_AKM_MEASURE_DATA,
1176 BYTES_PER_SENSOR, data);
1180 x = le16_to_cpup((__le16 *)(&data[0]));
1181 y = le16_to_cpup((__le16 *)(&data[2]));
1182 z = le16_to_cpup((__le16 *)(&data[4]));
1183 x = ((x * (sens[0] + 128)) >> 8);
1184 y = ((y * (sens[1] + 128)) >> 8);
1185 z = ((z * (sens[2] + 128)) >> 8);
1186 if (COMPASS_ID_AK8963 == st->plat_data.sec_slave_id) {
1187 result = inv_secondary_read(REG_AKM8963_CNTL1, 1, &cntl);
1190 if (0 == (cntl & DATA_AKM8963_BIT)) {
1191 x <<= DEF_ST_COMPASS_8963_SHIFT;
1192 y <<= DEF_ST_COMPASS_8963_SHIFT;
1193 z <<= DEF_ST_COMPASS_8963_SHIFT;
1197 if (x > st->compass_st_upper[X] || x < st->compass_st_lower[X])
1199 if (y > st->compass_st_upper[Y] || y < st->compass_st_lower[Y])
1201 if (z > st->compass_st_upper[Z] || z < st->compass_st_lower[Z])
1205 /*write 0 to ASTC register */
1206 result |= inv_secondary_write(REG_AKM_ST_CTRL, 0);
1207 /*set to power down mode */
1208 result |= inv_secondary_write(REG_AKM_MODE, DATA_AKM_MODE_PD);
1209 /*restore to non-bypass mode */
1210 result |= inv_i2c_single_write(st, REG_INT_PIN_CFG,
1211 st->plat_data.int_config);
1215 int inv_power_up_self_test(struct inv_mpu_iio_s *st)
1219 result = st->set_power_state(st, true);
1222 result = st->switch_accl_engine(st, true);
1225 result = st->switch_gyro_engine(st, true);
1233 * inv_hw_self_test() - main function to do hardware self test
1235 int inv_hw_self_test(struct inv_mpu_iio_s *st)
1238 int gyro_bias_st[THREE_AXIS], gyro_bias_regular[THREE_AXIS];
1239 int accl_bias_st[THREE_AXIS], accl_bias_regular[THREE_AXIS];
1241 char compass_result, accel_result, gyro_result;
1243 result = inv_power_up_self_test(st);
1249 test_times = DEF_ST_TRY_TIMES;
1250 while (test_times > 0) {
1251 result = inv_do_test(st, 0, gyro_bias_regular,
1253 if (result == -EAGAIN)
1261 test_times = DEF_ST_TRY_TIMES;
1262 while (test_times > 0) {
1263 result = inv_do_test(st, BITS_SELF_TEST_EN, gyro_bias_st,
1265 if (result == -EAGAIN)
1272 if (st->chip_type == INV_ITG3500) {
1273 gyro_result = !inv_check_3500_gyro_self_test(st,
1274 gyro_bias_regular, gyro_bias_st);
1276 if (st->chip_config.has_compass)
1277 compass_result = !inv_check_compass_self_test(st);
1279 if (INV_MPU6050 == st->chip_type) {
1280 accel_result = !inv_check_accl_self_test(st,
1281 accl_bias_regular, accl_bias_st);
1282 gyro_result = !inv_check_6050_gyro_self_test(st,
1283 gyro_bias_regular, gyro_bias_st);
1284 } else if (INV_MPU6500 == st->chip_type) {
1285 accel_result = !inv_check_6500_accel_self_test(st,
1286 accl_bias_regular, accl_bias_st);
1287 gyro_result = !inv_check_6500_gyro_self_test(st,
1288 gyro_bias_regular, gyro_bias_st);
1292 inv_recover_setting(st);
1294 return (compass_result << DEF_ST_COMPASS_RESULT_SHIFT) |
1295 (accel_result << DEF_ST_ACCEL_RESULT_SHIFT) | gyro_result;
1298 static int inv_load_firmware(struct inv_mpu_iio_s *st,
1301 int bank, write_size;
1305 /* Write and verify memory */
1306 for (bank = 0; size > 0; bank++,
1308 data += write_size) {
1309 if (size > MPU_MEM_BANK_SIZE)
1310 write_size = MPU_MEM_BANK_SIZE;
1314 memaddr = ((bank << 8) | 0x00);
1316 result = mem_w(memaddr, write_size, data);
1323 static int inv_verify_firmware(struct inv_mpu_iio_s *st,
1326 int bank, write_size;
1329 u8 firmware[MPU_MEM_BANK_SIZE];
1331 /* Write and verify memory */
1332 for (bank = 0; size > 0; bank++,
1334 data += write_size) {
1335 if (size > MPU_MEM_BANK_SIZE)
1336 write_size = MPU_MEM_BANK_SIZE;
1340 memaddr = ((bank << 8) | 0x00);
1341 result = mpu_memory_read(st,
1342 st->i2c_addr, memaddr, write_size, firmware);
1345 if (0 != memcmp(firmware, data, write_size))
1351 static int inv_set_fifo_div(struct inv_mpu_iio_s *st,
1356 /*For some reason DINAC4 is defined as 0xb8, but DINBC4 is not*/
1357 const u8 regs_end[] = {DINAFE, DINAF2, DINAAB, 0xc4,
1358 DINAAA, DINAF1, DINADF, DINADF,
1359 0xbb, 0xaf, DINADF, DINADF};
1361 regs[0] = (u8)((fifoRate >> 8) & 0xff);
1362 regs[1] = (u8)(fifoRate & 0xff);
1363 result = mem_w_key(KEY_D_0_22, ARRAY_SIZE(regs), regs);
1367 /*Modify the FIFO handler to reset the tap/orient interrupt flags*/
1368 /* each time the FIFO handler runs*/
1369 result = mem_w_key(KEY_CFG_6, ARRAY_SIZE(regs_end), regs_end);
1374 int inv_send_quaternion(struct inv_mpu_iio_s *st, bool on)
1376 const u8 regs_on[] = {DINBC0, DINBC2,
1378 const u8 regs_off[] = {DINA80, DINA80,
1386 result = mem_w_key(KEY_CFG_LP_QUAT, ARRAY_SIZE(regs_on), regs);
1391 int inv_set_display_orient_interrupt_dmp(struct inv_mpu_iio_s *st,
1394 /*Turn on the display orientation interrupt in the DMP*/
1400 result = mem_w_key(KEY_CFG_DISPLAY_ORIENT_INT, 1, regs);
1404 int inv_set_fifo_rate(struct inv_mpu_iio_s *st, u16 fifo_rate)
1409 divider = (u8)(ONE_K_HZ / fifo_rate) - 1;
1410 if (divider > DMP_MAX_DIVIDER) {
1411 st->sample_divider = DMP_MAX_DIVIDER;
1413 (u8)(DMP_DEFAULT_FIFO_RATE / fifo_rate) - 1;
1415 st->sample_divider = divider;
1416 st->fifo_divider = 0;
1419 result = inv_set_fifo_div(st, st->fifo_divider);
1423 static int inv_set_tap_interrupt_dmp(struct inv_mpu_iio_s *st,
1433 result = mem_w_key(KEY_CFG_20, ARRAY_SIZE(regs), regs);
1439 int inv_set_tap_threshold_dmp(struct inv_mpu_iio_s *st,
1440 u32 axis, u16 threshold)
1442 /* Sets the tap threshold in the dmp
1443 Simultaneously sets secondary tap threshold to help correct the tap
1444 direction for soft taps */
1449 int scaledThreshold;
1452 const u32 accel_sens = (0x20000000 / 0x00010000);
1454 if ((axis & ~(INV_TAP_AXIS_ALL)) || (threshold > (1 << 15)))
1456 sample_div = st->sample_divider;
1458 sampleDivider = (1 + sample_div);
1459 /* Scale factor corresponds linearly using
1468 /*multiply by 1000 to avoid floating point 1000/1000*/
1469 scaledThreshold = threshold;
1470 /* Convert to per sample */
1471 scaledThreshold *= sampleDivider;
1473 /* Scale to DMP 16 bit value */
1474 if (accel_sens != 0)
1475 dmpThreshold = (u32)(scaledThreshold * accel_sens);
1478 dmpThreshold = dmpThreshold / DMP_PRECISION;
1480 data[0] = dmpThreshold >> 8;
1481 data[1] = dmpThreshold & 0xFF;
1484 if (axis & INV_TAP_AXIS_X) {
1485 result = mem_w_key(KEY_DMP_TAP_THR_X, ARRAY_SIZE(data), data);
1489 /*Also set additional threshold for correcting the direction
1490 of taps that were very near the threshold. */
1491 data[0] = (dmpThreshold * 3 / 4) >> 8;
1492 data[1] = (dmpThreshold * 3 / 4) & 0xFF;
1493 result = mem_w_key(KEY_D_1_36, ARRAY_SIZE(data), data);
1497 if (axis & INV_TAP_AXIS_Y) {
1498 result = mem_w_key(KEY_DMP_TAP_THR_Y, 2, data);
1501 data[0] = (dmpThreshold * 3 / 4) >> 8;
1502 data[1] = (dmpThreshold * 3 / 4) & 0xFF;
1504 result = mem_w_key(KEY_D_1_40, ARRAY_SIZE(data), data);
1508 if (axis & INV_TAP_AXIS_Z) {
1509 result = mem_w_key(KEY_DMP_TAP_THR_Z, ARRAY_SIZE(data), data);
1512 data[0] = (dmpThreshold * 3 / 4) >> 8;
1513 data[1] = (dmpThreshold * 3 / 4) & 0xFF;
1515 result = mem_w_key(KEY_D_1_44, ARRAY_SIZE(data), data);
1522 static int inv_set_tap_axes_dmp(struct inv_mpu_iio_s *st,
1525 /* Sets a mask in the DMP that indicates what tap events
1526 should result in an interrupt */
1530 /* check if any spurious bit other the ones expected are set */
1531 if (axes & (~(INV_TAP_ALL_DIRECTIONS)))
1535 result = mem_w_key(KEY_D_1_72, 1, regs);
1540 int inv_set_min_taps_dmp(struct inv_mpu_iio_s *st,
1542 /*Indicates the minimum number of consecutive taps required
1543 before the DMP will generate an interrupt */
1546 /* check if any spurious bit other the ones expected are set */
1547 if ((min_taps > DMP_MAX_MIN_TAPS) || (min_taps < 1))
1549 regs[0] = (u8)(min_taps-1);
1550 result = mem_w_key(KEY_D_1_79, ARRAY_SIZE(regs), regs);
1555 int inv_set_tap_time_dmp(struct inv_mpu_iio_s *st, u16 time)
1557 /* Determines how long after a tap the DMP requires before
1558 another tap can be registered*/
1565 sampleDivider = st->sample_divider;
1568 /* 60 ms minimum time added */
1569 dmpTime = ((time) / sampleDivider);
1570 data[0] = dmpTime >> 8;
1571 data[1] = dmpTime & 0xFF;
1573 result = mem_w_key(KEY_DMP_TAPW_MIN, ARRAY_SIZE(data), data);
1578 static int inv_set_multiple_tap_time_dmp(struct inv_mpu_iio_s *st,
1581 /*Determines how close together consecutive taps must occur
1582 to be considered double/triple taps*/
1589 sampleDivider = st->sample_divider;
1592 /* 60 ms minimum time added */
1593 dmpTime = ((time) / sampleDivider);
1594 data[0] = dmpTime >> 8;
1595 data[1] = dmpTime & 0xFF;
1596 result = mem_w_key(KEY_D_1_218, ARRAY_SIZE(data), data);
1601 int inv_q30_mult(int a, int b)
1607 result = (int)(temp >> DMP_MULTI_SHIFT);
1612 static u16 inv_row_2_scale(const s8 *row)
1618 else if (row[0] < 0)
1620 else if (row[1] > 0)
1622 else if (row[1] < 0)
1624 else if (row[2] > 0)
1626 else if (row[2] < 0)
1634 /** Converts an orientation matrix made up of 0,+1,and -1 to a scalar
1636 * @param[in] mtx Orientation matrix to convert to a scalar.
1637 * @return Description of orientation matrix. The lowest 2 bits (0 and 1)
1638 * represent the column the one is on for the
1639 * first row, with the bit number 2 being the sign. The next 2 bits
1640 * (3 and 4) represent
1641 * the column the one is on for the second row with bit number 5 being
1643 * The next 2 bits (6 and 7) represent the column the one is on for the
1645 * bit number 8 being the sign. In binary the identity matrix would therefor
1646 * be: 010_001_000 or 0x88 in hex.
1648 static u16 inv_orientation_matrix_to_scaler(const signed char *mtx)
1652 scalar = inv_row_2_scale(mtx);
1653 scalar |= inv_row_2_scale(mtx + 3) << 3;
1654 scalar |= inv_row_2_scale(mtx + 6) << 6;
1659 static int inv_disable_gyro_cal(struct inv_mpu_iio_s *st)
1662 0xb8, 0xaa, 0xaa, 0xaa,
1663 0xb0, 0x88, 0xc3, 0xc5,
1666 return mem_w_key(KEY_CFG_MOTION_BIAS, ARRAY_SIZE(regs), regs);
1670 static int inv_gyro_dmp_cal(struct inv_mpu_iio_s *st)
1672 int inv_gyro_orient;
1681 inv_orientation_matrix_to_scaler(st->plat_data.orientation);
1683 if ((inv_gyro_orient & 3) == 0)
1685 else if ((inv_gyro_orient & 3) == 1)
1687 else if ((inv_gyro_orient & 3) == 2)
1689 if ((inv_gyro_orient & 0x18) == 0)
1691 else if ((inv_gyro_orient & 0x18) == 0x8)
1693 else if ((inv_gyro_orient & 0x18) == 0x10)
1695 if ((inv_gyro_orient & 0xc0) == 0)
1697 else if ((inv_gyro_orient & 0xc0) == 0x40)
1699 else if ((inv_gyro_orient & 0xc0) == 0x80)
1702 result = mem_w_key(KEY_FCFG_1, ARRAY_SIZE(regs), regs);
1706 if (inv_gyro_orient & 4)
1707 regs[0] = DINA36 | 1;
1710 if (inv_gyro_orient & 0x20)
1711 regs[1] = DINA56 | 1;
1714 if (inv_gyro_orient & 0x100)
1715 regs[2] = DINA76 | 1;
1719 result = mem_w_key(KEY_FCFG_3, ARRAY_SIZE(regs), regs);
1724 static int inv_accel_dmp_cal(struct inv_mpu_iio_s *st)
1726 int inv_accel_orient;
1729 const u8 tmp[3] = { DINA0C, DINAC9, DINA2C };
1731 inv_orientation_matrix_to_scaler(st->plat_data.orientation);
1733 regs[0] = tmp[inv_accel_orient & 3];
1734 regs[1] = tmp[(inv_accel_orient >> 3) & 3];
1735 regs[2] = tmp[(inv_accel_orient >> 6) & 3];
1736 result = mem_w_key(KEY_FCFG_2, ARRAY_SIZE(regs), regs);
1743 if (inv_accel_orient & 4)
1745 if (inv_accel_orient & 0x20)
1747 if (inv_accel_orient & 0x100)
1749 result = mem_w_key(KEY_FCFG_7, ARRAY_SIZE(regs), regs);
1754 static u16 inv_orientation_matrix_to_scalar(const s8 *mtx)
1760 XYZ 010_001_000 Identity Matrix
1768 scalar = inv_row_2_scale(mtx);
1769 scalar |= inv_row_2_scale(mtx + 3) << 3;
1770 scalar |= inv_row_2_scale(mtx + 6) << 6;
1775 int inv_set_accel_bias_dmp(struct inv_mpu_iio_s *st)
1777 int inv_accel_orient, result, i, accel_bias_body[3], out[3];
1778 int tmp[] = {1, 1, 1};
1779 int mask[] = {4, 0x20, 0x100};
1780 int accel_sf = 0x20000000;/* 536870912 */
1784 inv_orientation_matrix_to_scalar(st->plat_data.orientation);
1786 for (i = 0; i < 3; i++)
1787 if (inv_accel_orient & mask[i])
1790 for (i = 0; i < 3; i++)
1791 accel_bias_body[i] = st->input_accel_bias[(inv_accel_orient >>
1792 (i * 3)) & 3] * tmp[i];
1793 for (i = 0; i < 3; i++)
1794 accel_bias_body[i] = inv_q30_mult(accel_sf,
1795 accel_bias_body[i]);
1796 for (i = 0; i < 3; i++)
1797 out[i] = cpu_to_be32p(&accel_bias_body[i]);
1799 result = mem_w_key(KEY_D_ACCEL_BIAS, sizeof(out), regs);
1804 static int inv_set_gyro_sf_dmp(struct inv_mpu_iio_s *st)
1806 /*The gyro threshold, in dps, above which taps will be rejected*/
1811 const u32 gyro_sens = 0x03e80000;
1813 sampleDivider = st->sample_divider;
1814 gyro_sf = inv_q30_mult(gyro_sens,
1815 (int)(DMP_TAP_SCALE * (sampleDivider + 1)));
1816 result = write_be32_key_to_mem(st, gyro_sf, KEY_D_0_104);
1821 static int inv_set_shake_reject_thresh_dmp(struct inv_mpu_iio_s *st,
1823 { /*THIS FUNCTION FAILS MEM_W*/
1824 /*The gyro threshold, in dps, above which taps will be rejected */
1830 const u32 gyro_sens = 0x03e80000;
1831 sampleDivider = st->sample_divider;
1832 gyro_sf = inv_q30_mult(gyro_sens, (int)(DMP_TAP_SCALE *
1833 (sampleDivider + 1)));
1834 /* We're in units of DPS, convert it back to chip units*/
1835 /*split the operation to aviod overflow of integer*/
1836 thresh_scaled = gyro_sens / (1L << 16);
1837 thresh_scaled = thresh_scaled / thresh;
1838 thresh_scaled = gyro_sf / thresh_scaled;
1839 result = write_be32_key_to_mem(st, thresh_scaled, KEY_D_1_92);
1844 static int inv_set_shake_reject_time_dmp(struct inv_mpu_iio_s *st,
1847 /* How long a gyro axis must remain above its threshold
1848 before taps are rejected */
1855 sampleDivider = st->sample_divider;
1858 /* 60 ms minimum time added */
1859 dmpTime = ((time) / sampleDivider);
1860 data[0] = dmpTime >> 8;
1861 data[1] = dmpTime & 0xFF;
1863 result = mem_w_key(KEY_D_1_88, ARRAY_SIZE(data), data);
1867 static int inv_set_shake_reject_timeout_dmp(struct inv_mpu_iio_s *st,
1870 /*How long the gyros must remain below their threshold,
1871 after taps have been rejected, before taps can be detected again*/
1878 sampleDivider = st->sample_divider;
1881 /* 60 ms minimum time added */
1882 dmpTime = ((time) / sampleDivider);
1883 data[0] = dmpTime >> 8;
1884 data[1] = dmpTime & 0xFF;
1886 result = mem_w_key(KEY_D_1_90, ARRAY_SIZE(data), data);
1890 int inv_set_interrupt_on_gesture_event(struct inv_mpu_iio_s *st, bool on)
1893 const u8 regs_on[] = {DINADA, DINAB1, DINAB9,
1894 DINAF3, DINA8B, DINAA3, DINA91,
1895 DINAB6, DINADA, DINAB4, DINADA};
1896 const u8 regs_off[] = {0xd8, 0xb1, 0xb9, 0xf3, 0x8b,
1897 0xa3, 0x91, 0xb6, 0x09, 0xb4, 0xd9};
1898 /*For some reason DINAC4 is defined as 0xb8,
1899 but DINBC4 is not defined.*/
1900 const u8 regs_end[] = {DINAFE, DINAF2, DINAAB, 0xc4,
1901 DINAAA, DINAF1, DINADF, DINADF,
1902 0xbb, 0xaf, DINADF, DINADF};
1903 const u8 regs[] = {0, 0};
1904 /* reset fifo count to zero */
1905 result = mem_w_key(KEY_D_1_178, ARRAY_SIZE(regs), regs);
1910 /*Sets the DMP to send an interrupt and put a FIFO packet
1911 in the FIFO if and only if a tap/orientation event
1913 result = mem_w_key(KEY_CFG_FIFO_ON_EVENT, ARRAY_SIZE(regs_on),
1916 /*Sets the DMP to send an interrupt and put a FIFO packet
1917 in the FIFO at the rate specified by the FIFO div.
1918 see inv_set_fifo_div in hw_setup.c to set the FIFO div.*/
1919 result = mem_w_key(KEY_CFG_FIFO_ON_EVENT, ARRAY_SIZE(regs_off),
1924 result = mem_w_key(KEY_CFG_6, ARRAY_SIZE(regs_end), regs_end);
1930 * inv_enable_tap_dmp() - calling this function will enable/disable tap function.
1932 int inv_enable_tap_dmp(struct inv_mpu_iio_s *st, bool on)
1936 result = inv_set_tap_interrupt_dmp(st, on);
1940 result = inv_set_tap_threshold_dmp(st, INV_TAP_AXIS_X,
1944 result = inv_set_tap_threshold_dmp(st, INV_TAP_AXIS_Y,
1948 result = inv_set_tap_threshold_dmp(st, INV_TAP_AXIS_Z,
1954 result = inv_set_tap_axes_dmp(st, INV_TAP_ALL_DIRECTIONS);
1957 result = inv_set_min_taps_dmp(st, st->tap.min_count);
1961 result = inv_set_tap_time_dmp(st, st->tap.time);
1965 result = inv_set_multiple_tap_time_dmp(st, DMP_MULTI_TAP_TIME);
1969 result = inv_set_gyro_sf_dmp(st);
1973 result = inv_set_shake_reject_thresh_dmp(st, DMP_SHAKE_REJECT_THRESH);
1977 result = inv_set_shake_reject_time_dmp(st, DMP_SHAKE_REJECT_TIME);
1981 result = inv_set_shake_reject_timeout_dmp(st,
1982 DMP_SHAKE_REJECT_TIMEOUT);
1986 int inv_send_sensor_data(struct inv_mpu_iio_s *st, u16 elements)
1989 u8 regs[] = {DINAA0 + 3, DINAA0 + 3, DINAA0 + 3,
1990 DINAA0 + 3, DINAA0 + 3, DINAA0 + 3,
1991 DINAA0 + 3, DINAA0 + 3, DINAA0 + 3,
1994 if (elements & INV_ELEMENT_1)
1996 if (elements & INV_ELEMENT_2)
1998 if (elements & INV_ELEMENT_3)
2000 if (elements & INV_ELEMENT_4)
2002 if ((elements & INV_ELEMENT_5) || (elements & INV_ELEMENT_6) ||
2003 (elements & INV_ELEMENT_7)) {
2008 result = mem_w_key(KEY_CFG_15, ARRAY_SIZE(regs), regs);
2012 int inv_send_interrupt_word(struct inv_mpu_iio_s *st, bool on)
2014 const u8 regs_on[] = { DINA20 };
2015 const u8 regs_off[] = { DINAA3 };
2019 result = mem_w_key(KEY_CFG_27, ARRAY_SIZE(regs_on), regs_on);
2021 result = mem_w_key(KEY_CFG_27, ARRAY_SIZE(regs_off), regs_off);
2027 * inv_dmp_firmware_write() - calling this function will load the firmware.
2028 * This is the write function of file "dmp_firmware".
2030 ssize_t inv_dmp_firmware_write(struct file *fp, struct kobject *kobj,
2031 struct bin_attribute *attr,
2032 char *buf, loff_t pos, size_t size)
2036 struct inv_reg_map_s *reg;
2037 struct iio_dev *indio_dev;
2038 struct inv_mpu_iio_s *st;
2040 indio_dev = dev_get_drvdata(container_of(kobj, struct device, kobj));
2041 st = iio_priv(indio_dev);
2043 if (st->chip_config.firmware_loaded)
2045 if (st->chip_config.enable)
2049 if (DMP_IMAGE_SIZE != size) {
2050 pr_err("wrong DMP image size\n");
2054 firmware = kmalloc(size, GFP_KERNEL);
2058 mutex_lock(&indio_dev->mlock);
2060 memcpy(firmware, buf, size);
2061 result = crc32(CRC_FIRMWARE_SEED, firmware, size);
2062 if (DMP_IMAGE_CRC_VALUE != result) {
2063 pr_err("firmware CRC error - 0x%08x vs 0x%08x\n",
2064 result, DMP_IMAGE_CRC_VALUE);
2066 goto firmware_write_fail;
2069 result = st->set_power_state(st, true);
2071 goto firmware_write_fail;
2073 result = inv_load_firmware(st, firmware, size);
2075 goto firmware_write_fail;
2077 result = inv_verify_firmware(st, firmware, size);
2079 goto firmware_write_fail;
2081 result = inv_i2c_single_write(st, reg->prgm_strt_addrh,
2082 st->chip_config.prog_start_addr >> 8);
2084 goto firmware_write_fail;
2085 result = inv_i2c_single_write(st, reg->prgm_strt_addrh + 1,
2086 st->chip_config.prog_start_addr & 0xff);
2088 goto firmware_write_fail;
2090 result = inv_set_fifo_rate(st, DMP_DEFAULT_FIFO_RATE);
2092 goto firmware_write_fail;
2093 result = inv_gyro_dmp_cal(st);
2095 goto firmware_write_fail;
2096 result = inv_accel_dmp_cal(st);
2098 goto firmware_write_fail;
2099 /* result = inv_disable_gyro_cal(st);*/
2101 goto firmware_write_fail;
2103 st->chip_config.firmware_loaded = 1;
2105 firmware_write_fail:
2106 result |= st->set_power_state(st, false);
2107 mutex_unlock(&indio_dev->mlock);
2114 ssize_t inv_dmp_firmware_read(struct file *filp,
2115 struct kobject *kobj,
2116 struct bin_attribute *bin_attr,
2117 char *buf, loff_t off, size_t count)
2119 int bank, write_size, size, data, result;
2121 struct iio_dev *indio_dev;
2122 struct inv_mpu_iio_s *st;
2125 indio_dev = dev_get_drvdata(container_of(kobj, struct device, kobj));
2126 st = iio_priv(indio_dev);
2129 mutex_lock(&indio_dev->mlock);
2130 if (!st->chip_config.enable) {
2131 result = st->set_power_state(st, true);
2133 mutex_unlock(&indio_dev->mlock);
2137 for (bank = 0; size > 0; bank++, size -= write_size,
2138 data += write_size) {
2139 if (size > MPU_MEM_BANK_SIZE)
2140 write_size = MPU_MEM_BANK_SIZE;
2144 memaddr = (bank << 8);
2145 result = mpu_memory_read(st,
2146 st->i2c_addr, memaddr, write_size, &buf[data]);
2148 mutex_unlock(&indio_dev->mlock);
2152 if (!st->chip_config.enable)
2153 result = st->set_power_state(st, false);
2154 mutex_unlock(&indio_dev->mlock);