drivers/soc/rockchip/rk_fiq_debugger.c

   1 /*
   2  * drivers/soc/rockchip/rk_fiq_debugger.c
   3  *
   4  * Serial Debugger Interface for Rockchip
   5  *
   6  * Copyright (C) 2012 ROCKCHIP, Inc.
   7  * Copyright (C) 2008 Google, Inc.
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <stdarg.h>
  20 #include <linux/module.h>
  21 #include <linux/io.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/clk.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/irq.h>
  29 #include <linux/serial_reg.h>
  30 #include <linux/slab.h>
  31 #include <linux/stacktrace.h>
  32 #include <linux/uaccess.h>
  33 #include <linux/kfifo.h>
  34 #include <linux/kthread.h>
  35 #include <linux/sched/rt.h>
  36 #include <../drivers/staging/android/fiq_debugger/fiq_debugger.h>
  37 #include <linux/irqchip/arm-gic.h>
  38 #include <linux/clk.h>
  39 #include <linux/delay.h>
  40 #include <linux/soc/rockchip/rk_fiq_debugger.h>
  41
  42 #ifdef CONFIG_FIQ_DEBUGGER_EL3_TO_EL1
  43 #include "linux/rockchip/psci.h"
  44 #endif
  45
  46 #define UART_USR        0x1f    /* In: UART Status Register */
  47 #define UART_USR_RX_FIFO_FULL           0x10 /* Receive FIFO full */
  48 #define UART_USR_RX_FIFO_NOT_EMPTY      0x08 /* Receive FIFO not empty */
  49 #define UART_USR_TX_FIFO_EMPTY          0x04 /* Transmit FIFO empty */
  50 #define UART_USR_TX_FIFO_NOT_FULL       0x02 /* Transmit FIFO not full */
  51 #define UART_USR_BUSY                   0x01 /* UART busy indicator */
  52 #define UART_SRR                        0x22 /* software reset register */
  53
  54 struct rk_fiq_debugger {
  55         int irq;
  56         int baudrate;
  57         struct fiq_debugger_pdata pdata;
  58         void __iomem *debug_port_base;
  59         bool break_seen;
  60 #ifdef CONFIG_RK_CONSOLE_THREAD
  61         struct task_struct *console_task;
  62 #endif
  63 };
  64
  65 static inline void rk_fiq_write(struct rk_fiq_debugger *t,
  66         unsigned int val, unsigned int off)
  67 {
  68         __raw_writel(val, t->debug_port_base + off * 4);
  69 }
  70
  71 static inline unsigned int rk_fiq_read(struct rk_fiq_debugger *t,
  72         unsigned int off)
  73 {
  74         return __raw_readl(t->debug_port_base + off * 4);
  75 }
  76
  77 static inline unsigned int rk_fiq_read_lsr(struct rk_fiq_debugger *t)
  78 {
  79         unsigned int lsr;
  80
  81         lsr = rk_fiq_read(t, UART_LSR);
  82         if (lsr & UART_LSR_BI)
  83                 t->break_seen = true;
  84
  85         return lsr;
  86 }
  87
  88 static int debug_port_init(struct platform_device *pdev)
  89 {
  90         int dll = 0, dlm = 0;
  91         struct rk_fiq_debugger *t;
  92
  93         t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
  94
  95         if (rk_fiq_read(t, UART_LSR) & UART_LSR_DR)
  96                 (void)rk_fiq_read(t, UART_RX);
  97
  98         switch (t->baudrate) {
  99         case 1500000:
 100                 dll = 0x1;
 101                 break;
 102         case 115200:
 103         default:
 104                 dll = 0xd;
 105                 break;
 106         }
 107         /* reset uart */
 108         rk_fiq_write(t, 0x07, UART_SRR);
 109         udelay(10);
 110         /* set uart to loop back mode */
 111         rk_fiq_write(t, 0x10, UART_MCR);
 112
 113         rk_fiq_write(t, 0x83, UART_LCR);
 114         /* set baud rate */
 115         rk_fiq_write(t, dll, UART_DLL);
 116         rk_fiq_write(t, dlm, UART_DLM);
 117         rk_fiq_write(t, 0x03, UART_LCR);
 118
 119         /* enable rx and lsr interrupt */
 120         rk_fiq_write(t, UART_IER_RLSI | UART_IER_RDI, UART_IER);
 121         /* interrupt on every character when receive,but we can enable fifo for TX
 122         I found that if we enable the RX fifo, some problem may vanish such as when
 123         you continuously input characters in the command line the uart irq may be disable
 124         because of the uart irq is served when CPU is at IRQ exception,but it is
 125         found unregistered, so it is disable.
 126         hhb@rock-chips.com */
 127         rk_fiq_write(t, 0xc1, UART_FCR);
 128         rk_fiq_write(t, 0x0, UART_MCR);
 129
 130         return 0;
 131 }
 132
 133 static int debug_getc(struct platform_device *pdev)
 134 {
 135         unsigned int lsr;
 136         struct rk_fiq_debugger *t;
 137         unsigned int temp;
 138         static unsigned int n;
 139         static char buf[32];
 140
 141         t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
 142
 143         lsr = rk_fiq_read_lsr(t);
 144
 145         if (lsr & UART_LSR_BI || t->break_seen) {
 146                 t->break_seen = false;
 147                 return FIQ_DEBUGGER_NO_CHAR;
 148         }
 149
 150         if (lsr & UART_LSR_DR) {
 151                 temp = rk_fiq_read(t, UART_RX);
 152                 buf[n & 0x1f] = temp;
 153                 n++;
 154                 if (temp == 'q' && n > 2) {
 155                         if ((buf[(n - 2) & 0x1f] == 'i') &&
 156                             (buf[(n - 3) & 0x1f] == 'f'))
 157                                 return FIQ_DEBUGGER_BREAK;
 158                         else
 159                                 return temp;
 160                 } else {
 161                         return temp;
 162                 }
 163         }
 164
 165         return FIQ_DEBUGGER_NO_CHAR;
 166 }
 167
 168 static void debug_putc(struct platform_device *pdev, unsigned int c)
 169 {
 170         struct rk_fiq_debugger *t;
 171
 172         t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
 173
 174         while (!(rk_fiq_read(t, UART_USR) & UART_USR_TX_FIFO_NOT_FULL))
 175                 cpu_relax();
 176         rk_fiq_write(t, c, UART_TX);
 177 }
 178
 179 static void debug_flush(struct platform_device *pdev)
 180 {
 181         struct rk_fiq_debugger *t;
 182         t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
 183
 184         while (!(rk_fiq_read_lsr(t) & UART_LSR_TEMT))
 185                 cpu_relax();
 186 }
 187
 188 static int uart_dev_resume(struct platform_device *pdev)
 189 {
 190         debug_port_init(pdev);
 191         return 0;
 192 }
 193
 194 #ifdef CONFIG_RK_CONSOLE_THREAD
 195 #define FIFO_SIZE SZ_64K
 196 static DEFINE_KFIFO(fifo, unsigned char, FIFO_SIZE);
 197 static bool console_thread_stop;
 198
 199 static int console_thread(void *data)
 200 {
 201         struct platform_device *pdev = data;
 202         struct rk_fiq_debugger *t;
 203         unsigned char c;
 204         t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
 205
 206         while (1) {
 207                 set_current_state(TASK_INTERRUPTIBLE);
 208                 schedule();
 209                 if (kthread_should_stop())
 210                         break;
 211                 set_current_state(TASK_RUNNING);
 212                 while (!console_thread_stop && kfifo_get(&fifo, &c))
 213                         debug_putc(pdev, c);
 214                 if (!console_thread_stop)
 215                         debug_flush(pdev);
 216         }
 217
 218         return 0;
 219 }
 220
 221 static void console_write(struct platform_device *pdev, const char *s, unsigned int count)
 222 {
 223         unsigned int fifo_count = FIFO_SIZE;
 224         unsigned char c, r = '\r';
 225         struct rk_fiq_debugger *t;
 226         t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
 227
 228         if (console_thread_stop ||
 229             oops_in_progress ||
 230             system_state == SYSTEM_HALT ||
 231             system_state == SYSTEM_POWER_OFF ||
 232             system_state == SYSTEM_RESTART) {
 233                 if (!console_thread_stop) {
 234                         console_thread_stop = true;
 235                         smp_wmb();
 236                         debug_flush(pdev);
 237                         while (fifo_count-- && kfifo_get(&fifo, &c))
 238                                 debug_putc(pdev, c);
 239                 }
 240                 while (count--) {
 241                         if (*s == '\n') {
 242                                 debug_putc(pdev, r);
 243                         }
 244                         debug_putc(pdev, *s++);
 245                 }
 246                 debug_flush(pdev);
 247         } else {
 248                 while (count--) {
 249                         if (*s == '\n') {
 250                                 kfifo_put(&fifo, r);
 251                         }
 252                         kfifo_put(&fifo, *s++);
 253                 }
 254                 wake_up_process(t->console_task);
 255         }
 256 }
 257 #endif
 258
 259
 260 static void fiq_enable(struct platform_device *pdev, unsigned int irq, bool on)
 261 {
 262         if (on)
 263                 enable_irq(irq);
 264         else
 265                 disable_irq(irq);
 266 }
 267
 268 #ifdef CONFIG_FIQ_DEBUGGER_EL3_TO_EL1
 269 static struct pt_regs fiq_pt_regs;
 270
 271 static void rk_fiq_debugger_switch_cpu(struct platform_device *pdev,
 272                                        unsigned int cpu)
 273 {
 274         psci_fiq_debugger_switch_cpu(cpu);
 275 }
 276
 277 static void rk_fiq_debugger_enable_debug(struct platform_device *pdev, bool val)
 278 {
 279         psci_fiq_debugger_enable_debug(val);
 280 }
 281
 282 static void fiq_debugger_uart_irq_tf(void *reg_base, u64 sp_el1)
 283 {
 284         memcpy(&fiq_pt_regs, reg_base, 8*31);
 285
 286         memcpy(&fiq_pt_regs.pstate, reg_base + 0x110, 8);
 287         if (fiq_pt_regs.pstate & 0x10)
 288                 memcpy(&fiq_pt_regs.sp, reg_base + 0xf8, 8);
 289         else
 290                 fiq_pt_regs.sp = sp_el1;
 291
 292         memcpy(&fiq_pt_regs.pc, reg_base + 0x118, 8);
 293
 294         fiq_debugger_fiq(&fiq_pt_regs);
 295 }
 296
 297 static int fiq_debugger_uart_dev_resume(struct platform_device *pdev)
 298 {
 299         struct rk_fiq_debugger *t;
 300
 301         t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
 302         psci_fiq_debugger_uart_irq_tf_init(t->irq, fiq_debugger_uart_irq_tf);
 303         return 0;
 304 }
 305 #endif
 306
 307 static int rk_fiq_debugger_id;
 308
 309 void rk_serial_debug_init(void __iomem *base, int irq, int signal_irq,
 310                           int wakeup_irq, unsigned int baudrate)
 311 {
 312         struct rk_fiq_debugger *t = NULL;
 313         struct platform_device *pdev = NULL;
 314         struct resource *res = NULL;
 315         int res_count = 0;
 316 #ifdef CONFIG_FIQ_DEBUGGER_EL3_TO_EL1
 317         /* tf means trust firmware*/
 318         int tf_ver = 0;
 319         bool tf_fiq_sup = false;
 320 #endif
 321
 322         if (!base) {
 323                 pr_err("Invalid fiq debugger uart base\n");
 324                 return;
 325         }
 326
 327         t = kzalloc(sizeof(struct rk_fiq_debugger), GFP_KERNEL);
 328         if (!t) {
 329                 pr_err("Failed to allocate for fiq debugger\n");
 330                 return;
 331         }
 332
 333         t->irq = irq;
 334         t->baudrate = baudrate;
 335         t->pdata.uart_init = debug_port_init;
 336         t->pdata.uart_getc = debug_getc;
 337         t->pdata.uart_putc = debug_putc;
 338         t->pdata.uart_dev_resume = uart_dev_resume;
 339 #ifndef CONFIG_RK_CONSOLE_THREAD
 340         t->pdata.uart_flush = debug_flush;
 341 #endif
 342         t->pdata.fiq_enable = fiq_enable;
 343         t->pdata.force_irq = NULL;  //force_irq;
 344         t->debug_port_base = base;
 345
 346         res = kzalloc(sizeof(struct resource) * 3, GFP_KERNEL);
 347         if (!res) {
 348                 pr_err("Failed to alloc fiq debugger resources\n");
 349                 goto out2;
 350         }
 351
 352         pdev = kzalloc(sizeof(struct platform_device), GFP_KERNEL);
 353         if (!pdev) {
 354                 pr_err("Failed to alloc fiq debugger platform device\n");
 355                 goto out3;
 356         };
 357
 358 #ifdef CONFIG_FIQ_DEBUGGER_EL3_TO_EL1
 359         tf_ver = rockchip_psci_smc_get_tf_ver();
 360
 361         if (tf_ver >= 0x00010005)
 362                 tf_fiq_sup = true;
 363         else
 364                 tf_fiq_sup = false;
 365
 366         if (tf_fiq_sup && (signal_irq > 0)) {
 367                 t->pdata.switch_cpu = rk_fiq_debugger_switch_cpu;
 368                 t->pdata.enable_debug = rk_fiq_debugger_enable_debug;
 369                 t->pdata.uart_dev_resume = fiq_debugger_uart_dev_resume;
 370                 psci_fiq_debugger_uart_irq_tf_init(irq,
 371                                                    fiq_debugger_uart_irq_tf);
 372         } else {
 373                 t->pdata.switch_cpu = NULL;
 374                 t->pdata.enable_debug = NULL;
 375         }
 376 #endif
 377
 378         if (irq > 0) {
 379                 res[0].flags = IORESOURCE_IRQ;
 380                 res[0].start = irq;
 381                 res[0].end = irq;
 382 #if defined(CONFIG_FIQ_GLUE)
 383                 if (signal_irq > 0)
 384                         res[0].name = "fiq";
 385                 else
 386                         res[0].name = "uart_irq";
 387 #elif defined(CONFIG_FIQ_DEBUGGER_EL3_TO_EL1)
 388                 if (tf_fiq_sup && (signal_irq > 0))
 389                         res[0].name = "fiq";
 390                 else
 391                         res[0].name = "uart_irq";
 392 #else
 393                 res[0].name = "uart_irq";
 394 #endif
 395                 res_count++;
 396         }
 397
 398         if (signal_irq > 0) {
 399                 res[1].flags = IORESOURCE_IRQ;
 400                 res[1].start = signal_irq;
 401                 res[1].end = signal_irq;
 402                 res[1].name = "signal";
 403                 res_count++;
 404         }
 405
 406         if (wakeup_irq > 0) {
 407                 res[2].flags = IORESOURCE_IRQ;
 408                 res[2].start = wakeup_irq;
 409                 res[2].end = wakeup_irq;
 410                 res[2].name = "wakeup";
 411                 res_count++;
 412         }
 413
 414 #ifdef CONFIG_RK_CONSOLE_THREAD
 415         t->console_task = kthread_create(console_thread, pdev, "kconsole");
 416         if (!IS_ERR(t->console_task))
 417                 t->pdata.console_write = console_write;
 418 #endif
 419
 420         pdev->name = "fiq_debugger";
 421         pdev->id = rk_fiq_debugger_id++;
 422         pdev->dev.platform_data = &t->pdata;
 423         pdev->resource = res;
 424         pdev->num_resources = res_count;
 425         if (platform_device_register(pdev)) {
 426                 pr_err("Failed to register fiq debugger\n");
 427                 goto out4;
 428         }
 429         return;
 430
 431 out4:
 432         kfree(pdev);
 433 out3:
 434         kfree(res);
 435 out2:
 436         kfree(t);
 437 }
 438
 439 static const struct of_device_id ids[] __initconst = {
 440         { .compatible = "rockchip,fiq-debugger" },
 441         {}
 442 };
 443
 444 static int __init rk_fiq_debugger_init(void) {
 445
 446         void __iomem *base;
 447         struct device_node *np;
 448         unsigned int id, serial_id, ok = 0;
 449         unsigned int irq, signal_irq = 0, wake_irq = 0;
 450         unsigned int baudrate = 0, irq_mode = 0;
 451         struct clk *clk;
 452         struct clk *pclk;
 453
 454         np = of_find_matching_node(NULL, ids);
 455
 456         if (!np) {
 457                 pr_err("fiq-debugger is missing in device tree!\n");
 458                 return -ENODEV;
 459         }
 460
 461         if (!of_device_is_available(np)) {
 462                 pr_err("fiq-debugger is disabled in device tree\n");
 463                 return -ENODEV;
 464         }
 465
 466         if (of_property_read_u32(np, "rockchip,serial-id", &serial_id))
 467                 return -EINVAL;
 468
 469         if (of_property_read_u32(np, "rockchip,irq-mode-enable", &irq_mode))
 470                 irq_mode = -1;
 471
 472         if (irq_mode == 1)
 473                 signal_irq = -1;
 474         else if (of_property_read_u32(np, "rockchip,signal-irq", &signal_irq))
 475                         signal_irq = -1;
 476
 477         if (of_property_read_u32(np, "rockchip,wake-irq", &wake_irq))
 478                 wake_irq = -1;
 479
 480         if (of_property_read_u32(np, "rockchip,baudrate", &baudrate))
 481                 baudrate = -1;
 482
 483         np = NULL;
 484
 485         do {
 486                 np = of_find_node_by_name(np, "serial");
 487                 if (np) {
 488                         id = of_alias_get_id(np, "serial");
 489                         if (id == serial_id) {
 490                                 ok = 1;
 491                                 break;
 492                         }
 493                 }
 494         } while(np);
 495
 496         if (!ok)
 497                 return -EINVAL;
 498
 499         pclk = of_clk_get_by_name(np, "apb_pclk");
 500         clk = of_clk_get_by_name(np, "baudclk");
 501         if (unlikely(IS_ERR(clk)) || unlikely(IS_ERR(pclk))) {
 502                 pr_err("fiq-debugger get clock fail\n");
 503                 return -EINVAL;
 504         }
 505
 506         clk_prepare_enable(clk);
 507         clk_prepare_enable(pclk);
 508
 509         irq = irq_of_parse_and_map(np, 0);
 510         if (!irq)
 511                 return -EINVAL;
 512
 513         base = of_iomap(np, 0);
 514         if (base)
 515                 rk_serial_debug_init(base, irq, signal_irq, wake_irq, baudrate);
 516
 517         return 0;
 518 }
 519 #ifdef CONFIG_FIQ_GLUE
 520 postcore_initcall_sync(rk_fiq_debugger_init);
 521 #else
 522 arch_initcall_sync(rk_fiq_debugger_init);
 523 #endif