drivers/scsi/stex.c

   1 /*
   2  * SuperTrak EX Series Storage Controller driver for Linux
   3  *
   4  *      Copyright (C) 2005-2009 Promise Technology Inc.
   5  *
   6  *      This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License
   8  *      as published by the Free Software Foundation; either version
   9  *      2 of the License, or (at your option) any later version.
  10  *
  11  *      Written By:
  12  *              Ed Lin <promise_linux@promise.com>
  13  *
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/kernel.h>
  19 #include <linux/delay.h>
  20 #include <linux/slab.h>
  21 #include <linux/time.h>
  22 #include <linux/pci.h>
  23 #include <linux/blkdev.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/types.h>
  26 #include <linux/module.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/ktime.h>
  29 #include <asm/io.h>
  30 #include <asm/irq.h>
  31 #include <asm/byteorder.h>
  32 #include <scsi/scsi.h>
  33 #include <scsi/scsi_device.h>
  34 #include <scsi/scsi_cmnd.h>
  35 #include <scsi/scsi_host.h>
  36 #include <scsi/scsi_tcq.h>
  37 #include <scsi/scsi_dbg.h>
  38 #include <scsi/scsi_eh.h>
  39
  40 #define DRV_NAME "stex"
  41 #define ST_DRIVER_VERSION "4.6.0000.4"
  42 #define ST_VER_MAJOR            4
  43 #define ST_VER_MINOR            6
  44 #define ST_OEM                  0
  45 #define ST_BUILD_VER            4
  46
  47 enum {
  48         /* MU register offset */
  49         IMR0    = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
  50         IMR1    = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
  51         OMR0    = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
  52         OMR1    = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
  53         IDBL    = 0x20, /* MU_INBOUND_DOORBELL */
  54         IIS     = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
  55         IIM     = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
  56         ODBL    = 0x2c, /* MU_OUTBOUND_DOORBELL */
  57         OIS     = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
  58         OIM     = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
  59
  60         YIOA_STATUS                             = 0x00,
  61         YH2I_INT                                = 0x20,
  62         YINT_EN                                 = 0x34,
  63         YI2H_INT                                = 0x9c,
  64         YI2H_INT_C                              = 0xa0,
  65         YH2I_REQ                                = 0xc0,
  66         YH2I_REQ_HI                             = 0xc4,
  67
  68         /* MU register value */
  69         MU_INBOUND_DOORBELL_HANDSHAKE           = (1 << 0),
  70         MU_INBOUND_DOORBELL_REQHEADCHANGED      = (1 << 1),
  71         MU_INBOUND_DOORBELL_STATUSTAILCHANGED   = (1 << 2),
  72         MU_INBOUND_DOORBELL_HMUSTOPPED          = (1 << 3),
  73         MU_INBOUND_DOORBELL_RESET               = (1 << 4),
  74
  75         MU_OUTBOUND_DOORBELL_HANDSHAKE          = (1 << 0),
  76         MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = (1 << 1),
  77         MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED  = (1 << 2),
  78         MU_OUTBOUND_DOORBELL_BUSCHANGE          = (1 << 3),
  79         MU_OUTBOUND_DOORBELL_HASEVENT           = (1 << 4),
  80         MU_OUTBOUND_DOORBELL_REQUEST_RESET      = (1 << 27),
  81
  82         /* MU status code */
  83         MU_STATE_STARTING                       = 1,
  84         MU_STATE_STARTED                        = 2,
  85         MU_STATE_RESETTING                      = 3,
  86         MU_STATE_FAILED                         = 4,
  87
  88         MU_MAX_DELAY                            = 120,
  89         MU_HANDSHAKE_SIGNATURE                  = 0x55aaaa55,
  90         MU_HANDSHAKE_SIGNATURE_HALF             = 0x5a5a0000,
  91         MU_HARD_RESET_WAIT                      = 30000,
  92         HMU_PARTNER_TYPE                        = 2,
  93
  94         /* firmware returned values */
  95         SRB_STATUS_SUCCESS                      = 0x01,
  96         SRB_STATUS_ERROR                        = 0x04,
  97         SRB_STATUS_BUSY                         = 0x05,
  98         SRB_STATUS_INVALID_REQUEST              = 0x06,
  99         SRB_STATUS_SELECTION_TIMEOUT            = 0x0A,
 100         SRB_SEE_SENSE                           = 0x80,
 101
 102         /* task attribute */
 103         TASK_ATTRIBUTE_SIMPLE                   = 0x0,
 104         TASK_ATTRIBUTE_HEADOFQUEUE              = 0x1,
 105         TASK_ATTRIBUTE_ORDERED                  = 0x2,
 106         TASK_ATTRIBUTE_ACA                      = 0x4,
 107
 108         SS_STS_NORMAL                           = 0x80000000,
 109         SS_STS_DONE                             = 0x40000000,
 110         SS_STS_HANDSHAKE                        = 0x20000000,
 111
 112         SS_HEAD_HANDSHAKE                       = 0x80,
 113
 114         SS_H2I_INT_RESET                        = 0x100,
 115
 116         SS_I2H_REQUEST_RESET                    = 0x2000,
 117
 118         SS_MU_OPERATIONAL                       = 0x80000000,
 119
 120         STEX_CDB_LENGTH                         = 16,
 121         STATUS_VAR_LEN                          = 128,
 122
 123         /* sg flags */
 124         SG_CF_EOT                               = 0x80, /* end of table */
 125         SG_CF_64B                               = 0x40, /* 64 bit item */
 126         SG_CF_HOST                              = 0x20, /* sg in host memory */
 127         MSG_DATA_DIR_ND                         = 0,
 128         MSG_DATA_DIR_IN                         = 1,
 129         MSG_DATA_DIR_OUT                        = 2,
 130
 131         st_shasta                               = 0,
 132         st_vsc                                  = 1,
 133         st_yosemite                             = 2,
 134         st_seq                                  = 3,
 135         st_yel                                  = 4,
 136
 137         PASSTHRU_REQ_TYPE                       = 0x00000001,
 138         PASSTHRU_REQ_NO_WAKEUP                  = 0x00000100,
 139         ST_INTERNAL_TIMEOUT                     = 180,
 140
 141         ST_TO_CMD                               = 0,
 142         ST_FROM_CMD                             = 1,
 143
 144         /* vendor specific commands of Promise */
 145         MGT_CMD                                 = 0xd8,
 146         SINBAND_MGT_CMD                         = 0xd9,
 147         ARRAY_CMD                               = 0xe0,
 148         CONTROLLER_CMD                          = 0xe1,
 149         DEBUGGING_CMD                           = 0xe2,
 150         PASSTHRU_CMD                            = 0xe3,
 151
 152         PASSTHRU_GET_ADAPTER                    = 0x05,
 153         PASSTHRU_GET_DRVVER                     = 0x10,
 154
 155         CTLR_CONFIG_CMD                         = 0x03,
 156         CTLR_SHUTDOWN                           = 0x0d,
 157
 158         CTLR_POWER_STATE_CHANGE                 = 0x0e,
 159         CTLR_POWER_SAVING                       = 0x01,
 160
 161         PASSTHRU_SIGNATURE                      = 0x4e415041,
 162         MGT_CMD_SIGNATURE                       = 0xba,
 163
 164         INQUIRY_EVPD                            = 0x01,
 165
 166         ST_ADDITIONAL_MEM                       = 0x200000,
 167         ST_ADDITIONAL_MEM_MIN                   = 0x80000,
 168 };
 169
 170 struct st_sgitem {
 171         u8 ctrl;        /* SG_CF_xxx */
 172         u8 reserved[3];
 173         __le32 count;
 174         __le64 addr;
 175 };
 176
 177 struct st_ss_sgitem {
 178         __le32 addr;
 179         __le32 addr_hi;
 180         __le32 count;
 181 };
 182
 183 struct st_sgtable {
 184         __le16 sg_count;
 185         __le16 max_sg_count;
 186         __le32 sz_in_byte;
 187 };
 188
 189 struct st_msg_header {
 190         __le64 handle;
 191         u8 flag;
 192         u8 channel;
 193         __le16 timeout;
 194         u32 reserved;
 195 };
 196
 197 struct handshake_frame {
 198         __le64 rb_phy;          /* request payload queue physical address */
 199         __le16 req_sz;          /* size of each request payload */
 200         __le16 req_cnt;         /* count of reqs the buffer can hold */
 201         __le16 status_sz;       /* size of each status payload */
 202         __le16 status_cnt;      /* count of status the buffer can hold */
 203         __le64 hosttime;        /* seconds from Jan 1, 1970 (GMT) */
 204         u8 partner_type;        /* who sends this frame */
 205         u8 reserved0[7];
 206         __le32 partner_ver_major;
 207         __le32 partner_ver_minor;
 208         __le32 partner_ver_oem;
 209         __le32 partner_ver_build;
 210         __le32 extra_offset;    /* NEW */
 211         __le32 extra_size;      /* NEW */
 212         __le32 scratch_size;
 213         u32 reserved1;
 214 };
 215
 216 struct req_msg {
 217         __le16 tag;
 218         u8 lun;
 219         u8 target;
 220         u8 task_attr;
 221         u8 task_manage;
 222         u8 data_dir;
 223         u8 payload_sz;          /* payload size in 4-byte, not used */
 224         u8 cdb[STEX_CDB_LENGTH];
 225         u32 variable[0];
 226 };
 227
 228 struct status_msg {
 229         __le16 tag;
 230         u8 lun;
 231         u8 target;
 232         u8 srb_status;
 233         u8 scsi_status;
 234         u8 reserved;
 235         u8 payload_sz;          /* payload size in 4-byte */
 236         u8 variable[STATUS_VAR_LEN];
 237 };
 238
 239 struct ver_info {
 240         u32 major;
 241         u32 minor;
 242         u32 oem;
 243         u32 build;
 244         u32 reserved[2];
 245 };
 246
 247 struct st_frame {
 248         u32 base[6];
 249         u32 rom_addr;
 250
 251         struct ver_info drv_ver;
 252         struct ver_info bios_ver;
 253
 254         u32 bus;
 255         u32 slot;
 256         u32 irq_level;
 257         u32 irq_vec;
 258         u32 id;
 259         u32 subid;
 260
 261         u32 dimm_size;
 262         u8 dimm_type;
 263         u8 reserved[3];
 264
 265         u32 channel;
 266         u32 reserved1;
 267 };
 268
 269 struct st_drvver {
 270         u32 major;
 271         u32 minor;
 272         u32 oem;
 273         u32 build;
 274         u32 signature[2];
 275         u8 console_id;
 276         u8 host_no;
 277         u8 reserved0[2];
 278         u32 reserved[3];
 279 };
 280
 281 struct st_ccb {
 282         struct req_msg *req;
 283         struct scsi_cmnd *cmd;
 284
 285         void *sense_buffer;
 286         unsigned int sense_bufflen;
 287         int sg_count;
 288
 289         u32 req_type;
 290         u8 srb_status;
 291         u8 scsi_status;
 292         u8 reserved[2];
 293 };
 294
 295 struct st_hba {
 296         void __iomem *mmio_base;        /* iomapped PCI memory space */
 297         void *dma_mem;
 298         dma_addr_t dma_handle;
 299         size_t dma_size;
 300
 301         struct Scsi_Host *host;
 302         struct pci_dev *pdev;
 303
 304         struct req_msg * (*alloc_rq) (struct st_hba *);
 305         int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
 306         void (*send) (struct st_hba *, struct req_msg *, u16);
 307
 308         u32 req_head;
 309         u32 req_tail;
 310         u32 status_head;
 311         u32 status_tail;
 312
 313         struct status_msg *status_buffer;
 314         void *copy_buffer; /* temp buffer for driver-handled commands */
 315         struct st_ccb *ccb;
 316         struct st_ccb *wait_ccb;
 317         __le32 *scratch;
 318
 319         char work_q_name[20];
 320         struct workqueue_struct *work_q;
 321         struct work_struct reset_work;
 322         wait_queue_head_t reset_waitq;
 323         unsigned int mu_status;
 324         unsigned int cardtype;
 325         int msi_enabled;
 326         int out_req_cnt;
 327         u32 extra_offset;
 328         u16 rq_count;
 329         u16 rq_size;
 330         u16 sts_count;
 331 };
 332
 333 struct st_card_info {
 334         struct req_msg * (*alloc_rq) (struct st_hba *);
 335         int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
 336         void (*send) (struct st_hba *, struct req_msg *, u16);
 337         unsigned int max_id;
 338         unsigned int max_lun;
 339         unsigned int max_channel;
 340         u16 rq_count;
 341         u16 rq_size;
 342         u16 sts_count;
 343 };
 344
 345 static int msi;
 346 module_param(msi, int, 0);
 347 MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)");
 348
 349 static const char console_inq_page[] =
 350 {
 351         0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
 352         0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20,        /* "Promise " */
 353         0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E,        /* "RAID Con" */
 354         0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20,        /* "sole    " */
 355         0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20,        /* "1.00    " */
 356         0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D,        /* "SX/RSAF-" */
 357         0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20,        /* "TE1.00  " */
 358         0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
 359 };
 360
 361 MODULE_AUTHOR("Ed Lin");
 362 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
 363 MODULE_LICENSE("GPL");
 364 MODULE_VERSION(ST_DRIVER_VERSION);
 365
 366 static struct status_msg *stex_get_status(struct st_hba *hba)
 367 {
 368         struct status_msg *status = hba->status_buffer + hba->status_tail;
 369
 370         ++hba->status_tail;
 371         hba->status_tail %= hba->sts_count+1;
 372
 373         return status;
 374 }
 375
 376 static void stex_invalid_field(struct scsi_cmnd *cmd,
 377                                void (*done)(struct scsi_cmnd *))
 378 {
 379         cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
 380
 381         /* "Invalid field in cdb" */
 382         scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24,
 383                                 0x0);
 384         done(cmd);
 385 }
 386
 387 static struct req_msg *stex_alloc_req(struct st_hba *hba)
 388 {
 389         struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size;
 390
 391         ++hba->req_head;
 392         hba->req_head %= hba->rq_count+1;
 393
 394         return req;
 395 }
 396
 397 static struct req_msg *stex_ss_alloc_req(struct st_hba *hba)
 398 {
 399         return (struct req_msg *)(hba->dma_mem +
 400                 hba->req_head * hba->rq_size + sizeof(struct st_msg_header));
 401 }
 402
 403 static int stex_map_sg(struct st_hba *hba,
 404         struct req_msg *req, struct st_ccb *ccb)
 405 {
 406         struct scsi_cmnd *cmd;
 407         struct scatterlist *sg;
 408         struct st_sgtable *dst;
 409         struct st_sgitem *table;
 410         int i, nseg;
 411
 412         cmd = ccb->cmd;
 413         nseg = scsi_dma_map(cmd);
 414         BUG_ON(nseg < 0);
 415         if (nseg) {
 416                 dst = (struct st_sgtable *)req->variable;
 417
 418                 ccb->sg_count = nseg;
 419                 dst->sg_count = cpu_to_le16((u16)nseg);
 420                 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
 421                 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
 422
 423                 table = (struct st_sgitem *)(dst + 1);
 424                 scsi_for_each_sg(cmd, sg, nseg, i) {
 425                         table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
 426                         table[i].addr = cpu_to_le64(sg_dma_address(sg));
 427                         table[i].ctrl = SG_CF_64B | SG_CF_HOST;
 428                 }
 429                 table[--i].ctrl |= SG_CF_EOT;
 430         }
 431
 432         return nseg;
 433 }
 434
 435 static int stex_ss_map_sg(struct st_hba *hba,
 436         struct req_msg *req, struct st_ccb *ccb)
 437 {
 438         struct scsi_cmnd *cmd;
 439         struct scatterlist *sg;
 440         struct st_sgtable *dst;
 441         struct st_ss_sgitem *table;
 442         int i, nseg;
 443
 444         cmd = ccb->cmd;
 445         nseg = scsi_dma_map(cmd);
 446         BUG_ON(nseg < 0);
 447         if (nseg) {
 448                 dst = (struct st_sgtable *)req->variable;
 449
 450                 ccb->sg_count = nseg;
 451                 dst->sg_count = cpu_to_le16((u16)nseg);
 452                 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
 453                 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
 454
 455                 table = (struct st_ss_sgitem *)(dst + 1);
 456                 scsi_for_each_sg(cmd, sg, nseg, i) {
 457                         table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
 458                         table[i].addr =
 459                                 cpu_to_le32(sg_dma_address(sg) & 0xffffffff);
 460                         table[i].addr_hi =
 461                                 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
 462                 }
 463         }
 464
 465         return nseg;
 466 }
 467
 468 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
 469 {
 470         struct st_frame *p;
 471         size_t count = sizeof(struct st_frame);
 472
 473         p = hba->copy_buffer;
 474         scsi_sg_copy_to_buffer(ccb->cmd, p, count);
 475         memset(p->base, 0, sizeof(u32)*6);
 476         *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
 477         p->rom_addr = 0;
 478
 479         p->drv_ver.major = ST_VER_MAJOR;
 480         p->drv_ver.minor = ST_VER_MINOR;
 481         p->drv_ver.oem = ST_OEM;
 482         p->drv_ver.build = ST_BUILD_VER;
 483
 484         p->bus = hba->pdev->bus->number;
 485         p->slot = hba->pdev->devfn;
 486         p->irq_level = 0;
 487         p->irq_vec = hba->pdev->irq;
 488         p->id = hba->pdev->vendor << 16 | hba->pdev->device;
 489         p->subid =
 490                 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
 491
 492         scsi_sg_copy_from_buffer(ccb->cmd, p, count);
 493 }
 494
 495 static void
 496 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 497 {
 498         req->tag = cpu_to_le16(tag);
 499
 500         hba->ccb[tag].req = req;
 501         hba->out_req_cnt++;
 502
 503         writel(hba->req_head, hba->mmio_base + IMR0);
 504         writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
 505         readl(hba->mmio_base + IDBL); /* flush */
 506 }
 507
 508 static void
 509 stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 510 {
 511         struct scsi_cmnd *cmd;
 512         struct st_msg_header *msg_h;
 513         dma_addr_t addr;
 514
 515         req->tag = cpu_to_le16(tag);
 516
 517         hba->ccb[tag].req = req;
 518         hba->out_req_cnt++;
 519
 520         cmd = hba->ccb[tag].cmd;
 521         msg_h = (struct st_msg_header *)req - 1;
 522         if (likely(cmd)) {
 523                 msg_h->channel = (u8)cmd->device->channel;
 524                 msg_h->timeout = cpu_to_le16(cmd->request->timeout/HZ);
 525         }
 526         addr = hba->dma_handle + hba->req_head * hba->rq_size;
 527         addr += (hba->ccb[tag].sg_count+4)/11;
 528         msg_h->handle = cpu_to_le64(addr);
 529
 530         ++hba->req_head;
 531         hba->req_head %= hba->rq_count+1;
 532
 533         writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
 534         readl(hba->mmio_base + YH2I_REQ_HI); /* flush */
 535         writel(addr, hba->mmio_base + YH2I_REQ);
 536         readl(hba->mmio_base + YH2I_REQ); /* flush */
 537 }
 538
 539 static int
 540 stex_slave_config(struct scsi_device *sdev)
 541 {
 542         sdev->use_10_for_rw = 1;
 543         sdev->use_10_for_ms = 1;
 544         blk_queue_rq_timeout(sdev->request_queue, 60 * HZ);
 545
 546         return 0;
 547 }
 548
 549 static int
 550 stex_queuecommand_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
 551 {
 552         struct st_hba *hba;
 553         struct Scsi_Host *host;
 554         unsigned int id, lun;
 555         struct req_msg *req;
 556         u16 tag;
 557
 558         host = cmd->device->host;
 559         id = cmd->device->id;
 560         lun = cmd->device->lun;
 561         hba = (struct st_hba *) &host->hostdata[0];
 562
 563         if (unlikely(hba->mu_status == MU_STATE_RESETTING))
 564                 return SCSI_MLQUEUE_HOST_BUSY;
 565
 566         switch (cmd->cmnd[0]) {
 567         case MODE_SENSE_10:
 568         {
 569                 static char ms10_caching_page[12] =
 570                         { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
 571                 unsigned char page;
 572
 573                 page = cmd->cmnd[2] & 0x3f;
 574                 if (page == 0x8 || page == 0x3f) {
 575                         scsi_sg_copy_from_buffer(cmd, ms10_caching_page,
 576                                                  sizeof(ms10_caching_page));
 577                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 578                         done(cmd);
 579                 } else
 580                         stex_invalid_field(cmd, done);
 581                 return 0;
 582         }
 583         case REPORT_LUNS:
 584                 /*
 585                  * The shasta firmware does not report actual luns in the
 586                  * target, so fail the command to force sequential lun scan.
 587                  * Also, the console device does not support this command.
 588                  */
 589                 if (hba->cardtype == st_shasta || id == host->max_id - 1) {
 590                         stex_invalid_field(cmd, done);
 591                         return 0;
 592                 }
 593                 break;
 594         case TEST_UNIT_READY:
 595                 if (id == host->max_id - 1) {
 596                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 597                         done(cmd);
 598                         return 0;
 599                 }
 600                 break;
 601         case INQUIRY:
 602                 if (lun >= host->max_lun) {
 603                         cmd->result = DID_NO_CONNECT << 16;
 604                         done(cmd);
 605                         return 0;
 606                 }
 607                 if (id != host->max_id - 1)
 608                         break;
 609                 if (!lun && !cmd->device->channel &&
 610                         (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
 611                         scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page,
 612                                                  sizeof(console_inq_page));
 613                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 614                         done(cmd);
 615                 } else
 616                         stex_invalid_field(cmd, done);
 617                 return 0;
 618         case PASSTHRU_CMD:
 619                 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
 620                         struct st_drvver ver;
 621                         size_t cp_len = sizeof(ver);
 622
 623                         ver.major = ST_VER_MAJOR;
 624                         ver.minor = ST_VER_MINOR;
 625                         ver.oem = ST_OEM;
 626                         ver.build = ST_BUILD_VER;
 627                         ver.signature[0] = PASSTHRU_SIGNATURE;
 628                         ver.console_id = host->max_id - 1;
 629                         ver.host_no = hba->host->host_no;
 630                         cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len);
 631                         cmd->result = sizeof(ver) == cp_len ?
 632                                 DID_OK << 16 | COMMAND_COMPLETE << 8 :
 633                                 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 634                         done(cmd);
 635                         return 0;
 636                 }
 637         default:
 638                 break;
 639         }
 640
 641         cmd->scsi_done = done;
 642
 643         tag = cmd->request->tag;
 644
 645         if (unlikely(tag >= host->can_queue))
 646                 return SCSI_MLQUEUE_HOST_BUSY;
 647
 648         req = hba->alloc_rq(hba);
 649
 650         req->lun = lun;
 651         req->target = id;
 652
 653         /* cdb */
 654         memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
 655
 656         if (cmd->sc_data_direction == DMA_FROM_DEVICE)
 657                 req->data_dir = MSG_DATA_DIR_IN;
 658         else if (cmd->sc_data_direction == DMA_TO_DEVICE)
 659                 req->data_dir = MSG_DATA_DIR_OUT;
 660         else
 661                 req->data_dir = MSG_DATA_DIR_ND;
 662
 663         hba->ccb[tag].cmd = cmd;
 664         hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
 665         hba->ccb[tag].sense_buffer = cmd->sense_buffer;
 666
 667         if (!hba->map_sg(hba, req, &hba->ccb[tag])) {
 668                 hba->ccb[tag].sg_count = 0;
 669                 memset(&req->variable[0], 0, 8);
 670         }
 671
 672         hba->send(hba, req, tag);
 673         return 0;
 674 }
 675
 676 static DEF_SCSI_QCMD(stex_queuecommand)
 677
 678 static void stex_scsi_done(struct st_ccb *ccb)
 679 {
 680         struct scsi_cmnd *cmd = ccb->cmd;
 681         int result;
 682
 683         if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
 684                 result = ccb->scsi_status;
 685                 switch (ccb->scsi_status) {
 686                 case SAM_STAT_GOOD:
 687                         result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
 688                         break;
 689                 case SAM_STAT_CHECK_CONDITION:
 690                         result |= DRIVER_SENSE << 24;
 691                         break;
 692                 case SAM_STAT_BUSY:
 693                         result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 694                         break;
 695                 default:
 696                         result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 697                         break;
 698                 }
 699         }
 700         else if (ccb->srb_status & SRB_SEE_SENSE)
 701                 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
 702         else switch (ccb->srb_status) {
 703                 case SRB_STATUS_SELECTION_TIMEOUT:
 704                         result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
 705                         break;
 706                 case SRB_STATUS_BUSY:
 707                         result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 708                         break;
 709                 case SRB_STATUS_INVALID_REQUEST:
 710                 case SRB_STATUS_ERROR:
 711                 default:
 712                         result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 713                         break;
 714         }
 715
 716         cmd->result = result;
 717         cmd->scsi_done(cmd);
 718 }
 719
 720 static void stex_copy_data(struct st_ccb *ccb,
 721         struct status_msg *resp, unsigned int variable)
 722 {
 723         if (resp->scsi_status != SAM_STAT_GOOD) {
 724                 if (ccb->sense_buffer != NULL)
 725                         memcpy(ccb->sense_buffer, resp->variable,
 726                                 min(variable, ccb->sense_bufflen));
 727                 return;
 728         }
 729
 730         if (ccb->cmd == NULL)
 731                 return;
 732         scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable);
 733 }
 734
 735 static void stex_check_cmd(struct st_hba *hba,
 736         struct st_ccb *ccb, struct status_msg *resp)
 737 {
 738         if (ccb->cmd->cmnd[0] == MGT_CMD &&
 739                 resp->scsi_status != SAM_STAT_CHECK_CONDITION)
 740                 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
 741                         le32_to_cpu(*(__le32 *)&resp->variable[0]));
 742 }
 743
 744 static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
 745 {
 746         void __iomem *base = hba->mmio_base;
 747         struct status_msg *resp;
 748         struct st_ccb *ccb;
 749         unsigned int size;
 750         u16 tag;
 751
 752         if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)))
 753                 return;
 754
 755         /* status payloads */
 756         hba->status_head = readl(base + OMR1);
 757         if (unlikely(hba->status_head > hba->sts_count)) {
 758                 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
 759                         pci_name(hba->pdev));
 760                 return;
 761         }
 762
 763         /*
 764          * it's not a valid status payload if:
 765          * 1. there are no pending requests(e.g. during init stage)
 766          * 2. there are some pending requests, but the controller is in
 767          *     reset status, and its type is not st_yosemite
 768          * firmware of st_yosemite in reset status will return pending requests
 769          * to driver, so we allow it to pass
 770          */
 771         if (unlikely(hba->out_req_cnt <= 0 ||
 772                         (hba->mu_status == MU_STATE_RESETTING &&
 773                          hba->cardtype != st_yosemite))) {
 774                 hba->status_tail = hba->status_head;
 775                 goto update_status;
 776         }
 777
 778         while (hba->status_tail != hba->status_head) {
 779                 resp = stex_get_status(hba);
 780                 tag = le16_to_cpu(resp->tag);
 781                 if (unlikely(tag >= hba->host->can_queue)) {
 782                         printk(KERN_WARNING DRV_NAME
 783                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 784                         continue;
 785                 }
 786
 787                 hba->out_req_cnt--;
 788                 ccb = &hba->ccb[tag];
 789                 if (unlikely(hba->wait_ccb == ccb))
 790                         hba->wait_ccb = NULL;
 791                 if (unlikely(ccb->req == NULL)) {
 792                         printk(KERN_WARNING DRV_NAME
 793                                 "(%s): lagging req\n", pci_name(hba->pdev));
 794                         continue;
 795                 }
 796
 797                 size = resp->payload_sz * sizeof(u32); /* payload size */
 798                 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 799                         size > sizeof(*resp))) {
 800                         printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
 801                                 pci_name(hba->pdev));
 802                 } else {
 803                         size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
 804                         if (size)
 805                                 stex_copy_data(ccb, resp, size);
 806                 }
 807
 808                 ccb->req = NULL;
 809                 ccb->srb_status = resp->srb_status;
 810                 ccb->scsi_status = resp->scsi_status;
 811
 812                 if (likely(ccb->cmd != NULL)) {
 813                         if (hba->cardtype == st_yosemite)
 814                                 stex_check_cmd(hba, ccb, resp);
 815
 816                         if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
 817                                 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
 818                                 stex_controller_info(hba, ccb);
 819
 820                         scsi_dma_unmap(ccb->cmd);
 821                         stex_scsi_done(ccb);
 822                 } else
 823                         ccb->req_type = 0;
 824         }
 825
 826 update_status:
 827         writel(hba->status_head, base + IMR1);
 828         readl(base + IMR1); /* flush */
 829 }
 830
 831 static irqreturn_t stex_intr(int irq, void *__hba)
 832 {
 833         struct st_hba *hba = __hba;
 834         void __iomem *base = hba->mmio_base;
 835         u32 data;
 836         unsigned long flags;
 837
 838         spin_lock_irqsave(hba->host->host_lock, flags);
 839
 840         data = readl(base + ODBL);
 841
 842         if (data && data != 0xffffffff) {
 843                 /* clear the interrupt */
 844                 writel(data, base + ODBL);
 845                 readl(base + ODBL); /* flush */
 846                 stex_mu_intr(hba, data);
 847                 spin_unlock_irqrestore(hba->host->host_lock, flags);
 848                 if (unlikely(data & MU_OUTBOUND_DOORBELL_REQUEST_RESET &&
 849                         hba->cardtype == st_shasta))
 850                         queue_work(hba->work_q, &hba->reset_work);
 851                 return IRQ_HANDLED;
 852         }
 853
 854         spin_unlock_irqrestore(hba->host->host_lock, flags);
 855
 856         return IRQ_NONE;
 857 }
 858
 859 static void stex_ss_mu_intr(struct st_hba *hba)
 860 {
 861         struct status_msg *resp;
 862         struct st_ccb *ccb;
 863         __le32 *scratch;
 864         unsigned int size;
 865         int count = 0;
 866         u32 value;
 867         u16 tag;
 868
 869         if (unlikely(hba->out_req_cnt <= 0 ||
 870                         hba->mu_status == MU_STATE_RESETTING))
 871                 return;
 872
 873         while (count < hba->sts_count) {
 874                 scratch = hba->scratch + hba->status_tail;
 875                 value = le32_to_cpu(*scratch);
 876                 if (unlikely(!(value & SS_STS_NORMAL)))
 877                         return;
 878
 879                 resp = hba->status_buffer + hba->status_tail;
 880                 *scratch = 0;
 881                 ++count;
 882                 ++hba->status_tail;
 883                 hba->status_tail %= hba->sts_count+1;
 884
 885                 tag = (u16)value;
 886                 if (unlikely(tag >= hba->host->can_queue)) {
 887                         printk(KERN_WARNING DRV_NAME
 888                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 889                         continue;
 890                 }
 891
 892                 hba->out_req_cnt--;
 893                 ccb = &hba->ccb[tag];
 894                 if (unlikely(hba->wait_ccb == ccb))
 895                         hba->wait_ccb = NULL;
 896                 if (unlikely(ccb->req == NULL)) {
 897                         printk(KERN_WARNING DRV_NAME
 898                                 "(%s): lagging req\n", pci_name(hba->pdev));
 899                         continue;
 900                 }
 901
 902                 ccb->req = NULL;
 903                 if (likely(value & SS_STS_DONE)) { /* normal case */
 904                         ccb->srb_status = SRB_STATUS_SUCCESS;
 905                         ccb->scsi_status = SAM_STAT_GOOD;
 906                 } else {
 907                         ccb->srb_status = resp->srb_status;
 908                         ccb->scsi_status = resp->scsi_status;
 909                         size = resp->payload_sz * sizeof(u32);
 910                         if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 911                                 size > sizeof(*resp))) {
 912                                 printk(KERN_WARNING DRV_NAME
 913                                         "(%s): bad status size\n",
 914                                         pci_name(hba->pdev));
 915                         } else {
 916                                 size -= sizeof(*resp) - STATUS_VAR_LEN;
 917                                 if (size)
 918                                         stex_copy_data(ccb, resp, size);
 919                         }
 920                         if (likely(ccb->cmd != NULL))
 921                                 stex_check_cmd(hba, ccb, resp);
 922                 }
 923
 924                 if (likely(ccb->cmd != NULL)) {
 925                         scsi_dma_unmap(ccb->cmd);
 926                         stex_scsi_done(ccb);
 927                 } else
 928                         ccb->req_type = 0;
 929         }
 930 }
 931
 932 static irqreturn_t stex_ss_intr(int irq, void *__hba)
 933 {
 934         struct st_hba *hba = __hba;
 935         void __iomem *base = hba->mmio_base;
 936         u32 data;
 937         unsigned long flags;
 938
 939         spin_lock_irqsave(hba->host->host_lock, flags);
 940
 941         data = readl(base + YI2H_INT);
 942         if (data && data != 0xffffffff) {
 943                 /* clear the interrupt */
 944                 writel(data, base + YI2H_INT_C);
 945                 stex_ss_mu_intr(hba);
 946                 spin_unlock_irqrestore(hba->host->host_lock, flags);
 947                 if (unlikely(data & SS_I2H_REQUEST_RESET))
 948                         queue_work(hba->work_q, &hba->reset_work);
 949                 return IRQ_HANDLED;
 950         }
 951
 952         spin_unlock_irqrestore(hba->host->host_lock, flags);
 953
 954         return IRQ_NONE;
 955 }
 956
 957 static int stex_common_handshake(struct st_hba *hba)
 958 {
 959         void __iomem *base = hba->mmio_base;
 960         struct handshake_frame *h;
 961         dma_addr_t status_phys;
 962         u32 data;
 963         unsigned long before;
 964
 965         if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 966                 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
 967                 readl(base + IDBL);
 968                 before = jiffies;
 969                 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 970                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
 971                                 printk(KERN_ERR DRV_NAME
 972                                         "(%s): no handshake signature\n",
 973                                         pci_name(hba->pdev));
 974                                 return -1;
 975                         }
 976                         rmb();
 977                         msleep(1);
 978                 }
 979         }
 980
 981         udelay(10);
 982
 983         data = readl(base + OMR1);
 984         if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
 985                 data &= 0x0000ffff;
 986                 if (hba->host->can_queue > data) {
 987                         hba->host->can_queue = data;
 988                         hba->host->cmd_per_lun = data;
 989                 }
 990         }
 991
 992         h = (struct handshake_frame *)hba->status_buffer;
 993         h->rb_phy = cpu_to_le64(hba->dma_handle);
 994         h->req_sz = cpu_to_le16(hba->rq_size);
 995         h->req_cnt = cpu_to_le16(hba->rq_count+1);
 996         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
 997         h->status_cnt = cpu_to_le16(hba->sts_count+1);
 998         h->hosttime = cpu_to_le64(ktime_get_real_seconds());
 999         h->partner_type = HMU_PARTNER_TYPE;
1000         if (hba->extra_offset) {
1001                 h->extra_offset = cpu_to_le32(hba->extra_offset);
1002                 h->extra_size = cpu_to_le32(hba->dma_size - hba->extra_offset);
1003         } else
1004                 h->extra_offset = h->extra_size = 0;
1005
1006         status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size;
1007         writel(status_phys, base + IMR0);
1008         readl(base + IMR0);
1009         writel((status_phys >> 16) >> 16, base + IMR1);
1010         readl(base + IMR1);
1011
1012         writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
1013         readl(base + OMR0);
1014         writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1015         readl(base + IDBL); /* flush */
1016
1017         udelay(10);
1018         before = jiffies;
1019         while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1020                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1021                         printk(KERN_ERR DRV_NAME
1022                                 "(%s): no signature after handshake frame\n",
1023                                 pci_name(hba->pdev));
1024                         return -1;
1025                 }
1026                 rmb();
1027                 msleep(1);
1028         }
1029
1030         writel(0, base + IMR0);
1031         readl(base + IMR0);
1032         writel(0, base + OMR0);
1033         readl(base + OMR0);
1034         writel(0, base + IMR1);
1035         readl(base + IMR1);
1036         writel(0, base + OMR1);
1037         readl(base + OMR1); /* flush */
1038         return 0;
1039 }
1040
1041 static int stex_ss_handshake(struct st_hba *hba)
1042 {
1043         void __iomem *base = hba->mmio_base;
1044         struct st_msg_header *msg_h;
1045         struct handshake_frame *h;
1046         __le32 *scratch;
1047         u32 data, scratch_size;
1048         unsigned long before;
1049         int ret = 0;
1050
1051         before = jiffies;
1052         while ((readl(base + YIOA_STATUS) & SS_MU_OPERATIONAL) == 0) {
1053                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1054                         printk(KERN_ERR DRV_NAME
1055                                 "(%s): firmware not operational\n",
1056                                 pci_name(hba->pdev));
1057                         return -1;
1058                 }
1059                 msleep(1);
1060         }
1061
1062         msg_h = (struct st_msg_header *)hba->dma_mem;
1063         msg_h->handle = cpu_to_le64(hba->dma_handle);
1064         msg_h->flag = SS_HEAD_HANDSHAKE;
1065
1066         h = (struct handshake_frame *)(msg_h + 1);
1067         h->rb_phy = cpu_to_le64(hba->dma_handle);
1068         h->req_sz = cpu_to_le16(hba->rq_size);
1069         h->req_cnt = cpu_to_le16(hba->rq_count+1);
1070         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1071         h->status_cnt = cpu_to_le16(hba->sts_count+1);
1072         h->hosttime = cpu_to_le64(ktime_get_real_seconds());
1073         h->partner_type = HMU_PARTNER_TYPE;
1074         h->extra_offset = h->extra_size = 0;
1075         scratch_size = (hba->sts_count+1)*sizeof(u32);
1076         h->scratch_size = cpu_to_le32(scratch_size);
1077
1078         data = readl(base + YINT_EN);
1079         data &= ~4;
1080         writel(data, base + YINT_EN);
1081         writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
1082         readl(base + YH2I_REQ_HI);
1083         writel(hba->dma_handle, base + YH2I_REQ);
1084         readl(base + YH2I_REQ); /* flush */
1085
1086         scratch = hba->scratch;
1087         before = jiffies;
1088         while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) {
1089                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1090                         printk(KERN_ERR DRV_NAME
1091                                 "(%s): no signature after handshake frame\n",
1092                                 pci_name(hba->pdev));
1093                         ret = -1;
1094                         break;
1095                 }
1096                 rmb();
1097                 msleep(1);
1098         }
1099
1100         memset(scratch, 0, scratch_size);
1101         msg_h->flag = 0;
1102         return ret;
1103 }
1104
1105 static int stex_handshake(struct st_hba *hba)
1106 {
1107         int err;
1108         unsigned long flags;
1109         unsigned int mu_status;
1110
1111         err = (hba->cardtype == st_yel) ?
1112                 stex_ss_handshake(hba) : stex_common_handshake(hba);
1113         spin_lock_irqsave(hba->host->host_lock, flags);
1114         mu_status = hba->mu_status;
1115         if (err == 0) {
1116                 hba->req_head = 0;
1117                 hba->req_tail = 0;
1118                 hba->status_head = 0;
1119                 hba->status_tail = 0;
1120                 hba->out_req_cnt = 0;
1121                 hba->mu_status = MU_STATE_STARTED;
1122         } else
1123                 hba->mu_status = MU_STATE_FAILED;
1124         if (mu_status == MU_STATE_RESETTING)
1125                 wake_up_all(&hba->reset_waitq);
1126         spin_unlock_irqrestore(hba->host->host_lock, flags);
1127         return err;
1128 }
1129
1130 static int stex_abort(struct scsi_cmnd *cmd)
1131 {
1132         struct Scsi_Host *host = cmd->device->host;
1133         struct st_hba *hba = (struct st_hba *)host->hostdata;
1134         u16 tag = cmd->request->tag;
1135         void __iomem *base;
1136         u32 data;
1137         int result = SUCCESS;
1138         unsigned long flags;
1139
1140         scmd_printk(KERN_INFO, cmd, "aborting command\n");
1141
1142         base = hba->mmio_base;
1143         spin_lock_irqsave(host->host_lock, flags);
1144         if (tag < host->can_queue &&
1145                 hba->ccb[tag].req && hba->ccb[tag].cmd == cmd)
1146                 hba->wait_ccb = &hba->ccb[tag];
1147         else
1148                 goto out;
1149
1150         if (hba->cardtype == st_yel) {
1151                 data = readl(base + YI2H_INT);
1152                 if (data == 0 || data == 0xffffffff)
1153                         goto fail_out;
1154
1155                 writel(data, base + YI2H_INT_C);
1156                 stex_ss_mu_intr(hba);
1157         } else {
1158                 data = readl(base + ODBL);
1159                 if (data == 0 || data == 0xffffffff)
1160                         goto fail_out;
1161
1162                 writel(data, base + ODBL);
1163                 readl(base + ODBL); /* flush */
1164
1165                 stex_mu_intr(hba, data);
1166         }
1167         if (hba->wait_ccb == NULL) {
1168                 printk(KERN_WARNING DRV_NAME
1169                         "(%s): lost interrupt\n", pci_name(hba->pdev));
1170                 goto out;
1171         }
1172
1173 fail_out:
1174         scsi_dma_unmap(cmd);
1175         hba->wait_ccb->req = NULL; /* nullify the req's future return */
1176         hba->wait_ccb = NULL;
1177         result = FAILED;
1178 out:
1179         spin_unlock_irqrestore(host->host_lock, flags);
1180         return result;
1181 }
1182
1183 static void stex_hard_reset(struct st_hba *hba)
1184 {
1185         struct pci_bus *bus;
1186         int i;
1187         u16 pci_cmd;
1188         u8 pci_bctl;
1189
1190         for (i = 0; i < 16; i++)
1191                 pci_read_config_dword(hba->pdev, i * 4,
1192                         &hba->pdev->saved_config_space[i]);
1193
1194         /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1195            secondary bus. Consult Intel 80331/3 developer's manual for detail */
1196         bus = hba->pdev->bus;
1197         pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1198         pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1199         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1200
1201         /*
1202          * 1 ms may be enough for 8-port controllers. But 16-port controllers
1203          * require more time to finish bus reset. Use 100 ms here for safety
1204          */
1205         msleep(100);
1206         pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1207         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1208
1209         for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
1210                 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
1211                 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
1212                         break;
1213                 msleep(1);
1214         }
1215
1216         ssleep(5);
1217         for (i = 0; i < 16; i++)
1218                 pci_write_config_dword(hba->pdev, i * 4,
1219                         hba->pdev->saved_config_space[i]);
1220 }
1221
1222 static int stex_yos_reset(struct st_hba *hba)
1223 {
1224         void __iomem *base;
1225         unsigned long flags, before;
1226         int ret = 0;
1227
1228         base = hba->mmio_base;
1229         writel(MU_INBOUND_DOORBELL_RESET, base + IDBL);
1230         readl(base + IDBL); /* flush */
1231         before = jiffies;
1232         while (hba->out_req_cnt > 0) {
1233                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1234                         printk(KERN_WARNING DRV_NAME
1235                                 "(%s): reset timeout\n", pci_name(hba->pdev));
1236                         ret = -1;
1237                         break;
1238                 }
1239                 msleep(1);
1240         }
1241
1242         spin_lock_irqsave(hba->host->host_lock, flags);
1243         if (ret == -1)
1244                 hba->mu_status = MU_STATE_FAILED;
1245         else
1246                 hba->mu_status = MU_STATE_STARTED;
1247         wake_up_all(&hba->reset_waitq);
1248         spin_unlock_irqrestore(hba->host->host_lock, flags);
1249
1250         return ret;
1251 }
1252
1253 static void stex_ss_reset(struct st_hba *hba)
1254 {
1255         writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1256         readl(hba->mmio_base + YH2I_INT);
1257         ssleep(5);
1258 }
1259
1260 static int stex_do_reset(struct st_hba *hba)
1261 {
1262         struct st_ccb *ccb;
1263         unsigned long flags;
1264         unsigned int mu_status = MU_STATE_RESETTING;
1265         u16 tag;
1266
1267         spin_lock_irqsave(hba->host->host_lock, flags);
1268         if (hba->mu_status == MU_STATE_STARTING) {
1269                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1270                 printk(KERN_INFO DRV_NAME "(%s): request reset during init\n",
1271                         pci_name(hba->pdev));
1272                 return 0;
1273         }
1274         while (hba->mu_status == MU_STATE_RESETTING) {
1275                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1276                 wait_event_timeout(hba->reset_waitq,
1277                                    hba->mu_status != MU_STATE_RESETTING,
1278                                    MU_MAX_DELAY * HZ);
1279                 spin_lock_irqsave(hba->host->host_lock, flags);
1280                 mu_status = hba->mu_status;
1281         }
1282
1283         if (mu_status != MU_STATE_RESETTING) {
1284                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1285                 return (mu_status == MU_STATE_STARTED) ? 0 : -1;
1286         }
1287
1288         hba->mu_status = MU_STATE_RESETTING;
1289         spin_unlock_irqrestore(hba->host->host_lock, flags);
1290
1291         if (hba->cardtype == st_yosemite)
1292                 return stex_yos_reset(hba);
1293
1294         if (hba->cardtype == st_shasta)
1295                 stex_hard_reset(hba);
1296         else if (hba->cardtype == st_yel)
1297                 stex_ss_reset(hba);
1298
1299         spin_lock_irqsave(hba->host->host_lock, flags);
1300         for (tag = 0; tag < hba->host->can_queue; tag++) {
1301                 ccb = &hba->ccb[tag];
1302                 if (ccb->req == NULL)
1303                         continue;
1304                 ccb->req = NULL;
1305                 if (ccb->cmd) {
1306                         scsi_dma_unmap(ccb->cmd);
1307                         ccb->cmd->result = DID_RESET << 16;
1308                         ccb->cmd->scsi_done(ccb->cmd);
1309                         ccb->cmd = NULL;
1310                 }
1311         }
1312         spin_unlock_irqrestore(hba->host->host_lock, flags);
1313
1314         if (stex_handshake(hba) == 0)
1315                 return 0;
1316
1317         printk(KERN_WARNING DRV_NAME "(%s): resetting: handshake failed\n",
1318                 pci_name(hba->pdev));
1319         return -1;
1320 }
1321
1322 static int stex_reset(struct scsi_cmnd *cmd)
1323 {
1324         struct st_hba *hba;
1325
1326         hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1327
1328         shost_printk(KERN_INFO, cmd->device->host,
1329                      "resetting host\n");
1330
1331         return stex_do_reset(hba) ? FAILED : SUCCESS;
1332 }
1333
1334 static void stex_reset_work(struct work_struct *work)
1335 {
1336         struct st_hba *hba = container_of(work, struct st_hba, reset_work);
1337
1338         stex_do_reset(hba);
1339 }
1340
1341 static int stex_biosparam(struct scsi_device *sdev,
1342         struct block_device *bdev, sector_t capacity, int geom[])
1343 {
1344         int heads = 255, sectors = 63;
1345
1346         if (capacity < 0x200000) {
1347                 heads = 64;
1348                 sectors = 32;
1349         }
1350
1351         sector_div(capacity, heads * sectors);
1352
1353         geom[0] = heads;
1354         geom[1] = sectors;
1355         geom[2] = capacity;
1356
1357         return 0;
1358 }
1359
1360 static struct scsi_host_template driver_template = {
1361         .module                         = THIS_MODULE,
1362         .name                           = DRV_NAME,
1363         .proc_name                      = DRV_NAME,
1364         .bios_param                     = stex_biosparam,
1365         .queuecommand                   = stex_queuecommand,
1366         .slave_configure                = stex_slave_config,
1367         .eh_abort_handler               = stex_abort,
1368         .eh_host_reset_handler          = stex_reset,
1369         .this_id                        = -1,
1370 };
1371
1372 static struct pci_device_id stex_pci_tbl[] = {
1373         /* st_shasta */
1374         { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1375                 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1376         { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1377                 st_shasta }, /* SuperTrak EX12350 */
1378         { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1379                 st_shasta }, /* SuperTrak EX4350 */
1380         { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1381                 st_shasta }, /* SuperTrak EX24350 */
1382
1383         /* st_vsc */
1384         { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1385
1386         /* st_yosemite */
1387         { 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite },
1388
1389         /* st_seq */
1390         { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq },
1391
1392         /* st_yel */
1393         { 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel },
1394         { 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel },
1395         { }     /* terminate list */
1396 };
1397
1398 static struct st_card_info stex_card_info[] = {
1399         /* st_shasta */
1400         {
1401                 .max_id         = 17,
1402                 .max_lun        = 8,
1403                 .max_channel    = 0,
1404                 .rq_count       = 32,
1405                 .rq_size        = 1048,
1406                 .sts_count      = 32,
1407                 .alloc_rq       = stex_alloc_req,
1408                 .map_sg         = stex_map_sg,
1409                 .send           = stex_send_cmd,
1410         },
1411
1412         /* st_vsc */
1413         {
1414                 .max_id         = 129,
1415                 .max_lun        = 1,
1416                 .max_channel    = 0,
1417                 .rq_count       = 32,
1418                 .rq_size        = 1048,
1419                 .sts_count      = 32,
1420                 .alloc_rq       = stex_alloc_req,
1421                 .map_sg         = stex_map_sg,
1422                 .send           = stex_send_cmd,
1423         },
1424
1425         /* st_yosemite */
1426         {
1427                 .max_id         = 2,
1428                 .max_lun        = 256,
1429                 .max_channel    = 0,
1430                 .rq_count       = 256,
1431                 .rq_size        = 1048,
1432                 .sts_count      = 256,
1433                 .alloc_rq       = stex_alloc_req,
1434                 .map_sg         = stex_map_sg,
1435                 .send           = stex_send_cmd,
1436         },
1437
1438         /* st_seq */
1439         {
1440                 .max_id         = 129,
1441                 .max_lun        = 1,
1442                 .max_channel    = 0,
1443                 .rq_count       = 32,
1444                 .rq_size        = 1048,
1445                 .sts_count      = 32,
1446                 .alloc_rq       = stex_alloc_req,
1447                 .map_sg         = stex_map_sg,
1448                 .send           = stex_send_cmd,
1449         },
1450
1451         /* st_yel */
1452         {
1453                 .max_id         = 129,
1454                 .max_lun        = 256,
1455                 .max_channel    = 3,
1456                 .rq_count       = 801,
1457                 .rq_size        = 512,
1458                 .sts_count      = 801,
1459                 .alloc_rq       = stex_ss_alloc_req,
1460                 .map_sg         = stex_ss_map_sg,
1461                 .send           = stex_ss_send_cmd,
1462         },
1463 };
1464
1465 static int stex_set_dma_mask(struct pci_dev * pdev)
1466 {
1467         int ret;
1468
1469         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
1470                 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
1471                 return 0;
1472         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1473         if (!ret)
1474                 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1475         return ret;
1476 }
1477
1478 static int stex_request_irq(struct st_hba *hba)
1479 {
1480         struct pci_dev *pdev = hba->pdev;
1481         int status;
1482
1483         if (msi) {
1484                 status = pci_enable_msi(pdev);
1485                 if (status != 0)
1486                         printk(KERN_ERR DRV_NAME
1487                                 "(%s): error %d setting up MSI\n",
1488                                 pci_name(pdev), status);
1489                 else
1490                         hba->msi_enabled = 1;
1491         } else
1492                 hba->msi_enabled = 0;
1493
1494         status = request_irq(pdev->irq, hba->cardtype == st_yel ?
1495                 stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba);
1496
1497         if (status != 0) {
1498                 if (hba->msi_enabled)
1499                         pci_disable_msi(pdev);
1500         }
1501         return status;
1502 }
1503
1504 static void stex_free_irq(struct st_hba *hba)
1505 {
1506         struct pci_dev *pdev = hba->pdev;
1507
1508         free_irq(pdev->irq, hba);
1509         if (hba->msi_enabled)
1510                 pci_disable_msi(pdev);
1511 }
1512
1513 static int stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1514 {
1515         struct st_hba *hba;
1516         struct Scsi_Host *host;
1517         const struct st_card_info *ci = NULL;
1518         u32 sts_offset, cp_offset, scratch_offset;
1519         int err;
1520
1521         err = pci_enable_device(pdev);
1522         if (err)
1523                 return err;
1524
1525         pci_set_master(pdev);
1526
1527         host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1528
1529         if (!host) {
1530                 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1531                         pci_name(pdev));
1532                 err = -ENOMEM;
1533                 goto out_disable;
1534         }
1535
1536         hba = (struct st_hba *)host->hostdata;
1537         memset(hba, 0, sizeof(struct st_hba));
1538
1539         err = pci_request_regions(pdev, DRV_NAME);
1540         if (err < 0) {
1541                 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1542                         pci_name(pdev));
1543                 goto out_scsi_host_put;
1544         }
1545
1546         hba->mmio_base = pci_ioremap_bar(pdev, 0);
1547         if ( !hba->mmio_base) {
1548                 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1549                         pci_name(pdev));
1550                 err = -ENOMEM;
1551                 goto out_release_regions;
1552         }
1553
1554         err = stex_set_dma_mask(pdev);
1555         if (err) {
1556                 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1557                         pci_name(pdev));
1558                 goto out_iounmap;
1559         }
1560
1561         hba->cardtype = (unsigned int) id->driver_data;
1562         ci = &stex_card_info[hba->cardtype];
1563         sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size;
1564         if (hba->cardtype == st_yel)
1565                 sts_offset += (ci->sts_count+1) * sizeof(u32);
1566         cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg);
1567         hba->dma_size = cp_offset + sizeof(struct st_frame);
1568         if (hba->cardtype == st_seq ||
1569                 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1570                 hba->extra_offset = hba->dma_size;
1571                 hba->dma_size += ST_ADDITIONAL_MEM;
1572         }
1573         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1574                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1575         if (!hba->dma_mem) {
1576                 /* Retry minimum coherent mapping for st_seq and st_vsc */
1577                 if (hba->cardtype == st_seq ||
1578                     (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1579                         printk(KERN_WARNING DRV_NAME
1580                                 "(%s): allocating min buffer for controller\n",
1581                                 pci_name(pdev));
1582                         hba->dma_size = hba->extra_offset
1583                                 + ST_ADDITIONAL_MEM_MIN;
1584                         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1585                                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1586                 }
1587
1588                 if (!hba->dma_mem) {
1589                         err = -ENOMEM;
1590                         printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1591                                 pci_name(pdev));
1592                         goto out_iounmap;
1593                 }
1594         }
1595
1596         hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL);
1597         if (!hba->ccb) {
1598                 err = -ENOMEM;
1599                 printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n",
1600                         pci_name(pdev));
1601                 goto out_pci_free;
1602         }
1603
1604         if (hba->cardtype == st_yel)
1605                 hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset);
1606         hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset);
1607         hba->copy_buffer = hba->dma_mem + cp_offset;
1608         hba->rq_count = ci->rq_count;
1609         hba->rq_size = ci->rq_size;
1610         hba->sts_count = ci->sts_count;
1611         hba->alloc_rq = ci->alloc_rq;
1612         hba->map_sg = ci->map_sg;
1613         hba->send = ci->send;
1614         hba->mu_status = MU_STATE_STARTING;
1615
1616         if (hba->cardtype == st_yel)
1617                 host->sg_tablesize = 38;
1618         else
1619                 host->sg_tablesize = 32;
1620         host->can_queue = ci->rq_count;
1621         host->cmd_per_lun = ci->rq_count;
1622         host->max_id = ci->max_id;
1623         host->max_lun = ci->max_lun;
1624         host->max_channel = ci->max_channel;
1625         host->unique_id = host->host_no;
1626         host->max_cmd_len = STEX_CDB_LENGTH;
1627
1628         hba->host = host;
1629         hba->pdev = pdev;
1630         init_waitqueue_head(&hba->reset_waitq);
1631
1632         snprintf(hba->work_q_name, sizeof(hba->work_q_name),
1633                  "stex_wq_%d", host->host_no);
1634         hba->work_q = create_singlethread_workqueue(hba->work_q_name);
1635         if (!hba->work_q) {
1636                 printk(KERN_ERR DRV_NAME "(%s): create workqueue failed\n",
1637                         pci_name(pdev));
1638                 err = -ENOMEM;
1639                 goto out_ccb_free;
1640         }
1641         INIT_WORK(&hba->reset_work, stex_reset_work);
1642
1643         err = stex_request_irq(hba);
1644         if (err) {
1645                 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1646                         pci_name(pdev));
1647                 goto out_free_wq;
1648         }
1649
1650         err = stex_handshake(hba);
1651         if (err)
1652                 goto out_free_irq;
1653
1654         pci_set_drvdata(pdev, hba);
1655
1656         err = scsi_add_host(host, &pdev->dev);
1657         if (err) {
1658                 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1659                         pci_name(pdev));
1660                 goto out_free_irq;
1661         }
1662
1663         scsi_scan_host(host);
1664
1665         return 0;
1666
1667 out_free_irq:
1668         stex_free_irq(hba);
1669 out_free_wq:
1670         destroy_workqueue(hba->work_q);
1671 out_ccb_free:
1672         kfree(hba->ccb);
1673 out_pci_free:
1674         dma_free_coherent(&pdev->dev, hba->dma_size,
1675                           hba->dma_mem, hba->dma_handle);
1676 out_iounmap:
1677         iounmap(hba->mmio_base);
1678 out_release_regions:
1679         pci_release_regions(pdev);
1680 out_scsi_host_put:
1681         scsi_host_put(host);
1682 out_disable:
1683         pci_disable_device(pdev);
1684
1685         return err;
1686 }
1687
1688 static void stex_hba_stop(struct st_hba *hba)
1689 {
1690         struct req_msg *req;
1691         struct st_msg_header *msg_h;
1692         unsigned long flags;
1693         unsigned long before;
1694         u16 tag = 0;
1695
1696         spin_lock_irqsave(hba->host->host_lock, flags);
1697         req = hba->alloc_rq(hba);
1698         if (hba->cardtype == st_yel) {
1699                 msg_h = (struct st_msg_header *)req - 1;
1700                 memset(msg_h, 0, hba->rq_size);
1701         } else
1702                 memset(req, 0, hba->rq_size);
1703
1704         if (hba->cardtype == st_yosemite || hba->cardtype == st_yel) {
1705                 req->cdb[0] = MGT_CMD;
1706                 req->cdb[1] = MGT_CMD_SIGNATURE;
1707                 req->cdb[2] = CTLR_CONFIG_CMD;
1708                 req->cdb[3] = CTLR_SHUTDOWN;
1709         } else {
1710                 req->cdb[0] = CONTROLLER_CMD;
1711                 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1712                 req->cdb[2] = CTLR_POWER_SAVING;
1713         }
1714
1715         hba->ccb[tag].cmd = NULL;
1716         hba->ccb[tag].sg_count = 0;
1717         hba->ccb[tag].sense_bufflen = 0;
1718         hba->ccb[tag].sense_buffer = NULL;
1719         hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE;
1720
1721         hba->send(hba, req, tag);
1722         spin_unlock_irqrestore(hba->host->host_lock, flags);
1723
1724         before = jiffies;
1725         while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1726                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1727                         hba->ccb[tag].req_type = 0;
1728                         return;
1729                 }
1730                 msleep(1);
1731         }
1732 }
1733
1734 static void stex_hba_free(struct st_hba *hba)
1735 {
1736         stex_free_irq(hba);
1737
1738         destroy_workqueue(hba->work_q);
1739
1740         iounmap(hba->mmio_base);
1741
1742         pci_release_regions(hba->pdev);
1743
1744         kfree(hba->ccb);
1745
1746         dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1747                           hba->dma_mem, hba->dma_handle);
1748 }
1749
1750 static void stex_remove(struct pci_dev *pdev)
1751 {
1752         struct st_hba *hba = pci_get_drvdata(pdev);
1753
1754         scsi_remove_host(hba->host);
1755
1756         stex_hba_stop(hba);
1757
1758         stex_hba_free(hba);
1759
1760         scsi_host_put(hba->host);
1761
1762         pci_disable_device(pdev);
1763 }
1764
1765 static void stex_shutdown(struct pci_dev *pdev)
1766 {
1767         struct st_hba *hba = pci_get_drvdata(pdev);
1768
1769         stex_hba_stop(hba);
1770 }
1771
1772 MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1773
1774 static struct pci_driver stex_pci_driver = {
1775         .name           = DRV_NAME,
1776         .id_table       = stex_pci_tbl,
1777         .probe          = stex_probe,
1778         .remove         = stex_remove,
1779         .shutdown       = stex_shutdown,
1780 };
1781
1782 static int __init stex_init(void)
1783 {
1784         printk(KERN_INFO DRV_NAME
1785                 ": Promise SuperTrak EX Driver version: %s\n",
1786                  ST_DRIVER_VERSION);
1787
1788         return pci_register_driver(&stex_pci_driver);
1789 }
1790
1791 static void __exit stex_exit(void)
1792 {
1793         pci_unregister_driver(&stex_pci_driver);
1794 }
1795
1796 module_init(stex_init);
1797 module_exit(stex_exit);