drivers/scsi/pm8001/pm8001_hwi.c

   1 /*
   2  * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40  #include <linux/slab.h>
  41  #include "pm8001_sas.h"
  42  #include "pm8001_hwi.h"
  43  #include "pm8001_chips.h"
  44  #include "pm8001_ctl.h"
  45
  46 /**
  47  * read_main_config_table - read the configure table and save it.
  48  * @pm8001_ha: our hba card information
  49  */
  50 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
  51 {
  52         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
  53         pm8001_ha->main_cfg_tbl.pm8001_tbl.signature    =
  54                                 pm8001_mr32(address, 0x00);
  55         pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev =
  56                                 pm8001_mr32(address, 0x04);
  57         pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev =
  58                                 pm8001_mr32(address, 0x08);
  59         pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io   =
  60                                 pm8001_mr32(address, 0x0C);
  61         pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl      =
  62                                 pm8001_mr32(address, 0x10);
  63         pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag =
  64                                 pm8001_mr32(address, 0x14);
  65         pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset   =
  66                                 pm8001_mr32(address, 0x18);
  67         pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset =
  68                 pm8001_mr32(address, MAIN_IBQ_OFFSET);
  69         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset =
  70                 pm8001_mr32(address, MAIN_OBQ_OFFSET);
  71         pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag        =
  72                 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
  73
  74         /* read analog Setting offset from the configuration table */
  75         pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset =
  76                 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
  77
  78         /* read Error Dump Offset and Length */
  79         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 =
  80                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
  81         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 =
  82                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
  83         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 =
  84                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
  85         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 =
  86                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
  87 }
  88
  89 /**
  90  * read_general_status_table - read the general status table and save it.
  91  * @pm8001_ha: our hba card information
  92  */
  93 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
  94 {
  95         void __iomem *address = pm8001_ha->general_stat_tbl_addr;
  96         pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate   =
  97                                 pm8001_mr32(address, 0x00);
  98         pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0   =
  99                                 pm8001_mr32(address, 0x04);
 100         pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1   =
 101                                 pm8001_mr32(address, 0x08);
 102         pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt          =
 103                                 pm8001_mr32(address, 0x0C);
 104         pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt           =
 105                                 pm8001_mr32(address, 0x10);
 106         pm8001_ha->gs_tbl.pm8001_tbl.rsvd               =
 107                                 pm8001_mr32(address, 0x14);
 108         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0]       =
 109                                 pm8001_mr32(address, 0x18);
 110         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1]       =
 111                                 pm8001_mr32(address, 0x1C);
 112         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2]       =
 113                                 pm8001_mr32(address, 0x20);
 114         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3]       =
 115                                 pm8001_mr32(address, 0x24);
 116         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4]       =
 117                                 pm8001_mr32(address, 0x28);
 118         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5]       =
 119                                 pm8001_mr32(address, 0x2C);
 120         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6]       =
 121                                 pm8001_mr32(address, 0x30);
 122         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7]       =
 123                                 pm8001_mr32(address, 0x34);
 124         pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val     =
 125                                 pm8001_mr32(address, 0x38);
 126         pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0]           =
 127                                 pm8001_mr32(address, 0x3C);
 128         pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1]           =
 129                                 pm8001_mr32(address, 0x40);
 130         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0]        =
 131                                 pm8001_mr32(address, 0x44);
 132         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1]        =
 133                                 pm8001_mr32(address, 0x48);
 134         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2]        =
 135                                 pm8001_mr32(address, 0x4C);
 136         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3]        =
 137                                 pm8001_mr32(address, 0x50);
 138         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4]        =
 139                                 pm8001_mr32(address, 0x54);
 140         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5]        =
 141                                 pm8001_mr32(address, 0x58);
 142         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6]        =
 143                                 pm8001_mr32(address, 0x5C);
 144         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7]        =
 145                                 pm8001_mr32(address, 0x60);
 146 }
 147
 148 /**
 149  * read_inbnd_queue_table - read the inbound queue table and save it.
 150  * @pm8001_ha: our hba card information
 151  */
 152 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 153 {
 154         int i;
 155         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 156         for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
 157                 u32 offset = i * 0x20;
 158                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
 159                       get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 160                 pm8001_ha->inbnd_q_tbl[i].pi_offset =
 161                         pm8001_mr32(address, (offset + 0x18));
 162         }
 163 }
 164
 165 /**
 166  * read_outbnd_queue_table - read the outbound queue table and save it.
 167  * @pm8001_ha: our hba card information
 168  */
 169 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 170 {
 171         int i;
 172         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 173         for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
 174                 u32 offset = i * 0x24;
 175                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
 176                       get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 177                 pm8001_ha->outbnd_q_tbl[i].ci_offset =
 178                         pm8001_mr32(address, (offset + 0x18));
 179         }
 180 }
 181
 182 /**
 183  * init_default_table_values - init the default table.
 184  * @pm8001_ha: our hba card information
 185  */
 186 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
 187 {
 188         int i;
 189         u32 offsetib, offsetob;
 190         void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
 191         void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
 192
 193         pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd          = 0;
 194         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3     = 0;
 195         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7     = 0;
 196         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3    = 0;
 197         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7    = 0;
 198         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 =
 199                                                                          0;
 200         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 =
 201                                                                          0;
 202         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
 203         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
 204         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0;
 205         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0;
 206
 207         pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr         =
 208                 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
 209         pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr         =
 210                 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
 211         pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size               =
 212                 PM8001_EVENT_LOG_SIZE;
 213         pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option             = 0x01;
 214         pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr     =
 215                 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
 216         pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr     =
 217                 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
 218         pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size           =
 219                 PM8001_EVENT_LOG_SIZE;
 220         pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option         = 0x01;
 221         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt          = 0x01;
 222         for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
 223                 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt  =
 224                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
 225                 pm8001_ha->inbnd_q_tbl[i].upper_base_addr       =
 226                         pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
 227                 pm8001_ha->inbnd_q_tbl[i].lower_base_addr       =
 228                 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
 229                 pm8001_ha->inbnd_q_tbl[i].base_virt             =
 230                         (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
 231                 pm8001_ha->inbnd_q_tbl[i].total_length          =
 232                         pm8001_ha->memoryMap.region[IB + i].total_len;
 233                 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr    =
 234                         pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
 235                 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr    =
 236                         pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
 237                 pm8001_ha->inbnd_q_tbl[i].ci_virt               =
 238                         pm8001_ha->memoryMap.region[CI + i].virt_ptr;
 239                 offsetib = i * 0x20;
 240                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar            =
 241                         get_pci_bar_index(pm8001_mr32(addressib,
 242                                 (offsetib + 0x14)));
 243                 pm8001_ha->inbnd_q_tbl[i].pi_offset             =
 244                         pm8001_mr32(addressib, (offsetib + 0x18));
 245                 pm8001_ha->inbnd_q_tbl[i].producer_idx          = 0;
 246                 pm8001_ha->inbnd_q_tbl[i].consumer_index        = 0;
 247         }
 248         for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
 249                 pm8001_ha->outbnd_q_tbl[i].element_size_cnt     =
 250                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
 251                 pm8001_ha->outbnd_q_tbl[i].upper_base_addr      =
 252                         pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
 253                 pm8001_ha->outbnd_q_tbl[i].lower_base_addr      =
 254                         pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
 255                 pm8001_ha->outbnd_q_tbl[i].base_virt            =
 256                         (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
 257                 pm8001_ha->outbnd_q_tbl[i].total_length         =
 258                         pm8001_ha->memoryMap.region[OB + i].total_len;
 259                 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr   =
 260                         pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
 261                 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr   =
 262                         pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
 263                 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay       =
 264                         0 | (10 << 16) | (i << 24);
 265                 pm8001_ha->outbnd_q_tbl[i].pi_virt              =
 266                         pm8001_ha->memoryMap.region[PI + i].virt_ptr;
 267                 offsetob = i * 0x24;
 268                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar           =
 269                         get_pci_bar_index(pm8001_mr32(addressob,
 270                         offsetob + 0x14));
 271                 pm8001_ha->outbnd_q_tbl[i].ci_offset            =
 272                         pm8001_mr32(addressob, (offsetob + 0x18));
 273                 pm8001_ha->outbnd_q_tbl[i].consumer_idx         = 0;
 274                 pm8001_ha->outbnd_q_tbl[i].producer_index       = 0;
 275         }
 276 }
 277
 278 /**
 279  * update_main_config_table - update the main default table to the HBA.
 280  * @pm8001_ha: our hba card information
 281  */
 282 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
 283 {
 284         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 285         pm8001_mw32(address, 0x24,
 286                 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd);
 287         pm8001_mw32(address, 0x28,
 288                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3);
 289         pm8001_mw32(address, 0x2C,
 290                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7);
 291         pm8001_mw32(address, 0x30,
 292                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3);
 293         pm8001_mw32(address, 0x34,
 294                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7);
 295         pm8001_mw32(address, 0x38,
 296                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 297                                         outbound_tgt_ITNexus_event_pid0_3);
 298         pm8001_mw32(address, 0x3C,
 299                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 300                                         outbound_tgt_ITNexus_event_pid4_7);
 301         pm8001_mw32(address, 0x40,
 302                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 303                                         outbound_tgt_ssp_event_pid0_3);
 304         pm8001_mw32(address, 0x44,
 305                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 306                                         outbound_tgt_ssp_event_pid4_7);
 307         pm8001_mw32(address, 0x48,
 308                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 309                                         outbound_tgt_smp_event_pid0_3);
 310         pm8001_mw32(address, 0x4C,
 311                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 312                                         outbound_tgt_smp_event_pid4_7);
 313         pm8001_mw32(address, 0x50,
 314                 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr);
 315         pm8001_mw32(address, 0x54,
 316                 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr);
 317         pm8001_mw32(address, 0x58,
 318                 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size);
 319         pm8001_mw32(address, 0x5C,
 320                 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option);
 321         pm8001_mw32(address, 0x60,
 322                 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr);
 323         pm8001_mw32(address, 0x64,
 324                 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr);
 325         pm8001_mw32(address, 0x68,
 326                 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size);
 327         pm8001_mw32(address, 0x6C,
 328                 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option);
 329         pm8001_mw32(address, 0x70,
 330                 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt);
 331 }
 332
 333 /**
 334  * update_inbnd_queue_table - update the inbound queue table to the HBA.
 335  * @pm8001_ha: our hba card information
 336  */
 337 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 338                                      int number)
 339 {
 340         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 341         u16 offset = number * 0x20;
 342         pm8001_mw32(address, offset + 0x00,
 343                 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 344         pm8001_mw32(address, offset + 0x04,
 345                 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
 346         pm8001_mw32(address, offset + 0x08,
 347                 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 348         pm8001_mw32(address, offset + 0x0C,
 349                 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
 350         pm8001_mw32(address, offset + 0x10,
 351                 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 352 }
 353
 354 /**
 355  * update_outbnd_queue_table - update the outbound queue table to the HBA.
 356  * @pm8001_ha: our hba card information
 357  */
 358 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 359                                       int number)
 360 {
 361         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 362         u16 offset = number * 0x24;
 363         pm8001_mw32(address, offset + 0x00,
 364                 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 365         pm8001_mw32(address, offset + 0x04,
 366                 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
 367         pm8001_mw32(address, offset + 0x08,
 368                 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 369         pm8001_mw32(address, offset + 0x0C,
 370                 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
 371         pm8001_mw32(address, offset + 0x10,
 372                 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 373         pm8001_mw32(address, offset + 0x1C,
 374                 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
 375 }
 376
 377 /**
 378  * pm8001_bar4_shift - function is called to shift BAR base address
 379  * @pm8001_ha : our hba card infomation
 380  * @shiftValue : shifting value in memory bar.
 381  */
 382 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
 383 {
 384         u32 regVal;
 385         unsigned long start;
 386
 387         /* program the inbound AXI translation Lower Address */
 388         pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
 389
 390         /* confirm the setting is written */
 391         start = jiffies + HZ; /* 1 sec */
 392         do {
 393                 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
 394         } while ((regVal != shiftValue) && time_before(jiffies, start));
 395
 396         if (regVal != shiftValue) {
 397                 PM8001_INIT_DBG(pm8001_ha,
 398                         pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW"
 399                         " = 0x%x\n", regVal));
 400                 return -1;
 401         }
 402         return 0;
 403 }
 404
 405 /**
 406  * mpi_set_phys_g3_with_ssc
 407  * @pm8001_ha: our hba card information
 408  * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
 409  */
 410 static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha,
 411                                      u32 SSCbit)
 412 {
 413         u32 value, offset, i;
 414         unsigned long flags;
 415
 416 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
 417 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
 418 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
 419 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
 420 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
 421 #define PHY_G3_WITH_SSC_BIT_SHIFT 13
 422 #define SNW3_PHY_CAPABILITIES_PARITY 31
 423
 424    /*
 425     * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
 426     * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
 427     */
 428         spin_lock_irqsave(&pm8001_ha->lock, flags);
 429         if (-1 == pm8001_bar4_shift(pm8001_ha,
 430                                 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) {
 431                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 432                 return;
 433         }
 434
 435         for (i = 0; i < 4; i++) {
 436                 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
 437                 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
 438         }
 439         /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
 440         if (-1 == pm8001_bar4_shift(pm8001_ha,
 441                                 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) {
 442                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 443                 return;
 444         }
 445         for (i = 4; i < 8; i++) {
 446                 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 447                 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
 448         }
 449         /*************************************************************
 450         Change the SSC upspreading value to 0x0 so that upspreading is disabled.
 451         Device MABC SMOD0 Controls
 452         Address: (via MEMBASE-III):
 453         Using shifted destination address 0x0_0000: with Offset 0xD8
 454
 455         31:28 R/W Reserved Do not change
 456         27:24 R/W SAS_SMOD_SPRDUP 0000
 457         23:20 R/W SAS_SMOD_SPRDDN 0000
 458         19:0  R/W  Reserved Do not change
 459         Upon power-up this register will read as 0x8990c016,
 460         and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
 461         so that the written value will be 0x8090c016.
 462         This will ensure only down-spreading SSC is enabled on the SPC.
 463         *************************************************************/
 464         value = pm8001_cr32(pm8001_ha, 2, 0xd8);
 465         pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
 466
 467         /*set the shifted destination address to 0x0 to avoid error operation */
 468         pm8001_bar4_shift(pm8001_ha, 0x0);
 469         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 470         return;
 471 }
 472
 473 /**
 474  * mpi_set_open_retry_interval_reg
 475  * @pm8001_ha: our hba card information
 476  * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us.
 477  */
 478 static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
 479                                             u32 interval)
 480 {
 481         u32 offset;
 482         u32 value;
 483         u32 i;
 484         unsigned long flags;
 485
 486 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
 487 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
 488 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
 489 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
 490 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
 491
 492         value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
 493         spin_lock_irqsave(&pm8001_ha->lock, flags);
 494         /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
 495         if (-1 == pm8001_bar4_shift(pm8001_ha,
 496                              OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) {
 497                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 498                 return;
 499         }
 500         for (i = 0; i < 4; i++) {
 501                 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
 502                 pm8001_cw32(pm8001_ha, 2, offset, value);
 503         }
 504
 505         if (-1 == pm8001_bar4_shift(pm8001_ha,
 506                              OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) {
 507                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 508                 return;
 509         }
 510         for (i = 4; i < 8; i++) {
 511                 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 512                 pm8001_cw32(pm8001_ha, 2, offset, value);
 513         }
 514         /*set the shifted destination address to 0x0 to avoid error operation */
 515         pm8001_bar4_shift(pm8001_ha, 0x0);
 516         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 517         return;
 518 }
 519
 520 /**
 521  * mpi_init_check - check firmware initialization status.
 522  * @pm8001_ha: our hba card information
 523  */
 524 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
 525 {
 526         u32 max_wait_count;
 527         u32 value;
 528         u32 gst_len_mpistate;
 529         /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
 530         table is updated */
 531         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
 532         /* wait until Inbound DoorBell Clear Register toggled */
 533         max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 534         do {
 535                 udelay(1);
 536                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 537                 value &= SPC_MSGU_CFG_TABLE_UPDATE;
 538         } while ((value != 0) && (--max_wait_count));
 539
 540         if (!max_wait_count)
 541                 return -1;
 542         /* check the MPI-State for initialization */
 543         gst_len_mpistate =
 544                 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 545                 GST_GSTLEN_MPIS_OFFSET);
 546         if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
 547                 return -1;
 548         /* check MPI Initialization error */
 549         gst_len_mpistate = gst_len_mpistate >> 16;
 550         if (0x0000 != gst_len_mpistate)
 551                 return -1;
 552         return 0;
 553 }
 554
 555 /**
 556  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
 557  * @pm8001_ha: our hba card information
 558  */
 559 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
 560 {
 561         u32 value, value1;
 562         u32 max_wait_count;
 563         /* check error state */
 564         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 565         value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 566         /* check AAP error */
 567         if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
 568                 /* error state */
 569                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 570                 return -1;
 571         }
 572
 573         /* check IOP error */
 574         if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
 575                 /* error state */
 576                 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
 577                 return -1;
 578         }
 579
 580         /* bit 4-31 of scratch pad1 should be zeros if it is not
 581         in error state*/
 582         if (value & SCRATCH_PAD1_STATE_MASK) {
 583                 /* error case */
 584                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 585                 return -1;
 586         }
 587
 588         /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
 589         in error state */
 590         if (value1 & SCRATCH_PAD2_STATE_MASK) {
 591                 /* error case */
 592                 return -1;
 593         }
 594
 595         max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
 596
 597         /* wait until scratch pad 1 and 2 registers in ready state  */
 598         do {
 599                 udelay(1);
 600                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 601                         & SCRATCH_PAD1_RDY;
 602                 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 603                         & SCRATCH_PAD2_RDY;
 604                 if ((--max_wait_count) == 0)
 605                         return -1;
 606         } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
 607         return 0;
 608 }
 609
 610 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
 611 {
 612         void __iomem *base_addr;
 613         u32     value;
 614         u32     offset;
 615         u32     pcibar;
 616         u32     pcilogic;
 617
 618         value = pm8001_cr32(pm8001_ha, 0, 0x44);
 619         offset = value & 0x03FFFFFF;
 620         PM8001_INIT_DBG(pm8001_ha,
 621                 pm8001_printk("Scratchpad 0 Offset: %x\n", offset));
 622         pcilogic = (value & 0xFC000000) >> 26;
 623         pcibar = get_pci_bar_index(pcilogic);
 624         PM8001_INIT_DBG(pm8001_ha,
 625                 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
 626         pm8001_ha->main_cfg_tbl_addr = base_addr =
 627                 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
 628         pm8001_ha->general_stat_tbl_addr =
 629                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
 630         pm8001_ha->inbnd_q_tbl_addr =
 631                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
 632         pm8001_ha->outbnd_q_tbl_addr =
 633                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
 634 }
 635
 636 /**
 637  * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
 638  * @pm8001_ha: our hba card information
 639  */
 640 static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
 641 {
 642         u8 i = 0;
 643         u16 deviceid;
 644         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 645         /* 8081 controllers need BAR shift to access MPI space
 646         * as this is shared with BIOS data */
 647         if (deviceid == 0x8081) {
 648                 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
 649                         PM8001_FAIL_DBG(pm8001_ha,
 650                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 651                                         GSM_SM_BASE));
 652                         return -1;
 653                 }
 654         }
 655         /* check the firmware status */
 656         if (-1 == check_fw_ready(pm8001_ha)) {
 657                 PM8001_FAIL_DBG(pm8001_ha,
 658                         pm8001_printk("Firmware is not ready!\n"));
 659                 return -EBUSY;
 660         }
 661
 662         /* Initialize pci space address eg: mpi offset */
 663         init_pci_device_addresses(pm8001_ha);
 664         init_default_table_values(pm8001_ha);
 665         read_main_config_table(pm8001_ha);
 666         read_general_status_table(pm8001_ha);
 667         read_inbnd_queue_table(pm8001_ha);
 668         read_outbnd_queue_table(pm8001_ha);
 669         /* update main config table ,inbound table and outbound table */
 670         update_main_config_table(pm8001_ha);
 671         for (i = 0; i < PM8001_MAX_INB_NUM; i++)
 672                 update_inbnd_queue_table(pm8001_ha, i);
 673         for (i = 0; i < PM8001_MAX_OUTB_NUM; i++)
 674                 update_outbnd_queue_table(pm8001_ha, i);
 675         /* 8081 controller donot require these operations */
 676         if (deviceid != 0x8081) {
 677                 mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
 678                 /* 7->130ms, 34->500ms, 119->1.5s */
 679                 mpi_set_open_retry_interval_reg(pm8001_ha, 119);
 680         }
 681         /* notify firmware update finished and check initialization status */
 682         if (0 == mpi_init_check(pm8001_ha)) {
 683                 PM8001_INIT_DBG(pm8001_ha,
 684                         pm8001_printk("MPI initialize successful!\n"));
 685         } else
 686                 return -EBUSY;
 687         /*This register is a 16-bit timer with a resolution of 1us. This is the
 688         timer used for interrupt delay/coalescing in the PCIe Application Layer.
 689         Zero is not a valid value. A value of 1 in the register will cause the
 690         interrupts to be normal. A value greater than 1 will cause coalescing
 691         delays.*/
 692         pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
 693         pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
 694         return 0;
 695 }
 696
 697 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
 698 {
 699         u32 max_wait_count;
 700         u32 value;
 701         u32 gst_len_mpistate;
 702         u16 deviceid;
 703         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 704         if (deviceid == 0x8081) {
 705                 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
 706                         PM8001_FAIL_DBG(pm8001_ha,
 707                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 708                                         GSM_SM_BASE));
 709                         return -1;
 710                 }
 711         }
 712         init_pci_device_addresses(pm8001_ha);
 713         /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
 714         table is stop */
 715         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
 716
 717         /* wait until Inbound DoorBell Clear Register toggled */
 718         max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 719         do {
 720                 udelay(1);
 721                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 722                 value &= SPC_MSGU_CFG_TABLE_RESET;
 723         } while ((value != 0) && (--max_wait_count));
 724
 725         if (!max_wait_count) {
 726                 PM8001_FAIL_DBG(pm8001_ha,
 727                         pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value));
 728                 return -1;
 729         }
 730
 731         /* check the MPI-State for termination in progress */
 732         /* wait until Inbound DoorBell Clear Register toggled */
 733         max_wait_count = 1 * 1000 * 1000;  /* 1 sec */
 734         do {
 735                 udelay(1);
 736                 gst_len_mpistate =
 737                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 738                         GST_GSTLEN_MPIS_OFFSET);
 739                 if (GST_MPI_STATE_UNINIT ==
 740                         (gst_len_mpistate & GST_MPI_STATE_MASK))
 741                         break;
 742         } while (--max_wait_count);
 743         if (!max_wait_count) {
 744                 PM8001_FAIL_DBG(pm8001_ha,
 745                         pm8001_printk(" TIME OUT MPI State = 0x%x\n",
 746                                 gst_len_mpistate & GST_MPI_STATE_MASK));
 747                 return -1;
 748         }
 749         return 0;
 750 }
 751
 752 /**
 753  * soft_reset_ready_check - Function to check FW is ready for soft reset.
 754  * @pm8001_ha: our hba card information
 755  */
 756 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
 757 {
 758         u32 regVal, regVal1, regVal2;
 759         if (mpi_uninit_check(pm8001_ha) != 0) {
 760                 PM8001_FAIL_DBG(pm8001_ha,
 761                         pm8001_printk("MPI state is not ready\n"));
 762                 return -1;
 763         }
 764         /* read the scratch pad 2 register bit 2 */
 765         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 766                 & SCRATCH_PAD2_FWRDY_RST;
 767         if (regVal == SCRATCH_PAD2_FWRDY_RST) {
 768                 PM8001_INIT_DBG(pm8001_ha,
 769                         pm8001_printk("Firmware is ready for reset .\n"));
 770         } else {
 771                 unsigned long flags;
 772                 /* Trigger NMI twice via RB6 */
 773                 spin_lock_irqsave(&pm8001_ha->lock, flags);
 774                 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
 775                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 776                         PM8001_FAIL_DBG(pm8001_ha,
 777                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 778                                         RB6_ACCESS_REG));
 779                         return -1;
 780                 }
 781                 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
 782                         RB6_MAGIC_NUMBER_RST);
 783                 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
 784                 /* wait for 100 ms */
 785                 mdelay(100);
 786                 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
 787                         SCRATCH_PAD2_FWRDY_RST;
 788                 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
 789                         regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 790                         regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 791                         PM8001_FAIL_DBG(pm8001_ha,
 792                                 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1"
 793                                 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
 794                                 regVal1, regVal2));
 795                         PM8001_FAIL_DBG(pm8001_ha,
 796                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
 797                                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
 798                         PM8001_FAIL_DBG(pm8001_ha,
 799                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
 800                                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
 801                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 802                         return -1;
 803                 }
 804                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 805         }
 806         return 0;
 807 }
 808
 809 /**
 810  * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
 811  * the FW register status to the originated status.
 812  * @pm8001_ha: our hba card information
 813  */
 814 static int
 815 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
 816 {
 817         u32     regVal, toggleVal;
 818         u32     max_wait_count;
 819         u32     regVal1, regVal2, regVal3;
 820         u32     signature = 0x252acbcd; /* for host scratch pad0 */
 821         unsigned long flags;
 822
 823         /* step1: Check FW is ready for soft reset */
 824         if (soft_reset_ready_check(pm8001_ha) != 0) {
 825                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n"));
 826                 return -1;
 827         }
 828
 829         /* step 2: clear NMI status register on AAP1 and IOP, write the same
 830         value to clear */
 831         /* map 0x60000 to BAR4(0x20), BAR2(win) */
 832         spin_lock_irqsave(&pm8001_ha->lock, flags);
 833         if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
 834                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 835                 PM8001_FAIL_DBG(pm8001_ha,
 836                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 837                         MBIC_AAP1_ADDR_BASE));
 838                 return -1;
 839         }
 840         regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
 841         PM8001_INIT_DBG(pm8001_ha,
 842                 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal));
 843         pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
 844         /* map 0x70000 to BAR4(0x20), BAR2(win) */
 845         if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
 846                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 847                 PM8001_FAIL_DBG(pm8001_ha,
 848                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 849                         MBIC_IOP_ADDR_BASE));
 850                 return -1;
 851         }
 852         regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
 853         PM8001_INIT_DBG(pm8001_ha,
 854                 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal));
 855         pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
 856
 857         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
 858         PM8001_INIT_DBG(pm8001_ha,
 859                 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal));
 860         pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
 861
 862         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
 863         PM8001_INIT_DBG(pm8001_ha,
 864                 pm8001_printk("PCIE - Event Interrupt  = 0x%x\n", regVal));
 865         pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
 866
 867         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
 868         PM8001_INIT_DBG(pm8001_ha,
 869                 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal));
 870         pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
 871
 872         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
 873         PM8001_INIT_DBG(pm8001_ha,
 874                 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal));
 875         pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
 876
 877         /* read the scratch pad 1 register bit 2 */
 878         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 879                 & SCRATCH_PAD1_RST;
 880         toggleVal = regVal ^ SCRATCH_PAD1_RST;
 881
 882         /* set signature in host scratch pad0 register to tell SPC that the
 883         host performs the soft reset */
 884         pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
 885
 886         /* read required registers for confirmming */
 887         /* map 0x0700000 to BAR4(0x20), BAR2(win) */
 888         if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
 889                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 890                 PM8001_FAIL_DBG(pm8001_ha,
 891                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 892                         GSM_ADDR_BASE));
 893                 return -1;
 894         }
 895         PM8001_INIT_DBG(pm8001_ha,
 896                 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and"
 897                 " Reset = 0x%x\n",
 898                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 899
 900         /* step 3: host read GSM Configuration and Reset register */
 901         regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
 902         /* Put those bits to low */
 903         /* GSM XCBI offset = 0x70 0000
 904         0x00 Bit 13 COM_SLV_SW_RSTB 1
 905         0x00 Bit 12 QSSP_SW_RSTB 1
 906         0x00 Bit 11 RAAE_SW_RSTB 1
 907         0x00 Bit 9 RB_1_SW_RSTB 1
 908         0x00 Bit 8 SM_SW_RSTB 1
 909         */
 910         regVal &= ~(0x00003b00);
 911         /* host write GSM Configuration and Reset register */
 912         pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
 913         PM8001_INIT_DBG(pm8001_ha,
 914                 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM "
 915                 "Configuration and Reset is set to = 0x%x\n",
 916                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 917
 918         /* step 4: */
 919         /* disable GSM - Read Address Parity Check */
 920         regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
 921         PM8001_INIT_DBG(pm8001_ha,
 922                 pm8001_printk("GSM 0x700038 - Read Address Parity Check "
 923                 "Enable = 0x%x\n", regVal1));
 924         pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
 925         PM8001_INIT_DBG(pm8001_ha,
 926                 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
 927                 "is set to = 0x%x\n",
 928                 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
 929
 930         /* disable GSM - Write Address Parity Check */
 931         regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
 932         PM8001_INIT_DBG(pm8001_ha,
 933                 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
 934                 " Enable = 0x%x\n", regVal2));
 935         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
 936         PM8001_INIT_DBG(pm8001_ha,
 937                 pm8001_printk("GSM 0x700040 - Write Address Parity Check "
 938                 "Enable is set to = 0x%x\n",
 939                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
 940
 941         /* disable GSM - Write Data Parity Check */
 942         regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
 943         PM8001_INIT_DBG(pm8001_ha,
 944                 pm8001_printk("GSM 0x300048 - Write Data Parity Check"
 945                 " Enable = 0x%x\n", regVal3));
 946         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
 947         PM8001_INIT_DBG(pm8001_ha,
 948                 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable"
 949                 "is set to = 0x%x\n",
 950         pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
 951
 952         /* step 5: delay 10 usec */
 953         udelay(10);
 954         /* step 5-b: set GPIO-0 output control to tristate anyway */
 955         if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
 956                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 957                 PM8001_INIT_DBG(pm8001_ha,
 958                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 959                                 GPIO_ADDR_BASE));
 960                 return -1;
 961         }
 962         regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
 963                 PM8001_INIT_DBG(pm8001_ha,
 964                                 pm8001_printk("GPIO Output Control Register:"
 965                                 " = 0x%x\n", regVal));
 966         /* set GPIO-0 output control to tri-state */
 967         regVal &= 0xFFFFFFFC;
 968         pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
 969
 970         /* Step 6: Reset the IOP and AAP1 */
 971         /* map 0x00000 to BAR4(0x20), BAR2(win) */
 972         if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
 973                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 974                 PM8001_FAIL_DBG(pm8001_ha,
 975                         pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
 976                         SPC_TOP_LEVEL_ADDR_BASE));
 977                 return -1;
 978         }
 979         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 980         PM8001_INIT_DBG(pm8001_ha,
 981                 pm8001_printk("Top Register before resetting IOP/AAP1"
 982                 ":= 0x%x\n", regVal));
 983         regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
 984         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 985
 986         /* step 7: Reset the BDMA/OSSP */
 987         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 988         PM8001_INIT_DBG(pm8001_ha,
 989                 pm8001_printk("Top Register before resetting BDMA/OSSP"
 990                 ": = 0x%x\n", regVal));
 991         regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
 992         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 993
 994         /* step 8: delay 10 usec */
 995         udelay(10);
 996
 997         /* step 9: bring the BDMA and OSSP out of reset */
 998         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 999         PM8001_INIT_DBG(pm8001_ha,
1000                 pm8001_printk("Top Register before bringing up BDMA/OSSP"
1001                 ":= 0x%x\n", regVal));
1002         regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
1003         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1004
1005         /* step 10: delay 10 usec */
1006         udelay(10);
1007
1008         /* step 11: reads and sets the GSM Configuration and Reset Register */
1009         /* map 0x0700000 to BAR4(0x20), BAR2(win) */
1010         if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
1011                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1012                 PM8001_FAIL_DBG(pm8001_ha,
1013                         pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
1014                         GSM_ADDR_BASE));
1015                 return -1;
1016         }
1017         PM8001_INIT_DBG(pm8001_ha,
1018                 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and "
1019                 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
1020         regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
1021         /* Put those bits to high */
1022         /* GSM XCBI offset = 0x70 0000
1023         0x00 Bit 13 COM_SLV_SW_RSTB 1
1024         0x00 Bit 12 QSSP_SW_RSTB 1
1025         0x00 Bit 11 RAAE_SW_RSTB 1
1026         0x00 Bit 9   RB_1_SW_RSTB 1
1027         0x00 Bit 8   SM_SW_RSTB 1
1028         */
1029         regVal |= (GSM_CONFIG_RESET_VALUE);
1030         pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
1031         PM8001_INIT_DBG(pm8001_ha,
1032                 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM"
1033                 " Configuration and Reset is set to = 0x%x\n",
1034                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
1035
1036         /* step 12: Restore GSM - Read Address Parity Check */
1037         regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
1038         /* just for debugging */
1039         PM8001_INIT_DBG(pm8001_ha,
1040                 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
1041                 " = 0x%x\n", regVal));
1042         pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
1043         PM8001_INIT_DBG(pm8001_ha,
1044                 pm8001_printk("GSM 0x700038 - Read Address Parity"
1045                 " Check Enable is set to = 0x%x\n",
1046                 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
1047         /* Restore GSM - Write Address Parity Check */
1048         regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
1049         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
1050         PM8001_INIT_DBG(pm8001_ha,
1051                 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
1052                 " Enable is set to = 0x%x\n",
1053                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
1054         /* Restore GSM - Write Data Parity Check */
1055         regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
1056         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
1057         PM8001_INIT_DBG(pm8001_ha,
1058                 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable"
1059                 "is set to = 0x%x\n",
1060                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
1061
1062         /* step 13: bring the IOP and AAP1 out of reset */
1063         /* map 0x00000 to BAR4(0x20), BAR2(win) */
1064         if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
1065                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1066                 PM8001_FAIL_DBG(pm8001_ha,
1067                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
1068                         SPC_TOP_LEVEL_ADDR_BASE));
1069                 return -1;
1070         }
1071         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
1072         regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1073         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1074
1075         /* step 14: delay 10 usec - Normal Mode */
1076         udelay(10);
1077         /* check Soft Reset Normal mode or Soft Reset HDA mode */
1078         if (signature == SPC_SOFT_RESET_SIGNATURE) {
1079                 /* step 15 (Normal Mode): wait until scratch pad1 register
1080                 bit 2 toggled */
1081                 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1082                 do {
1083                         udelay(1);
1084                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1085                                 SCRATCH_PAD1_RST;
1086                 } while ((regVal != toggleVal) && (--max_wait_count));
1087
1088                 if (!max_wait_count) {
1089                         regVal = pm8001_cr32(pm8001_ha, 0,
1090                                 MSGU_SCRATCH_PAD_1);
1091                         PM8001_FAIL_DBG(pm8001_ha,
1092                                 pm8001_printk("TIMEOUT : ToggleVal 0x%x,"
1093                                 "MSGU_SCRATCH_PAD1 = 0x%x\n",
1094                                 toggleVal, regVal));
1095                         PM8001_FAIL_DBG(pm8001_ha,
1096                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1097                                 pm8001_cr32(pm8001_ha, 0,
1098                                 MSGU_SCRATCH_PAD_0)));
1099                         PM8001_FAIL_DBG(pm8001_ha,
1100                                 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n",
1101                                 pm8001_cr32(pm8001_ha, 0,
1102                                 MSGU_SCRATCH_PAD_2)));
1103                         PM8001_FAIL_DBG(pm8001_ha,
1104                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1105                                 pm8001_cr32(pm8001_ha, 0,
1106                                 MSGU_SCRATCH_PAD_3)));
1107                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1108                         return -1;
1109                 }
1110
1111                 /* step 16 (Normal) - Clear ODMR and ODCR */
1112                 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1113                 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1114
1115                 /* step 17 (Normal Mode): wait for the FW and IOP to get
1116                 ready - 1 sec timeout */
1117                 /* Wait for the SPC Configuration Table to be ready */
1118                 if (check_fw_ready(pm8001_ha) == -1) {
1119                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1120                         /* return error if MPI Configuration Table not ready */
1121                         PM8001_INIT_DBG(pm8001_ha,
1122                                 pm8001_printk("FW not ready SCRATCH_PAD1"
1123                                 " = 0x%x\n", regVal));
1124                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1125                         /* return error if MPI Configuration Table not ready */
1126                         PM8001_INIT_DBG(pm8001_ha,
1127                                 pm8001_printk("FW not ready SCRATCH_PAD2"
1128                                 " = 0x%x\n", regVal));
1129                         PM8001_INIT_DBG(pm8001_ha,
1130                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1131                                 pm8001_cr32(pm8001_ha, 0,
1132                                 MSGU_SCRATCH_PAD_0)));
1133                         PM8001_INIT_DBG(pm8001_ha,
1134                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1135                                 pm8001_cr32(pm8001_ha, 0,
1136                                 MSGU_SCRATCH_PAD_3)));
1137                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1138                         return -1;
1139                 }
1140         }
1141         pm8001_bar4_shift(pm8001_ha, 0);
1142         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1143
1144         PM8001_INIT_DBG(pm8001_ha,
1145                 pm8001_printk("SPC soft reset Complete\n"));
1146         return 0;
1147 }
1148
1149 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1150 {
1151         u32 i;
1152         u32 regVal;
1153         PM8001_INIT_DBG(pm8001_ha,
1154                 pm8001_printk("chip reset start\n"));
1155
1156         /* do SPC chip reset. */
1157         regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1158         regVal &= ~(SPC_REG_RESET_DEVICE);
1159         pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1160
1161         /* delay 10 usec */
1162         udelay(10);
1163
1164         /* bring chip reset out of reset */
1165         regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1166         regVal |= SPC_REG_RESET_DEVICE;
1167         pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1168
1169         /* delay 10 usec */
1170         udelay(10);
1171
1172         /* wait for 20 msec until the firmware gets reloaded */
1173         i = 20;
1174         do {
1175                 mdelay(1);
1176         } while ((--i) != 0);
1177
1178         PM8001_INIT_DBG(pm8001_ha,
1179                 pm8001_printk("chip reset finished\n"));
1180 }
1181
1182 /**
1183  * pm8001_chip_iounmap - which maped when initialized.
1184  * @pm8001_ha: our hba card information
1185  */
1186 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1187 {
1188         s8 bar, logical = 0;
1189         for (bar = 0; bar < 6; bar++) {
1190                 /*
1191                 ** logical BARs for SPC:
1192                 ** bar 0 and 1 - logical BAR0
1193                 ** bar 2 and 3 - logical BAR1
1194                 ** bar4 - logical BAR2
1195                 ** bar5 - logical BAR3
1196                 ** Skip the appropriate assignments:
1197                 */
1198                 if ((bar == 1) || (bar == 3))
1199                         continue;
1200                 if (pm8001_ha->io_mem[logical].memvirtaddr) {
1201                         iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1202                         logical++;
1203                 }
1204         }
1205 }
1206
1207 /**
1208  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1209  * @pm8001_ha: our hba card information
1210  */
1211 static void
1212 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1213 {
1214         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1215         pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1216 }
1217
1218  /**
1219   * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1220   * @pm8001_ha: our hba card information
1221   */
1222 static void
1223 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1224 {
1225         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1226 }
1227
1228 /**
1229  * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1230  * @pm8001_ha: our hba card information
1231  */
1232 static void
1233 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1234         u32 int_vec_idx)
1235 {
1236         u32 msi_index;
1237         u32 value;
1238         msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1239         msi_index += MSIX_TABLE_BASE;
1240         pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1241         value = (1 << int_vec_idx);
1242         pm8001_cw32(pm8001_ha, 0,  MSGU_ODCR, value);
1243
1244 }
1245
1246 /**
1247  * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1248  * @pm8001_ha: our hba card information
1249  */
1250 static void
1251 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1252         u32 int_vec_idx)
1253 {
1254         u32 msi_index;
1255         msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1256         msi_index += MSIX_TABLE_BASE;
1257         pm8001_cw32(pm8001_ha, 0,  msi_index, MSIX_INTERRUPT_DISABLE);
1258 }
1259
1260 /**
1261  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1262  * @pm8001_ha: our hba card information
1263  */
1264 static void
1265 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1266 {
1267 #ifdef PM8001_USE_MSIX
1268         pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1269         return;
1270 #endif
1271         pm8001_chip_intx_interrupt_enable(pm8001_ha);
1272
1273 }
1274
1275 /**
1276  * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1277  * @pm8001_ha: our hba card information
1278  */
1279 static void
1280 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1281 {
1282 #ifdef PM8001_USE_MSIX
1283         pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1284         return;
1285 #endif
1286         pm8001_chip_intx_interrupt_disable(pm8001_ha);
1287
1288 }
1289
1290 /**
1291  * pm8001_mpi_msg_free_get - get the free message buffer for transfer
1292  * inbound queue.
1293  * @circularQ: the inbound queue  we want to transfer to HBA.
1294  * @messageSize: the message size of this transfer, normally it is 64 bytes
1295  * @messagePtr: the pointer to message.
1296  */
1297 int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
1298                             u16 messageSize, void **messagePtr)
1299 {
1300         u32 offset, consumer_index;
1301         struct mpi_msg_hdr *msgHeader;
1302         u8 bcCount = 1; /* only support single buffer */
1303
1304         /* Checks is the requested message size can be allocated in this queue*/
1305         if (messageSize > IOMB_SIZE_SPCV) {
1306                 *messagePtr = NULL;
1307                 return -1;
1308         }
1309
1310         /* Stores the new consumer index */
1311         consumer_index = pm8001_read_32(circularQ->ci_virt);
1312         circularQ->consumer_index = cpu_to_le32(consumer_index);
1313         if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) ==
1314                 le32_to_cpu(circularQ->consumer_index)) {
1315                 *messagePtr = NULL;
1316                 return -1;
1317         }
1318         /* get memory IOMB buffer address */
1319         offset = circularQ->producer_idx * messageSize;
1320         /* increment to next bcCount element */
1321         circularQ->producer_idx = (circularQ->producer_idx + bcCount)
1322                                 % PM8001_MPI_QUEUE;
1323         /* Adds that distance to the base of the region virtual address plus
1324         the message header size*/
1325         msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
1326         *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1327         return 0;
1328 }
1329
1330 /**
1331  * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to
1332  * FW to tell the fw to get this message from IOMB.
1333  * @pm8001_ha: our hba card information
1334  * @circularQ: the inbound queue we want to transfer to HBA.
1335  * @opCode: the operation code represents commands which LLDD and fw recognized.
1336  * @payload: the command payload of each operation command.
1337  */
1338 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1339                          struct inbound_queue_table *circularQ,
1340                          u32 opCode, void *payload, u32 responseQueue)
1341 {
1342         u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1343         void *pMessage;
1344
1345         if (pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size,
1346                 &pMessage) < 0) {
1347                 PM8001_IO_DBG(pm8001_ha,
1348                         pm8001_printk("No free mpi buffer\n"));
1349                 return -1;
1350         }
1351         BUG_ON(!payload);
1352         /*Copy to the payload*/
1353         memcpy(pMessage, payload, (pm8001_ha->iomb_size -
1354                                 sizeof(struct mpi_msg_hdr)));
1355
1356         /*Build the header*/
1357         Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1358                 | ((responseQueue & 0x3F) << 16)
1359                 | ((category & 0xF) << 12) | (opCode & 0xFFF));
1360
1361         pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1362         /*Update the PI to the firmware*/
1363         pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1364                 circularQ->pi_offset, circularQ->producer_idx);
1365         PM8001_IO_DBG(pm8001_ha,
1366                 pm8001_printk("INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n",
1367                         responseQueue, opCode, circularQ->producer_idx,
1368                         circularQ->consumer_index));
1369         return 0;
1370 }
1371
1372 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
1373                             struct outbound_queue_table *circularQ, u8 bc)
1374 {
1375         u32 producer_index;
1376         struct mpi_msg_hdr *msgHeader;
1377         struct mpi_msg_hdr *pOutBoundMsgHeader;
1378
1379         msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
1380         pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
1381                                 circularQ->consumer_idx * pm8001_ha->iomb_size);
1382         if (pOutBoundMsgHeader != msgHeader) {
1383                 PM8001_FAIL_DBG(pm8001_ha,
1384                         pm8001_printk("consumer_idx = %d msgHeader = %p\n",
1385                         circularQ->consumer_idx, msgHeader));
1386
1387                 /* Update the producer index from SPC */
1388                 producer_index = pm8001_read_32(circularQ->pi_virt);
1389                 circularQ->producer_index = cpu_to_le32(producer_index);
1390                 PM8001_FAIL_DBG(pm8001_ha,
1391                         pm8001_printk("consumer_idx = %d producer_index = %d"
1392                         "msgHeader = %p\n", circularQ->consumer_idx,
1393                         circularQ->producer_index, msgHeader));
1394                 return 0;
1395         }
1396         /* free the circular queue buffer elements associated with the message*/
1397         circularQ->consumer_idx = (circularQ->consumer_idx + bc)
1398                                 % PM8001_MPI_QUEUE;
1399         /* update the CI of outbound queue */
1400         pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1401                 circularQ->consumer_idx);
1402         /* Update the producer index from SPC*/
1403         producer_index = pm8001_read_32(circularQ->pi_virt);
1404         circularQ->producer_index = cpu_to_le32(producer_index);
1405         PM8001_IO_DBG(pm8001_ha,
1406                 pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx,
1407                 circularQ->producer_index));
1408         return 0;
1409 }
1410
1411 /**
1412  * pm8001_mpi_msg_consume- get the MPI message from outbound queue
1413  * message table.
1414  * @pm8001_ha: our hba card information
1415  * @circularQ: the outbound queue  table.
1416  * @messagePtr1: the message contents of this outbound message.
1417  * @pBC: the message size.
1418  */
1419 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1420                            struct outbound_queue_table *circularQ,
1421                            void **messagePtr1, u8 *pBC)
1422 {
1423         struct mpi_msg_hdr      *msgHeader;
1424         __le32  msgHeader_tmp;
1425         u32 header_tmp;
1426         do {
1427                 /* If there are not-yet-delivered messages ... */
1428                 if (le32_to_cpu(circularQ->producer_index)
1429                         != circularQ->consumer_idx) {
1430                         /*Get the pointer to the circular queue buffer element*/
1431                         msgHeader = (struct mpi_msg_hdr *)
1432                                 (circularQ->base_virt +
1433                                 circularQ->consumer_idx * pm8001_ha->iomb_size);
1434                         /* read header */
1435                         header_tmp = pm8001_read_32(msgHeader);
1436                         msgHeader_tmp = cpu_to_le32(header_tmp);
1437                         if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) {
1438                                 if (OPC_OUB_SKIP_ENTRY !=
1439                                         (le32_to_cpu(msgHeader_tmp) & 0xfff)) {
1440                                         *messagePtr1 =
1441                                                 ((u8 *)msgHeader) +
1442                                                 sizeof(struct mpi_msg_hdr);
1443                                         *pBC = (u8)((le32_to_cpu(msgHeader_tmp)
1444                                                 >> 24) & 0x1f);
1445                                         PM8001_IO_DBG(pm8001_ha,
1446                                                 pm8001_printk(": CI=%d PI=%d "
1447                                                 "msgHeader=%x\n",
1448                                                 circularQ->consumer_idx,
1449                                                 circularQ->producer_index,
1450                                                 msgHeader_tmp));
1451                                         return MPI_IO_STATUS_SUCCESS;
1452                                 } else {
1453                                         circularQ->consumer_idx =
1454                                                 (circularQ->consumer_idx +
1455                                                 ((le32_to_cpu(msgHeader_tmp)
1456                                                  >> 24) & 0x1f))
1457                                                         % PM8001_MPI_QUEUE;
1458                                         msgHeader_tmp = 0;
1459                                         pm8001_write_32(msgHeader, 0, 0);
1460                                         /* update the CI of outbound queue */
1461                                         pm8001_cw32(pm8001_ha,
1462                                                 circularQ->ci_pci_bar,
1463                                                 circularQ->ci_offset,
1464                                                 circularQ->consumer_idx);
1465                                 }
1466                         } else {
1467                                 circularQ->consumer_idx =
1468                                         (circularQ->consumer_idx +
1469                                         ((le32_to_cpu(msgHeader_tmp) >> 24) &
1470                                         0x1f)) % PM8001_MPI_QUEUE;
1471                                 msgHeader_tmp = 0;
1472                                 pm8001_write_32(msgHeader, 0, 0);
1473                                 /* update the CI of outbound queue */
1474                                 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
1475                                         circularQ->ci_offset,
1476                                         circularQ->consumer_idx);
1477                                 return MPI_IO_STATUS_FAIL;
1478                         }
1479                 } else {
1480                         u32 producer_index;
1481                         void *pi_virt = circularQ->pi_virt;
1482                         /* Update the producer index from SPC */
1483                         producer_index = pm8001_read_32(pi_virt);
1484                         circularQ->producer_index = cpu_to_le32(producer_index);
1485                 }
1486         } while (le32_to_cpu(circularQ->producer_index) !=
1487                 circularQ->consumer_idx);
1488         /* while we don't have any more not-yet-delivered message */
1489         /* report empty */
1490         return MPI_IO_STATUS_BUSY;
1491 }
1492
1493 void pm8001_work_fn(struct work_struct *work)
1494 {
1495         struct pm8001_work *pw = container_of(work, struct pm8001_work, work);
1496         struct pm8001_device *pm8001_dev;
1497         struct domain_device *dev;
1498
1499         /*
1500          * So far, all users of this stash an associated structure here.
1501          * If we get here, and this pointer is null, then the action
1502          * was cancelled. This nullification happens when the device
1503          * goes away.
1504          */
1505         pm8001_dev = pw->data; /* Most stash device structure */
1506         if ((pm8001_dev == NULL)
1507          || ((pw->handler != IO_XFER_ERROR_BREAK)
1508           && (pm8001_dev->dev_type == SAS_PHY_UNUSED))) {
1509                 kfree(pw);
1510                 return;
1511         }
1512
1513         switch (pw->handler) {
1514         case IO_XFER_ERROR_BREAK:
1515         {       /* This one stashes the sas_task instead */
1516                 struct sas_task *t = (struct sas_task *)pm8001_dev;
1517                 u32 tag;
1518                 struct pm8001_ccb_info *ccb;
1519                 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1520                 unsigned long flags, flags1;
1521                 struct task_status_struct *ts;
1522                 int i;
1523
1524                 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC)
1525                         break; /* Task still on lu */
1526                 spin_lock_irqsave(&pm8001_ha->lock, flags);
1527
1528                 spin_lock_irqsave(&t->task_state_lock, flags1);
1529                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1530                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1531                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1532                         break; /* Task got completed by another */
1533                 }
1534                 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1535
1536                 /* Search for a possible ccb that matches the task */
1537                 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1538                         ccb = &pm8001_ha->ccb_info[i];
1539                         tag = ccb->ccb_tag;
1540                         if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1541                                 break;
1542                 }
1543                 if (!ccb) {
1544                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1545                         break; /* Task got freed by another */
1546                 }
1547                 ts = &t->task_status;
1548                 ts->resp = SAS_TASK_COMPLETE;
1549                 /* Force the midlayer to retry */
1550                 ts->stat = SAS_QUEUE_FULL;
1551                 pm8001_dev = ccb->device;
1552                 if (pm8001_dev)
1553                         pm8001_dev->running_req--;
1554                 spin_lock_irqsave(&t->task_state_lock, flags1);
1555                 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1556                 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1557                 t->task_state_flags |= SAS_TASK_STATE_DONE;
1558                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1559                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1560                         PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p"
1561                                 " done with event 0x%x resp 0x%x stat 0x%x but"
1562                                 " aborted by upper layer!\n",
1563                                 t, pw->handler, ts->resp, ts->stat));
1564                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1565                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1566                 } else {
1567                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1568                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1569                         mb();/* in order to force CPU ordering */
1570                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1571                         t->task_done(t);
1572                 }
1573         }       break;
1574         case IO_XFER_OPEN_RETRY_TIMEOUT:
1575         {       /* This one stashes the sas_task instead */
1576                 struct sas_task *t = (struct sas_task *)pm8001_dev;
1577                 u32 tag;
1578                 struct pm8001_ccb_info *ccb;
1579                 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1580                 unsigned long flags, flags1;
1581                 int i, ret = 0;
1582
1583                 PM8001_IO_DBG(pm8001_ha,
1584                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1585
1586                 ret = pm8001_query_task(t);
1587
1588                 PM8001_IO_DBG(pm8001_ha,
1589                         switch (ret) {
1590                         case TMF_RESP_FUNC_SUCC:
1591                                 pm8001_printk("...Task on lu\n");
1592                                 break;
1593
1594                         case TMF_RESP_FUNC_COMPLETE:
1595                                 pm8001_printk("...Task NOT on lu\n");
1596                                 break;
1597
1598                         default:
1599                                 pm8001_printk("...query task failed!!!\n");
1600                                 break;
1601                         });
1602
1603                 spin_lock_irqsave(&pm8001_ha->lock, flags);
1604
1605                 spin_lock_irqsave(&t->task_state_lock, flags1);
1606
1607                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1608                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1609                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1610                         if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1611                                 (void)pm8001_abort_task(t);
1612                         break; /* Task got completed by another */
1613                 }
1614
1615                 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1616
1617                 /* Search for a possible ccb that matches the task */
1618                 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1619                         ccb = &pm8001_ha->ccb_info[i];
1620                         tag = ccb->ccb_tag;
1621                         if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1622                                 break;
1623                 }
1624                 if (!ccb) {
1625                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1626                         if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1627                                 (void)pm8001_abort_task(t);
1628                         break; /* Task got freed by another */
1629                 }
1630
1631                 pm8001_dev = ccb->device;
1632                 dev = pm8001_dev->sas_device;
1633
1634                 switch (ret) {
1635                 case TMF_RESP_FUNC_SUCC: /* task on lu */
1636                         ccb->open_retry = 1; /* Snub completion */
1637                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1638                         ret = pm8001_abort_task(t);
1639                         ccb->open_retry = 0;
1640                         switch (ret) {
1641                         case TMF_RESP_FUNC_SUCC:
1642                         case TMF_RESP_FUNC_COMPLETE:
1643                                 break;
1644                         default: /* device misbehavior */
1645                                 ret = TMF_RESP_FUNC_FAILED;
1646                                 PM8001_IO_DBG(pm8001_ha,
1647                                         pm8001_printk("...Reset phy\n"));
1648                                 pm8001_I_T_nexus_reset(dev);
1649                                 break;
1650                         }
1651                         break;
1652
1653                 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */
1654                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1655                         /* Do we need to abort the task locally? */
1656                         break;
1657
1658                 default: /* device misbehavior */
1659                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1660                         ret = TMF_RESP_FUNC_FAILED;
1661                         PM8001_IO_DBG(pm8001_ha,
1662                                 pm8001_printk("...Reset phy\n"));
1663                         pm8001_I_T_nexus_reset(dev);
1664                 }
1665
1666                 if (ret == TMF_RESP_FUNC_FAILED)
1667                         t = NULL;
1668                 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev);
1669                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("...Complete\n"));
1670         }       break;
1671         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1672                 dev = pm8001_dev->sas_device;
1673                 pm8001_I_T_nexus_event_handler(dev);
1674                 break;
1675         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1676                 dev = pm8001_dev->sas_device;
1677                 pm8001_I_T_nexus_reset(dev);
1678                 break;
1679         case IO_DS_IN_ERROR:
1680                 dev = pm8001_dev->sas_device;
1681                 pm8001_I_T_nexus_reset(dev);
1682                 break;
1683         case IO_DS_NON_OPERATIONAL:
1684                 dev = pm8001_dev->sas_device;
1685                 pm8001_I_T_nexus_reset(dev);
1686                 break;
1687         }
1688         kfree(pw);
1689 }
1690
1691 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1692                                int handler)
1693 {
1694         struct pm8001_work *pw;
1695         int ret = 0;
1696
1697         pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC);
1698         if (pw) {
1699                 pw->pm8001_ha = pm8001_ha;
1700                 pw->data = data;
1701                 pw->handler = handler;
1702                 INIT_WORK(&pw->work, pm8001_work_fn);
1703                 queue_work(pm8001_wq, &pw->work);
1704         } else
1705                 ret = -ENOMEM;
1706
1707         return ret;
1708 }
1709
1710 static void pm8001_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1711                 struct pm8001_device *pm8001_ha_dev)
1712 {
1713         int res;
1714         u32 ccb_tag;
1715         struct pm8001_ccb_info *ccb;
1716         struct sas_task *task = NULL;
1717         struct task_abort_req task_abort;
1718         struct inbound_queue_table *circularQ;
1719         u32 opc = OPC_INB_SATA_ABORT;
1720         int ret;
1721
1722         if (!pm8001_ha_dev) {
1723                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1724                 return;
1725         }
1726
1727         task = sas_alloc_slow_task(GFP_ATOMIC);
1728
1729         if (!task) {
1730                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1731                                                 "allocate task\n"));
1732                 return;
1733         }
1734
1735         task->task_done = pm8001_task_done;
1736
1737         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1738         if (res)
1739                 return;
1740
1741         ccb = &pm8001_ha->ccb_info[ccb_tag];
1742         ccb->device = pm8001_ha_dev;
1743         ccb->ccb_tag = ccb_tag;
1744         ccb->task = task;
1745
1746         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1747
1748         memset(&task_abort, 0, sizeof(task_abort));
1749         task_abort.abort_all = cpu_to_le32(1);
1750         task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1751         task_abort.tag = cpu_to_le32(ccb_tag);
1752
1753         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
1754
1755 }
1756
1757 static void pm8001_send_read_log(struct pm8001_hba_info *pm8001_ha,
1758                 struct pm8001_device *pm8001_ha_dev)
1759 {
1760         struct sata_start_req sata_cmd;
1761         int res;
1762         u32 ccb_tag;
1763         struct pm8001_ccb_info *ccb;
1764         struct sas_task *task = NULL;
1765         struct host_to_dev_fis fis;
1766         struct domain_device *dev;
1767         struct inbound_queue_table *circularQ;
1768         u32 opc = OPC_INB_SATA_HOST_OPSTART;
1769
1770         task = sas_alloc_slow_task(GFP_ATOMIC);
1771
1772         if (!task) {
1773                 PM8001_FAIL_DBG(pm8001_ha,
1774                         pm8001_printk("cannot allocate task !!!\n"));
1775                 return;
1776         }
1777         task->task_done = pm8001_task_done;
1778
1779         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1780         if (res) {
1781                 PM8001_FAIL_DBG(pm8001_ha,
1782                         pm8001_printk("cannot allocate tag !!!\n"));
1783                 return;
1784         }
1785
1786         /* allocate domain device by ourselves as libsas
1787          * is not going to provide any
1788         */
1789         dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1790         if (!dev) {
1791                 PM8001_FAIL_DBG(pm8001_ha,
1792                         pm8001_printk("Domain device cannot be allocated\n"));
1793                 sas_free_task(task);
1794                 return;
1795         } else {
1796                 task->dev = dev;
1797                 task->dev->lldd_dev = pm8001_ha_dev;
1798         }
1799
1800         ccb = &pm8001_ha->ccb_info[ccb_tag];
1801         ccb->device = pm8001_ha_dev;
1802         ccb->ccb_tag = ccb_tag;
1803         ccb->task = task;
1804         pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1805         pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1806
1807         memset(&sata_cmd, 0, sizeof(sata_cmd));
1808         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1809
1810         /* construct read log FIS */
1811         memset(&fis, 0, sizeof(struct host_to_dev_fis));
1812         fis.fis_type = 0x27;
1813         fis.flags = 0x80;
1814         fis.command = ATA_CMD_READ_LOG_EXT;
1815         fis.lbal = 0x10;
1816         fis.sector_count = 0x1;
1817
1818         sata_cmd.tag = cpu_to_le32(ccb_tag);
1819         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1820         sata_cmd.ncqtag_atap_dir_m |= ((0x1 << 7) | (0x5 << 9));
1821         memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1822
1823         res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
1824
1825 }
1826
1827 /**
1828  * mpi_ssp_completion- process the event that FW response to the SSP request.
1829  * @pm8001_ha: our hba card information
1830  * @piomb: the message contents of this outbound message.
1831  *
1832  * When FW has completed a ssp request for example a IO request, after it has
1833  * filled the SG data with the data, it will trigger this event represent
1834  * that he has finished the job,please check the coresponding buffer.
1835  * So we will tell the caller who maybe waiting the result to tell upper layer
1836  * that the task has been finished.
1837  */
1838 static void
1839 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1840 {
1841         struct sas_task *t;
1842         struct pm8001_ccb_info *ccb;
1843         unsigned long flags;
1844         u32 status;
1845         u32 param;
1846         u32 tag;
1847         struct ssp_completion_resp *psspPayload;
1848         struct task_status_struct *ts;
1849         struct ssp_response_iu *iu;
1850         struct pm8001_device *pm8001_dev;
1851         psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1852         status = le32_to_cpu(psspPayload->status);
1853         tag = le32_to_cpu(psspPayload->tag);
1854         ccb = &pm8001_ha->ccb_info[tag];
1855         if ((status == IO_ABORTED) && ccb->open_retry) {
1856                 /* Being completed by another */
1857                 ccb->open_retry = 0;
1858                 return;
1859         }
1860         pm8001_dev = ccb->device;
1861         param = le32_to_cpu(psspPayload->param);
1862
1863         t = ccb->task;
1864
1865         if (status && status != IO_UNDERFLOW)
1866                 PM8001_FAIL_DBG(pm8001_ha,
1867                         pm8001_printk("sas IO status 0x%x\n", status));
1868         if (unlikely(!t || !t->lldd_task || !t->dev))
1869                 return;
1870         ts = &t->task_status;
1871         switch (status) {
1872         case IO_SUCCESS:
1873                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS"
1874                         ",param = %d\n", param));
1875                 if (param == 0) {
1876                         ts->resp = SAS_TASK_COMPLETE;
1877                         ts->stat = SAM_STAT_GOOD;
1878                 } else {
1879                         ts->resp = SAS_TASK_COMPLETE;
1880                         ts->stat = SAS_PROTO_RESPONSE;
1881                         ts->residual = param;
1882                         iu = &psspPayload->ssp_resp_iu;
1883                         sas_ssp_task_response(pm8001_ha->dev, t, iu);
1884                 }
1885                 if (pm8001_dev)
1886                         pm8001_dev->running_req--;
1887                 break;
1888         case IO_ABORTED:
1889                 PM8001_IO_DBG(pm8001_ha,
1890                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
1891                 ts->resp = SAS_TASK_COMPLETE;
1892                 ts->stat = SAS_ABORTED_TASK;
1893                 break;
1894         case IO_UNDERFLOW:
1895                 /* SSP Completion with error */
1896                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW"
1897                         ",param = %d\n", param));
1898                 ts->resp = SAS_TASK_COMPLETE;
1899                 ts->stat = SAS_DATA_UNDERRUN;
1900                 ts->residual = param;
1901                 if (pm8001_dev)
1902                         pm8001_dev->running_req--;
1903                 break;
1904         case IO_NO_DEVICE:
1905                 PM8001_IO_DBG(pm8001_ha,
1906                         pm8001_printk("IO_NO_DEVICE\n"));
1907                 ts->resp = SAS_TASK_UNDELIVERED;
1908                 ts->stat = SAS_PHY_DOWN;
1909                 break;
1910         case IO_XFER_ERROR_BREAK:
1911                 PM8001_IO_DBG(pm8001_ha,
1912                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1913                 ts->resp = SAS_TASK_COMPLETE;
1914                 ts->stat = SAS_OPEN_REJECT;
1915                 /* Force the midlayer to retry */
1916                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1917                 break;
1918         case IO_XFER_ERROR_PHY_NOT_READY:
1919                 PM8001_IO_DBG(pm8001_ha,
1920                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1921                 ts->resp = SAS_TASK_COMPLETE;
1922                 ts->stat = SAS_OPEN_REJECT;
1923                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1924                 break;
1925         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1926                 PM8001_IO_DBG(pm8001_ha,
1927                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1928                 ts->resp = SAS_TASK_COMPLETE;
1929                 ts->stat = SAS_OPEN_REJECT;
1930                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1931                 break;
1932         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1933                 PM8001_IO_DBG(pm8001_ha,
1934                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1935                 ts->resp = SAS_TASK_COMPLETE;
1936                 ts->stat = SAS_OPEN_REJECT;
1937                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1938                 break;
1939         case IO_OPEN_CNX_ERROR_BREAK:
1940                 PM8001_IO_DBG(pm8001_ha,
1941                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1942                 ts->resp = SAS_TASK_COMPLETE;
1943                 ts->stat = SAS_OPEN_REJECT;
1944                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1945                 break;
1946         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1947                 PM8001_IO_DBG(pm8001_ha,
1948                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1949                 ts->resp = SAS_TASK_COMPLETE;
1950                 ts->stat = SAS_OPEN_REJECT;
1951                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1952                 if (!t->uldd_task)
1953                         pm8001_handle_event(pm8001_ha,
1954                                 pm8001_dev,
1955                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1956                 break;
1957         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1958                 PM8001_IO_DBG(pm8001_ha,
1959                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1960                 ts->resp = SAS_TASK_COMPLETE;
1961                 ts->stat = SAS_OPEN_REJECT;
1962                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1963                 break;
1964         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1965                 PM8001_IO_DBG(pm8001_ha,
1966                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1967                         "NOT_SUPPORTED\n"));
1968                 ts->resp = SAS_TASK_COMPLETE;
1969                 ts->stat = SAS_OPEN_REJECT;
1970                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1971                 break;
1972         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1973                 PM8001_IO_DBG(pm8001_ha,
1974                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1975                 ts->resp = SAS_TASK_UNDELIVERED;
1976                 ts->stat = SAS_OPEN_REJECT;
1977                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1978                 break;
1979         case IO_XFER_ERROR_NAK_RECEIVED:
1980                 PM8001_IO_DBG(pm8001_ha,
1981                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1982                 ts->resp = SAS_TASK_COMPLETE;
1983                 ts->stat = SAS_OPEN_REJECT;
1984                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1985                 break;
1986         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1987                 PM8001_IO_DBG(pm8001_ha,
1988                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1989                 ts->resp = SAS_TASK_COMPLETE;
1990                 ts->stat = SAS_NAK_R_ERR;
1991                 break;
1992         case IO_XFER_ERROR_DMA:
1993                 PM8001_IO_DBG(pm8001_ha,
1994                 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1995                 ts->resp = SAS_TASK_COMPLETE;
1996                 ts->stat = SAS_OPEN_REJECT;
1997                 break;
1998         case IO_XFER_OPEN_RETRY_TIMEOUT:
1999                 PM8001_IO_DBG(pm8001_ha,
2000                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2001                 ts->resp = SAS_TASK_COMPLETE;
2002                 ts->stat = SAS_OPEN_REJECT;
2003                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2004                 break;
2005         case IO_XFER_ERROR_OFFSET_MISMATCH:
2006                 PM8001_IO_DBG(pm8001_ha,
2007                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2008                 ts->resp = SAS_TASK_COMPLETE;
2009                 ts->stat = SAS_OPEN_REJECT;
2010                 break;
2011         case IO_PORT_IN_RESET:
2012                 PM8001_IO_DBG(pm8001_ha,
2013                         pm8001_printk("IO_PORT_IN_RESET\n"));
2014                 ts->resp = SAS_TASK_COMPLETE;
2015                 ts->stat = SAS_OPEN_REJECT;
2016                 break;
2017         case IO_DS_NON_OPERATIONAL:
2018                 PM8001_IO_DBG(pm8001_ha,
2019                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2020                 ts->resp = SAS_TASK_COMPLETE;
2021                 ts->stat = SAS_OPEN_REJECT;
2022                 if (!t->uldd_task)
2023                         pm8001_handle_event(pm8001_ha,
2024                                 pm8001_dev,
2025                                 IO_DS_NON_OPERATIONAL);
2026                 break;
2027         case IO_DS_IN_RECOVERY:
2028                 PM8001_IO_DBG(pm8001_ha,
2029                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
2030                 ts->resp = SAS_TASK_COMPLETE;
2031                 ts->stat = SAS_OPEN_REJECT;
2032                 break;
2033         case IO_TM_TAG_NOT_FOUND:
2034                 PM8001_IO_DBG(pm8001_ha,
2035                         pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
2036                 ts->resp = SAS_TASK_COMPLETE;
2037                 ts->stat = SAS_OPEN_REJECT;
2038                 break;
2039         case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2040                 PM8001_IO_DBG(pm8001_ha,
2041                         pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
2042                 ts->resp = SAS_TASK_COMPLETE;
2043                 ts->stat = SAS_OPEN_REJECT;
2044                 break;
2045         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2046                 PM8001_IO_DBG(pm8001_ha,
2047                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2048                 ts->resp = SAS_TASK_COMPLETE;
2049                 ts->stat = SAS_OPEN_REJECT;
2050                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2051                 break;
2052         default:
2053                 PM8001_IO_DBG(pm8001_ha,
2054                         pm8001_printk("Unknown status 0x%x\n", status));
2055                 /* not allowed case. Therefore, return failed status */
2056                 ts->resp = SAS_TASK_COMPLETE;
2057                 ts->stat = SAS_OPEN_REJECT;
2058                 break;
2059         }
2060         PM8001_IO_DBG(pm8001_ha,
2061                 pm8001_printk("scsi_status = %x\n ",
2062                 psspPayload->ssp_resp_iu.status));
2063         spin_lock_irqsave(&t->task_state_lock, flags);
2064         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2065         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2066         t->task_state_flags |= SAS_TASK_STATE_DONE;
2067         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2068                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2069                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2070                         " io_status 0x%x resp 0x%x "
2071                         "stat 0x%x but aborted by upper layer!\n",
2072                         t, status, ts->resp, ts->stat));
2073                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2074         } else {
2075                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2076                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2077                 mb();/* in order to force CPU ordering */
2078                 t->task_done(t);
2079         }
2080 }
2081
2082 /*See the comments for mpi_ssp_completion */
2083 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2084 {
2085         struct sas_task *t;
2086         unsigned long flags;
2087         struct task_status_struct *ts;
2088         struct pm8001_ccb_info *ccb;
2089         struct pm8001_device *pm8001_dev;
2090         struct ssp_event_resp *psspPayload =
2091                 (struct ssp_event_resp *)(piomb + 4);
2092         u32 event = le32_to_cpu(psspPayload->event);
2093         u32 tag = le32_to_cpu(psspPayload->tag);
2094         u32 port_id = le32_to_cpu(psspPayload->port_id);
2095         u32 dev_id = le32_to_cpu(psspPayload->device_id);
2096
2097         ccb = &pm8001_ha->ccb_info[tag];
2098         t = ccb->task;
2099         pm8001_dev = ccb->device;
2100         if (event)
2101                 PM8001_FAIL_DBG(pm8001_ha,
2102                         pm8001_printk("sas IO status 0x%x\n", event));
2103         if (unlikely(!t || !t->lldd_task || !t->dev))
2104                 return;
2105         ts = &t->task_status;
2106         PM8001_IO_DBG(pm8001_ha,
2107                 pm8001_printk("port_id = %x,device_id = %x\n",
2108                 port_id, dev_id));
2109         switch (event) {
2110         case IO_OVERFLOW:
2111                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
2112                 ts->resp = SAS_TASK_COMPLETE;
2113                 ts->stat = SAS_DATA_OVERRUN;
2114                 ts->residual = 0;
2115                 if (pm8001_dev)
2116                         pm8001_dev->running_req--;
2117                 break;
2118         case IO_XFER_ERROR_BREAK:
2119                 PM8001_IO_DBG(pm8001_ha,
2120                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2121                 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2122                 return;
2123         case IO_XFER_ERROR_PHY_NOT_READY:
2124                 PM8001_IO_DBG(pm8001_ha,
2125                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2126                 ts->resp = SAS_TASK_COMPLETE;
2127                 ts->stat = SAS_OPEN_REJECT;
2128                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2129                 break;
2130         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2131                 PM8001_IO_DBG(pm8001_ha,
2132                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2133                         "_SUPPORTED\n"));
2134                 ts->resp = SAS_TASK_COMPLETE;
2135                 ts->stat = SAS_OPEN_REJECT;
2136                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2137                 break;
2138         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2139                 PM8001_IO_DBG(pm8001_ha,
2140                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2141                 ts->resp = SAS_TASK_COMPLETE;
2142                 ts->stat = SAS_OPEN_REJECT;
2143                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2144                 break;
2145         case IO_OPEN_CNX_ERROR_BREAK:
2146                 PM8001_IO_DBG(pm8001_ha,
2147                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2148                 ts->resp = SAS_TASK_COMPLETE;
2149                 ts->stat = SAS_OPEN_REJECT;
2150                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2151                 break;
2152         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2153                 PM8001_IO_DBG(pm8001_ha,
2154                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2155                 ts->resp = SAS_TASK_COMPLETE;
2156                 ts->stat = SAS_OPEN_REJECT;
2157                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2158                 if (!t->uldd_task)
2159                         pm8001_handle_event(pm8001_ha,
2160                                 pm8001_dev,
2161                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2162                 break;
2163         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2164                 PM8001_IO_DBG(pm8001_ha,
2165                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2166                 ts->resp = SAS_TASK_COMPLETE;
2167                 ts->stat = SAS_OPEN_REJECT;
2168                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2169                 break;
2170         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2171                 PM8001_IO_DBG(pm8001_ha,
2172                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2173                         "NOT_SUPPORTED\n"));
2174                 ts->resp = SAS_TASK_COMPLETE;
2175                 ts->stat = SAS_OPEN_REJECT;
2176                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2177                 break;
2178         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2179                 PM8001_IO_DBG(pm8001_ha,
2180                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2181                 ts->resp = SAS_TASK_COMPLETE;
2182                 ts->stat = SAS_OPEN_REJECT;
2183                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2184                 break;
2185         case IO_XFER_ERROR_NAK_RECEIVED:
2186                 PM8001_IO_DBG(pm8001_ha,
2187                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2188                 ts->resp = SAS_TASK_COMPLETE;
2189                 ts->stat = SAS_OPEN_REJECT;
2190                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2191                 break;
2192         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2193                 PM8001_IO_DBG(pm8001_ha,
2194                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2195                 ts->resp = SAS_TASK_COMPLETE;
2196                 ts->stat = SAS_NAK_R_ERR;
2197                 break;
2198         case IO_XFER_OPEN_RETRY_TIMEOUT:
2199                 PM8001_IO_DBG(pm8001_ha,
2200                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2201                 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2202                 return;
2203         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2204                 PM8001_IO_DBG(pm8001_ha,
2205                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2206                 ts->resp = SAS_TASK_COMPLETE;
2207                 ts->stat = SAS_DATA_OVERRUN;
2208                 break;
2209         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2210                 PM8001_IO_DBG(pm8001_ha,
2211                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2212                 ts->resp = SAS_TASK_COMPLETE;
2213                 ts->stat = SAS_DATA_OVERRUN;
2214                 break;
2215         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2216                 PM8001_IO_DBG(pm8001_ha,
2217                        pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2218                 ts->resp = SAS_TASK_COMPLETE;
2219                 ts->stat = SAS_DATA_OVERRUN;
2220                 break;
2221         case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2222                 PM8001_IO_DBG(pm8001_ha,
2223                 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
2224                 ts->resp = SAS_TASK_COMPLETE;
2225                 ts->stat = SAS_DATA_OVERRUN;
2226                 break;
2227         case IO_XFER_ERROR_OFFSET_MISMATCH:
2228                 PM8001_IO_DBG(pm8001_ha,
2229                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2230                 ts->resp = SAS_TASK_COMPLETE;
2231                 ts->stat = SAS_DATA_OVERRUN;
2232                 break;
2233         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2234                 PM8001_IO_DBG(pm8001_ha,
2235                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2236                 ts->resp = SAS_TASK_COMPLETE;
2237                 ts->stat = SAS_DATA_OVERRUN;
2238                 break;
2239         case IO_XFER_CMD_FRAME_ISSUED:
2240                 PM8001_IO_DBG(pm8001_ha,
2241                         pm8001_printk("  IO_XFER_CMD_FRAME_ISSUED\n"));
2242                 return;
2243         default:
2244                 PM8001_IO_DBG(pm8001_ha,
2245                         pm8001_printk("Unknown status 0x%x\n", event));
2246                 /* not allowed case. Therefore, return failed status */
2247                 ts->resp = SAS_TASK_COMPLETE;
2248                 ts->stat = SAS_DATA_OVERRUN;
2249                 break;
2250         }
2251         spin_lock_irqsave(&t->task_state_lock, flags);
2252         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2253         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2254         t->task_state_flags |= SAS_TASK_STATE_DONE;
2255         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2256                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2257                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2258                         " event 0x%x resp 0x%x "
2259                         "stat 0x%x but aborted by upper layer!\n",
2260                         t, event, ts->resp, ts->stat));
2261                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2262         } else {
2263                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2264                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2265                 mb();/* in order to force CPU ordering */
2266                 t->task_done(t);
2267         }
2268 }
2269
2270 /*See the comments for mpi_ssp_completion */
2271 static void
2272 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2273 {
2274         struct sas_task *t;
2275         struct pm8001_ccb_info *ccb;
2276         u32 param;
2277         u32 status;
2278         u32 tag;
2279         struct sata_completion_resp *psataPayload;
2280         struct task_status_struct *ts;
2281         struct ata_task_resp *resp ;
2282         u32 *sata_resp;
2283         struct pm8001_device *pm8001_dev;
2284         unsigned long flags;
2285
2286         psataPayload = (struct sata_completion_resp *)(piomb + 4);
2287         status = le32_to_cpu(psataPayload->status);
2288         tag = le32_to_cpu(psataPayload->tag);
2289
2290         if (!tag) {
2291                 PM8001_FAIL_DBG(pm8001_ha,
2292                         pm8001_printk("tag null\n"));
2293                 return;
2294         }
2295         ccb = &pm8001_ha->ccb_info[tag];
2296         param = le32_to_cpu(psataPayload->param);
2297         if (ccb) {
2298                 t = ccb->task;
2299                 pm8001_dev = ccb->device;
2300         } else {
2301                 PM8001_FAIL_DBG(pm8001_ha,
2302                         pm8001_printk("ccb null\n"));
2303                 return;
2304         }
2305
2306         if (t) {
2307                 if (t->dev && (t->dev->lldd_dev))
2308                         pm8001_dev = t->dev->lldd_dev;
2309         } else {
2310                 PM8001_FAIL_DBG(pm8001_ha,
2311                         pm8001_printk("task null\n"));
2312                 return;
2313         }
2314
2315         if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2316                 && unlikely(!t || !t->lldd_task || !t->dev)) {
2317                 PM8001_FAIL_DBG(pm8001_ha,
2318                         pm8001_printk("task or dev null\n"));
2319                 return;
2320         }
2321
2322         ts = &t->task_status;
2323         if (!ts) {
2324                 PM8001_FAIL_DBG(pm8001_ha,
2325                         pm8001_printk("ts null\n"));
2326                 return;
2327         }
2328
2329         switch (status) {
2330         case IO_SUCCESS:
2331                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2332                 if (param == 0) {
2333                         ts->resp = SAS_TASK_COMPLETE;
2334                         ts->stat = SAM_STAT_GOOD;
2335                         /* check if response is for SEND READ LOG */
2336                         if (pm8001_dev &&
2337                                 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2338                                 /* set new bit for abort_all */
2339                                 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2340                                 /* clear bit for read log */
2341                                 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2342                                 pm8001_send_abort_all(pm8001_ha, pm8001_dev);
2343                                 /* Free the tag */
2344                                 pm8001_tag_free(pm8001_ha, tag);
2345                                 sas_free_task(t);
2346                                 return;
2347                         }
2348                 } else {
2349                         u8 len;
2350                         ts->resp = SAS_TASK_COMPLETE;
2351                         ts->stat = SAS_PROTO_RESPONSE;
2352                         ts->residual = param;
2353                         PM8001_IO_DBG(pm8001_ha,
2354                                 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2355                                 param));
2356                         sata_resp = &psataPayload->sata_resp[0];
2357                         resp = (struct ata_task_resp *)ts->buf;
2358                         if (t->ata_task.dma_xfer == 0 &&
2359                         t->data_dir == PCI_DMA_FROMDEVICE) {
2360                                 len = sizeof(struct pio_setup_fis);
2361                                 PM8001_IO_DBG(pm8001_ha,
2362                                 pm8001_printk("PIO read len = %d\n", len));
2363                         } else if (t->ata_task.use_ncq) {
2364                                 len = sizeof(struct set_dev_bits_fis);
2365                                 PM8001_IO_DBG(pm8001_ha,
2366                                         pm8001_printk("FPDMA len = %d\n", len));
2367                         } else {
2368                                 len = sizeof(struct dev_to_host_fis);
2369                                 PM8001_IO_DBG(pm8001_ha,
2370                                 pm8001_printk("other len = %d\n", len));
2371                         }
2372                         if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2373                                 resp->frame_len = len;
2374                                 memcpy(&resp->ending_fis[0], sata_resp, len);
2375                                 ts->buf_valid_size = sizeof(*resp);
2376                         } else
2377                                 PM8001_IO_DBG(pm8001_ha,
2378                                         pm8001_printk("response to large\n"));
2379                 }
2380                 if (pm8001_dev)
2381                         pm8001_dev->running_req--;
2382                 break;
2383         case IO_ABORTED:
2384                 PM8001_IO_DBG(pm8001_ha,
2385                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
2386                 ts->resp = SAS_TASK_COMPLETE;
2387                 ts->stat = SAS_ABORTED_TASK;
2388                 if (pm8001_dev)
2389                         pm8001_dev->running_req--;
2390                 break;
2391                 /* following cases are to do cases */
2392         case IO_UNDERFLOW:
2393                 /* SATA Completion with error */
2394                 PM8001_IO_DBG(pm8001_ha,
2395                         pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2396                 ts->resp = SAS_TASK_COMPLETE;
2397                 ts->stat = SAS_DATA_UNDERRUN;
2398                 ts->residual =  param;
2399                 if (pm8001_dev)
2400                         pm8001_dev->running_req--;
2401                 break;
2402         case IO_NO_DEVICE:
2403                 PM8001_IO_DBG(pm8001_ha,
2404                         pm8001_printk("IO_NO_DEVICE\n"));
2405                 ts->resp = SAS_TASK_UNDELIVERED;
2406                 ts->stat = SAS_PHY_DOWN;
2407                 break;
2408         case IO_XFER_ERROR_BREAK:
2409                 PM8001_IO_DBG(pm8001_ha,
2410                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2411                 ts->resp = SAS_TASK_COMPLETE;
2412                 ts->stat = SAS_INTERRUPTED;
2413                 break;
2414         case IO_XFER_ERROR_PHY_NOT_READY:
2415                 PM8001_IO_DBG(pm8001_ha,
2416                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2417                 ts->resp = SAS_TASK_COMPLETE;
2418                 ts->stat = SAS_OPEN_REJECT;
2419                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2420                 break;
2421         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2422                 PM8001_IO_DBG(pm8001_ha,
2423                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2424                         "_SUPPORTED\n"));
2425                 ts->resp = SAS_TASK_COMPLETE;
2426                 ts->stat = SAS_OPEN_REJECT;
2427                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2428                 break;
2429         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2430                 PM8001_IO_DBG(pm8001_ha,
2431                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2432                 ts->resp = SAS_TASK_COMPLETE;
2433                 ts->stat = SAS_OPEN_REJECT;
2434                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2435                 break;
2436         case IO_OPEN_CNX_ERROR_BREAK:
2437                 PM8001_IO_DBG(pm8001_ha,
2438                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2439                 ts->resp = SAS_TASK_COMPLETE;
2440                 ts->stat = SAS_OPEN_REJECT;
2441                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2442                 break;
2443         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2444                 PM8001_IO_DBG(pm8001_ha,
2445                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2446                 ts->resp = SAS_TASK_COMPLETE;
2447                 ts->stat = SAS_DEV_NO_RESPONSE;
2448                 if (!t->uldd_task) {
2449                         pm8001_handle_event(pm8001_ha,
2450                                 pm8001_dev,
2451                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2452                         ts->resp = SAS_TASK_UNDELIVERED;
2453                         ts->stat = SAS_QUEUE_FULL;
2454                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2455                         mb();/*in order to force CPU ordering*/
2456                         spin_unlock_irq(&pm8001_ha->lock);
2457                         t->task_done(t);
2458                         spin_lock_irq(&pm8001_ha->lock);
2459                         return;
2460                 }
2461                 break;
2462         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2463                 PM8001_IO_DBG(pm8001_ha,
2464                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2465                 ts->resp = SAS_TASK_UNDELIVERED;
2466                 ts->stat = SAS_OPEN_REJECT;
2467                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2468                 if (!t->uldd_task) {
2469                         pm8001_handle_event(pm8001_ha,
2470                                 pm8001_dev,
2471                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2472                         ts->resp = SAS_TASK_UNDELIVERED;
2473                         ts->stat = SAS_QUEUE_FULL;
2474                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2475                         mb();/*ditto*/
2476                         spin_unlock_irq(&pm8001_ha->lock);
2477                         t->task_done(t);
2478                         spin_lock_irq(&pm8001_ha->lock);
2479                         return;
2480                 }
2481                 break;
2482         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2483                 PM8001_IO_DBG(pm8001_ha,
2484                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2485                         "NOT_SUPPORTED\n"));
2486                 ts->resp = SAS_TASK_COMPLETE;
2487                 ts->stat = SAS_OPEN_REJECT;
2488                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2489                 break;
2490         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2491                 PM8001_IO_DBG(pm8001_ha,
2492                         pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES"
2493                         "_BUSY\n"));
2494                 ts->resp = SAS_TASK_COMPLETE;
2495                 ts->stat = SAS_DEV_NO_RESPONSE;
2496                 if (!t->uldd_task) {
2497                         pm8001_handle_event(pm8001_ha,
2498                                 pm8001_dev,
2499                                 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2500                         ts->resp = SAS_TASK_UNDELIVERED;
2501                         ts->stat = SAS_QUEUE_FULL;
2502                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2503                         mb();/* ditto*/
2504                         spin_unlock_irq(&pm8001_ha->lock);
2505                         t->task_done(t);
2506                         spin_lock_irq(&pm8001_ha->lock);
2507                         return;
2508                 }
2509                 break;
2510         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2511                 PM8001_IO_DBG(pm8001_ha,
2512                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2513                 ts->resp = SAS_TASK_COMPLETE;
2514                 ts->stat = SAS_OPEN_REJECT;
2515                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2516                 break;
2517         case IO_XFER_ERROR_NAK_RECEIVED:
2518                 PM8001_IO_DBG(pm8001_ha,
2519                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2520                 ts->resp = SAS_TASK_COMPLETE;
2521                 ts->stat = SAS_NAK_R_ERR;
2522                 break;
2523         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2524                 PM8001_IO_DBG(pm8001_ha,
2525                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2526                 ts->resp = SAS_TASK_COMPLETE;
2527                 ts->stat = SAS_NAK_R_ERR;
2528                 break;
2529         case IO_XFER_ERROR_DMA:
2530                 PM8001_IO_DBG(pm8001_ha,
2531                         pm8001_printk("IO_XFER_ERROR_DMA\n"));
2532                 ts->resp = SAS_TASK_COMPLETE;
2533                 ts->stat = SAS_ABORTED_TASK;
2534                 break;
2535         case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2536                 PM8001_IO_DBG(pm8001_ha,
2537                         pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2538                 ts->resp = SAS_TASK_UNDELIVERED;
2539                 ts->stat = SAS_DEV_NO_RESPONSE;
2540                 break;
2541         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2542                 PM8001_IO_DBG(pm8001_ha,
2543                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2544                 ts->resp = SAS_TASK_COMPLETE;
2545                 ts->stat = SAS_DATA_UNDERRUN;
2546                 break;
2547         case IO_XFER_OPEN_RETRY_TIMEOUT:
2548                 PM8001_IO_DBG(pm8001_ha,
2549                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2550                 ts->resp = SAS_TASK_COMPLETE;
2551                 ts->stat = SAS_OPEN_TO;
2552                 break;
2553         case IO_PORT_IN_RESET:
2554                 PM8001_IO_DBG(pm8001_ha,
2555                         pm8001_printk("IO_PORT_IN_RESET\n"));
2556                 ts->resp = SAS_TASK_COMPLETE;
2557                 ts->stat = SAS_DEV_NO_RESPONSE;
2558                 break;
2559         case IO_DS_NON_OPERATIONAL:
2560                 PM8001_IO_DBG(pm8001_ha,
2561                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2562                 ts->resp = SAS_TASK_COMPLETE;
2563                 ts->stat = SAS_DEV_NO_RESPONSE;
2564                 if (!t->uldd_task) {
2565                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2566                                     IO_DS_NON_OPERATIONAL);
2567                         ts->resp = SAS_TASK_UNDELIVERED;
2568                         ts->stat = SAS_QUEUE_FULL;
2569                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2570                         mb();/*ditto*/
2571                         spin_unlock_irq(&pm8001_ha->lock);
2572                         t->task_done(t);
2573                         spin_lock_irq(&pm8001_ha->lock);
2574                         return;
2575                 }
2576                 break;
2577         case IO_DS_IN_RECOVERY:
2578                 PM8001_IO_DBG(pm8001_ha,
2579                         pm8001_printk("  IO_DS_IN_RECOVERY\n"));
2580                 ts->resp = SAS_TASK_COMPLETE;
2581                 ts->stat = SAS_DEV_NO_RESPONSE;
2582                 break;
2583         case IO_DS_IN_ERROR:
2584                 PM8001_IO_DBG(pm8001_ha,
2585                         pm8001_printk("IO_DS_IN_ERROR\n"));
2586                 ts->resp = SAS_TASK_COMPLETE;
2587                 ts->stat = SAS_DEV_NO_RESPONSE;
2588                 if (!t->uldd_task) {
2589                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2590                                     IO_DS_IN_ERROR);
2591                         ts->resp = SAS_TASK_UNDELIVERED;
2592                         ts->stat = SAS_QUEUE_FULL;
2593                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2594                         mb();/*ditto*/
2595                         spin_unlock_irq(&pm8001_ha->lock);
2596                         t->task_done(t);
2597                         spin_lock_irq(&pm8001_ha->lock);
2598                         return;
2599                 }
2600                 break;
2601         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2602                 PM8001_IO_DBG(pm8001_ha,
2603                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2604                 ts->resp = SAS_TASK_COMPLETE;
2605                 ts->stat = SAS_OPEN_REJECT;
2606                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2607         default:
2608                 PM8001_IO_DBG(pm8001_ha,
2609                         pm8001_printk("Unknown status 0x%x\n", status));
2610                 /* not allowed case. Therefore, return failed status */
2611                 ts->resp = SAS_TASK_COMPLETE;
2612                 ts->stat = SAS_DEV_NO_RESPONSE;
2613                 break;
2614         }
2615         spin_lock_irqsave(&t->task_state_lock, flags);
2616         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2617         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2618         t->task_state_flags |= SAS_TASK_STATE_DONE;
2619         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2620                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2621                 PM8001_FAIL_DBG(pm8001_ha,
2622                         pm8001_printk("task 0x%p done with io_status 0x%x"
2623                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2624                         t, status, ts->resp, ts->stat));
2625                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2626         } else if (t->uldd_task) {
2627                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2628                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2629                 mb();/* ditto */
2630                 spin_unlock_irq(&pm8001_ha->lock);
2631                 t->task_done(t);
2632                 spin_lock_irq(&pm8001_ha->lock);
2633         } else if (!t->uldd_task) {
2634                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2635                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2636                 mb();/*ditto*/
2637                 spin_unlock_irq(&pm8001_ha->lock);
2638                 t->task_done(t);
2639                 spin_lock_irq(&pm8001_ha->lock);
2640         }
2641 }
2642
2643 /*See the comments for mpi_ssp_completion */
2644 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2645 {
2646         struct sas_task *t;
2647         struct task_status_struct *ts;
2648         struct pm8001_ccb_info *ccb;
2649         struct pm8001_device *pm8001_dev;
2650         struct sata_event_resp *psataPayload =
2651                 (struct sata_event_resp *)(piomb + 4);
2652         u32 event = le32_to_cpu(psataPayload->event);
2653         u32 tag = le32_to_cpu(psataPayload->tag);
2654         u32 port_id = le32_to_cpu(psataPayload->port_id);
2655         u32 dev_id = le32_to_cpu(psataPayload->device_id);
2656         unsigned long flags;
2657
2658         ccb = &pm8001_ha->ccb_info[tag];
2659
2660         if (ccb) {
2661                 t = ccb->task;
2662                 pm8001_dev = ccb->device;
2663         } else {
2664                 PM8001_FAIL_DBG(pm8001_ha,
2665                         pm8001_printk("No CCB !!!. returning\n"));
2666         }
2667         if (event)
2668                 PM8001_FAIL_DBG(pm8001_ha,
2669                         pm8001_printk("SATA EVENT 0x%x\n", event));
2670
2671         /* Check if this is NCQ error */
2672         if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2673                 /* find device using device id */
2674                 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2675                 /* send read log extension */
2676                 if (pm8001_dev)
2677                         pm8001_send_read_log(pm8001_ha, pm8001_dev);
2678                 return;
2679         }
2680
2681         ccb = &pm8001_ha->ccb_info[tag];
2682         t = ccb->task;
2683         pm8001_dev = ccb->device;
2684         if (event)
2685                 PM8001_FAIL_DBG(pm8001_ha,
2686                         pm8001_printk("sata IO status 0x%x\n", event));
2687         if (unlikely(!t || !t->lldd_task || !t->dev))
2688                 return;
2689         ts = &t->task_status;
2690         PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2691                 "port_id:0x%x, device_id:0x%x, tag:0x%x, event:0x%x\n",
2692                 port_id, dev_id, tag, event));
2693         switch (event) {
2694         case IO_OVERFLOW:
2695                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2696                 ts->resp = SAS_TASK_COMPLETE;
2697                 ts->stat = SAS_DATA_OVERRUN;
2698                 ts->residual = 0;
2699                 if (pm8001_dev)
2700                         pm8001_dev->running_req--;
2701                 break;
2702         case IO_XFER_ERROR_BREAK:
2703                 PM8001_IO_DBG(pm8001_ha,
2704                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2705                 ts->resp = SAS_TASK_COMPLETE;
2706                 ts->stat = SAS_INTERRUPTED;
2707                 break;
2708         case IO_XFER_ERROR_PHY_NOT_READY:
2709                 PM8001_IO_DBG(pm8001_ha,
2710                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2711                 ts->resp = SAS_TASK_COMPLETE;
2712                 ts->stat = SAS_OPEN_REJECT;
2713                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2714                 break;
2715         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2716                 PM8001_IO_DBG(pm8001_ha,
2717                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2718                         "_SUPPORTED\n"));
2719                 ts->resp = SAS_TASK_COMPLETE;
2720                 ts->stat = SAS_OPEN_REJECT;
2721                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2722                 break;
2723         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2724                 PM8001_IO_DBG(pm8001_ha,
2725                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2726                 ts->resp = SAS_TASK_COMPLETE;
2727                 ts->stat = SAS_OPEN_REJECT;
2728                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2729                 break;
2730         case IO_OPEN_CNX_ERROR_BREAK:
2731                 PM8001_IO_DBG(pm8001_ha,
2732                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2733                 ts->resp = SAS_TASK_COMPLETE;
2734                 ts->stat = SAS_OPEN_REJECT;
2735                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2736                 break;
2737         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2738                 PM8001_IO_DBG(pm8001_ha,
2739                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2740                 ts->resp = SAS_TASK_UNDELIVERED;
2741                 ts->stat = SAS_DEV_NO_RESPONSE;
2742                 if (!t->uldd_task) {
2743                         pm8001_handle_event(pm8001_ha,
2744                                 pm8001_dev,
2745                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2746                         ts->resp = SAS_TASK_COMPLETE;
2747                         ts->stat = SAS_QUEUE_FULL;
2748                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2749                         mb();/*ditto*/
2750                         spin_unlock_irq(&pm8001_ha->lock);
2751                         t->task_done(t);
2752                         spin_lock_irq(&pm8001_ha->lock);
2753                         return;
2754                 }
2755                 break;
2756         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2757                 PM8001_IO_DBG(pm8001_ha,
2758                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2759                 ts->resp = SAS_TASK_UNDELIVERED;
2760                 ts->stat = SAS_OPEN_REJECT;
2761                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2762                 break;
2763         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2764                 PM8001_IO_DBG(pm8001_ha,
2765                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2766                         "NOT_SUPPORTED\n"));
2767                 ts->resp = SAS_TASK_COMPLETE;
2768                 ts->stat = SAS_OPEN_REJECT;
2769                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2770                 break;
2771         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2772                 PM8001_IO_DBG(pm8001_ha,
2773                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2774                 ts->resp = SAS_TASK_COMPLETE;
2775                 ts->stat = SAS_OPEN_REJECT;
2776                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2777                 break;
2778         case IO_XFER_ERROR_NAK_RECEIVED:
2779                 PM8001_IO_DBG(pm8001_ha,
2780                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2781                 ts->resp = SAS_TASK_COMPLETE;
2782                 ts->stat = SAS_NAK_R_ERR;
2783                 break;
2784         case IO_XFER_ERROR_PEER_ABORTED:
2785                 PM8001_IO_DBG(pm8001_ha,
2786                         pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2787                 ts->resp = SAS_TASK_COMPLETE;
2788                 ts->stat = SAS_NAK_R_ERR;
2789                 break;
2790         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2791                 PM8001_IO_DBG(pm8001_ha,
2792                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2793                 ts->resp = SAS_TASK_COMPLETE;
2794                 ts->stat = SAS_DATA_UNDERRUN;
2795                 break;
2796         case IO_XFER_OPEN_RETRY_TIMEOUT:
2797                 PM8001_IO_DBG(pm8001_ha,
2798                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2799                 ts->resp = SAS_TASK_COMPLETE;
2800                 ts->stat = SAS_OPEN_TO;
2801                 break;
2802         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2803                 PM8001_IO_DBG(pm8001_ha,
2804                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2805                 ts->resp = SAS_TASK_COMPLETE;
2806                 ts->stat = SAS_OPEN_TO;
2807                 break;
2808         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2809                 PM8001_IO_DBG(pm8001_ha,
2810                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2811                 ts->resp = SAS_TASK_COMPLETE;
2812                 ts->stat = SAS_OPEN_TO;
2813                 break;
2814         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2815                 PM8001_IO_DBG(pm8001_ha,
2816                        pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2817                 ts->resp = SAS_TASK_COMPLETE;
2818                 ts->stat = SAS_OPEN_TO;
2819                 break;
2820         case IO_XFER_ERROR_OFFSET_MISMATCH:
2821                 PM8001_IO_DBG(pm8001_ha,
2822                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2823                 ts->resp = SAS_TASK_COMPLETE;
2824                 ts->stat = SAS_OPEN_TO;
2825                 break;
2826         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2827                 PM8001_IO_DBG(pm8001_ha,
2828                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2829                 ts->resp = SAS_TASK_COMPLETE;
2830                 ts->stat = SAS_OPEN_TO;
2831                 break;
2832         case IO_XFER_CMD_FRAME_ISSUED:
2833                 PM8001_IO_DBG(pm8001_ha,
2834                         pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2835                 break;
2836         case IO_XFER_PIO_SETUP_ERROR:
2837                 PM8001_IO_DBG(pm8001_ha,
2838                         pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2839                 ts->resp = SAS_TASK_COMPLETE;
2840                 ts->stat = SAS_OPEN_TO;
2841                 break;
2842         default:
2843                 PM8001_IO_DBG(pm8001_ha,
2844                         pm8001_printk("Unknown status 0x%x\n", event));
2845                 /* not allowed case. Therefore, return failed status */
2846                 ts->resp = SAS_TASK_COMPLETE;
2847                 ts->stat = SAS_OPEN_TO;
2848                 break;
2849         }
2850         spin_lock_irqsave(&t->task_state_lock, flags);
2851         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2852         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2853         t->task_state_flags |= SAS_TASK_STATE_DONE;
2854         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2855                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2856                 PM8001_FAIL_DBG(pm8001_ha,
2857                         pm8001_printk("task 0x%p done with io_status 0x%x"
2858                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2859                         t, event, ts->resp, ts->stat));
2860                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2861         } else if (t->uldd_task) {
2862                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2863                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2864                 mb();/* ditto */
2865                 spin_unlock_irq(&pm8001_ha->lock);
2866                 t->task_done(t);
2867                 spin_lock_irq(&pm8001_ha->lock);
2868         } else if (!t->uldd_task) {
2869                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2870                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2871                 mb();/*ditto*/
2872                 spin_unlock_irq(&pm8001_ha->lock);
2873                 t->task_done(t);
2874                 spin_lock_irq(&pm8001_ha->lock);
2875         }
2876 }
2877
2878 /*See the comments for mpi_ssp_completion */
2879 static void
2880 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2881 {
2882         u32 param;
2883         struct sas_task *t;
2884         struct pm8001_ccb_info *ccb;
2885         unsigned long flags;
2886         u32 status;
2887         u32 tag;
2888         struct smp_completion_resp *psmpPayload;
2889         struct task_status_struct *ts;
2890         struct pm8001_device *pm8001_dev;
2891
2892         psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2893         status = le32_to_cpu(psmpPayload->status);
2894         tag = le32_to_cpu(psmpPayload->tag);
2895
2896         ccb = &pm8001_ha->ccb_info[tag];
2897         param = le32_to_cpu(psmpPayload->param);
2898         t = ccb->task;
2899         ts = &t->task_status;
2900         pm8001_dev = ccb->device;
2901         if (status)
2902                 PM8001_FAIL_DBG(pm8001_ha,
2903                         pm8001_printk("smp IO status 0x%x\n", status));
2904         if (unlikely(!t || !t->lldd_task || !t->dev))
2905                 return;
2906
2907         switch (status) {
2908         case IO_SUCCESS:
2909                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2910                 ts->resp = SAS_TASK_COMPLETE;
2911                 ts->stat = SAM_STAT_GOOD;
2912         if (pm8001_dev)
2913                         pm8001_dev->running_req--;
2914                 break;
2915         case IO_ABORTED:
2916                 PM8001_IO_DBG(pm8001_ha,
2917                         pm8001_printk("IO_ABORTED IOMB\n"));
2918                 ts->resp = SAS_TASK_COMPLETE;
2919                 ts->stat = SAS_ABORTED_TASK;
2920                 if (pm8001_dev)
2921                         pm8001_dev->running_req--;
2922                 break;
2923         case IO_OVERFLOW:
2924                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2925                 ts->resp = SAS_TASK_COMPLETE;
2926                 ts->stat = SAS_DATA_OVERRUN;
2927                 ts->residual = 0;
2928                 if (pm8001_dev)
2929                         pm8001_dev->running_req--;
2930                 break;
2931         case IO_NO_DEVICE:
2932                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2933                 ts->resp = SAS_TASK_COMPLETE;
2934                 ts->stat = SAS_PHY_DOWN;
2935                 break;
2936         case IO_ERROR_HW_TIMEOUT:
2937                 PM8001_IO_DBG(pm8001_ha,
2938                         pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2939                 ts->resp = SAS_TASK_COMPLETE;
2940                 ts->stat = SAM_STAT_BUSY;
2941                 break;
2942         case IO_XFER_ERROR_BREAK:
2943                 PM8001_IO_DBG(pm8001_ha,
2944                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2945                 ts->resp = SAS_TASK_COMPLETE;
2946                 ts->stat = SAM_STAT_BUSY;
2947                 break;
2948         case IO_XFER_ERROR_PHY_NOT_READY:
2949                 PM8001_IO_DBG(pm8001_ha,
2950                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2951                 ts->resp = SAS_TASK_COMPLETE;
2952                 ts->stat = SAM_STAT_BUSY;
2953                 break;
2954         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2955                 PM8001_IO_DBG(pm8001_ha,
2956                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2957                 ts->resp = SAS_TASK_COMPLETE;
2958                 ts->stat = SAS_OPEN_REJECT;
2959                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2960                 break;
2961         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2962                 PM8001_IO_DBG(pm8001_ha,
2963                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2964                 ts->resp = SAS_TASK_COMPLETE;
2965                 ts->stat = SAS_OPEN_REJECT;
2966                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2967                 break;
2968         case IO_OPEN_CNX_ERROR_BREAK:
2969                 PM8001_IO_DBG(pm8001_ha,
2970                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2971                 ts->resp = SAS_TASK_COMPLETE;
2972                 ts->stat = SAS_OPEN_REJECT;
2973                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2974                 break;
2975         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2976                 PM8001_IO_DBG(pm8001_ha,
2977                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2978                 ts->resp = SAS_TASK_COMPLETE;
2979                 ts->stat = SAS_OPEN_REJECT;
2980                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2981                 pm8001_handle_event(pm8001_ha,
2982                                 pm8001_dev,
2983                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2984                 break;
2985         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2986                 PM8001_IO_DBG(pm8001_ha,
2987                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2988                 ts->resp = SAS_TASK_COMPLETE;
2989                 ts->stat = SAS_OPEN_REJECT;
2990                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2991                 break;
2992         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2993                 PM8001_IO_DBG(pm8001_ha,
2994                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2995                         "NOT_SUPPORTED\n"));
2996                 ts->resp = SAS_TASK_COMPLETE;
2997                 ts->stat = SAS_OPEN_REJECT;
2998                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2999                 break;
3000         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
3001                 PM8001_IO_DBG(pm8001_ha,
3002                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
3003                 ts->resp = SAS_TASK_COMPLETE;
3004                 ts->stat = SAS_OPEN_REJECT;
3005                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
3006                 break;
3007         case IO_XFER_ERROR_RX_FRAME:
3008                 PM8001_IO_DBG(pm8001_ha,
3009                         pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
3010                 ts->resp = SAS_TASK_COMPLETE;
3011                 ts->stat = SAS_DEV_NO_RESPONSE;
3012                 break;
3013         case IO_XFER_OPEN_RETRY_TIMEOUT:
3014                 PM8001_IO_DBG(pm8001_ha,
3015                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
3016                 ts->resp = SAS_TASK_COMPLETE;
3017                 ts->stat = SAS_OPEN_REJECT;
3018                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3019                 break;
3020         case IO_ERROR_INTERNAL_SMP_RESOURCE:
3021                 PM8001_IO_DBG(pm8001_ha,
3022                         pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
3023                 ts->resp = SAS_TASK_COMPLETE;
3024                 ts->stat = SAS_QUEUE_FULL;
3025                 break;
3026         case IO_PORT_IN_RESET:
3027                 PM8001_IO_DBG(pm8001_ha,
3028                         pm8001_printk("IO_PORT_IN_RESET\n"));
3029                 ts->resp = SAS_TASK_COMPLETE;
3030                 ts->stat = SAS_OPEN_REJECT;
3031                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3032                 break;
3033         case IO_DS_NON_OPERATIONAL:
3034                 PM8001_IO_DBG(pm8001_ha,
3035                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
3036                 ts->resp = SAS_TASK_COMPLETE;
3037                 ts->stat = SAS_DEV_NO_RESPONSE;
3038                 break;
3039         case IO_DS_IN_RECOVERY:
3040                 PM8001_IO_DBG(pm8001_ha,
3041                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
3042                 ts->resp = SAS_TASK_COMPLETE;
3043                 ts->stat = SAS_OPEN_REJECT;
3044                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3045                 break;
3046         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
3047                 PM8001_IO_DBG(pm8001_ha,
3048                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
3049                 ts->resp = SAS_TASK_COMPLETE;
3050                 ts->stat = SAS_OPEN_REJECT;
3051                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3052                 break;
3053         default:
3054                 PM8001_IO_DBG(pm8001_ha,
3055                         pm8001_printk("Unknown status 0x%x\n", status));
3056                 ts->resp = SAS_TASK_COMPLETE;
3057                 ts->stat = SAS_DEV_NO_RESPONSE;
3058                 /* not allowed case. Therefore, return failed status */
3059                 break;
3060         }
3061         spin_lock_irqsave(&t->task_state_lock, flags);
3062         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3063         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3064         t->task_state_flags |= SAS_TASK_STATE_DONE;
3065         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
3066                 spin_unlock_irqrestore(&t->task_state_lock, flags);
3067                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
3068                         " io_status 0x%x resp 0x%x "
3069                         "stat 0x%x but aborted by upper layer!\n",
3070                         t, status, ts->resp, ts->stat));
3071                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3072         } else {
3073                 spin_unlock_irqrestore(&t->task_state_lock, flags);
3074                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3075                 mb();/* in order to force CPU ordering */
3076                 t->task_done(t);
3077         }
3078 }
3079
3080 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
3081                 void *piomb)
3082 {
3083         struct set_dev_state_resp *pPayload =
3084                 (struct set_dev_state_resp *)(piomb + 4);
3085         u32 tag = le32_to_cpu(pPayload->tag);
3086         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3087         struct pm8001_device *pm8001_dev = ccb->device;
3088         u32 status = le32_to_cpu(pPayload->status);
3089         u32 device_id = le32_to_cpu(pPayload->device_id);
3090         u8 pds = le32_to_cpu(pPayload->pds_nds) | PDS_BITS;
3091         u8 nds = le32_to_cpu(pPayload->pds_nds) | NDS_BITS;
3092         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state "
3093                 "from 0x%x to 0x%x status = 0x%x!\n",
3094                 device_id, pds, nds, status));
3095         complete(pm8001_dev->setds_completion);
3096         ccb->task = NULL;
3097         ccb->ccb_tag = 0xFFFFFFFF;
3098         pm8001_ccb_free(pm8001_ha, tag);
3099 }
3100
3101 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3102 {
3103         struct get_nvm_data_resp *pPayload =
3104                 (struct get_nvm_data_resp *)(piomb + 4);
3105         u32 tag = le32_to_cpu(pPayload->tag);
3106         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3107         u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3108         complete(pm8001_ha->nvmd_completion);
3109         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n"));
3110         if ((dlen_status & NVMD_STAT) != 0) {
3111                 PM8001_FAIL_DBG(pm8001_ha,
3112                         pm8001_printk("Set nvm data error!\n"));
3113                 return;
3114         }
3115         ccb->task = NULL;
3116         ccb->ccb_tag = 0xFFFFFFFF;
3117         pm8001_ccb_free(pm8001_ha, tag);
3118 }
3119
3120 void
3121 pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3122 {
3123         struct fw_control_ex    *fw_control_context;
3124         struct get_nvm_data_resp *pPayload =
3125                 (struct get_nvm_data_resp *)(piomb + 4);
3126         u32 tag = le32_to_cpu(pPayload->tag);
3127         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3128         u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3129         u32 ir_tds_bn_dps_das_nvm =
3130                 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
3131         void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
3132         fw_control_context = ccb->fw_control_context;
3133
3134         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n"));
3135         if ((dlen_status & NVMD_STAT) != 0) {
3136                 PM8001_FAIL_DBG(pm8001_ha,
3137                         pm8001_printk("Get nvm data error!\n"));
3138                 complete(pm8001_ha->nvmd_completion);
3139                 return;
3140         }
3141
3142         if (ir_tds_bn_dps_das_nvm & IPMode) {
3143                 /* indirect mode - IR bit set */
3144                 PM8001_MSG_DBG(pm8001_ha,
3145                         pm8001_printk("Get NVMD success, IR=1\n"));
3146                 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
3147                         if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
3148                                 memcpy(pm8001_ha->sas_addr,
3149                                       ((u8 *)virt_addr + 4),
3150                                        SAS_ADDR_SIZE);
3151                                 PM8001_MSG_DBG(pm8001_ha,
3152                                         pm8001_printk("Get SAS address"
3153                                         " from VPD successfully!\n"));
3154                         }
3155                 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
3156                         || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
3157                         ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
3158                                 ;
3159                 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
3160                         || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
3161                         ;
3162                 } else {
3163                         /* Should not be happened*/
3164                         PM8001_MSG_DBG(pm8001_ha,
3165                                 pm8001_printk("(IR=1)Wrong Device type 0x%x\n",
3166                                 ir_tds_bn_dps_das_nvm));
3167                 }
3168         } else /* direct mode */{
3169                 PM8001_MSG_DBG(pm8001_ha,
3170                         pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n",
3171                         (dlen_status & NVMD_LEN) >> 24));
3172         }
3173         memcpy(fw_control_context->usrAddr,
3174                 pm8001_ha->memoryMap.region[NVMD].virt_ptr,
3175                 fw_control_context->len);
3176         complete(pm8001_ha->nvmd_completion);
3177         ccb->task = NULL;
3178         ccb->ccb_tag = 0xFFFFFFFF;
3179         pm8001_ccb_free(pm8001_ha, tag);
3180 }
3181
3182 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
3183 {
3184         struct local_phy_ctl_resp *pPayload =
3185                 (struct local_phy_ctl_resp *)(piomb + 4);
3186         u32 status = le32_to_cpu(pPayload->status);
3187         u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
3188         u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
3189         if (status != 0) {
3190                 PM8001_MSG_DBG(pm8001_ha,
3191                         pm8001_printk("%x phy execute %x phy op failed!\n",
3192                         phy_id, phy_op));
3193         } else
3194                 PM8001_MSG_DBG(pm8001_ha,
3195                         pm8001_printk("%x phy execute %x phy op success!\n",
3196                         phy_id, phy_op));
3197         return 0;
3198 }
3199
3200 /**
3201  * pm8001_bytes_dmaed - one of the interface function communication with libsas
3202  * @pm8001_ha: our hba card information
3203  * @i: which phy that received the event.
3204  *
3205  * when HBA driver received the identify done event or initiate FIS received
3206  * event(for SATA), it will invoke this function to notify the sas layer that
3207  * the sas toplogy has formed, please discover the the whole sas domain,
3208  * while receive a broadcast(change) primitive just tell the sas
3209  * layer to discover the changed domain rather than the whole domain.
3210  */
3211 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
3212 {
3213         struct pm8001_phy *phy = &pm8001_ha->phy[i];
3214         struct asd_sas_phy *sas_phy = &phy->sas_phy;
3215         struct sas_ha_struct *sas_ha;
3216         if (!phy->phy_attached)
3217                 return;
3218
3219         sas_ha = pm8001_ha->sas;
3220         if (sas_phy->phy) {
3221                 struct sas_phy *sphy = sas_phy->phy;
3222                 sphy->negotiated_linkrate = sas_phy->linkrate;
3223                 sphy->minimum_linkrate = phy->minimum_linkrate;
3224                 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3225                 sphy->maximum_linkrate = phy->maximum_linkrate;
3226                 sphy->maximum_linkrate_hw = phy->maximum_linkrate;
3227         }
3228
3229         if (phy->phy_type & PORT_TYPE_SAS) {
3230                 struct sas_identify_frame *id;
3231                 id = (struct sas_identify_frame *)phy->frame_rcvd;
3232                 id->dev_type = phy->identify.device_type;
3233                 id->initiator_bits = SAS_PROTOCOL_ALL;
3234                 id->target_bits = phy->identify.target_port_protocols;
3235         } else if (phy->phy_type & PORT_TYPE_SATA) {
3236                 /*Nothing*/
3237         }
3238         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i));
3239
3240         sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
3241         pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED);
3242 }
3243
3244 /* Get the link rate speed  */
3245 void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
3246 {
3247         struct sas_phy *sas_phy = phy->sas_phy.phy;
3248
3249         switch (link_rate) {
3250         case PHY_SPEED_60:
3251                 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
3252                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
3253                 break;
3254         case PHY_SPEED_30:
3255                 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
3256                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
3257                 break;
3258         case PHY_SPEED_15:
3259                 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
3260                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
3261                 break;
3262         }
3263         sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
3264         sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
3265         sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3266         sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
3267         sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
3268 }
3269
3270 /**
3271  * asd_get_attached_sas_addr -- extract/generate attached SAS address
3272  * @phy: pointer to asd_phy
3273  * @sas_addr: pointer to buffer where the SAS address is to be written
3274  *
3275  * This function extracts the SAS address from an IDENTIFY frame
3276  * received.  If OOB is SATA, then a SAS address is generated from the
3277  * HA tables.
3278  *
3279  * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
3280  * buffer.
3281  */
3282 void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
3283         u8 *sas_addr)
3284 {
3285         if (phy->sas_phy.frame_rcvd[0] == 0x34
3286                 && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
3287                 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
3288                 /* FIS device-to-host */
3289                 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
3290                 addr += phy->sas_phy.id;
3291                 *(__be64 *)sas_addr = cpu_to_be64(addr);
3292         } else {
3293                 struct sas_identify_frame *idframe =
3294                         (void *) phy->sas_phy.frame_rcvd;
3295                 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
3296         }
3297 }
3298
3299 /**
3300  * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3301  * @pm8001_ha: our hba card information
3302  * @Qnum: the outbound queue message number.
3303  * @SEA: source of event to ack
3304  * @port_id: port id.
3305  * @phyId: phy id.
3306  * @param0: parameter 0.
3307  * @param1: parameter 1.
3308  */
3309 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3310         u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3311 {
3312         struct hw_event_ack_req  payload;
3313         u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3314
3315         struct inbound_queue_table *circularQ;
3316
3317         memset((u8 *)&payload, 0, sizeof(payload));
3318         circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
3319         payload.tag = cpu_to_le32(1);
3320         payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3321                 ((phyId & 0x0F) << 4) | (port_id & 0x0F));
3322         payload.param0 = cpu_to_le32(param0);
3323         payload.param1 = cpu_to_le32(param1);
3324         pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
3325 }
3326
3327 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3328         u32 phyId, u32 phy_op);
3329
3330 /**
3331  * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3332  * @pm8001_ha: our hba card information
3333  * @piomb: IO message buffer
3334  */
3335 static void
3336 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3337 {
3338         struct hw_event_resp *pPayload =
3339                 (struct hw_event_resp *)(piomb + 4);
3340         u32 lr_evt_status_phyid_portid =
3341                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3342         u8 link_rate =
3343                 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3344         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3345         u8 phy_id =
3346                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3347         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3348         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3349         struct pm8001_port *port = &pm8001_ha->port[port_id];
3350         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3351         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3352         unsigned long flags;
3353         u8 deviceType = pPayload->sas_identify.dev_type;
3354         port->port_state =  portstate;
3355         PM8001_MSG_DBG(pm8001_ha,
3356                 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
3357                 port_id, phy_id));
3358
3359         switch (deviceType) {
3360         case SAS_PHY_UNUSED:
3361                 PM8001_MSG_DBG(pm8001_ha,
3362                         pm8001_printk("device type no device.\n"));
3363                 break;
3364         case SAS_END_DEVICE:
3365                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
3366                 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
3367                         PHY_NOTIFY_ENABLE_SPINUP);
3368                 port->port_attached = 1;
3369                 pm8001_get_lrate_mode(phy, link_rate);
3370                 break;
3371         case SAS_EDGE_EXPANDER_DEVICE:
3372                 PM8001_MSG_DBG(pm8001_ha,
3373                         pm8001_printk("expander device.\n"));
3374                 port->port_attached = 1;
3375                 pm8001_get_lrate_mode(phy, link_rate);
3376                 break;
3377         case SAS_FANOUT_EXPANDER_DEVICE:
3378                 PM8001_MSG_DBG(pm8001_ha,
3379                         pm8001_printk("fanout expander device.\n"));
3380                 port->port_attached = 1;
3381                 pm8001_get_lrate_mode(phy, link_rate);
3382                 break;
3383         default:
3384                 PM8001_MSG_DBG(pm8001_ha,
3385                         pm8001_printk("unknown device type(%x)\n", deviceType));
3386                 break;
3387         }
3388         phy->phy_type |= PORT_TYPE_SAS;
3389         phy->identify.device_type = deviceType;
3390         phy->phy_attached = 1;
3391         if (phy->identify.device_type == SAS_END_DEVICE)
3392                 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3393         else if (phy->identify.device_type != SAS_PHY_UNUSED)
3394                 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3395         phy->sas_phy.oob_mode = SAS_OOB_MODE;
3396         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3397         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3398         memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3399                 sizeof(struct sas_identify_frame)-4);
3400         phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3401         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3402         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3403         if (pm8001_ha->flags == PM8001F_RUN_TIME)
3404                 mdelay(200);/*delay a moment to wait disk to spinup*/
3405         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3406 }
3407
3408 /**
3409  * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3410  * @pm8001_ha: our hba card information
3411  * @piomb: IO message buffer
3412  */
3413 static void
3414 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3415 {
3416         struct hw_event_resp *pPayload =
3417                 (struct hw_event_resp *)(piomb + 4);
3418         u32 lr_evt_status_phyid_portid =
3419                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3420         u8 link_rate =
3421                 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3422         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3423         u8 phy_id =
3424                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3425         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3426         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3427         struct pm8001_port *port = &pm8001_ha->port[port_id];
3428         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3429         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3430         unsigned long flags;
3431         PM8001_MSG_DBG(pm8001_ha,
3432                 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d,"
3433                 " phy id = %d\n", port_id, phy_id));
3434         port->port_state =  portstate;
3435         port->port_attached = 1;
3436         pm8001_get_lrate_mode(phy, link_rate);
3437         phy->phy_type |= PORT_TYPE_SATA;
3438         phy->phy_attached = 1;
3439         phy->sas_phy.oob_mode = SATA_OOB_MODE;
3440         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3441         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3442         memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3443                 sizeof(struct dev_to_host_fis));
3444         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3445         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3446         phy->identify.device_type = SAS_SATA_DEV;
3447         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3448         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3449         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3450 }
3451
3452 /**
3453  * hw_event_phy_down -we should notify the libsas the phy is down.
3454  * @pm8001_ha: our hba card information
3455  * @piomb: IO message buffer
3456  */
3457 static void
3458 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3459 {
3460         struct hw_event_resp *pPayload =
3461                 (struct hw_event_resp *)(piomb + 4);
3462         u32 lr_evt_status_phyid_portid =
3463                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3464         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3465         u8 phy_id =
3466                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3467         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3468         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3469         struct pm8001_port *port = &pm8001_ha->port[port_id];
3470         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3471         port->port_state =  portstate;
3472         phy->phy_type = 0;
3473         phy->identify.device_type = 0;
3474         phy->phy_attached = 0;
3475         memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3476         switch (portstate) {
3477         case PORT_VALID:
3478                 break;
3479         case PORT_INVALID:
3480                 PM8001_MSG_DBG(pm8001_ha,
3481                         pm8001_printk(" PortInvalid portID %d\n", port_id));
3482                 PM8001_MSG_DBG(pm8001_ha,
3483                         pm8001_printk(" Last phy Down and port invalid\n"));
3484                 port->port_attached = 0;
3485                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3486                         port_id, phy_id, 0, 0);
3487                 break;
3488         case PORT_IN_RESET:
3489                 PM8001_MSG_DBG(pm8001_ha,
3490                         pm8001_printk(" Port In Reset portID %d\n", port_id));
3491                 break;
3492         case PORT_NOT_ESTABLISHED:
3493                 PM8001_MSG_DBG(pm8001_ha,
3494                         pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
3495                 port->port_attached = 0;
3496                 break;
3497         case PORT_LOSTCOMM:
3498                 PM8001_MSG_DBG(pm8001_ha,
3499                         pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
3500                 PM8001_MSG_DBG(pm8001_ha,
3501                         pm8001_printk(" Last phy Down and port invalid\n"));
3502                 port->port_attached = 0;
3503                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3504                         port_id, phy_id, 0, 0);
3505                 break;
3506         default:
3507                 port->port_attached = 0;
3508                 PM8001_MSG_DBG(pm8001_ha,
3509                         pm8001_printk(" phy Down and(default) = %x\n",
3510                         portstate));
3511                 break;
3512
3513         }
3514 }
3515
3516 /**
3517  * pm8001_mpi_reg_resp -process register device ID response.
3518  * @pm8001_ha: our hba card information
3519  * @piomb: IO message buffer
3520  *
3521  * when sas layer find a device it will notify LLDD, then the driver register
3522  * the domain device to FW, this event is the return device ID which the FW
3523  * has assigned, from now,inter-communication with FW is no longer using the
3524  * SAS address, use device ID which FW assigned.
3525  */
3526 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3527 {
3528         u32 status;
3529         u32 device_id;
3530         u32 htag;
3531         struct pm8001_ccb_info *ccb;
3532         struct pm8001_device *pm8001_dev;
3533         struct dev_reg_resp *registerRespPayload =
3534                 (struct dev_reg_resp *)(piomb + 4);
3535
3536         htag = le32_to_cpu(registerRespPayload->tag);
3537         ccb = &pm8001_ha->ccb_info[htag];
3538         pm8001_dev = ccb->device;
3539         status = le32_to_cpu(registerRespPayload->status);
3540         device_id = le32_to_cpu(registerRespPayload->device_id);
3541         PM8001_MSG_DBG(pm8001_ha,
3542                 pm8001_printk(" register device is status = %d\n", status));
3543         switch (status) {
3544         case DEVREG_SUCCESS:
3545                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n"));
3546                 pm8001_dev->device_id = device_id;
3547                 break;
3548         case DEVREG_FAILURE_OUT_OF_RESOURCE:
3549                 PM8001_MSG_DBG(pm8001_ha,
3550                         pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n"));
3551                 break;
3552         case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3553                 PM8001_MSG_DBG(pm8001_ha,
3554                    pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n"));
3555                 break;
3556         case DEVREG_FAILURE_INVALID_PHY_ID:
3557                 PM8001_MSG_DBG(pm8001_ha,
3558                         pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n"));
3559                 break;
3560         case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3561                 PM8001_MSG_DBG(pm8001_ha,
3562                    pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n"));
3563                 break;
3564         case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3565                 PM8001_MSG_DBG(pm8001_ha,
3566                         pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n"));
3567                 break;
3568         case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3569                 PM8001_MSG_DBG(pm8001_ha,
3570                         pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n"));
3571                 break;
3572         case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3573                 PM8001_MSG_DBG(pm8001_ha,
3574                        pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n"));
3575                 break;
3576         default:
3577                 PM8001_MSG_DBG(pm8001_ha,
3578                  pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_UNSORPORTED\n"));
3579                 break;
3580         }
3581         complete(pm8001_dev->dcompletion);
3582         ccb->task = NULL;
3583         ccb->ccb_tag = 0xFFFFFFFF;
3584         pm8001_ccb_free(pm8001_ha, htag);
3585         return 0;
3586 }
3587
3588 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3589 {
3590         u32 status;
3591         u32 device_id;
3592         struct dev_reg_resp *registerRespPayload =
3593                 (struct dev_reg_resp *)(piomb + 4);
3594
3595         status = le32_to_cpu(registerRespPayload->status);
3596         device_id = le32_to_cpu(registerRespPayload->device_id);
3597         if (status != 0)
3598                 PM8001_MSG_DBG(pm8001_ha,
3599                         pm8001_printk(" deregister device failed ,status = %x"
3600                         ", device_id = %x\n", status, device_id));
3601         return 0;
3602 }
3603
3604 /**
3605  * fw_flash_update_resp - Response from FW for flash update command.
3606  * @pm8001_ha: our hba card information
3607  * @piomb: IO message buffer
3608  */
3609 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
3610                 void *piomb)
3611 {
3612         u32 status;
3613         struct fw_control_ex    fw_control_context;
3614         struct fw_flash_Update_resp *ppayload =
3615                 (struct fw_flash_Update_resp *)(piomb + 4);
3616         u32 tag = le32_to_cpu(ppayload->tag);
3617         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3618         status = le32_to_cpu(ppayload->status);
3619         memcpy(&fw_control_context,
3620                 ccb->fw_control_context,
3621                 sizeof(fw_control_context));
3622         switch (status) {
3623         case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3624                 PM8001_MSG_DBG(pm8001_ha,
3625                 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n"));
3626                 break;
3627         case FLASH_UPDATE_IN_PROGRESS:
3628                 PM8001_MSG_DBG(pm8001_ha,
3629                         pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n"));
3630                 break;
3631         case FLASH_UPDATE_HDR_ERR:
3632                 PM8001_MSG_DBG(pm8001_ha,
3633                         pm8001_printk(": FLASH_UPDATE_HDR_ERR\n"));
3634                 break;
3635         case FLASH_UPDATE_OFFSET_ERR:
3636                 PM8001_MSG_DBG(pm8001_ha,
3637                         pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n"));
3638                 break;
3639         case FLASH_UPDATE_CRC_ERR:
3640                 PM8001_MSG_DBG(pm8001_ha,
3641                         pm8001_printk(": FLASH_UPDATE_CRC_ERR\n"));
3642                 break;
3643         case FLASH_UPDATE_LENGTH_ERR:
3644                 PM8001_MSG_DBG(pm8001_ha,
3645                         pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n"));
3646                 break;
3647         case FLASH_UPDATE_HW_ERR:
3648                 PM8001_MSG_DBG(pm8001_ha,
3649                         pm8001_printk(": FLASH_UPDATE_HW_ERR\n"));
3650                 break;
3651         case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3652                 PM8001_MSG_DBG(pm8001_ha,
3653                         pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n"));
3654                 break;
3655         case FLASH_UPDATE_DISABLED:
3656                 PM8001_MSG_DBG(pm8001_ha,
3657                         pm8001_printk(": FLASH_UPDATE_DISABLED\n"));
3658                 break;
3659         default:
3660                 PM8001_MSG_DBG(pm8001_ha,
3661                         pm8001_printk("No matched status = %d\n", status));
3662                 break;
3663         }
3664         ccb->fw_control_context->fw_control->retcode = status;
3665         complete(pm8001_ha->nvmd_completion);
3666         ccb->task = NULL;
3667         ccb->ccb_tag = 0xFFFFFFFF;
3668         pm8001_ccb_free(pm8001_ha, tag);
3669         return 0;
3670 }
3671
3672 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
3673 {
3674         u32 status;
3675         int i;
3676         struct general_event_resp *pPayload =
3677                 (struct general_event_resp *)(piomb + 4);
3678         status = le32_to_cpu(pPayload->status);
3679         PM8001_MSG_DBG(pm8001_ha,
3680                 pm8001_printk(" status = 0x%x\n", status));
3681         for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3682                 PM8001_MSG_DBG(pm8001_ha,
3683                         pm8001_printk("inb_IOMB_payload[0x%x] 0x%x,\n", i,
3684                         pPayload->inb_IOMB_payload[i]));
3685         return 0;
3686 }
3687
3688 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3689 {
3690         struct sas_task *t;
3691         struct pm8001_ccb_info *ccb;
3692         unsigned long flags;
3693         u32 status ;
3694         u32 tag, scp;
3695         struct task_status_struct *ts;
3696         struct pm8001_device *pm8001_dev;
3697
3698         struct task_abort_resp *pPayload =
3699                 (struct task_abort_resp *)(piomb + 4);
3700
3701         status = le32_to_cpu(pPayload->status);
3702         tag = le32_to_cpu(pPayload->tag);
3703         if (!tag) {
3704                 PM8001_FAIL_DBG(pm8001_ha,
3705                         pm8001_printk(" TAG NULL. RETURNING !!!"));
3706                 return -1;
3707         }
3708
3709         scp = le32_to_cpu(pPayload->scp);
3710         ccb = &pm8001_ha->ccb_info[tag];
3711         t = ccb->task;
3712         pm8001_dev = ccb->device; /* retrieve device */
3713
3714         if (!t) {
3715                 PM8001_FAIL_DBG(pm8001_ha,
3716                         pm8001_printk(" TASK NULL. RETURNING !!!"));
3717                 return -1;
3718         }
3719         ts = &t->task_status;
3720         if (status != 0)
3721                 PM8001_FAIL_DBG(pm8001_ha,
3722                         pm8001_printk("task abort failed status 0x%x ,"
3723                         "tag = 0x%x, scp= 0x%x\n", status, tag, scp));
3724         switch (status) {
3725         case IO_SUCCESS:
3726                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
3727                 ts->resp = SAS_TASK_COMPLETE;
3728                 ts->stat = SAM_STAT_GOOD;
3729                 break;
3730         case IO_NOT_VALID:
3731                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n"));
3732                 ts->resp = TMF_RESP_FUNC_FAILED;
3733                 break;
3734         }
3735         spin_lock_irqsave(&t->task_state_lock, flags);
3736         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3737         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3738         t->task_state_flags |= SAS_TASK_STATE_DONE;
3739         spin_unlock_irqrestore(&t->task_state_lock, flags);
3740         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3741         mb();
3742
3743         if ((pm8001_dev->id & NCQ_ABORT_ALL_FLAG) && t) {
3744                 pm8001_tag_free(pm8001_ha, tag);
3745                 sas_free_task(t);
3746                 /* clear the flag */
3747                 pm8001_dev->id &= 0xBFFFFFFF;
3748         } else
3749                 t->task_done(t);
3750
3751         return 0;
3752 }
3753
3754 /**
3755  * mpi_hw_event -The hw event has come.
3756  * @pm8001_ha: our hba card information
3757  * @piomb: IO message buffer
3758  */
3759 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb)
3760 {
3761         unsigned long flags;
3762         struct hw_event_resp *pPayload =
3763                 (struct hw_event_resp *)(piomb + 4);
3764         u32 lr_evt_status_phyid_portid =
3765                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3766         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3767         u8 phy_id =
3768                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3769         u16 eventType =
3770                 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3771         u8 status =
3772                 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3773         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3774         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3775         struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3776         PM8001_MSG_DBG(pm8001_ha,
3777                 pm8001_printk("outbound queue HW event & event type : "));
3778         switch (eventType) {
3779         case HW_EVENT_PHY_START_STATUS:
3780                 PM8001_MSG_DBG(pm8001_ha,
3781                 pm8001_printk("HW_EVENT_PHY_START_STATUS"
3782                         " status = %x\n", status));
3783                 if (status == 0) {
3784                         phy->phy_state = 1;
3785                         if (pm8001_ha->flags == PM8001F_RUN_TIME)
3786                                 complete(phy->enable_completion);
3787                 }
3788                 break;
3789         case HW_EVENT_SAS_PHY_UP:
3790                 PM8001_MSG_DBG(pm8001_ha,
3791                         pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3792                 hw_event_sas_phy_up(pm8001_ha, piomb);
3793                 break;
3794         case HW_EVENT_SATA_PHY_UP:
3795                 PM8001_MSG_DBG(pm8001_ha,
3796                         pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3797                 hw_event_sata_phy_up(pm8001_ha, piomb);
3798                 break;
3799         case HW_EVENT_PHY_STOP_STATUS:
3800                 PM8001_MSG_DBG(pm8001_ha,
3801                         pm8001_printk("HW_EVENT_PHY_STOP_STATUS "
3802                         "status = %x\n", status));
3803                 if (status == 0)
3804                         phy->phy_state = 0;
3805                 break;
3806         case HW_EVENT_SATA_SPINUP_HOLD:
3807                 PM8001_MSG_DBG(pm8001_ha,
3808                         pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3809                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3810                 break;
3811         case HW_EVENT_PHY_DOWN:
3812                 PM8001_MSG_DBG(pm8001_ha,
3813                         pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3814                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3815                 phy->phy_attached = 0;
3816                 phy->phy_state = 0;
3817                 hw_event_phy_down(pm8001_ha, piomb);
3818                 break;
3819         case HW_EVENT_PORT_INVALID:
3820                 PM8001_MSG_DBG(pm8001_ha,
3821                         pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3822                 sas_phy_disconnected(sas_phy);
3823                 phy->phy_attached = 0;
3824                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3825                 break;
3826         /* the broadcast change primitive received, tell the LIBSAS this event
3827         to revalidate the sas domain*/
3828         case HW_EVENT_BROADCAST_CHANGE:
3829                 PM8001_MSG_DBG(pm8001_ha,
3830                         pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3831                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3832                         port_id, phy_id, 1, 0);
3833                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3834                 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3835                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3836                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3837                 break;
3838         case HW_EVENT_PHY_ERROR:
3839                 PM8001_MSG_DBG(pm8001_ha,
3840                         pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3841                 sas_phy_disconnected(&phy->sas_phy);
3842                 phy->phy_attached = 0;
3843                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3844                 break;
3845         case HW_EVENT_BROADCAST_EXP:
3846                 PM8001_MSG_DBG(pm8001_ha,
3847                         pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3848                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3849                 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3850                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3851                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3852                 break;
3853         case HW_EVENT_LINK_ERR_INVALID_DWORD:
3854                 PM8001_MSG_DBG(pm8001_ha,
3855                         pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3856                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3857                         HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3858                 sas_phy_disconnected(sas_phy);
3859                 phy->phy_attached = 0;
3860                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3861                 break;
3862         case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3863                 PM8001_MSG_DBG(pm8001_ha,
3864                         pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3865                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3866                         HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3867                         port_id, phy_id, 0, 0);
3868                 sas_phy_disconnected(sas_phy);
3869                 phy->phy_attached = 0;
3870                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3871                 break;
3872         case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3873                 PM8001_MSG_DBG(pm8001_ha,
3874                         pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3875                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3876                         HW_EVENT_LINK_ERR_CODE_VIOLATION,
3877                         port_id, phy_id, 0, 0);
3878                 sas_phy_disconnected(sas_phy);
3879                 phy->phy_attached = 0;
3880                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3881                 break;
3882         case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3883                 PM8001_MSG_DBG(pm8001_ha,
3884                       pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3885                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3886                         HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3887                         port_id, phy_id, 0, 0);
3888                 sas_phy_disconnected(sas_phy);
3889                 phy->phy_attached = 0;
3890                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3891                 break;
3892         case HW_EVENT_MALFUNCTION:
3893                 PM8001_MSG_DBG(pm8001_ha,
3894                         pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3895                 break;
3896         case HW_EVENT_BROADCAST_SES:
3897                 PM8001_MSG_DBG(pm8001_ha,
3898                         pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3899                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3900                 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3901                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3902                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3903                 break;
3904         case HW_EVENT_INBOUND_CRC_ERROR:
3905                 PM8001_MSG_DBG(pm8001_ha,
3906                         pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3907                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3908                         HW_EVENT_INBOUND_CRC_ERROR,
3909                         port_id, phy_id, 0, 0);
3910                 break;
3911         case HW_EVENT_HARD_RESET_RECEIVED:
3912                 PM8001_MSG_DBG(pm8001_ha,
3913                         pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3914                 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3915                 break;
3916         case HW_EVENT_ID_FRAME_TIMEOUT:
3917                 PM8001_MSG_DBG(pm8001_ha,
3918                         pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3919                 sas_phy_disconnected(sas_phy);
3920                 phy->phy_attached = 0;
3921                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3922                 break;
3923         case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3924                 PM8001_MSG_DBG(pm8001_ha,
3925                         pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3926                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3927                         HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3928                         port_id, phy_id, 0, 0);
3929                 sas_phy_disconnected(sas_phy);
3930                 phy->phy_attached = 0;
3931                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3932                 break;
3933         case HW_EVENT_PORT_RESET_TIMER_TMO:
3934                 PM8001_MSG_DBG(pm8001_ha,
3935                         pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3936                 sas_phy_disconnected(sas_phy);
3937                 phy->phy_attached = 0;
3938                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3939                 break;
3940         case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3941                 PM8001_MSG_DBG(pm8001_ha,
3942                         pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3943                 sas_phy_disconnected(sas_phy);
3944                 phy->phy_attached = 0;
3945                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3946                 break;
3947         case HW_EVENT_PORT_RECOVER:
3948                 PM8001_MSG_DBG(pm8001_ha,
3949                         pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3950                 break;
3951         case HW_EVENT_PORT_RESET_COMPLETE:
3952                 PM8001_MSG_DBG(pm8001_ha,
3953                         pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3954                 break;
3955         case EVENT_BROADCAST_ASYNCH_EVENT:
3956                 PM8001_MSG_DBG(pm8001_ha,
3957                         pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3958                 break;
3959         default:
3960                 PM8001_MSG_DBG(pm8001_ha,
3961                         pm8001_printk("Unknown event type = %x\n", eventType));
3962                 break;
3963         }
3964         return 0;
3965 }
3966
3967 /**
3968  * process_one_iomb - process one outbound Queue memory block
3969  * @pm8001_ha: our hba card information
3970  * @piomb: IO message buffer
3971  */
3972 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3973 {
3974         __le32 pHeader = *(__le32 *)piomb;
3975         u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
3976
3977         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:"));
3978
3979         switch (opc) {
3980         case OPC_OUB_ECHO:
3981                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3982                 break;
3983         case OPC_OUB_HW_EVENT:
3984                 PM8001_MSG_DBG(pm8001_ha,
3985                         pm8001_printk("OPC_OUB_HW_EVENT\n"));
3986                 mpi_hw_event(pm8001_ha, piomb);
3987                 break;
3988         case OPC_OUB_SSP_COMP:
3989                 PM8001_MSG_DBG(pm8001_ha,
3990                         pm8001_printk("OPC_OUB_SSP_COMP\n"));
3991                 mpi_ssp_completion(pm8001_ha, piomb);
3992                 break;
3993         case OPC_OUB_SMP_COMP:
3994                 PM8001_MSG_DBG(pm8001_ha,
3995                         pm8001_printk("OPC_OUB_SMP_COMP\n"));
3996                 mpi_smp_completion(pm8001_ha, piomb);
3997                 break;
3998         case OPC_OUB_LOCAL_PHY_CNTRL:
3999                 PM8001_MSG_DBG(pm8001_ha,
4000                         pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
4001                 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
4002                 break;
4003         case OPC_OUB_DEV_REGIST:
4004                 PM8001_MSG_DBG(pm8001_ha,
4005                         pm8001_printk("OPC_OUB_DEV_REGIST\n"));
4006                 pm8001_mpi_reg_resp(pm8001_ha, piomb);
4007                 break;
4008         case OPC_OUB_DEREG_DEV:
4009                 PM8001_MSG_DBG(pm8001_ha,
4010                         pm8001_printk("unregister the device\n"));
4011                 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
4012                 break;
4013         case OPC_OUB_GET_DEV_HANDLE:
4014                 PM8001_MSG_DBG(pm8001_ha,
4015                         pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
4016                 break;
4017         case OPC_OUB_SATA_COMP:
4018                 PM8001_MSG_DBG(pm8001_ha,
4019                         pm8001_printk("OPC_OUB_SATA_COMP\n"));
4020                 mpi_sata_completion(pm8001_ha, piomb);
4021                 break;
4022         case OPC_OUB_SATA_EVENT:
4023                 PM8001_MSG_DBG(pm8001_ha,
4024                         pm8001_printk("OPC_OUB_SATA_EVENT\n"));
4025                 mpi_sata_event(pm8001_ha, piomb);
4026                 break;
4027         case OPC_OUB_SSP_EVENT:
4028                 PM8001_MSG_DBG(pm8001_ha,
4029                         pm8001_printk("OPC_OUB_SSP_EVENT\n"));
4030                 mpi_ssp_event(pm8001_ha, piomb);
4031                 break;
4032         case OPC_OUB_DEV_HANDLE_ARRIV:
4033                 PM8001_MSG_DBG(pm8001_ha,
4034                         pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
4035                 /*This is for target*/
4036                 break;
4037         case OPC_OUB_SSP_RECV_EVENT:
4038                 PM8001_MSG_DBG(pm8001_ha,
4039                         pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
4040                 /*This is for target*/
4041                 break;
4042         case OPC_OUB_DEV_INFO:
4043                 PM8001_MSG_DBG(pm8001_ha,
4044                         pm8001_printk("OPC_OUB_DEV_INFO\n"));
4045                 break;
4046         case OPC_OUB_FW_FLASH_UPDATE:
4047                 PM8001_MSG_DBG(pm8001_ha,
4048                         pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
4049                 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
4050                 break;
4051         case OPC_OUB_GPIO_RESPONSE:
4052                 PM8001_MSG_DBG(pm8001_ha,
4053                         pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
4054                 break;
4055         case OPC_OUB_GPIO_EVENT:
4056                 PM8001_MSG_DBG(pm8001_ha,
4057                         pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
4058                 break;
4059         case OPC_OUB_GENERAL_EVENT:
4060                 PM8001_MSG_DBG(pm8001_ha,
4061                         pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
4062                 pm8001_mpi_general_event(pm8001_ha, piomb);
4063                 break;
4064         case OPC_OUB_SSP_ABORT_RSP:
4065                 PM8001_MSG_DBG(pm8001_ha,
4066                         pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
4067                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4068                 break;
4069         case OPC_OUB_SATA_ABORT_RSP:
4070                 PM8001_MSG_DBG(pm8001_ha,
4071                         pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
4072                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4073                 break;
4074         case OPC_OUB_SAS_DIAG_MODE_START_END:
4075                 PM8001_MSG_DBG(pm8001_ha,
4076                         pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
4077                 break;
4078         case OPC_OUB_SAS_DIAG_EXECUTE:
4079                 PM8001_MSG_DBG(pm8001_ha,
4080                         pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
4081                 break;
4082         case OPC_OUB_GET_TIME_STAMP:
4083                 PM8001_MSG_DBG(pm8001_ha,
4084                         pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
4085                 break;
4086         case OPC_OUB_SAS_HW_EVENT_ACK:
4087                 PM8001_MSG_DBG(pm8001_ha,
4088                         pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
4089                 break;
4090         case OPC_OUB_PORT_CONTROL:
4091                 PM8001_MSG_DBG(pm8001_ha,
4092                         pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
4093                 break;
4094         case OPC_OUB_SMP_ABORT_RSP:
4095                 PM8001_MSG_DBG(pm8001_ha,
4096                         pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
4097                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4098                 break;
4099         case OPC_OUB_GET_NVMD_DATA:
4100                 PM8001_MSG_DBG(pm8001_ha,
4101                         pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
4102                 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
4103                 break;
4104         case OPC_OUB_SET_NVMD_DATA:
4105                 PM8001_MSG_DBG(pm8001_ha,
4106                         pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
4107                 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
4108                 break;
4109         case OPC_OUB_DEVICE_HANDLE_REMOVAL:
4110                 PM8001_MSG_DBG(pm8001_ha,
4111                         pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
4112                 break;
4113         case OPC_OUB_SET_DEVICE_STATE:
4114                 PM8001_MSG_DBG(pm8001_ha,
4115                         pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
4116                 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
4117                 break;
4118         case OPC_OUB_GET_DEVICE_STATE:
4119                 PM8001_MSG_DBG(pm8001_ha,
4120                         pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
4121                 break;
4122         case OPC_OUB_SET_DEV_INFO:
4123                 PM8001_MSG_DBG(pm8001_ha,
4124                         pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
4125                 break;
4126         case OPC_OUB_SAS_RE_INITIALIZE:
4127                 PM8001_MSG_DBG(pm8001_ha,
4128                         pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n"));
4129                 break;
4130         default:
4131                 PM8001_MSG_DBG(pm8001_ha,
4132                         pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n",
4133                         opc));
4134                 break;
4135         }
4136 }
4137
4138 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
4139 {
4140         struct outbound_queue_table *circularQ;
4141         void *pMsg1 = NULL;
4142         u8 uninitialized_var(bc);
4143         u32 ret = MPI_IO_STATUS_FAIL;
4144         unsigned long flags;
4145
4146         spin_lock_irqsave(&pm8001_ha->lock, flags);
4147         circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4148         do {
4149                 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4150                 if (MPI_IO_STATUS_SUCCESS == ret) {
4151                         /* process the outbound message */
4152                         process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
4153                         /* free the message from the outbound circular buffer */
4154                         pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4155                                                         circularQ, bc);
4156                 }
4157                 if (MPI_IO_STATUS_BUSY == ret) {
4158                         /* Update the producer index from SPC */
4159                         circularQ->producer_index =
4160                                 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4161                         if (le32_to_cpu(circularQ->producer_index) ==
4162                                 circularQ->consumer_idx)
4163                                 /* OQ is empty */
4164                                 break;
4165                 }
4166         } while (1);
4167         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
4168         return ret;
4169 }
4170
4171 /* PCI_DMA_... to our direction translation. */
4172 static const u8 data_dir_flags[] = {
4173         [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
4174         [PCI_DMA_TODEVICE]      = DATA_DIR_OUT,/* OUTBOUND */
4175         [PCI_DMA_FROMDEVICE]    = DATA_DIR_IN,/* INBOUND */
4176         [PCI_DMA_NONE]          = DATA_DIR_NONE,/* NO TRANSFER */
4177 };
4178 void
4179 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
4180 {
4181         int i;
4182         struct scatterlist *sg;
4183         struct pm8001_prd *buf_prd = prd;
4184
4185         for_each_sg(scatter, sg, nr, i) {
4186                 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
4187                 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
4188                 buf_prd->im_len.e = 0;
4189                 buf_prd++;
4190         }
4191 }
4192
4193 static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd)
4194 {
4195         psmp_cmd->tag = hTag;
4196         psmp_cmd->device_id = cpu_to_le32(deviceID);
4197         psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4198 }
4199
4200 /**
4201  * pm8001_chip_smp_req - send a SMP task to FW
4202  * @pm8001_ha: our hba card information.
4203  * @ccb: the ccb information this request used.
4204  */
4205 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4206         struct pm8001_ccb_info *ccb)
4207 {
4208         int elem, rc;
4209         struct sas_task *task = ccb->task;
4210         struct domain_device *dev = task->dev;
4211         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4212         struct scatterlist *sg_req, *sg_resp;
4213         u32 req_len, resp_len;
4214         struct smp_req smp_cmd;
4215         u32 opc;
4216         struct inbound_queue_table *circularQ;
4217
4218         memset(&smp_cmd, 0, sizeof(smp_cmd));
4219         /*
4220          * DMA-map SMP request, response buffers
4221          */
4222         sg_req = &task->smp_task.smp_req;
4223         elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
4224         if (!elem)
4225                 return -ENOMEM;
4226         req_len = sg_dma_len(sg_req);
4227
4228         sg_resp = &task->smp_task.smp_resp;
4229         elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
4230         if (!elem) {
4231                 rc = -ENOMEM;
4232                 goto err_out;
4233         }
4234         resp_len = sg_dma_len(sg_resp);
4235         /* must be in dwords */
4236         if ((req_len & 0x3) || (resp_len & 0x3)) {
4237                 rc = -EINVAL;
4238                 goto err_out_2;
4239         }
4240
4241         opc = OPC_INB_SMP_REQUEST;
4242         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4243         smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4244         smp_cmd.long_smp_req.long_req_addr =
4245                 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
4246         smp_cmd.long_smp_req.long_req_size =
4247                 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4248         smp_cmd.long_smp_req.long_resp_addr =
4249                 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
4250         smp_cmd.long_smp_req.long_resp_size =
4251                 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4252         build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
4253         pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd, 0);
4254         return 0;
4255
4256 err_out_2:
4257         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4258                         PCI_DMA_FROMDEVICE);
4259 err_out:
4260         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4261                         PCI_DMA_TODEVICE);
4262         return rc;
4263 }
4264
4265 /**
4266  * pm8001_chip_ssp_io_req - send a SSP task to FW
4267  * @pm8001_ha: our hba card information.
4268  * @ccb: the ccb information this request used.
4269  */
4270 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4271         struct pm8001_ccb_info *ccb)
4272 {
4273         struct sas_task *task = ccb->task;
4274         struct domain_device *dev = task->dev;
4275         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4276         struct ssp_ini_io_start_req ssp_cmd;
4277         u32 tag = ccb->ccb_tag;
4278         int ret;
4279         u64 phys_addr;
4280         struct inbound_queue_table *circularQ;
4281         u32 opc = OPC_INB_SSPINIIOSTART;
4282         memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4283         memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4284         ssp_cmd.dir_m_tlr =
4285                 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
4286         SAS 1.1 compatible TLR*/
4287         ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4288         ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4289         ssp_cmd.tag = cpu_to_le32(tag);
4290         if (task->ssp_task.enable_first_burst)
4291                 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4292         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4293         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4294         memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cdb, 16);
4295         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4296
4297         /* fill in PRD (scatter/gather) table, if any */
4298         if (task->num_scatter > 1) {
4299                 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4300                 phys_addr = ccb->ccb_dma_handle +
4301                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4302                 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr));
4303                 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr));
4304                 ssp_cmd.esgl = cpu_to_le32(1<<31);
4305         } else if (task->num_scatter == 1) {
4306                 u64 dma_addr = sg_dma_address(task->scatter);
4307                 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4308                 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr));
4309                 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4310                 ssp_cmd.esgl = 0;
4311         } else if (task->num_scatter == 0) {
4312                 ssp_cmd.addr_low = 0;
4313                 ssp_cmd.addr_high = 0;
4314                 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4315                 ssp_cmd.esgl = 0;
4316         }
4317         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd, 0);
4318         return ret;
4319 }
4320
4321 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4322         struct pm8001_ccb_info *ccb)
4323 {
4324         struct sas_task *task = ccb->task;
4325         struct domain_device *dev = task->dev;
4326         struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4327         u32 tag = ccb->ccb_tag;
4328         int ret;
4329         struct sata_start_req sata_cmd;
4330         u32 hdr_tag, ncg_tag = 0;
4331         u64 phys_addr;
4332         u32 ATAP = 0x0;
4333         u32 dir;
4334         struct inbound_queue_table *circularQ;
4335         unsigned long flags;
4336         u32  opc = OPC_INB_SATA_HOST_OPSTART;
4337         memset(&sata_cmd, 0, sizeof(sata_cmd));
4338         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4339         if (task->data_dir == PCI_DMA_NONE) {
4340                 ATAP = 0x04;  /* no data*/
4341                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4342         } else if (likely(!task->ata_task.device_control_reg_update)) {
4343                 if (task->ata_task.dma_xfer) {
4344                         ATAP = 0x06; /* DMA */
4345                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4346                 } else {
4347                         ATAP = 0x05; /* PIO*/
4348                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4349                 }
4350                 if (task->ata_task.use_ncq &&
4351                         dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
4352                         ATAP = 0x07; /* FPDMA */
4353                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4354                 }
4355         }
4356         if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4357                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4358                 ncg_tag = hdr_tag;
4359         }
4360         dir = data_dir_flags[task->data_dir] << 8;
4361         sata_cmd.tag = cpu_to_le32(tag);
4362         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4363         sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4364         sata_cmd.ncqtag_atap_dir_m =
4365                 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
4366         sata_cmd.sata_fis = task->ata_task.fis;
4367         if (likely(!task->ata_task.device_control_reg_update))
4368                 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4369         sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4370         /* fill in PRD (scatter/gather) table, if any */
4371         if (task->num_scatter > 1) {
4372                 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4373                 phys_addr = ccb->ccb_dma_handle +
4374                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4375                 sata_cmd.addr_low = lower_32_bits(phys_addr);
4376                 sata_cmd.addr_high = upper_32_bits(phys_addr);
4377                 sata_cmd.esgl = cpu_to_le32(1 << 31);
4378         } else if (task->num_scatter == 1) {
4379                 u64 dma_addr = sg_dma_address(task->scatter);
4380                 sata_cmd.addr_low = lower_32_bits(dma_addr);
4381                 sata_cmd.addr_high = upper_32_bits(dma_addr);
4382                 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4383                 sata_cmd.esgl = 0;
4384         } else if (task->num_scatter == 0) {
4385                 sata_cmd.addr_low = 0;
4386                 sata_cmd.addr_high = 0;
4387                 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4388                 sata_cmd.esgl = 0;
4389         }
4390
4391         /* Check for read log for failed drive and return */
4392         if (sata_cmd.sata_fis.command == 0x2f) {
4393                 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4394                         (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4395                         (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4396                         struct task_status_struct *ts;
4397
4398                         pm8001_ha_dev->id &= 0xDFFFFFFF;
4399                         ts = &task->task_status;
4400
4401                         spin_lock_irqsave(&task->task_state_lock, flags);
4402                         ts->resp = SAS_TASK_COMPLETE;
4403                         ts->stat = SAM_STAT_GOOD;
4404                         task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4405                         task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4406                         task->task_state_flags |= SAS_TASK_STATE_DONE;
4407                         if (unlikely((task->task_state_flags &
4408                                         SAS_TASK_STATE_ABORTED))) {
4409                                 spin_unlock_irqrestore(&task->task_state_lock,
4410                                                         flags);
4411                                 PM8001_FAIL_DBG(pm8001_ha,
4412                                         pm8001_printk("task 0x%p resp 0x%x "
4413                                         " stat 0x%x but aborted by upper layer "
4414                                         "\n", task, ts->resp, ts->stat));
4415                                 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4416                         } else if (task->uldd_task) {
4417                                 spin_unlock_irqrestore(&task->task_state_lock,
4418                                                         flags);
4419                                 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4420                                 mb();/* ditto */
4421                                 spin_unlock_irq(&pm8001_ha->lock);
4422                                 task->task_done(task);
4423                                 spin_lock_irq(&pm8001_ha->lock);
4424                                 return 0;
4425                         } else if (!task->uldd_task) {
4426                                 spin_unlock_irqrestore(&task->task_state_lock,
4427                                                         flags);
4428                                 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4429                                 mb();/*ditto*/
4430                                 spin_unlock_irq(&pm8001_ha->lock);
4431                                 task->task_done(task);
4432                                 spin_lock_irq(&pm8001_ha->lock);
4433                                 return 0;
4434                         }
4435                 }
4436         }
4437
4438         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
4439         return ret;
4440 }
4441
4442 /**
4443  * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
4444  * @pm8001_ha: our hba card information.
4445  * @num: the inbound queue number
4446  * @phy_id: the phy id which we wanted to start up.
4447  */
4448 static int
4449 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4450 {
4451         struct phy_start_req payload;
4452         struct inbound_queue_table *circularQ;
4453         int ret;
4454         u32 tag = 0x01;
4455         u32 opcode = OPC_INB_PHYSTART;
4456         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4457         memset(&payload, 0, sizeof(payload));
4458         payload.tag = cpu_to_le32(tag);
4459         /*
4460          ** [0:7]   PHY Identifier
4461          ** [8:11]  link rate 1.5G, 3G, 6G
4462          ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
4463          ** [14]    0b disable spin up hold; 1b enable spin up hold
4464          */
4465         payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4466                 LINKMODE_AUTO | LINKRATE_15 |
4467                 LINKRATE_30 | LINKRATE_60 | phy_id);
4468         payload.sas_identify.dev_type = SAS_END_DEVICE;
4469         payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4470         memcpy(payload.sas_identify.sas_addr,
4471                 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4472         payload.sas_identify.phy_id = phy_id;
4473         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4474         return ret;
4475 }
4476
4477 /**
4478  * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4479  * @pm8001_ha: our hba card information.
4480  * @num: the inbound queue number
4481  * @phy_id: the phy id which we wanted to start up.
4482  */
4483 int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4484         u8 phy_id)
4485 {
4486         struct phy_stop_req payload;
4487         struct inbound_queue_table *circularQ;
4488         int ret;
4489         u32 tag = 0x01;
4490         u32 opcode = OPC_INB_PHYSTOP;
4491         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4492         memset(&payload, 0, sizeof(payload));
4493         payload.tag = cpu_to_le32(tag);
4494         payload.phy_id = cpu_to_le32(phy_id);
4495         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4496         return ret;
4497 }
4498
4499 /**
4500  * see comments on pm8001_mpi_reg_resp.
4501  */
4502 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4503         struct pm8001_device *pm8001_dev, u32 flag)
4504 {
4505         struct reg_dev_req payload;
4506         u32     opc;
4507         u32 stp_sspsmp_sata = 0x4;
4508         struct inbound_queue_table *circularQ;
4509         u32 linkrate, phy_id;
4510         int rc, tag = 0xdeadbeef;
4511         struct pm8001_ccb_info *ccb;
4512         u8 retryFlag = 0x1;
4513         u16 firstBurstSize = 0;
4514         u16 ITNT = 2000;
4515         struct domain_device *dev = pm8001_dev->sas_device;
4516         struct domain_device *parent_dev = dev->parent;
4517         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4518
4519         memset(&payload, 0, sizeof(payload));
4520         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4521         if (rc)
4522                 return rc;
4523         ccb = &pm8001_ha->ccb_info[tag];
4524         ccb->device = pm8001_dev;
4525         ccb->ccb_tag = tag;
4526         payload.tag = cpu_to_le32(tag);
4527         if (flag == 1)
4528                 stp_sspsmp_sata = 0x02; /*direct attached sata */
4529         else {
4530                 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4531                         stp_sspsmp_sata = 0x00; /* stp*/
4532                 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4533                         pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4534                         pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4535                         stp_sspsmp_sata = 0x01; /*ssp or smp*/
4536         }
4537         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4538                 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4539         else
4540                 phy_id = pm8001_dev->attached_phy;
4541         opc = OPC_INB_REG_DEV;
4542         linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4543                         pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4544         payload.phyid_portid =
4545                 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) |
4546                 ((phy_id & 0x0F) << 4));
4547         payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
4548                 ((linkrate & 0x0F) * 0x1000000) |
4549                 ((stp_sspsmp_sata & 0x03) * 0x10000000));
4550         payload.firstburstsize_ITNexustimeout =
4551                 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4552         memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4553                 SAS_ADDR_SIZE);
4554         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4555         return rc;
4556 }
4557
4558 /**
4559  * see comments on pm8001_mpi_reg_resp.
4560  */
4561 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
4562         u32 device_id)
4563 {
4564         struct dereg_dev_req payload;
4565         u32 opc = OPC_INB_DEREG_DEV_HANDLE;
4566         int ret;
4567         struct inbound_queue_table *circularQ;
4568
4569         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4570         memset(&payload, 0, sizeof(payload));
4571         payload.tag = cpu_to_le32(1);
4572         payload.device_id = cpu_to_le32(device_id);
4573         PM8001_MSG_DBG(pm8001_ha,
4574                 pm8001_printk("unregister device device_id = %d\n", device_id));
4575         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4576         return ret;
4577 }
4578
4579 /**
4580  * pm8001_chip_phy_ctl_req - support the local phy operation
4581  * @pm8001_ha: our hba card information.
4582  * @num: the inbound queue number
4583  * @phy_id: the phy id which we wanted to operate
4584  * @phy_op:
4585  */
4586 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4587         u32 phyId, u32 phy_op)
4588 {
4589         struct local_phy_ctl_req payload;
4590         struct inbound_queue_table *circularQ;
4591         int ret;
4592         u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4593         memset(&payload, 0, sizeof(payload));
4594         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4595         payload.tag = cpu_to_le32(1);
4596         payload.phyop_phyid =
4597                 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
4598         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4599         return ret;
4600 }
4601
4602 static u32 pm8001_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4603 {
4604         u32 value;
4605 #ifdef PM8001_USE_MSIX
4606         return 1;
4607 #endif
4608         value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4609         if (value)
4610                 return 1;
4611         return 0;
4612
4613 }
4614
4615 /**
4616  * pm8001_chip_isr - PM8001 isr handler.
4617  * @pm8001_ha: our hba card information.
4618  * @irq: irq number.
4619  * @stat: stat.
4620  */
4621 static irqreturn_t
4622 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4623 {
4624         pm8001_chip_interrupt_disable(pm8001_ha, vec);
4625         process_oq(pm8001_ha, vec);
4626         pm8001_chip_interrupt_enable(pm8001_ha, vec);
4627         return IRQ_HANDLED;
4628 }
4629
4630 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4631         u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
4632 {
4633         struct task_abort_req task_abort;
4634         struct inbound_queue_table *circularQ;
4635         int ret;
4636         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4637         memset(&task_abort, 0, sizeof(task_abort));
4638         if (ABORT_SINGLE == (flag & ABORT_MASK)) {
4639                 task_abort.abort_all = 0;
4640                 task_abort.device_id = cpu_to_le32(dev_id);
4641                 task_abort.tag_to_abort = cpu_to_le32(task_tag);
4642                 task_abort.tag = cpu_to_le32(cmd_tag);
4643         } else if (ABORT_ALL == (flag & ABORT_MASK)) {
4644                 task_abort.abort_all = cpu_to_le32(1);
4645                 task_abort.device_id = cpu_to_le32(dev_id);
4646                 task_abort.tag = cpu_to_le32(cmd_tag);
4647         }
4648         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
4649         return ret;
4650 }
4651
4652 /**
4653  * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4654  * @task: the task we wanted to aborted.
4655  * @flag: the abort flag.
4656  */
4657 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
4658         struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
4659 {
4660         u32 opc, device_id;
4661         int rc = TMF_RESP_FUNC_FAILED;
4662         PM8001_EH_DBG(pm8001_ha,
4663                 pm8001_printk("cmd_tag = %x, abort task tag = 0x%x",
4664                         cmd_tag, task_tag));
4665         if (pm8001_dev->dev_type == SAS_END_DEVICE)
4666                 opc = OPC_INB_SSP_ABORT;
4667         else if (pm8001_dev->dev_type == SAS_SATA_DEV)
4668                 opc = OPC_INB_SATA_ABORT;
4669         else
4670                 opc = OPC_INB_SMP_ABORT;/* SMP */
4671         device_id = pm8001_dev->device_id;
4672         rc = send_task_abort(pm8001_ha, opc, device_id, flag,
4673                 task_tag, cmd_tag);
4674         if (rc != TMF_RESP_FUNC_COMPLETE)
4675                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc));
4676         return rc;
4677 }
4678
4679 /**
4680  * pm8001_chip_ssp_tm_req - built the task management command.
4681  * @pm8001_ha: our hba card information.
4682  * @ccb: the ccb information.
4683  * @tmf: task management function.
4684  */
4685 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
4686         struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
4687 {
4688         struct sas_task *task = ccb->task;
4689         struct domain_device *dev = task->dev;
4690         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4691         u32 opc = OPC_INB_SSPINITMSTART;
4692         struct inbound_queue_table *circularQ;
4693         struct ssp_ini_tm_start_req sspTMCmd;
4694         int ret;
4695
4696         memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4697         sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4698         sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
4699         sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
4700         memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4701         sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4702         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4703         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd, 0);
4704         return ret;
4705 }
4706
4707 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4708         void *payload)
4709 {
4710         u32 opc = OPC_INB_GET_NVMD_DATA;
4711         u32 nvmd_type;
4712         int rc;
4713         u32 tag;
4714         struct pm8001_ccb_info *ccb;
4715         struct inbound_queue_table *circularQ;
4716         struct get_nvm_data_req nvmd_req;
4717         struct fw_control_ex *fw_control_context;
4718         struct pm8001_ioctl_payload *ioctl_payload = payload;
4719
4720         nvmd_type = ioctl_payload->minor_function;
4721         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4722         if (!fw_control_context)
4723                 return -ENOMEM;
4724         fw_control_context->usrAddr = (u8 *)ioctl_payload->func_specific;
4725         fw_control_context->len = ioctl_payload->length;
4726         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4727         memset(&nvmd_req, 0, sizeof(nvmd_req));
4728         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4729         if (rc) {
4730                 kfree(fw_control_context);
4731                 return rc;
4732         }
4733         ccb = &pm8001_ha->ccb_info[tag];
4734         ccb->ccb_tag = tag;
4735         ccb->fw_control_context = fw_control_context;
4736         nvmd_req.tag = cpu_to_le32(tag);
4737
4738         switch (nvmd_type) {
4739         case TWI_DEVICE: {
4740                 u32 twi_addr, twi_page_size;
4741                 twi_addr = 0xa8;
4742                 twi_page_size = 2;
4743
4744                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4745                         twi_page_size << 8 | TWI_DEVICE);
4746                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4747                 nvmd_req.resp_addr_hi =
4748                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4749                 nvmd_req.resp_addr_lo =
4750                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4751                 break;
4752         }
4753         case C_SEEPROM: {
4754                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4755                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4756                 nvmd_req.resp_addr_hi =
4757                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4758                 nvmd_req.resp_addr_lo =
4759                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4760                 break;
4761         }
4762         case VPD_FLASH: {
4763                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4764                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4765                 nvmd_req.resp_addr_hi =
4766                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4767                 nvmd_req.resp_addr_lo =
4768                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4769                 break;
4770         }
4771         case EXPAN_ROM: {
4772                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4773                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4774                 nvmd_req.resp_addr_hi =
4775                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4776                 nvmd_req.resp_addr_lo =
4777                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4778                 break;
4779         }
4780         default:
4781                 break;
4782         }
4783         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 0);
4784         return rc;
4785 }
4786
4787 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4788         void *payload)
4789 {
4790         u32 opc = OPC_INB_SET_NVMD_DATA;
4791         u32 nvmd_type;
4792         int rc;
4793         u32 tag;
4794         struct pm8001_ccb_info *ccb;
4795         struct inbound_queue_table *circularQ;
4796         struct set_nvm_data_req nvmd_req;
4797         struct fw_control_ex *fw_control_context;
4798         struct pm8001_ioctl_payload *ioctl_payload = payload;
4799
4800         nvmd_type = ioctl_payload->minor_function;
4801         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4802         if (!fw_control_context)
4803                 return -ENOMEM;
4804         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4805         memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
4806                 &ioctl_payload->func_specific,
4807                 ioctl_payload->length);
4808         memset(&nvmd_req, 0, sizeof(nvmd_req));
4809         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4810         if (rc) {
4811                 kfree(fw_control_context);
4812                 return rc;
4813         }
4814         ccb = &pm8001_ha->ccb_info[tag];
4815         ccb->fw_control_context = fw_control_context;
4816         ccb->ccb_tag = tag;
4817         nvmd_req.tag = cpu_to_le32(tag);
4818         switch (nvmd_type) {
4819         case TWI_DEVICE: {
4820                 u32 twi_addr, twi_page_size;
4821                 twi_addr = 0xa8;
4822                 twi_page_size = 2;
4823                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4824                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4825                         twi_page_size << 8 | TWI_DEVICE);
4826                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4827                 nvmd_req.resp_addr_hi =
4828                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4829                 nvmd_req.resp_addr_lo =
4830                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4831                 break;
4832         }
4833         case C_SEEPROM:
4834                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4835                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4836                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4837                 nvmd_req.resp_addr_hi =
4838                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4839                 nvmd_req.resp_addr_lo =
4840                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4841                 break;
4842         case VPD_FLASH:
4843                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4844                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4845                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4846                 nvmd_req.resp_addr_hi =
4847                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4848                 nvmd_req.resp_addr_lo =
4849                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4850                 break;
4851         case EXPAN_ROM:
4852                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4853                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4854                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4855                 nvmd_req.resp_addr_hi =
4856                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4857                 nvmd_req.resp_addr_lo =
4858                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4859                 break;
4860         default:
4861                 break;
4862         }
4863         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 0);
4864         return rc;
4865 }
4866
4867 /**
4868  * pm8001_chip_fw_flash_update_build - support the firmware update operation
4869  * @pm8001_ha: our hba card information.
4870  * @fw_flash_updata_info: firmware flash update param
4871  */
4872 int
4873 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4874         void *fw_flash_updata_info, u32 tag)
4875 {
4876         struct fw_flash_Update_req payload;
4877         struct fw_flash_updata_info *info;
4878         struct inbound_queue_table *circularQ;
4879         int ret;
4880         u32 opc = OPC_INB_FW_FLASH_UPDATE;
4881
4882         memset(&payload, 0, sizeof(struct fw_flash_Update_req));
4883         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4884         info = fw_flash_updata_info;
4885         payload.tag = cpu_to_le32(tag);
4886         payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4887         payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4888         payload.total_image_len = cpu_to_le32(info->total_image_len);
4889         payload.len = info->sgl.im_len.len ;
4890         payload.sgl_addr_lo =
4891                 cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr)));
4892         payload.sgl_addr_hi =
4893                 cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr)));
4894         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4895         return ret;
4896 }
4897
4898 int
4899 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4900         void *payload)
4901 {
4902         struct fw_flash_updata_info flash_update_info;
4903         struct fw_control_info *fw_control;
4904         struct fw_control_ex *fw_control_context;
4905         int rc;
4906         u32 tag;
4907         struct pm8001_ccb_info *ccb;
4908         void *buffer = pm8001_ha->memoryMap.region[FW_FLASH].virt_ptr;
4909         dma_addr_t phys_addr = pm8001_ha->memoryMap.region[FW_FLASH].phys_addr;
4910         struct pm8001_ioctl_payload *ioctl_payload = payload;
4911
4912         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4913         if (!fw_control_context)
4914                 return -ENOMEM;
4915         fw_control = (struct fw_control_info *)&ioctl_payload->func_specific;
4916         memcpy(buffer, fw_control->buffer, fw_control->len);
4917         flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
4918         flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
4919         flash_update_info.sgl.im_len.e = 0;
4920         flash_update_info.cur_image_offset = fw_control->offset;
4921         flash_update_info.cur_image_len = fw_control->len;
4922         flash_update_info.total_image_len = fw_control->size;
4923         fw_control_context->fw_control = fw_control;
4924         fw_control_context->virtAddr = buffer;
4925         fw_control_context->phys_addr = phys_addr;
4926         fw_control_context->len = fw_control->len;
4927         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4928         if (rc) {
4929                 kfree(fw_control_context);
4930                 return rc;
4931         }
4932         ccb = &pm8001_ha->ccb_info[tag];
4933         ccb->fw_control_context = fw_control_context;
4934         ccb->ccb_tag = tag;
4935         rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
4936                 tag);
4937         return rc;
4938 }
4939
4940 int
4941 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
4942         struct pm8001_device *pm8001_dev, u32 state)
4943 {
4944         struct set_dev_state_req payload;
4945         struct inbound_queue_table *circularQ;
4946         struct pm8001_ccb_info *ccb;
4947         int rc;
4948         u32 tag;
4949         u32 opc = OPC_INB_SET_DEVICE_STATE;
4950         memset(&payload, 0, sizeof(payload));
4951         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4952         if (rc)
4953                 return -1;
4954         ccb = &pm8001_ha->ccb_info[tag];
4955         ccb->ccb_tag = tag;
4956         ccb->device = pm8001_dev;
4957         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4958         payload.tag = cpu_to_le32(tag);
4959         payload.device_id = cpu_to_le32(pm8001_dev->device_id);
4960         payload.nds = cpu_to_le32(state);
4961         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4962         return rc;
4963
4964 }
4965
4966 static int
4967 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
4968 {
4969         struct sas_re_initialization_req payload;
4970         struct inbound_queue_table *circularQ;
4971         struct pm8001_ccb_info *ccb;
4972         int rc;
4973         u32 tag;
4974         u32 opc = OPC_INB_SAS_RE_INITIALIZE;
4975         memset(&payload, 0, sizeof(payload));
4976         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4977         if (rc)
4978                 return -1;
4979         ccb = &pm8001_ha->ccb_info[tag];
4980         ccb->ccb_tag = tag;
4981         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4982         payload.tag = cpu_to_le32(tag);
4983         payload.SSAHOLT = cpu_to_le32(0xd << 25);
4984         payload.sata_hol_tmo = cpu_to_le32(80);
4985         payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
4986         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4987         return rc;
4988
4989 }
4990
4991 const struct pm8001_dispatch pm8001_8001_dispatch = {
4992         .name                   = "pmc8001",
4993         .chip_init              = pm8001_chip_init,
4994         .chip_soft_rst          = pm8001_chip_soft_rst,
4995         .chip_rst               = pm8001_hw_chip_rst,
4996         .chip_iounmap           = pm8001_chip_iounmap,
4997         .isr                    = pm8001_chip_isr,
4998         .is_our_interupt        = pm8001_chip_is_our_interupt,
4999         .isr_process_oq         = process_oq,
5000         .interrupt_enable       = pm8001_chip_interrupt_enable,
5001         .interrupt_disable      = pm8001_chip_interrupt_disable,
5002         .make_prd               = pm8001_chip_make_sg,
5003         .smp_req                = pm8001_chip_smp_req,
5004         .ssp_io_req             = pm8001_chip_ssp_io_req,
5005         .sata_req               = pm8001_chip_sata_req,
5006         .phy_start_req          = pm8001_chip_phy_start_req,
5007         .phy_stop_req           = pm8001_chip_phy_stop_req,
5008         .reg_dev_req            = pm8001_chip_reg_dev_req,
5009         .dereg_dev_req          = pm8001_chip_dereg_dev_req,
5010         .phy_ctl_req            = pm8001_chip_phy_ctl_req,
5011         .task_abort             = pm8001_chip_abort_task,
5012         .ssp_tm_req             = pm8001_chip_ssp_tm_req,
5013         .get_nvmd_req           = pm8001_chip_get_nvmd_req,
5014         .set_nvmd_req           = pm8001_chip_set_nvmd_req,
5015         .fw_flash_update_req    = pm8001_chip_fw_flash_update_req,
5016         .set_dev_state_req      = pm8001_chip_set_dev_state_req,
5017         .sas_re_init_req        = pm8001_chip_sas_re_initialization,
5018 };