drivers/pinctrl/pinctrl-rockchip.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2013 MundoReader S.L.
   5  * Author: Heiko Stuebner <heiko@sntech.de>
   6  *
   7  * With some ideas taken from pinctrl-samsung:
   8  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9  *              http://www.samsung.com
  10  * Copyright (c) 2012 Linaro Ltd
  11  *              http://www.linaro.org
  12  *
  13  * and pinctrl-at91:
  14  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as published
  18  * by the Free Software Foundation.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/bitops.h>
  30 #include <linux/gpio.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/pinctrl/machine.h>
  34 #include <linux/pinctrl/pinconf.h>
  35 #include <linux/pinctrl/pinctrl.h>
  36 #include <linux/pinctrl/pinmux.h>
  37 #include <linux/pinctrl/pinconf-generic.h>
  38 #include <linux/irqchip/chained_irq.h>
  39 #include <linux/clk.h>
  40 #include <linux/regmap.h>
  41 #include <linux/mfd/syscon.h>
  42 #include <dt-bindings/pinctrl/rockchip.h>
  43
  44 #include "core.h"
  45 #include "pinconf.h"
  46
  47 /* GPIO control registers */
  48 #define GPIO_SWPORT_DR          0x00
  49 #define GPIO_SWPORT_DDR         0x04
  50 #define GPIO_INTEN              0x30
  51 #define GPIO_INTMASK            0x34
  52 #define GPIO_INTTYPE_LEVEL      0x38
  53 #define GPIO_INT_POLARITY       0x3c
  54 #define GPIO_INT_STATUS         0x40
  55 #define GPIO_INT_RAWSTATUS      0x44
  56 #define GPIO_DEBOUNCE           0x48
  57 #define GPIO_PORTS_EOI          0x4c
  58 #define GPIO_EXT_PORT           0x50
  59 #define GPIO_LS_SYNC            0x60
  60
  61 enum rockchip_pinctrl_type {
  62         RK2928,
  63         RK3066B,
  64         RK3188,
  65         RK3288,
  66         RK3366,
  67         RK3368,
  68         RK3399,
  69 };
  70
  71 /**
  72  * Encode variants of iomux registers into a type variable
  73  */
  74 #define IOMUX_GPIO_ONLY         BIT(0)
  75 #define IOMUX_WIDTH_4BIT        BIT(1)
  76 #define IOMUX_SOURCE_PMU        BIT(2)
  77 #define IOMUX_UNROUTED          BIT(3)
  78 #define IOMUX_WIDTH_3BIT        BIT(4)
  79 #define IOMUX_RECALCED_FLAG     BIT(5)
  80
  81 /**
  82  * @type: iomux variant using IOMUX_* constants
  83  * @offset: if initialized to -1 it will be autocalculated, by specifying
  84  *          an initial offset value the relevant source offset can be reset
  85  *          to a new value for autocalculating the following iomux registers.
  86  */
  87 struct rockchip_iomux {
  88         int                             type;
  89         int                             offset;
  90 };
  91
  92 /**
  93  * enum type index corresponding to rockchip_perpin_drv_list arrays index.
  94  */
  95 enum rockchip_pin_drv_type {
  96         DRV_TYPE_IO_DEFAULT = 0,
  97         DRV_TYPE_IO_1V8_OR_3V0,
  98         DRV_TYPE_IO_1V8_ONLY,
  99         DRV_TYPE_IO_1V8_3V0_AUTO,
 100         DRV_TYPE_IO_3V3_ONLY,
 101         DRV_TYPE_IO_WIDE_LEVEL,
 102         DRV_TYPE_IO_NARROW_LEVEL,
 103         DRV_TYPE_MAX
 104 };
 105
 106 /**
 107  * enum type index corresponding to rockchip_pull_list arrays index.
 108  */
 109 enum rockchip_pin_pull_type {
 110         PULL_TYPE_IO_DEFAULT = 0,
 111         PULL_TYPE_IO_1V8_ONLY,
 112         PULL_TYPE_MAX
 113 };
 114
 115 /**
 116  * enum type of pin extra drive alignment.
 117  */
 118 enum rockchip_pin_extra_drv_type {
 119         DRV_TYPE_EXTRA_DEFAULT = 0,
 120         DRV_TYPE_EXTRA_SAME_OFFSET,
 121         DRV_TYPE_EXTRA_SAME_BITS
 122 };
 123
 124 /**
 125  * @drv_type: drive strength variant using rockchip_pin_drv_type
 126  * @offset: if initialized to -1 it will be autocalculated, by specifying
 127  *          an initial offset value the relevant source offset can be reset
 128  *          to a new value for autocalculating the following drive strength
 129  *          registers. if used chips own cal_drv func instead to calculate
 130  *          registers offset, the variant could be ignored.
 131  */
 132 struct rockchip_drv {
 133         enum rockchip_pin_drv_type      drv_type;
 134         int                             offset;
 135 };
 136
 137 /**
 138  * @reg_base: register base of the gpio bank
 139  * @reg_pull: optional separate register for additional pull settings
 140  * @clk: clock of the gpio bank
 141  * @irq: interrupt of the gpio bank
 142  * @saved_masks: Saved content of GPIO_INTEN at suspend time.
 143  * @pin_base: first pin number
 144  * @nr_pins: number of pins in this bank
 145  * @name: name of the bank
 146  * @bank_num: number of the bank, to account for holes
 147  * @iomux: array describing the 4 iomux sources of the bank
 148  * @drv: array describing the 4 drive strength sources of the bank
 149  * @pull_type: array describing the 4 pull type sources of the bank
 150  * @valid: are all necessary informations present
 151  * @of_node: dt node of this bank
 152  * @drvdata: common pinctrl basedata
 153  * @domain: irqdomain of the gpio bank
 154  * @gpio_chip: gpiolib chip
 155  * @grange: gpio range
 156  * @slock: spinlock for the gpio bank
 157  */
 158 struct rockchip_pin_bank {
 159         void __iomem                    *reg_base;
 160         struct regmap                   *regmap_pull;
 161         struct clk                      *clk;
 162         int                             irq;
 163         u32                             saved_masks;
 164         u32                             pin_base;
 165         u8                              nr_pins;
 166         char                            *name;
 167         u8                              bank_num;
 168         struct rockchip_iomux           iomux[4];
 169         struct rockchip_drv             drv[4];
 170         enum rockchip_pin_pull_type     pull_type[4];
 171         bool                            valid;
 172         struct device_node              *of_node;
 173         struct rockchip_pinctrl         *drvdata;
 174         struct irq_domain               *domain;
 175         struct gpio_chip                gpio_chip;
 176         struct pinctrl_gpio_range       grange;
 177         spinlock_t                      slock;
 178         u32                             toggle_edge_mode;
 179 };
 180
 181 #define PIN_BANK(id, pins, label)                       \
 182         {                                               \
 183                 .bank_num       = id,                   \
 184                 .nr_pins        = pins,                 \
 185                 .name           = label,                \
 186                 .iomux          = {                     \
 187                         { .offset = -1 },               \
 188                         { .offset = -1 },               \
 189                         { .offset = -1 },               \
 190                         { .offset = -1 },               \
 191                 },                                      \
 192         }
 193
 194 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
 195         {                                                               \
 196                 .bank_num       = id,                                   \
 197                 .nr_pins        = pins,                                 \
 198                 .name           = label,                                \
 199                 .iomux          = {                                     \
 200                         { .type = iom0, .offset = -1 },                 \
 201                         { .type = iom1, .offset = -1 },                 \
 202                         { .type = iom2, .offset = -1 },                 \
 203                         { .type = iom3, .offset = -1 },                 \
 204                 },                                                      \
 205         }
 206
 207 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
 208         {                                                               \
 209                 .bank_num       = id,                                   \
 210                 .nr_pins        = pins,                                 \
 211                 .name           = label,                                \
 212                 .iomux          = {                                     \
 213                         { .offset = -1 },                               \
 214                         { .offset = -1 },                               \
 215                         { .offset = -1 },                               \
 216                         { .offset = -1 },                               \
 217                 },                                                      \
 218                 .drv            = {                                     \
 219                         { .drv_type = type0, .offset = -1 },            \
 220                         { .drv_type = type1, .offset = -1 },            \
 221                         { .drv_type = type2, .offset = -1 },            \
 222                         { .drv_type = type3, .offset = -1 },            \
 223                 },                                                      \
 224         }
 225
 226 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, drv2,\
 227                                       drv3, pull0, pull1, pull2, pull3) \
 228         {                                                               \
 229                 .bank_num       = id,                                   \
 230                 .nr_pins        = pins,                                 \
 231                 .name           = label,                                \
 232                 .iomux          = {                                     \
 233                         { .offset = -1 },                               \
 234                         { .offset = -1 },                               \
 235                         { .offset = -1 },                               \
 236                         { .offset = -1 },                               \
 237                 },                                                      \
 238                 .drv            = {                                     \
 239                         { .drv_type = drv0, .offset = -1 },             \
 240                         { .drv_type = drv1, .offset = -1 },             \
 241                         { .drv_type = drv2, .offset = -1 },             \
 242                         { .drv_type = drv3, .offset = -1 },             \
 243                 },                                                      \
 244                 .pull_type[0] = pull0,                                  \
 245                 .pull_type[1] = pull1,                                  \
 246                 .pull_type[2] = pull2,                                  \
 247                 .pull_type[3] = pull3,                                  \
 248         }
 249
 250 #define PIN_BANK_IOMUX_DRV_FLAGS(id, pins, label, iom0, iom1, iom2,     \
 251                                 iom3, drv0, drv1, drv2, drv3)           \
 252         {                                                               \
 253                 .bank_num       = id,                                   \
 254                 .nr_pins        = pins,                                 \
 255                 .name           = label,                                \
 256                 .iomux          = {                                     \
 257                         { .type = iom0, .offset = -1 },                 \
 258                         { .type = iom1, .offset = -1 },                 \
 259                         { .type = iom2, .offset = -1 },                 \
 260                         { .type = iom3, .offset = -1 },                 \
 261                 },                                                      \
 262                 .drv            = {                                     \
 263                         { .drv_type = drv0, .offset = -1 },             \
 264                         { .drv_type = drv1, .offset = -1 },             \
 265                         { .drv_type = drv2, .offset = -1 },             \
 266                         { .drv_type = drv3, .offset = -1 },             \
 267                 },                                                      \
 268         }
 269
 270 #define PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(id, pins, label, iom0,    \
 271                                              iom1, iom2, iom3, offset0, \
 272                                              offset1, offset2, offset3, \
 273                                              drv0, drv1, drv2, drv3)    \
 274         {                                                               \
 275                 .bank_num       = id,                                   \
 276                 .nr_pins        = pins,                                 \
 277                 .name           = label,                                \
 278                 .iomux          = {                                     \
 279                         { .type = iom0, .offset = offset0 },            \
 280                         { .type = iom1, .offset = offset1 },            \
 281                         { .type = iom2, .offset = offset2 },            \
 282                         { .type = iom3, .offset = offset3 },            \
 283                 },                                                      \
 284                 .drv            = {                                     \
 285                         { .drv_type = drv0, .offset = -1 },             \
 286                         { .drv_type = drv1, .offset = -1 },             \
 287                         { .drv_type = drv2, .offset = -1 },             \
 288                         { .drv_type = drv3, .offset = -1 },             \
 289                 },                                                      \
 290         }
 291
 292 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET(id, pins, label, iom0,    \
 293                                               iom1, iom2, iom3, drv0,   \
 294                                               drv1, drv2, drv3, offset0,\
 295                                               offset1, offset2, offset3)\
 296         {                                                               \
 297                 .bank_num       = id,                                   \
 298                 .nr_pins        = pins,                                 \
 299                 .name           = label,                                \
 300                 .iomux          = {                                     \
 301                         { .type = iom0, .offset = -1 },                 \
 302                         { .type = iom1, .offset = -1 },                 \
 303                         { .type = iom2, .offset = -1 },                 \
 304                         { .type = iom3, .offset = -1 },                 \
 305                 },                                                      \
 306                 .drv            = {                                     \
 307                         { .drv_type = drv0, .offset = offset0 },        \
 308                         { .drv_type = drv1, .offset = offset1 },        \
 309                         { .drv_type = drv2, .offset = offset2 },        \
 310                         { .drv_type = drv3, .offset = offset3 },        \
 311                 },                                                      \
 312         }
 313
 314 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins,      \
 315                                               label, iom0, iom1, iom2,  \
 316                                               iom3, drv0, drv1, drv2,   \
 317                                               drv3, offset0, offset1,   \
 318                                               offset2, offset3, pull0,  \
 319                                               pull1, pull2, pull3)      \
 320         {                                                               \
 321                 .bank_num       = id,                                   \
 322                 .nr_pins        = pins,                                 \
 323                 .name           = label,                                \
 324                 .iomux          = {                                     \
 325                         { .type = iom0, .offset = -1 },                 \
 326                         { .type = iom1, .offset = -1 },                 \
 327                         { .type = iom2, .offset = -1 },                 \
 328                         { .type = iom3, .offset = -1 },                 \
 329                 },                                                      \
 330                 .drv            = {                                     \
 331                         { .drv_type = drv0, .offset = offset0 },        \
 332                         { .drv_type = drv1, .offset = offset1 },        \
 333                         { .drv_type = drv2, .offset = offset2 },        \
 334                         { .drv_type = drv3, .offset = offset3 },        \
 335                 },                                                      \
 336                 .pull_type[0] = pull0,                                  \
 337                 .pull_type[1] = pull1,                                  \
 338                 .pull_type[2] = pull2,                                  \
 339                 .pull_type[3] = pull3,                                  \
 340         }
 341
 342 /**
 343  */
 344 struct rockchip_pin_ctrl {
 345         struct rockchip_pin_bank        *pin_banks;
 346         u32                             nr_banks;
 347         u32                             nr_pins;
 348         char                            *label;
 349         enum rockchip_pinctrl_type      type;
 350         int                             grf_mux_offset;
 351         int                             pmu_mux_offset;
 352         int                             grf_drv_offset;
 353         int                             pmu_drv_offset;
 354
 355         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank,
 356                                  int pin_num, struct regmap **regmap,
 357                                  int *reg, u8 *bit);
 358         enum rockchip_pin_drv_type (*drv_calc_reg)(
 359                                 struct rockchip_pin_bank *bank,
 360                                 int pin_num, struct regmap **regmap,
 361                                 int *reg, u8 *bit);
 362         enum rockchip_pin_extra_drv_type (*drv_calc_extra_reg)(
 363                                       struct rockchip_pin_bank *bank,
 364                                       int pin_num, struct regmap **regmap,
 365                                       int *reg, u8 *bit);
 366         void    (*iomux_recalc)(u8 bank_num, int pin, int *reg,
 367                                 int *mask, u8 *bit);
 368 };
 369
 370 struct rockchip_pin_config {
 371         unsigned int            func;
 372         unsigned long           *configs;
 373         unsigned int            nconfigs;
 374 };
 375
 376 /**
 377  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 378  * @name: name of the pin group, used to lookup the group.
 379  * @pins: the pins included in this group.
 380  * @npins: number of pins included in this group.
 381  * @func: the mux function number to be programmed when selected.
 382  * @configs: the config values to be set for each pin
 383  * @nconfigs: number of configs for each pin
 384  */
 385 struct rockchip_pin_group {
 386         const char                      *name;
 387         unsigned int                    npins;
 388         unsigned int                    *pins;
 389         struct rockchip_pin_config      *data;
 390 };
 391
 392 /**
 393  * struct rockchip_pmx_func: represent a pin function.
 394  * @name: name of the pin function, used to lookup the function.
 395  * @groups: one or more names of pin groups that provide this function.
 396  * @num_groups: number of groups included in @groups.
 397  */
 398 struct rockchip_pmx_func {
 399         const char              *name;
 400         const char              **groups;
 401         u8                      ngroups;
 402 };
 403
 404 struct rockchip_pinctrl {
 405         struct regmap                   *regmap_base;
 406         int                             reg_size;
 407         struct regmap                   *regmap_pull;
 408         struct regmap                   *regmap_pmu;
 409         struct device                   *dev;
 410         struct rockchip_pin_ctrl        *ctrl;
 411         struct pinctrl_desc             pctl;
 412         struct pinctrl_dev              *pctl_dev;
 413         struct rockchip_pin_group       *groups;
 414         unsigned int                    ngroups;
 415         struct rockchip_pmx_func        *functions;
 416         unsigned int                    nfunctions;
 417 };
 418
 419 /**
 420  * struct rockchip_mux_recalced_data: represent a pin iomux data.
 421  * @num: bank num.
 422  * @bit: index at register or used to calc index.
 423  * @min_pin: the min pin.
 424  * @max_pin: the max pin.
 425  * @reg: the register offset.
 426  * @mask: mask bit
 427  */
 428 struct rockchip_mux_recalced_data {
 429         u8 num;
 430         u8 bit;
 431         int min_pin;
 432         int max_pin;
 433         int reg;
 434         int mask;
 435 };
 436
 437 static struct regmap_config rockchip_regmap_config = {
 438         .reg_bits = 32,
 439         .val_bits = 32,
 440         .reg_stride = 4,
 441 };
 442
 443 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
 444 {
 445         return container_of(gc, struct rockchip_pin_bank, gpio_chip);
 446 }
 447
 448 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
 449                                         const struct rockchip_pinctrl *info,
 450                                         const char *name)
 451 {
 452         int i;
 453
 454         for (i = 0; i < info->ngroups; i++) {
 455                 if (!strcmp(info->groups[i].name, name))
 456                         return &info->groups[i];
 457         }
 458
 459         return NULL;
 460 }
 461
 462 /*
 463  * given a pin number that is local to a pin controller, find out the pin bank
 464  * and the register base of the pin bank.
 465  */
 466 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 467                                                                 unsigned pin)
 468 {
 469         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 470
 471         while (pin >= (b->pin_base + b->nr_pins))
 472                 b++;
 473
 474         return b;
 475 }
 476
 477 static struct rockchip_pin_bank *bank_num_to_bank(
 478                                         struct rockchip_pinctrl *info,
 479                                         unsigned num)
 480 {
 481         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 482         int i;
 483
 484         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 485                 if (b->bank_num == num)
 486                         return b;
 487         }
 488
 489         return ERR_PTR(-EINVAL);
 490 }
 491
 492 /*
 493  * Pinctrl_ops handling
 494  */
 495
 496 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 497 {
 498         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 499
 500         return info->ngroups;
 501 }
 502
 503 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 504                                                         unsigned selector)
 505 {
 506         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 507
 508         return info->groups[selector].name;
 509 }
 510
 511 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 512                                       unsigned selector, const unsigned **pins,
 513                                       unsigned *npins)
 514 {
 515         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 516
 517         if (selector >= info->ngroups)
 518                 return -EINVAL;
 519
 520         *pins = info->groups[selector].pins;
 521         *npins = info->groups[selector].npins;
 522
 523         return 0;
 524 }
 525
 526 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 527                                  struct device_node *np,
 528                                  struct pinctrl_map **map, unsigned *num_maps)
 529 {
 530         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 531         const struct rockchip_pin_group *grp;
 532         struct pinctrl_map *new_map;
 533         struct device_node *parent;
 534         int map_num = 1;
 535         int i;
 536
 537         /*
 538          * first find the group of this node and check if we need to create
 539          * config maps for pins
 540          */
 541         grp = pinctrl_name_to_group(info, np->name);
 542         if (!grp) {
 543                 dev_err(info->dev, "unable to find group for node %s\n",
 544                         np->name);
 545                 return -EINVAL;
 546         }
 547
 548         map_num += grp->npins;
 549         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 550                                                                 GFP_KERNEL);
 551         if (!new_map)
 552                 return -ENOMEM;
 553
 554         *map = new_map;
 555         *num_maps = map_num;
 556
 557         /* create mux map */
 558         parent = of_get_parent(np);
 559         if (!parent) {
 560                 devm_kfree(pctldev->dev, new_map);
 561                 return -EINVAL;
 562         }
 563         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 564         new_map[0].data.mux.function = parent->name;
 565         new_map[0].data.mux.group = np->name;
 566         of_node_put(parent);
 567
 568         /* create config map */
 569         new_map++;
 570         for (i = 0; i < grp->npins; i++) {
 571                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 572                 new_map[i].data.configs.group_or_pin =
 573                                 pin_get_name(pctldev, grp->pins[i]);
 574                 new_map[i].data.configs.configs = grp->data[i].configs;
 575                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 576         }
 577
 578         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 579                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 580
 581         return 0;
 582 }
 583
 584 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 585                                     struct pinctrl_map *map, unsigned num_maps)
 586 {
 587 }
 588
 589 static const struct pinctrl_ops rockchip_pctrl_ops = {
 590         .get_groups_count       = rockchip_get_groups_count,
 591         .get_group_name         = rockchip_get_group_name,
 592         .get_group_pins         = rockchip_get_group_pins,
 593         .dt_node_to_map         = rockchip_dt_node_to_map,
 594         .dt_free_map            = rockchip_dt_free_map,
 595 };
 596
 597 /*
 598  * Hardware access
 599  */
 600
 601 static const struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
 602         {
 603                 .num = 2,
 604                 .bit = 0x2,
 605                 .min_pin = 8,
 606                 .max_pin = 14,
 607                 .reg = 0x24,
 608                 .mask = 0x3
 609         },
 610         {
 611                 .num = 2,
 612                 .bit = 0,
 613                 .min_pin = 15,
 614                 .max_pin = 15,
 615                 .reg = 0x28,
 616                 .mask = 0x7
 617         },
 618         {
 619                 .num = 2,
 620                 .bit = 14,
 621                 .min_pin = 23,
 622                 .max_pin = 23,
 623                 .reg = 0x30,
 624                 .mask = 0x3
 625         },
 626         {
 627                 .num = 3,
 628                 .bit = 0,
 629                 .min_pin = 8,
 630                 .max_pin = 8,
 631                 .reg = 0x40,
 632                 .mask = 0x7
 633         },
 634         {
 635                 .num = 3,
 636                 .bit = 0x2,
 637                 .min_pin = 9,
 638                 .max_pin = 15,
 639                 .reg = 0x44,
 640                 .mask = 0x3
 641         },
 642 };
 643
 644 static void rk3328_recalc_mux(u8 bank_num, int pin, int *reg,
 645                               int *mask, u8 *bit)
 646 {
 647         const struct rockchip_mux_recalced_data *data = NULL;
 648         int i;
 649
 650         for (i = 0; i < ARRAY_SIZE(rk3328_mux_recalced_data); i++)
 651                 if (rk3328_mux_recalced_data[i].num == bank_num &&
 652                     rk3328_mux_recalced_data[i].min_pin <= pin &&
 653                     rk3328_mux_recalced_data[i].max_pin >= pin) {
 654                         data = &rk3328_mux_recalced_data[i];
 655                         break;
 656                 }
 657
 658         if (!data)
 659                 return;
 660
 661         *reg = data->reg;
 662         *mask = data->mask;
 663
 664         if (data->min_pin == data->max_pin)
 665                 *bit = data->bit;
 666         else
 667                 *bit = (pin % 8) * data->bit;
 668 }
 669
 670 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
 671 {
 672         struct rockchip_pinctrl *info = bank->drvdata;
 673         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 674         int iomux_num = (pin / 8);
 675         struct regmap *regmap;
 676         unsigned int val;
 677         int reg, ret, mask, mux_type;
 678         u8 bit;
 679
 680         if (iomux_num > 3)
 681                 return -EINVAL;
 682
 683         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 684                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 685                 return -EINVAL;
 686         }
 687
 688         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
 689                 return RK_FUNC_GPIO;
 690
 691         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 692                                 ? info->regmap_pmu : info->regmap_base;
 693
 694         /* get basic quadrupel of mux registers and the correct reg inside */
 695         mux_type = bank->iomux[iomux_num].type;
 696         reg = bank->iomux[iomux_num].offset;
 697         if (mux_type & IOMUX_WIDTH_4BIT) {
 698                 mask = 0xf;
 699                 if ((pin % 8) >= 4)
 700                         reg += 0x4;
 701                 bit = (pin % 4) * 4;
 702         } else if (mux_type & IOMUX_WIDTH_3BIT) {
 703                 mask = 0x7;
 704                 if ((pin % 8) >= 5) {
 705                         reg += 0x4;
 706                         bit = ((pin % 8) % 5) * 3;
 707                 } else {
 708                         bit = (pin % 8) * 3;
 709                 }
 710         } else {
 711                 mask = 0x3;
 712                 bit = (pin % 8) * 2;
 713         }
 714
 715         if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED_FLAG))
 716                 ctrl->iomux_recalc(bank->bank_num, pin, &reg, &mask, &bit);
 717
 718         ret = regmap_read(regmap, reg, &val);
 719         if (ret)
 720                 return ret;
 721
 722         return ((val >> bit) & mask);
 723 }
 724
 725 /*
 726  * Set a new mux function for a pin.
 727  *
 728  * The register is divided into the upper and lower 16 bit. When changing
 729  * a value, the previous register value is not read and changed. Instead
 730  * it seems the changed bits are marked in the upper 16 bit, while the
 731  * changed value gets set in the same offset in the lower 16 bit.
 732  * All pin settings seem to be 2 bit wide in both the upper and lower
 733  * parts.
 734  * @bank: pin bank to change
 735  * @pin: pin to change
 736  * @mux: new mux function to set
 737  */
 738 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 739 {
 740         struct rockchip_pinctrl *info = bank->drvdata;
 741         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 742         int iomux_num = (pin / 8);
 743         struct regmap *regmap;
 744         int reg, ret, mask, mux_type;
 745         unsigned long flags;
 746         u8 bit;
 747         u32 data, rmask;
 748
 749         if (iomux_num > 3)
 750                 return -EINVAL;
 751
 752         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 753                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 754                 return -EINVAL;
 755         }
 756
 757         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
 758                 if (mux != RK_FUNC_GPIO) {
 759                         dev_err(info->dev,
 760                                 "pin %d only supports a gpio mux\n", pin);
 761                         return -ENOTSUPP;
 762                 } else {
 763                         return 0;
 764                 }
 765         }
 766
 767         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
 768                                                 bank->bank_num, pin, mux);
 769
 770         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 771                                 ? info->regmap_pmu : info->regmap_base;
 772
 773         /* get basic quadrupel of mux registers and the correct reg inside */
 774         mux_type = bank->iomux[iomux_num].type;
 775         reg = bank->iomux[iomux_num].offset;
 776         if (mux_type & IOMUX_WIDTH_4BIT) {
 777                 mask = 0xf;
 778                 if ((pin % 8) >= 4)
 779                         reg += 0x4;
 780                 bit = (pin % 4) * 4;
 781         } else if (mux_type & IOMUX_WIDTH_3BIT) {
 782                 mask = 0x7;
 783                 if ((pin % 8) >= 5) {
 784                         reg += 0x4;
 785                         bit = ((pin % 8) % 5) * 3;
 786                 } else {
 787                         bit = (pin % 8) * 3;
 788                 }
 789         } else {
 790                 mask = 0x3;
 791                 bit = (pin % 8) * 2;
 792         }
 793
 794         if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED_FLAG))
 795                 ctrl->iomux_recalc(bank->bank_num, pin, &reg, &mask, &bit);
 796
 797         spin_lock_irqsave(&bank->slock, flags);
 798
 799         data = (mask << (bit + 16));
 800         rmask = data | (data >> 16);
 801         data |= (mux & mask) << bit;
 802         ret = regmap_update_bits(regmap, reg, rmask, data);
 803
 804         spin_unlock_irqrestore(&bank->slock, flags);
 805
 806         return ret;
 807 }
 808
 809 #define RK2928_PULL_OFFSET              0x118
 810 #define RK2928_PULL_PINS_PER_REG        16
 811 #define RK2928_PULL_BANK_STRIDE         8
 812
 813 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 814                                     int pin_num, struct regmap **regmap,
 815                                     int *reg, u8 *bit)
 816 {
 817         struct rockchip_pinctrl *info = bank->drvdata;
 818
 819         *regmap = info->regmap_base;
 820         *reg = RK2928_PULL_OFFSET;
 821         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
 822         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
 823
 824         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
 825 };
 826
 827 #define RK3188_PULL_OFFSET              0x164
 828 #define RK3188_PULL_BITS_PER_PIN        2
 829 #define RK3188_PULL_PINS_PER_REG        8
 830 #define RK3188_PULL_BANK_STRIDE         16
 831 #define RK3188_PULL_PMU_OFFSET          0x64
 832
 833 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 834                                     int pin_num, struct regmap **regmap,
 835                                     int *reg, u8 *bit)
 836 {
 837         struct rockchip_pinctrl *info = bank->drvdata;
 838
 839         /* The first 12 pins of the first bank are located elsewhere */
 840         if (bank->bank_num == 0 && pin_num < 12) {
 841                 *regmap = info->regmap_pmu ? info->regmap_pmu
 842                                            : bank->regmap_pull;
 843                 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
 844                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 845                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 846                 *bit *= RK3188_PULL_BITS_PER_PIN;
 847         } else {
 848                 *regmap = info->regmap_pull ? info->regmap_pull
 849                                             : info->regmap_base;
 850                 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
 851
 852                 /* correct the offset, as it is the 2nd pull register */
 853                 *reg -= 4;
 854                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 855                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 856
 857                 /*
 858                  * The bits in these registers have an inverse ordering
 859                  * with the lowest pin being in bits 15:14 and the highest
 860                  * pin in bits 1:0
 861                  */
 862                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
 863                 *bit *= RK3188_PULL_BITS_PER_PIN;
 864         }
 865 }
 866
 867 #define RK3288_PULL_OFFSET              0x140
 868 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 869                                     int pin_num, struct regmap **regmap,
 870                                     int *reg, u8 *bit)
 871 {
 872         struct rockchip_pinctrl *info = bank->drvdata;
 873
 874         /* The first 24 pins of the first bank are located in PMU */
 875         if (bank->bank_num == 0) {
 876                 *regmap = info->regmap_pmu;
 877                 *reg = RK3188_PULL_PMU_OFFSET;
 878
 879                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 880                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 881                 *bit *= RK3188_PULL_BITS_PER_PIN;
 882         } else {
 883                 *regmap = info->regmap_base;
 884                 *reg = RK3288_PULL_OFFSET;
 885
 886                 /* correct the offset, as we're starting with the 2nd bank */
 887                 *reg -= 0x10;
 888                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 889                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 890
 891                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
 892                 *bit *= RK3188_PULL_BITS_PER_PIN;
 893         }
 894 }
 895
 896 #define RK3288_DRV_PMU_OFFSET           0x70
 897 #define RK3288_DRV_GRF_OFFSET           0x1c0
 898 #define RK3288_DRV_BITS_PER_PIN         2
 899 #define RK3288_DRV_PINS_PER_REG         8
 900 #define RK3288_DRV_BANK_STRIDE          16
 901
 902 static enum rockchip_pin_drv_type rk3288_calc_drv_reg_and_bit(
 903                                        struct rockchip_pin_bank *bank,
 904                                        int pin_num, struct regmap **regmap,
 905                                        int *reg, u8 *bit)
 906 {
 907         struct rockchip_pinctrl *info = bank->drvdata;
 908
 909         /* The first 24 pins of the first bank are located in PMU */
 910         if (bank->bank_num == 0) {
 911                 *regmap = info->regmap_pmu;
 912                 *reg = RK3288_DRV_PMU_OFFSET;
 913
 914                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 915                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
 916                 *bit *= RK3288_DRV_BITS_PER_PIN;
 917         } else {
 918                 *regmap = info->regmap_base;
 919                 *reg = RK3288_DRV_GRF_OFFSET;
 920
 921                 /* correct the offset, as we're starting with the 2nd bank */
 922                 *reg -= 0x10;
 923                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
 924                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 925
 926                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
 927                 *bit *= RK3288_DRV_BITS_PER_PIN;
 928         }
 929
 930         return DRV_TYPE_IO_DEFAULT;
 931 }
 932
 933 #define RK3228_PULL_OFFSET              0x100
 934
 935 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 936                                     int pin_num, struct regmap **regmap,
 937                                     int *reg, u8 *bit)
 938 {
 939         struct rockchip_pinctrl *info = bank->drvdata;
 940
 941         *regmap = info->regmap_base;
 942         *reg = RK3228_PULL_OFFSET;
 943         *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 944         *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 945
 946         *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
 947         *bit *= RK3188_PULL_BITS_PER_PIN;
 948 }
 949
 950 #define RK3228_DRV_GRF_OFFSET           0x200
 951
 952 static enum rockchip_pin_drv_type rk3228_calc_drv_reg_and_bit(
 953                                        struct rockchip_pin_bank *bank,
 954                                        int pin_num, struct regmap **regmap,
 955                                        int *reg, u8 *bit)
 956 {
 957         struct rockchip_pinctrl *info = bank->drvdata;
 958
 959         *regmap = info->regmap_base;
 960         *reg = RK3228_DRV_GRF_OFFSET;
 961         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
 962         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 963
 964         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
 965         *bit *= RK3288_DRV_BITS_PER_PIN;
 966
 967         return DRV_TYPE_IO_DEFAULT;
 968 }
 969
 970 #define RK3366_PULL_GRF_OFFSET          0x110
 971 #define RK3366_PULL_PMU_OFFSET          0x10
 972
 973 static void rk3366_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 974                                          int pin_num, struct regmap **regmap,
 975                                          int *reg, u8 *bit)
 976 {
 977         struct rockchip_pinctrl *info = bank->drvdata;
 978
 979         /* The bank0:32 and bank1:16 pins are located in PMU */
 980         if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
 981                 *regmap = info->regmap_pmu;
 982                 *reg = RK3366_PULL_PMU_OFFSET + bank->bank_num * 0x30;
 983
 984                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 985                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 986                 *bit *= RK3188_PULL_BITS_PER_PIN;
 987         } else {
 988                 *regmap = info->regmap_base;
 989                 *reg = RK3366_PULL_GRF_OFFSET;
 990
 991                 /* correct the offset, as we're starting with the 2nd bank */
 992                 *reg -= 0x20;
 993                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 994                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 995
 996                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
 997                 *bit *= RK3188_PULL_BITS_PER_PIN;
 998         }
 999 }
1000
1001 #define RK3366_DRV_PMU_OFFSET           0x20
1002 #define RK3366_DRV_GRF_OFFSET           0x210
1003
1004 #define RK3366_DRV_GPIO2B3_OFFSET       0x378
1005 #define RK3366_DRV_GPIO2B3_BITS         4
1006
1007 #define RK3366_DRV_GPIO3A4_OFFSET       0x37c
1008 #define RK3366_DRV_GPIO3A4_BITS         4
1009
1010 static enum rockchip_pin_drv_type rk3366_calc_drv_reg_and_bit(
1011                                        struct rockchip_pin_bank *bank,
1012                                        int pin_num, struct regmap **regmap,
1013                                        int *reg, u8 *bit)
1014 {
1015         struct rockchip_pinctrl *info = bank->drvdata;
1016
1017         /* The bank0:32 and bank1:16 pins are located in PMU */
1018         if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1019                 *regmap = info->regmap_pmu;
1020                 *reg = RK3366_DRV_PMU_OFFSET + bank->bank_num * 0x30;
1021
1022                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1023                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1024                 *bit *= RK3288_DRV_BITS_PER_PIN;
1025
1026                 return DRV_TYPE_IO_DEFAULT;
1027         } else if ((bank->bank_num == 2) && (pin_num == 11)) {
1028                 /* GPIO2B3 is a special case in bank2 */
1029                 *regmap = info->regmap_base;
1030                 *reg = RK3366_DRV_GPIO2B3_OFFSET;
1031                 *bit = RK3366_DRV_GPIO2B3_BITS;
1032
1033                 return DRV_TYPE_IO_WIDE_LEVEL;
1034         } else if ((bank->bank_num == 3) && (pin_num == 4)) {
1035                 /* GPIO3A4 is a special case in bank3 */
1036                 *regmap = info->regmap_base;
1037                 *reg = RK3366_DRV_GPIO3A4_OFFSET;
1038                 *bit = RK3366_DRV_GPIO3A4_BITS;
1039
1040                 return DRV_TYPE_IO_WIDE_LEVEL;
1041         }
1042
1043         *regmap = info->regmap_base;
1044         *reg = RK3366_DRV_GRF_OFFSET;
1045
1046         /* correct the offset, as we're starting with the 2nd bank */
1047         *reg -= 0x20;
1048         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1049         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1050
1051         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1052         *bit *= RK3288_DRV_BITS_PER_PIN;
1053
1054         /* special cases need special handle */
1055         if ((bank->bank_num == 2) && (pin_num == 14))
1056                 return DRV_TYPE_IO_WIDE_LEVEL;
1057         else if ((bank->bank_num == 2) && (pin_num == 16))
1058                 return DRV_TYPE_IO_NARROW_LEVEL;
1059         else if ((bank->bank_num == 2) && (pin_num >= 24) && (pin_num <= 26))
1060                 return DRV_TYPE_IO_WIDE_LEVEL;
1061
1062         return DRV_TYPE_IO_DEFAULT;
1063 }
1064
1065 #define RK3366_DRV_GPIO2A_EN_OFFSET     0x360
1066 #define RK3366_DRV_GPIO2A_EP_OFFSET     0x364
1067
1068 #define RK3366_DRV_GPIO2C_EN_OFFSET     0x368
1069 #define RK3366_DRV_GPIO2C_EP_OFFSET     0x36C
1070
1071 #define RK3366_DRV_GPIO2D_EN_OFFSET     0x370
1072 #define RK3366_DRV_GPIO2D_EP_OFFSET     0x374
1073
1074 #define RK3366_DRV_GPIO2B3_E_OFFSET     0x378
1075 #define RK3366_DRV_GPIO2B3_EN_BIT       0
1076 #define RK3366_DRV_GPIO2B3_EP_BIT       2
1077
1078 #define RK3366_DRV_GPIO3A4_E_OFFSET     0x37c
1079 #define RK3366_DRV_GPIO3A4_EN_BIT       0
1080 #define RK3366_DRV_GPIO3A4_EP_BIT       2
1081
1082 #define RK3366_DRV_GPIO2B6_E_OFFSET     0x404
1083 #define RK3366_DRV_GPIO2B6_EN_BIT       12
1084 #define RK3366_DRV_GPIO2B6_EP_BIT       14
1085
1086 static enum rockchip_pin_extra_drv_type rk3366_calc_drv_extra_reg_and_bit(
1087                                              struct rockchip_pin_bank *bank,
1088                                              int pin_num,
1089                                              struct regmap **regmap,
1090                                              int *reg, u8 *bit)
1091 {
1092         struct rockchip_pinctrl *info = bank->drvdata;
1093
1094         *regmap = info->regmap_base;
1095         if (bank->bank_num == 2) {
1096                 switch (pin_num / 8) {
1097                 case 0:
1098                         *reg = RK3366_DRV_GPIO2A_EN_OFFSET;
1099                         break;
1100                 case 1:
1101                         /* special cases need special handle */
1102                         if (pin_num == 11) {
1103                                 *reg = RK3366_DRV_GPIO2B3_E_OFFSET;
1104                                 *bit = RK3366_DRV_GPIO2B3_EN_BIT;
1105                         } else if (pin_num == 14) {
1106                                 *reg = RK3366_DRV_GPIO2B6_E_OFFSET;
1107                                 *bit = RK3366_DRV_GPIO2B6_EN_BIT;
1108                         } else {
1109                                 return -1;
1110                         }
1111
1112                         return DRV_TYPE_EXTRA_SAME_OFFSET;
1113                 case 2:
1114                         *reg = RK3366_DRV_GPIO2C_EN_OFFSET;
1115                         break;
1116                 case 3:
1117                         *reg = RK3366_DRV_GPIO2D_EN_OFFSET;
1118                         break;
1119                 default:
1120                         return -1;
1121                 }
1122
1123                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1124                 *bit *= RK3288_DRV_BITS_PER_PIN;
1125
1126                 return DRV_TYPE_EXTRA_SAME_BITS;
1127         }
1128
1129         /* GPIO3A4 is a special case */
1130         if ((pin_num != 4) && (bank->bank_num != 3))
1131                 return -1;
1132
1133         *reg = RK3366_DRV_GPIO3A4_E_OFFSET;
1134         *bit = RK3366_DRV_GPIO3A4_EN_BIT;
1135
1136         return DRV_TYPE_EXTRA_SAME_OFFSET;
1137 }
1138
1139 #define RK3368_PULL_GRF_OFFSET          0x100
1140 #define RK3368_PULL_PMU_OFFSET          0x10
1141
1142 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1143                                          int pin_num, struct regmap **regmap,
1144                                          int *reg, u8 *bit)
1145 {
1146         struct rockchip_pinctrl *info = bank->drvdata;
1147
1148         /* The first 32 pins of the first bank are located in PMU */
1149         if (bank->bank_num == 0) {
1150                 *regmap = info->regmap_pmu;
1151                 *reg = RK3368_PULL_PMU_OFFSET;
1152
1153                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1154                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1155                 *bit *= RK3188_PULL_BITS_PER_PIN;
1156         } else {
1157                 *regmap = info->regmap_base;
1158                 *reg = RK3368_PULL_GRF_OFFSET;
1159
1160                 /* correct the offset, as we're starting with the 2nd bank */
1161                 *reg -= 0x10;
1162                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1163                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1164
1165                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1166                 *bit *= RK3188_PULL_BITS_PER_PIN;
1167         }
1168 }
1169
1170 #define RK3368_DRV_PMU_OFFSET           0x20
1171 #define RK3368_DRV_GRF_OFFSET           0x200
1172
1173 static enum rockchip_pin_drv_type rk3368_calc_drv_reg_and_bit(
1174                                        struct rockchip_pin_bank *bank,
1175                                        int pin_num, struct regmap **regmap,
1176                                        int *reg, u8 *bit)
1177 {
1178         struct rockchip_pinctrl *info = bank->drvdata;
1179
1180         /* The first 32 pins of the first bank are located in PMU */
1181         if (bank->bank_num == 0) {
1182                 *regmap = info->regmap_pmu;
1183                 *reg = RK3368_DRV_PMU_OFFSET;
1184
1185                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1186                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1187                 *bit *= RK3288_DRV_BITS_PER_PIN;
1188         } else {
1189                 *regmap = info->regmap_base;
1190                 *reg = RK3368_DRV_GRF_OFFSET;
1191
1192                 /* correct the offset, as we're starting with the 2nd bank */
1193                 *reg -= 0x10;
1194                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1195                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1196
1197                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1198                 *bit *= RK3288_DRV_BITS_PER_PIN;
1199         }
1200
1201         return DRV_TYPE_IO_DEFAULT;
1202 }
1203
1204 #define RK3399_PULL_GRF_OFFSET          0xe040
1205 #define RK3399_PULL_PMU_OFFSET          0x40
1206 #define RK3399_DRV_3BITS_PER_PIN        3
1207
1208 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1209                                          int pin_num, struct regmap **regmap,
1210                                          int *reg, u8 *bit)
1211 {
1212         struct rockchip_pinctrl *info = bank->drvdata;
1213
1214         /* The bank0:16 and bank1:32 pins are located in PMU */
1215         if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1216                 *regmap = info->regmap_pmu;
1217                 *reg = RK3399_PULL_PMU_OFFSET;
1218
1219                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1220
1221                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1222                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1223                 *bit *= RK3188_PULL_BITS_PER_PIN;
1224         } else {
1225                 *regmap = info->regmap_base;
1226                 *reg = RK3399_PULL_GRF_OFFSET;
1227
1228                 /* correct the offset, as we're starting with the 3rd bank */
1229                 *reg -= 0x20;
1230                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1231                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1232
1233                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1234                 *bit *= RK3188_PULL_BITS_PER_PIN;
1235         }
1236 }
1237
1238 static enum rockchip_pin_drv_type rk3399_calc_drv_reg_and_bit(
1239                                        struct rockchip_pin_bank *bank,
1240                                        int pin_num, struct regmap **regmap,
1241                                        int *reg, u8 *bit)
1242 {
1243         struct rockchip_pinctrl *info = bank->drvdata;
1244         int drv_num = (pin_num / 8);
1245
1246         /*  The bank0:16 and bank1:32 pins are located in PMU */
1247         if ((bank->bank_num == 0) || (bank->bank_num == 1))
1248                 *regmap = info->regmap_pmu;
1249         else
1250                 *regmap = info->regmap_base;
1251
1252         *reg = bank->drv[drv_num].offset;
1253         if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1254             (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1255                 *bit = (pin_num % 8) * 3;
1256         else
1257                 *bit = (pin_num % 8) * 2;
1258
1259         return DRV_TYPE_IO_DEFAULT;
1260 }
1261
1262 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1263         { 2, 4, 8, 12, -1, -1, -1, -1 },
1264         { 3, 6, 9, 12, -1, -1, -1, -1 },
1265         { 5, 10, 15, 20, -1, -1, -1, -1 },
1266         { 4, 6, 8, 10, 12, 14, 16, 18 },
1267         { 4, 7, 10, 13, 16, 19, 22, 26 },
1268         { 0, 6, 12, 18, -1, -1, -1, -1 },
1269         { 4, 8, 12, 16, -1, -1, -1, -1 }
1270 };
1271
1272 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1273                                      int pin_num)
1274 {
1275         struct rockchip_pinctrl *info = bank->drvdata;
1276         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1277         struct regmap *regmap, *extra_regmap;
1278         int reg, ret, extra_reg;
1279         u32 data, temp, rmask_bits;
1280         u8 bit, extra_bit;
1281         int drv_type;
1282
1283         drv_type = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1284         if (!drv_type)
1285                 drv_type = bank->drv[pin_num / 8].drv_type;
1286
1287         switch (drv_type) {
1288         case DRV_TYPE_IO_1V8_3V0_AUTO:
1289         case DRV_TYPE_IO_3V3_ONLY:
1290                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1291                 switch (bit) {
1292                 case 0 ... 12:
1293                         /* regular case, nothing to do */
1294                         break;
1295                 case 15:
1296                         /*
1297                          * drive-strength offset is special, as it is
1298                          * spread over 2 registers
1299                          */
1300                         ret = regmap_read(regmap, reg, &data);
1301                         if (ret)
1302                                 return ret;
1303
1304                         ret = regmap_read(regmap, reg + 0x4, &temp);
1305                         if (ret)
1306                                 return ret;
1307
1308                         /*
1309                          * the bit data[15] contains bit 0 of the value
1310                          * while temp[1:0] contains bits 2 and 1
1311                          */
1312                         data >>= 15;
1313                         temp &= 0x3;
1314                         temp <<= 1;
1315                         data |= temp;
1316
1317                         return rockchip_perpin_drv_list[drv_type][data];
1318                 case 18 ... 21:
1319                         /* setting fully enclosed in the second register */
1320                         reg += 4;
1321                         bit -= 16;
1322                         break;
1323                 default:
1324                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1325                                 bit, drv_type);
1326                         return -EINVAL;
1327                 }
1328
1329                 break;
1330         case DRV_TYPE_IO_WIDE_LEVEL:
1331                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1332                 /* enable the write to the equivalent lower bits */
1333                 ret = regmap_read(regmap, reg, &data);
1334                 if (ret)
1335                         return ret;
1336                 data >>= bit;
1337                 data &= (1 << rmask_bits) - 1;
1338
1339                 /*
1340                  * assume the drive strength of N channel and
1341                  * P channel are the same.
1342                  */
1343                 if (ctrl->drv_calc_extra_reg)
1344                         ctrl->drv_calc_extra_reg(bank, pin_num,
1345                                                  &extra_regmap,
1346                                                  &extra_reg,
1347                                                  &extra_bit);
1348
1349                 /*
1350                  * It is enough to read one channel drive strength,
1351                  * this is N channel.
1352                  */
1353                 ret = regmap_read(extra_regmap, extra_reg, &temp);
1354                 if (ret)
1355                         return ret;
1356
1357                 temp >>= extra_bit;
1358                 temp &= (1 << rmask_bits) - 1;
1359
1360                 return (rockchip_perpin_drv_list[drv_type][data]) + (temp * 2);
1361         case DRV_TYPE_IO_DEFAULT:
1362         case DRV_TYPE_IO_1V8_OR_3V0:
1363         case DRV_TYPE_IO_1V8_ONLY:
1364         case DRV_TYPE_IO_NARROW_LEVEL:
1365                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1366                 break;
1367         default:
1368                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1369                         drv_type);
1370                 return -EINVAL;
1371         }
1372
1373         ret = regmap_read(regmap, reg, &data);
1374         if (ret)
1375                 return ret;
1376
1377         data >>= bit;
1378         data &= (1 << rmask_bits) - 1;
1379
1380         return rockchip_perpin_drv_list[drv_type][data];
1381 }
1382
1383 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1384                                      int pin_num, int strength)
1385 {
1386         struct rockchip_pinctrl *info = bank->drvdata;
1387         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1388         struct regmap *regmap, *extra_regmap;
1389         unsigned long flags;
1390         int reg, ret, i;
1391         u32 data, temp, rmask, rmask_bits;
1392         u8 bit, extra_bit;
1393         int drv_type, extra_drv_type = 0;
1394         int extra_value, extra_reg;
1395
1396         dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
1397                 bank->bank_num, pin_num, strength);
1398
1399         drv_type = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1400         if (!drv_type)
1401                 drv_type = bank->drv[pin_num / 8].drv_type;
1402
1403         ret = -EINVAL;
1404
1405         if (drv_type == DRV_TYPE_IO_WIDE_LEVEL) {
1406                 if ((strength % 2 == 0) && (strength <= 24))
1407                         ret = ((strength > 18) ? 18 : strength) / 6;
1408         } else {
1409                 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]);
1410                      i++) {
1411                         if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1412                                 ret = rockchip_perpin_drv_list[drv_type][i];
1413                                 break;
1414                         } else if (rockchip_perpin_drv_list[drv_type][i] ==
1415                                    strength) {
1416                                 ret = i;
1417                                 break;
1418                         }
1419                 }
1420         }
1421
1422         if (ret < 0) {
1423                 dev_err(info->dev, "unsupported driver strength %d\n",
1424                         strength);
1425                 return ret;
1426         }
1427
1428         spin_lock_irqsave(&bank->slock, flags);
1429
1430         switch (drv_type) {
1431         case DRV_TYPE_IO_1V8_3V0_AUTO:
1432         case DRV_TYPE_IO_3V3_ONLY:
1433                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1434                 switch (bit) {
1435                 case 0 ... 12:
1436                         /* regular case, nothing to do */
1437                         break;
1438                 case 15:
1439                         /*
1440                          * drive-strength offset is special, as it is spread
1441                          * over 2 registers, the bit data[15] contains bit 0
1442                          * of the value while temp[1:0] contains bits 2 and 1
1443                          */
1444                         data = (ret & 0x1) << 15;
1445                         temp = (ret >> 0x1) & 0x3;
1446
1447                         rmask = BIT(15) | BIT(31);
1448                         data |= BIT(31);
1449                         ret = regmap_update_bits(regmap, reg, rmask, data);
1450                         if (ret) {
1451                                 spin_unlock_irqrestore(&bank->slock, flags);
1452                                 return ret;
1453                         }
1454
1455                         rmask = 0x3 | (0x3 << 16);
1456                         temp |= (0x3 << 16);
1457                         reg += 0x4;
1458                         ret = regmap_update_bits(regmap, reg, rmask, temp);
1459
1460                         spin_unlock_irqrestore(&bank->slock, flags);
1461                         return ret;
1462                 case 18 ... 21:
1463                         /* setting fully enclosed in the second register */
1464                         reg += 4;
1465                         bit -= 16;
1466                         break;
1467                 default:
1468                         spin_unlock_irqrestore(&bank->slock, flags);
1469                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1470                                 bit, drv_type);
1471                         return -EINVAL;
1472                 }
1473                 break;
1474         case DRV_TYPE_IO_WIDE_LEVEL:
1475                 extra_value = ((strength -
1476                                 rockchip_perpin_drv_list[drv_type][ret])) >> 1;
1477                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1478
1479                 /*
1480                  * assume the drive strength of N channel and
1481                  * P channel are the same.
1482                  */
1483                 if (ctrl->drv_calc_extra_reg)
1484                         extra_drv_type = ctrl->drv_calc_extra_reg(bank, pin_num,
1485                                                                   &extra_regmap,
1486                                                                   &extra_reg,
1487                                                                   &extra_bit);
1488
1489                 /* enable the write to the equivalent lower bits */
1490                 data = ((1 << rmask_bits) - 1) << (extra_bit + 16);
1491                 rmask = data | (data >> 16);
1492                 data |= (extra_value << extra_bit);
1493
1494                 /* write drive strength of N channel */
1495                 if (regmap_update_bits(extra_regmap, extra_reg, rmask, data)) {
1496                         spin_unlock_irqrestore(&bank->slock, flags);
1497                         return -EINVAL;
1498                 }
1499
1500                 if (extra_drv_type == DRV_TYPE_EXTRA_SAME_OFFSET) {
1501                         extra_bit += 2;
1502                 } else if (extra_drv_type == DRV_TYPE_EXTRA_SAME_BITS) {
1503                         extra_reg += 0x4;
1504                 } else {
1505                         spin_unlock_irqrestore(&bank->slock, flags);
1506                         return -EINVAL;
1507                 }
1508
1509                 /* enable the write to the equivalent lower bits */
1510                 data = ((1 << rmask_bits) - 1) << (extra_bit + 16);
1511                 rmask = data | (data >> 16);
1512                 data |= (extra_value << extra_bit);
1513
1514                 /* write drive strength of P channel */
1515                 if (regmap_update_bits(extra_regmap, extra_reg, rmask, data)) {
1516                         spin_unlock_irqrestore(&bank->slock, flags);
1517                         return -EINVAL;
1518                 }
1519
1520                 break;
1521         case DRV_TYPE_IO_DEFAULT:
1522         case DRV_TYPE_IO_1V8_OR_3V0:
1523         case DRV_TYPE_IO_1V8_ONLY:
1524         case DRV_TYPE_IO_NARROW_LEVEL:
1525                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1526                 break;
1527         default:
1528                 spin_unlock_irqrestore(&bank->slock, flags);
1529                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1530                         drv_type);
1531                 return -EINVAL;
1532         }
1533
1534         /* enable the write to the equivalent lower bits */
1535         data = ((1 << rmask_bits) - 1) << (bit + 16);
1536         rmask = data | (data >> 16);
1537         data |= (ret << bit);
1538
1539         ret = regmap_update_bits(regmap, reg, rmask, data);
1540         spin_unlock_irqrestore(&bank->slock, flags);
1541
1542         return ret;
1543 }
1544
1545 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1546         {
1547                 PIN_CONFIG_BIAS_DISABLE,
1548                 PIN_CONFIG_BIAS_PULL_UP,
1549                 PIN_CONFIG_BIAS_PULL_DOWN,
1550                 PIN_CONFIG_BIAS_BUS_HOLD
1551         },
1552         {
1553                 PIN_CONFIG_BIAS_DISABLE,
1554                 PIN_CONFIG_BIAS_PULL_DOWN,
1555                 PIN_CONFIG_BIAS_DISABLE,
1556                 PIN_CONFIG_BIAS_PULL_UP
1557         },
1558 };
1559
1560 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1561 {
1562         struct rockchip_pinctrl *info = bank->drvdata;
1563         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1564         struct regmap *regmap;
1565         int reg, ret, pull_type;
1566         u8 bit;
1567         u32 data;
1568
1569         /* rk3066b does support any pulls */
1570         if (ctrl->type == RK3066B)
1571                 return PIN_CONFIG_BIAS_DISABLE;
1572
1573         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1574
1575         ret = regmap_read(regmap, reg, &data);
1576         if (ret)
1577                 return ret;
1578
1579         switch (ctrl->type) {
1580         case RK2928:
1581                 return !(data & BIT(bit))
1582                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1583                                 : PIN_CONFIG_BIAS_DISABLE;
1584         case RK3188:
1585         case RK3288:
1586         case RK3366:
1587         case RK3368:
1588         case RK3399:
1589                 pull_type = bank->pull_type[pin_num / 8];
1590                 data >>= bit;
1591                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1592
1593                 return rockchip_pull_list[pull_type][data];
1594         default:
1595                 dev_err(info->dev, "unsupported pinctrl type\n");
1596                 return -EINVAL;
1597         };
1598 }
1599
1600 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1601                                         int pin_num, int pull)
1602 {
1603         struct rockchip_pinctrl *info = bank->drvdata;
1604         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1605         struct regmap *regmap;
1606         int reg, ret, i, pull_type;
1607         unsigned long flags;
1608         u8 bit;
1609         u32 data, rmask;
1610
1611         dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
1612                  bank->bank_num, pin_num, pull);
1613
1614         /* rk3066b does support any pulls */
1615         if (ctrl->type == RK3066B)
1616                 return pull ? -EINVAL : 0;
1617
1618         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1619
1620         switch (ctrl->type) {
1621         case RK2928:
1622                 spin_lock_irqsave(&bank->slock, flags);
1623
1624                 data = BIT(bit + 16);
1625                 if (pull == PIN_CONFIG_BIAS_DISABLE)
1626                         data |= BIT(bit);
1627                 ret = regmap_write(regmap, reg, data);
1628
1629                 spin_unlock_irqrestore(&bank->slock, flags);
1630                 break;
1631         case RK3188:
1632         case RK3288:
1633         case RK3366:
1634         case RK3368:
1635         case RK3399:
1636                 pull_type = bank->pull_type[pin_num / 8];
1637                 ret = -EINVAL;
1638                 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
1639                         i++) {
1640                         if (rockchip_pull_list[pull_type][i] == pull) {
1641                                 ret = i;
1642                                 break;
1643                         }
1644                 }
1645
1646                 if (ret < 0) {
1647                         dev_err(info->dev, "unknown pull setting %d\n", pull);
1648                         return ret;
1649                 }
1650
1651                 spin_lock_irqsave(&bank->slock, flags);
1652
1653                 /* enable the write to the equivalent lower bits */
1654                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
1655                 rmask = data | (data >> 16);
1656                 data |= (ret << bit);
1657
1658                 ret = regmap_update_bits(regmap, reg, rmask, data);
1659
1660                 spin_unlock_irqrestore(&bank->slock, flags);
1661                 break;
1662         default:
1663                 dev_err(info->dev, "unsupported pinctrl type\n");
1664                 return -EINVAL;
1665         }
1666
1667         return ret;
1668 }
1669
1670 /*
1671  * Pinmux_ops handling
1672  */
1673
1674 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
1675 {
1676         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1677
1678         return info->nfunctions;
1679 }
1680
1681 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
1682                                           unsigned selector)
1683 {
1684         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1685
1686         return info->functions[selector].name;
1687 }
1688
1689 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
1690                                 unsigned selector, const char * const **groups,
1691                                 unsigned * const num_groups)
1692 {
1693         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1694
1695         *groups = info->functions[selector].groups;
1696         *num_groups = info->functions[selector].ngroups;
1697
1698         return 0;
1699 }
1700
1701 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
1702                             unsigned group)
1703 {
1704         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1705         const unsigned int *pins = info->groups[group].pins;
1706         const struct rockchip_pin_config *data = info->groups[group].data;
1707         struct rockchip_pin_bank *bank;
1708         int cnt, ret = 0;
1709
1710         dev_dbg(info->dev, "enable function %s group %s\n",
1711                 info->functions[selector].name, info->groups[group].name);
1712
1713         /*
1714          * for each pin in the pin group selected, program the correspoding pin
1715          * pin function number in the config register.
1716          */
1717         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
1718                 bank = pin_to_bank(info, pins[cnt]);
1719                 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
1720                                        data[cnt].func);
1721                 if (ret)
1722                         break;
1723         }
1724
1725         if (ret) {
1726                 /* revert the already done pin settings */
1727                 for (cnt--; cnt >= 0; cnt--)
1728                         rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
1729
1730                 return ret;
1731         }
1732
1733         return 0;
1734 }
1735
1736 /*
1737  * The calls to gpio_direction_output() and gpio_direction_input()
1738  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
1739  * function called from the gpiolib interface).
1740  */
1741 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
1742                                             int pin, bool input)
1743 {
1744         struct rockchip_pin_bank *bank;
1745         int ret;
1746         unsigned long flags;
1747         u32 data;
1748
1749         bank = gc_to_pin_bank(chip);
1750
1751         ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
1752         if (ret < 0)
1753                 return ret;
1754
1755         clk_enable(bank->clk);
1756         spin_lock_irqsave(&bank->slock, flags);
1757
1758         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1759         /* set bit to 1 for output, 0 for input */
1760         if (!input)
1761                 data |= BIT(pin);
1762         else
1763                 data &= ~BIT(pin);
1764         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1765
1766         spin_unlock_irqrestore(&bank->slock, flags);
1767         clk_disable(bank->clk);
1768
1769         return 0;
1770 }
1771
1772 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
1773                                               struct pinctrl_gpio_range *range,
1774                                               unsigned offset, bool input)
1775 {
1776         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1777         struct gpio_chip *chip;
1778         int pin;
1779
1780         chip = range->gc;
1781         pin = offset - chip->base;
1782         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
1783                  offset, range->name, pin, input ? "input" : "output");
1784
1785         return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
1786                                                 input);
1787 }
1788
1789 static const struct pinmux_ops rockchip_pmx_ops = {
1790         .get_functions_count    = rockchip_pmx_get_funcs_count,
1791         .get_function_name      = rockchip_pmx_get_func_name,
1792         .get_function_groups    = rockchip_pmx_get_groups,
1793         .set_mux                = rockchip_pmx_set,
1794         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
1795 };
1796
1797 /*
1798  * Pinconf_ops handling
1799  */
1800
1801 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
1802                                         enum pin_config_param pull)
1803 {
1804         switch (ctrl->type) {
1805         case RK2928:
1806                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
1807                                         pull == PIN_CONFIG_BIAS_DISABLE);
1808         case RK3066B:
1809                 return pull ? false : true;
1810         case RK3188:
1811         case RK3288:
1812         case RK3366:
1813         case RK3368:
1814         case RK3399:
1815                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
1816         }
1817
1818         return false;
1819 }
1820
1821 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
1822 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
1823
1824 /* set the pin config settings for a specified pin */
1825 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1826                                 unsigned long *configs, unsigned num_configs)
1827 {
1828         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1829         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1830         enum pin_config_param param;
1831         u16 arg;
1832         int i;
1833         int rc;
1834
1835         for (i = 0; i < num_configs; i++) {
1836                 param = pinconf_to_config_param(configs[i]);
1837                 arg = pinconf_to_config_argument(configs[i]);
1838
1839                 switch (param) {
1840                 case PIN_CONFIG_BIAS_DISABLE:
1841                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
1842                                 param);
1843                         if (rc)
1844                                 return rc;
1845                         break;
1846                 case PIN_CONFIG_BIAS_PULL_UP:
1847                 case PIN_CONFIG_BIAS_PULL_DOWN:
1848                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1849                 case PIN_CONFIG_BIAS_BUS_HOLD:
1850                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1851                                 return -ENOTSUPP;
1852
1853                         if (!arg)
1854                                 return -EINVAL;
1855
1856                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
1857                                 param);
1858                         if (rc)
1859                                 return rc;
1860                         break;
1861                 case PIN_CONFIG_OUTPUT:
1862                         rockchip_gpio_set(&bank->gpio_chip,
1863                                           pin - bank->pin_base, arg);
1864                         rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
1865                                           pin - bank->pin_base, false);
1866                         if (rc)
1867                                 return rc;
1868                         break;
1869                 case PIN_CONFIG_DRIVE_STRENGTH:
1870                         /* rk3288 is the first with per-pin drive-strength */
1871                         if (!info->ctrl->drv_calc_reg)
1872                                 return -ENOTSUPP;
1873
1874                         rc = rockchip_set_drive_perpin(bank,
1875                                                 pin - bank->pin_base, arg);
1876                         if (rc < 0)
1877                                 return rc;
1878                         break;
1879                 default:
1880                         return -ENOTSUPP;
1881                         break;
1882                 }
1883         } /* for each config */
1884
1885         return 0;
1886 }
1887
1888 /* get the pin config settings for a specified pin */
1889 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1890                                                         unsigned long *config)
1891 {
1892         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1893         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1894         enum pin_config_param param = pinconf_to_config_param(*config);
1895         u16 arg;
1896         int rc;
1897
1898         switch (param) {
1899         case PIN_CONFIG_BIAS_DISABLE:
1900                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1901                         return -EINVAL;
1902
1903                 arg = 0;
1904                 break;
1905         case PIN_CONFIG_BIAS_PULL_UP:
1906         case PIN_CONFIG_BIAS_PULL_DOWN:
1907         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1908         case PIN_CONFIG_BIAS_BUS_HOLD:
1909                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1910                         return -ENOTSUPP;
1911
1912                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1913                         return -EINVAL;
1914
1915                 arg = 1;
1916                 break;
1917         case PIN_CONFIG_OUTPUT:
1918                 rc = rockchip_get_mux(bank, pin - bank->pin_base);
1919                 if (rc != RK_FUNC_GPIO)
1920                         return -EINVAL;
1921
1922                 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
1923                 if (rc < 0)
1924                         return rc;
1925
1926                 arg = rc ? 1 : 0;
1927                 break;
1928         case PIN_CONFIG_DRIVE_STRENGTH:
1929                 /* rk3288 is the first with per-pin drive-strength */
1930                 if (!info->ctrl->drv_calc_reg)
1931                         return -ENOTSUPP;
1932
1933                 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
1934                 if (rc < 0)
1935                         return rc;
1936
1937                 arg = rc;
1938                 break;
1939         default:
1940                 return -ENOTSUPP;
1941                 break;
1942         }
1943
1944         *config = pinconf_to_config_packed(param, arg);
1945
1946         return 0;
1947 }
1948
1949 static const struct pinconf_ops rockchip_pinconf_ops = {
1950         .pin_config_get                 = rockchip_pinconf_get,
1951         .pin_config_set                 = rockchip_pinconf_set,
1952         .is_generic                     = true,
1953 };
1954
1955 static const struct of_device_id rockchip_bank_match[] = {
1956         { .compatible = "rockchip,gpio-bank" },
1957         { .compatible = "rockchip,rk3188-gpio-bank0" },
1958         {},
1959 };
1960
1961 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
1962                                                 struct device_node *np)
1963 {
1964         struct device_node *child;
1965
1966         for_each_child_of_node(np, child) {
1967                 if (of_match_node(rockchip_bank_match, child))
1968                         continue;
1969
1970                 info->nfunctions++;
1971                 info->ngroups += of_get_child_count(child);
1972         }
1973 }
1974
1975 static int rockchip_pinctrl_parse_groups(struct device_node *np,
1976                                               struct rockchip_pin_group *grp,
1977                                               struct rockchip_pinctrl *info,
1978                                               u32 index)
1979 {
1980         struct rockchip_pin_bank *bank;
1981         int size;
1982         const __be32 *list;
1983         int num;
1984         int i, j;
1985         int ret;
1986
1987         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1988
1989         /* Initialise group */
1990         grp->name = np->name;
1991
1992         /*
1993          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
1994          * do sanity check and calculate pins number
1995          */
1996         list = of_get_property(np, "rockchip,pins", &size);
1997         /* we do not check return since it's safe node passed down */
1998         size /= sizeof(*list);
1999         if (!size || size % 4) {
2000                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
2001                 return -EINVAL;
2002         }
2003
2004         grp->npins = size / 4;
2005
2006         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
2007                                                 GFP_KERNEL);
2008         grp->data = devm_kzalloc(info->dev, grp->npins *
2009                                           sizeof(struct rockchip_pin_config),
2010                                         GFP_KERNEL);
2011         if (!grp->pins || !grp->data)
2012                 return -ENOMEM;
2013
2014         for (i = 0, j = 0; i < size; i += 4, j++) {
2015                 const __be32 *phandle;
2016                 struct device_node *np_config;
2017
2018                 num = be32_to_cpu(*list++);
2019                 bank = bank_num_to_bank(info, num);
2020                 if (IS_ERR(bank))
2021                         return PTR_ERR(bank);
2022
2023                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2024                 grp->data[j].func = be32_to_cpu(*list++);
2025
2026                 phandle = list++;
2027                 if (!phandle)
2028                         return -EINVAL;
2029
2030                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
2031                 ret = pinconf_generic_parse_dt_config(np_config, NULL,
2032                                 &grp->data[j].configs, &grp->data[j].nconfigs);
2033                 if (ret)
2034                         return ret;
2035         }
2036
2037         return 0;
2038 }
2039
2040 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2041                                                 struct rockchip_pinctrl *info,
2042                                                 u32 index)
2043 {
2044         struct device_node *child;
2045         struct rockchip_pmx_func *func;
2046         struct rockchip_pin_group *grp;
2047         int ret;
2048         static u32 grp_index;
2049         u32 i = 0;
2050
2051         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
2052
2053         func = &info->functions[index];
2054
2055         /* Initialise function */
2056         func->name = np->name;
2057         func->ngroups = of_get_child_count(np);
2058         if (func->ngroups <= 0)
2059                 return 0;
2060
2061         func->groups = devm_kzalloc(info->dev,
2062                         func->ngroups * sizeof(char *), GFP_KERNEL);
2063         if (!func->groups)
2064                 return -ENOMEM;
2065
2066         for_each_child_of_node(np, child) {
2067                 func->groups[i] = child->name;
2068                 grp = &info->groups[grp_index++];
2069                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2070                 if (ret) {
2071                         of_node_put(child);
2072                         return ret;
2073                 }
2074         }
2075
2076         return 0;
2077 }
2078
2079 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2080                                               struct rockchip_pinctrl *info)
2081 {
2082         struct device *dev = &pdev->dev;
2083         struct device_node *np = dev->of_node;
2084         struct device_node *child;
2085         int ret;
2086         int i;
2087
2088         rockchip_pinctrl_child_count(info, np);
2089
2090         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2091         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2092
2093         info->functions = devm_kzalloc(dev, info->nfunctions *
2094                                               sizeof(struct rockchip_pmx_func),
2095                                               GFP_KERNEL);
2096         if (!info->functions) {
2097                 dev_err(dev, "failed to allocate memory for function list\n");
2098                 return -EINVAL;
2099         }
2100
2101         info->groups = devm_kzalloc(dev, info->ngroups *
2102                                             sizeof(struct rockchip_pin_group),
2103                                             GFP_KERNEL);
2104         if (!info->groups) {
2105                 dev_err(dev, "failed allocate memory for ping group list\n");
2106                 return -EINVAL;
2107         }
2108
2109         i = 0;
2110
2111         for_each_child_of_node(np, child) {
2112                 if (of_match_node(rockchip_bank_match, child))
2113                         continue;
2114
2115                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2116                 if (ret) {
2117                         dev_err(&pdev->dev, "failed to parse function\n");
2118                         of_node_put(child);
2119                         return ret;
2120                 }
2121         }
2122
2123         return 0;
2124 }
2125
2126 static int rockchip_pinctrl_register(struct platform_device *pdev,
2127                                         struct rockchip_pinctrl *info)
2128 {
2129         struct pinctrl_desc *ctrldesc = &info->pctl;
2130         struct pinctrl_pin_desc *pindesc, *pdesc;
2131         struct rockchip_pin_bank *pin_bank;
2132         int pin, bank, ret;
2133         int k;
2134
2135         ctrldesc->name = "rockchip-pinctrl";
2136         ctrldesc->owner = THIS_MODULE;
2137         ctrldesc->pctlops = &rockchip_pctrl_ops;
2138         ctrldesc->pmxops = &rockchip_pmx_ops;
2139         ctrldesc->confops = &rockchip_pinconf_ops;
2140
2141         pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
2142                         info->ctrl->nr_pins, GFP_KERNEL);
2143         if (!pindesc) {
2144                 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
2145                 return -ENOMEM;
2146         }
2147         ctrldesc->pins = pindesc;
2148         ctrldesc->npins = info->ctrl->nr_pins;
2149
2150         pdesc = pindesc;
2151         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
2152                 pin_bank = &info->ctrl->pin_banks[bank];
2153                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2154                         pdesc->number = k;
2155                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
2156                                                 pin_bank->name, pin);
2157                         pdesc++;
2158                 }
2159         }
2160
2161         ret = rockchip_pinctrl_parse_dt(pdev, info);
2162         if (ret)
2163                 return ret;
2164
2165         info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
2166         if (IS_ERR(info->pctl_dev)) {
2167                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
2168                 return PTR_ERR(info->pctl_dev);
2169         }
2170
2171         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
2172                 pin_bank = &info->ctrl->pin_banks[bank];
2173                 pin_bank->grange.name = pin_bank->name;
2174                 pin_bank->grange.id = bank;
2175                 pin_bank->grange.pin_base = pin_bank->pin_base;
2176                 pin_bank->grange.base = pin_bank->gpio_chip.base;
2177                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
2178                 pin_bank->grange.gc = &pin_bank->gpio_chip;
2179                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
2180         }
2181
2182         return 0;
2183 }
2184
2185 /*
2186  * GPIO handling
2187  */
2188
2189 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2190 {
2191         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2192         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
2193         unsigned long flags;
2194         u32 data;
2195
2196         clk_enable(bank->clk);
2197         spin_lock_irqsave(&bank->slock, flags);
2198
2199         data = readl(reg);
2200         data &= ~BIT(offset);
2201         if (value)
2202                 data |= BIT(offset);
2203         writel(data, reg);
2204
2205         spin_unlock_irqrestore(&bank->slock, flags);
2206         clk_disable(bank->clk);
2207 }
2208
2209 /*
2210  * Returns the level of the pin for input direction and setting of the DR
2211  * register for output gpios.
2212  */
2213 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
2214 {
2215         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2216         u32 data;
2217
2218         clk_enable(bank->clk);
2219         data = readl(bank->reg_base + GPIO_EXT_PORT);
2220         clk_disable(bank->clk);
2221         data >>= offset;
2222         data &= 1;
2223         return data;
2224 }
2225
2226 /*
2227  * gpiolib gpio_direction_input callback function. The setting of the pin
2228  * mux function as 'gpio input' will be handled by the pinctrl susbsystem
2229  * interface.
2230  */
2231 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2232 {
2233         return pinctrl_gpio_direction_input(gc->base + offset);
2234 }
2235
2236 /*
2237  * gpiolib gpio_direction_output callback function. The setting of the pin
2238  * mux function as 'gpio output' will be handled by the pinctrl susbsystem
2239  * interface.
2240  */
2241 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
2242                                           unsigned offset, int value)
2243 {
2244         rockchip_gpio_set(gc, offset, value);
2245         return pinctrl_gpio_direction_output(gc->base + offset);
2246 }
2247
2248 /*
2249  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
2250  * and a virtual IRQ, if not already present.
2251  */
2252 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2253 {
2254         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2255         unsigned int virq;
2256
2257         if (!bank->domain)
2258                 return -ENXIO;
2259
2260         virq = irq_create_mapping(bank->domain, offset);
2261
2262         return (virq) ? : -ENXIO;
2263 }
2264
2265 static const struct gpio_chip rockchip_gpiolib_chip = {
2266         .request = gpiochip_generic_request,
2267         .free = gpiochip_generic_free,
2268         .set = rockchip_gpio_set,
2269         .get = rockchip_gpio_get,
2270         .direction_input = rockchip_gpio_direction_input,
2271         .direction_output = rockchip_gpio_direction_output,
2272         .to_irq = rockchip_gpio_to_irq,
2273         .owner = THIS_MODULE,
2274 };
2275
2276 /*
2277  * Interrupt handling
2278  */
2279
2280 static void rockchip_irq_demux(struct irq_desc *desc)
2281 {
2282         struct irq_chip *chip = irq_desc_get_chip(desc);
2283         struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
2284         u32 pend;
2285
2286         dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
2287
2288         chained_irq_enter(chip, desc);
2289
2290         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2291
2292         while (pend) {
2293                 unsigned int irq, virq;
2294
2295                 irq = __ffs(pend);
2296                 pend &= ~BIT(irq);
2297                 virq = irq_linear_revmap(bank->domain, irq);
2298
2299                 if (!virq) {
2300                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2301                         continue;
2302                 }
2303
2304                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2305
2306                 /*
2307                  * Triggering IRQ on both rising and falling edge
2308                  * needs manual intervention.
2309                  */
2310                 if (bank->toggle_edge_mode & BIT(irq)) {
2311                         u32 data, data_old, polarity;
2312                         unsigned long flags;
2313
2314                         data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
2315                         do {
2316                                 spin_lock_irqsave(&bank->slock, flags);
2317
2318                                 polarity = readl_relaxed(bank->reg_base +
2319                                                          GPIO_INT_POLARITY);
2320                                 if (data & BIT(irq))
2321                                         polarity &= ~BIT(irq);
2322                                 else
2323                                         polarity |= BIT(irq);
2324                                 writel(polarity,
2325                                        bank->reg_base + GPIO_INT_POLARITY);
2326
2327                                 spin_unlock_irqrestore(&bank->slock, flags);
2328
2329                                 data_old = data;
2330                                 data = readl_relaxed(bank->reg_base +
2331                                                      GPIO_EXT_PORT);
2332                         } while ((data & BIT(irq)) != (data_old & BIT(irq)));
2333                 }
2334
2335                 generic_handle_irq(virq);
2336         }
2337
2338         chained_irq_exit(chip, desc);
2339 }
2340
2341 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
2342 {
2343         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2344         struct rockchip_pin_bank *bank = gc->private;
2345         u32 mask = BIT(d->hwirq);
2346         u32 polarity;
2347         u32 level;
2348         u32 data;
2349         unsigned long flags;
2350         int ret;
2351
2352         /* make sure the pin is configured as gpio input */
2353         ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
2354         if (ret < 0)
2355                 return ret;
2356
2357         clk_enable(bank->clk);
2358         spin_lock_irqsave(&bank->slock, flags);
2359
2360         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2361         data &= ~mask;
2362         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2363
2364         spin_unlock_irqrestore(&bank->slock, flags);
2365
2366         if (type & IRQ_TYPE_EDGE_BOTH)
2367                 irq_set_handler_locked(d, handle_edge_irq);
2368         else
2369                 irq_set_handler_locked(d, handle_level_irq);
2370
2371         spin_lock_irqsave(&bank->slock, flags);
2372         irq_gc_lock(gc);
2373
2374         level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
2375         polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
2376
2377         switch (type) {
2378         case IRQ_TYPE_EDGE_BOTH:
2379                 bank->toggle_edge_mode |= mask;
2380                 level |= mask;
2381
2382                 /*
2383                  * Determine gpio state. If 1 next interrupt should be falling
2384                  * otherwise rising.
2385                  */
2386                 data = readl(bank->reg_base + GPIO_EXT_PORT);
2387                 if (data & mask)
2388                         polarity &= ~mask;
2389                 else
2390                         polarity |= mask;
2391                 break;
2392         case IRQ_TYPE_EDGE_RISING:
2393                 bank->toggle_edge_mode &= ~mask;
2394                 level |= mask;
2395                 polarity |= mask;
2396                 break;
2397         case IRQ_TYPE_EDGE_FALLING:
2398                 bank->toggle_edge_mode &= ~mask;
2399                 level |= mask;
2400                 polarity &= ~mask;
2401                 break;
2402         case IRQ_TYPE_LEVEL_HIGH:
2403                 bank->toggle_edge_mode &= ~mask;
2404                 level &= ~mask;
2405                 polarity |= mask;
2406                 break;
2407         case IRQ_TYPE_LEVEL_LOW:
2408                 bank->toggle_edge_mode &= ~mask;
2409                 level &= ~mask;
2410                 polarity &= ~mask;
2411                 break;
2412         default:
2413                 irq_gc_unlock(gc);
2414                 spin_unlock_irqrestore(&bank->slock, flags);
2415                 clk_disable(bank->clk);
2416                 return -EINVAL;
2417         }
2418
2419         writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
2420         writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
2421
2422         irq_gc_unlock(gc);
2423         spin_unlock_irqrestore(&bank->slock, flags);
2424         clk_disable(bank->clk);
2425
2426         return 0;
2427 }
2428
2429 static void rockchip_irq_suspend(struct irq_data *d)
2430 {
2431         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2432         struct rockchip_pin_bank *bank = gc->private;
2433
2434         clk_enable(bank->clk);
2435         bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
2436         irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
2437         clk_disable(bank->clk);
2438 }
2439
2440 static void rockchip_irq_resume(struct irq_data *d)
2441 {
2442         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2443         struct rockchip_pin_bank *bank = gc->private;
2444
2445         clk_enable(bank->clk);
2446         irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
2447         clk_disable(bank->clk);
2448 }
2449
2450 static void rockchip_irq_gc_mask_clr_bit(struct irq_data *d)
2451 {
2452         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2453         struct rockchip_pin_bank *bank = gc->private;
2454
2455         clk_enable(bank->clk);
2456         irq_gc_mask_clr_bit(d);
2457 }
2458
2459 void rockchip_irq_gc_mask_set_bit(struct irq_data *d)
2460 {
2461         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2462         struct rockchip_pin_bank *bank = gc->private;
2463
2464         irq_gc_mask_set_bit(d);
2465         clk_disable(bank->clk);
2466 }
2467
2468 static int rockchip_interrupts_register(struct platform_device *pdev,
2469                                                 struct rockchip_pinctrl *info)
2470 {
2471         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2472         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2473         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
2474         struct irq_chip_generic *gc;
2475         int ret;
2476         int i, j;
2477
2478         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2479                 if (!bank->valid) {
2480                         dev_warn(&pdev->dev, "bank %s is not valid\n",
2481                                  bank->name);
2482                         continue;
2483                 }
2484
2485                 ret = clk_enable(bank->clk);
2486                 if (ret) {
2487                         dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
2488                                 bank->name);
2489                         continue;
2490                 }
2491
2492                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
2493                                                 &irq_generic_chip_ops, NULL);
2494                 if (!bank->domain) {
2495                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
2496                                  bank->name);
2497                         clk_disable(bank->clk);
2498                         continue;
2499                 }
2500
2501                 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
2502                                          bank->name, handle_level_irq,
2503                                          clr, 0, IRQ_GC_INIT_MASK_CACHE);
2504                 if (ret) {
2505                         dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
2506                                 bank->name);
2507                         irq_domain_remove(bank->domain);
2508                         clk_disable(bank->clk);
2509                         continue;
2510                 }
2511
2512                 /*
2513                  * Linux assumes that all interrupts start out disabled/masked.
2514                  * Our driver only uses the concept of masked and always keeps
2515                  * things enabled, so for us that's all masked and all enabled.
2516                  */
2517                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
2518                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
2519
2520                 gc = irq_get_domain_generic_chip(bank->domain, 0);
2521                 gc->reg_base = bank->reg_base;
2522                 gc->private = bank;
2523                 gc->chip_types[0].regs.mask = GPIO_INTMASK;
2524                 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
2525                 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
2526                 gc->chip_types[0].chip.irq_mask = rockchip_irq_gc_mask_set_bit;
2527                 gc->chip_types[0].chip.irq_unmask =
2528                                                   rockchip_irq_gc_mask_clr_bit;
2529                 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
2530                 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
2531                 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
2532                 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
2533                 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
2534
2535                 irq_set_chained_handler_and_data(bank->irq,
2536                                                  rockchip_irq_demux, bank);
2537
2538                 /* map the gpio irqs here, when the clock is still running */
2539                 for (j = 0 ; j < 32 ; j++)
2540                         irq_create_mapping(bank->domain, j);
2541
2542                 clk_disable(bank->clk);
2543         }
2544
2545         return 0;
2546 }
2547
2548 static int rockchip_gpiolib_register(struct platform_device *pdev,
2549                                                 struct rockchip_pinctrl *info)
2550 {
2551         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2552         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2553         struct gpio_chip *gc;
2554         int ret;
2555         int i;
2556
2557         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2558                 if (!bank->valid) {
2559                         dev_warn(&pdev->dev, "bank %s is not valid\n",
2560                                  bank->name);
2561                         continue;
2562                 }
2563
2564                 bank->gpio_chip = rockchip_gpiolib_chip;
2565
2566                 gc = &bank->gpio_chip;
2567                 gc->base = bank->pin_base;
2568                 gc->ngpio = bank->nr_pins;
2569                 gc->dev = &pdev->dev;
2570                 gc->of_node = bank->of_node;
2571                 gc->label = bank->name;
2572
2573                 ret = gpiochip_add(gc);
2574                 if (ret) {
2575                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
2576                                                         gc->label, ret);
2577                         goto fail;
2578                 }
2579         }
2580
2581         rockchip_interrupts_register(pdev, info);
2582
2583         return 0;
2584
2585 fail:
2586         for (--i, --bank; i >= 0; --i, --bank) {
2587                 if (!bank->valid)
2588                         continue;
2589                 gpiochip_remove(&bank->gpio_chip);
2590         }
2591         return ret;
2592 }
2593
2594 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
2595                                                 struct rockchip_pinctrl *info)
2596 {
2597         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2598         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2599         int i;
2600
2601         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2602                 if (!bank->valid)
2603                         continue;
2604                 gpiochip_remove(&bank->gpio_chip);
2605         }
2606
2607         return 0;
2608 }
2609
2610 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
2611                                   struct rockchip_pinctrl *info)
2612 {
2613         struct resource res;
2614         void __iomem *base;
2615
2616         if (of_address_to_resource(bank->of_node, 0, &res)) {
2617                 dev_err(info->dev, "cannot find IO resource for bank\n");
2618                 return -ENOENT;
2619         }
2620
2621         bank->reg_base = devm_ioremap_resource(info->dev, &res);
2622         if (IS_ERR(bank->reg_base))
2623                 return PTR_ERR(bank->reg_base);
2624
2625         /*
2626          * special case, where parts of the pull setting-registers are
2627          * part of the PMU register space
2628          */
2629         if (of_device_is_compatible(bank->of_node,
2630                                     "rockchip,rk3188-gpio-bank0")) {
2631                 struct device_node *node;
2632
2633                 node = of_parse_phandle(bank->of_node->parent,
2634                                         "rockchip,pmu", 0);
2635                 if (!node) {
2636                         if (of_address_to_resource(bank->of_node, 1, &res)) {
2637                                 dev_err(info->dev, "cannot find IO resource for bank\n");
2638                                 return -ENOENT;
2639                         }
2640
2641                         base = devm_ioremap_resource(info->dev, &res);
2642                         if (IS_ERR(base))
2643                                 return PTR_ERR(base);
2644                         rockchip_regmap_config.max_register =
2645                                                     resource_size(&res) - 4;
2646                         rockchip_regmap_config.name =
2647                                             "rockchip,rk3188-gpio-bank0-pull";
2648                         bank->regmap_pull = devm_regmap_init_mmio(info->dev,
2649                                                     base,
2650                                                     &rockchip_regmap_config);
2651                 }
2652         }
2653
2654         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
2655
2656         bank->clk = of_clk_get(bank->of_node, 0);
2657         if (IS_ERR(bank->clk))
2658                 return PTR_ERR(bank->clk);
2659
2660         return clk_prepare(bank->clk);
2661 }
2662
2663 static const struct of_device_id rockchip_pinctrl_dt_match[];
2664
2665 /* retrieve the soc specific data */
2666 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
2667                                                 struct rockchip_pinctrl *d,
2668                                                 struct platform_device *pdev)
2669 {
2670         const struct of_device_id *match;
2671         struct device_node *node = pdev->dev.of_node;
2672         struct device_node *np;
2673         struct rockchip_pin_ctrl *ctrl;
2674         struct rockchip_pin_bank *bank;
2675         int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
2676
2677         match = of_match_node(rockchip_pinctrl_dt_match, node);
2678         ctrl = (struct rockchip_pin_ctrl *)match->data;
2679
2680         for_each_child_of_node(node, np) {
2681                 if (!of_find_property(np, "gpio-controller", NULL))
2682                         continue;
2683
2684                 bank = ctrl->pin_banks;
2685                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2686                         if (!strcmp(bank->name, np->name)) {
2687                                 bank->of_node = np;
2688
2689                                 if (!rockchip_get_bank_data(bank, d))
2690                                         bank->valid = true;
2691
2692                                 break;
2693                         }
2694                 }
2695         }
2696
2697         grf_offs = ctrl->grf_mux_offset;
2698         pmu_offs = ctrl->pmu_mux_offset;
2699         drv_pmu_offs = ctrl->pmu_drv_offset;
2700         drv_grf_offs = ctrl->grf_drv_offset;
2701         bank = ctrl->pin_banks;
2702         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2703                 int bank_pins = 0;
2704
2705                 spin_lock_init(&bank->slock);
2706                 bank->drvdata = d;
2707                 bank->pin_base = ctrl->nr_pins;
2708                 ctrl->nr_pins += bank->nr_pins;
2709
2710                 /* calculate iomux and drv offsets */
2711                 for (j = 0; j < 4; j++) {
2712                         struct rockchip_iomux *iom = &bank->iomux[j];
2713                         struct rockchip_drv *drv = &bank->drv[j];
2714                         int inc;
2715
2716                         if (bank_pins >= bank->nr_pins)
2717                                 break;
2718
2719                         /* preset iomux offset value, set new start value */
2720                         if (iom->offset >= 0) {
2721                                 if (iom->type & IOMUX_SOURCE_PMU)
2722                                         pmu_offs = iom->offset;
2723                                 else
2724                                         grf_offs = iom->offset;
2725                         } else { /* set current iomux offset */
2726                                 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2727                                                         pmu_offs : grf_offs;
2728                         }
2729
2730                         /* preset drv offset value, set new start value */
2731                         if (drv->offset >= 0) {
2732                                 if (iom->type & IOMUX_SOURCE_PMU)
2733                                         drv_pmu_offs = drv->offset;
2734                                 else
2735                                         drv_grf_offs = drv->offset;
2736                         } else { /* set current drv offset */
2737                                 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2738                                                 drv_pmu_offs : drv_grf_offs;
2739                         }
2740
2741                         dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
2742                                 i, j, iom->offset, drv->offset);
2743
2744                         /*
2745                          * Increase offset according to iomux width.
2746                          * 4bit iomux'es are spread over two registers.
2747                          */
2748                         inc = (iom->type & (IOMUX_WIDTH_4BIT |
2749                                             IOMUX_WIDTH_3BIT)) ? 8 : 4;
2750                         if (iom->type & IOMUX_SOURCE_PMU)
2751                                 pmu_offs += inc;
2752                         else
2753                                 grf_offs += inc;
2754
2755                         /*
2756                          * Increase offset according to drv width.
2757                          * 3bit drive-strenth'es are spread over two registers.
2758                          */
2759                         if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2760                             (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
2761                                 inc = 8;
2762                         else
2763                                 inc = 4;
2764
2765                         if (iom->type & IOMUX_SOURCE_PMU)
2766                                 drv_pmu_offs += inc;
2767                         else
2768                                 drv_grf_offs += inc;
2769
2770                         bank_pins += 8;
2771                 }
2772         }
2773
2774         return ctrl;
2775 }
2776
2777 #define RK3288_GRF_GPIO6C_IOMUX         0x64
2778 #define GPIO6C6_SEL_WRITE_ENABLE        BIT(28)
2779
2780 static u32 rk3288_grf_gpio6c_iomux;
2781
2782 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
2783 {
2784         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2785         int ret = pinctrl_force_sleep(info->pctl_dev);
2786
2787         if (ret)
2788                 return ret;
2789
2790         /*
2791          * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
2792          * the setting here, and restore it at resume.
2793          */
2794         if (info->ctrl->type == RK3288) {
2795                 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2796                                   &rk3288_grf_gpio6c_iomux);
2797                 if (ret) {
2798                         pinctrl_force_default(info->pctl_dev);
2799                         return ret;
2800                 }
2801         }
2802
2803         return 0;
2804 }
2805
2806 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
2807 {
2808         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2809         int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2810                                rk3288_grf_gpio6c_iomux |
2811                                GPIO6C6_SEL_WRITE_ENABLE);
2812
2813         if (ret)
2814                 return ret;
2815
2816         return pinctrl_force_default(info->pctl_dev);
2817 }
2818
2819 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
2820                          rockchip_pinctrl_resume);
2821
2822 static int rockchip_pinctrl_probe(struct platform_device *pdev)
2823 {
2824         struct rockchip_pinctrl *info;
2825         struct device *dev = &pdev->dev;
2826         struct rockchip_pin_ctrl *ctrl;
2827         struct device_node *np = pdev->dev.of_node, *node;
2828         struct resource *res;
2829         void __iomem *base;
2830         int ret;
2831
2832         if (!dev->of_node) {
2833                 dev_err(dev, "device tree node not found\n");
2834                 return -ENODEV;
2835         }
2836
2837         info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
2838         if (!info)
2839                 return -ENOMEM;
2840
2841         info->dev = dev;
2842
2843         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2844         if (!ctrl) {
2845                 dev_err(dev, "driver data not available\n");
2846                 return -EINVAL;
2847         }
2848         info->ctrl = ctrl;
2849
2850         node = of_parse_phandle(np, "rockchip,grf", 0);
2851         if (node) {
2852                 info->regmap_base = syscon_node_to_regmap(node);
2853                 if (IS_ERR(info->regmap_base))
2854                         return PTR_ERR(info->regmap_base);
2855         } else {
2856                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2857                 base = devm_ioremap_resource(&pdev->dev, res);
2858                 if (IS_ERR(base))
2859                         return PTR_ERR(base);
2860
2861                 rockchip_regmap_config.max_register = resource_size(res) - 4;
2862                 rockchip_regmap_config.name = "rockchip,pinctrl";
2863                 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
2864                                                     &rockchip_regmap_config);
2865
2866                 /* to check for the old dt-bindings */
2867                 info->reg_size = resource_size(res);
2868
2869                 /* Honor the old binding, with pull registers as 2nd resource */
2870                 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
2871                         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2872                         base = devm_ioremap_resource(&pdev->dev, res);
2873                         if (IS_ERR(base))
2874                                 return PTR_ERR(base);
2875
2876                         rockchip_regmap_config.max_register =
2877                                                         resource_size(res) - 4;
2878                         rockchip_regmap_config.name = "rockchip,pinctrl-pull";
2879                         info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
2880                                                     base,
2881                                                     &rockchip_regmap_config);
2882                 }
2883         }
2884
2885         /* try to find the optional reference to the pmu syscon */
2886         node = of_parse_phandle(np, "rockchip,pmu", 0);
2887         if (node) {
2888                 info->regmap_pmu = syscon_node_to_regmap(node);
2889                 if (IS_ERR(info->regmap_pmu))
2890                         return PTR_ERR(info->regmap_pmu);
2891         }
2892
2893         ret = rockchip_gpiolib_register(pdev, info);
2894         if (ret)
2895                 return ret;
2896
2897         ret = rockchip_pinctrl_register(pdev, info);
2898         if (ret) {
2899                 rockchip_gpiolib_unregister(pdev, info);
2900                 return ret;
2901         }
2902
2903         platform_set_drvdata(pdev, info);
2904
2905         return 0;
2906 }
2907
2908 static struct rockchip_pin_bank rk2928_pin_banks[] = {
2909         PIN_BANK(0, 32, "gpio0"),
2910         PIN_BANK(1, 32, "gpio1"),
2911         PIN_BANK(2, 32, "gpio2"),
2912         PIN_BANK(3, 32, "gpio3"),
2913 };
2914
2915 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2916                 .pin_banks              = rk2928_pin_banks,
2917                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
2918                 .label                  = "RK2928-GPIO",
2919                 .type                   = RK2928,
2920                 .grf_mux_offset         = 0xa8,
2921                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2922 };
2923
2924 static struct rockchip_pin_bank rk3036_pin_banks[] = {
2925         PIN_BANK(0, 32, "gpio0"),
2926         PIN_BANK(1, 32, "gpio1"),
2927         PIN_BANK(2, 32, "gpio2"),
2928 };
2929
2930 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
2931                 .pin_banks              = rk3036_pin_banks,
2932                 .nr_banks               = ARRAY_SIZE(rk3036_pin_banks),
2933                 .label                  = "RK3036-GPIO",
2934                 .type                   = RK2928,
2935                 .grf_mux_offset         = 0xa8,
2936                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2937 };
2938
2939 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
2940         PIN_BANK(0, 32, "gpio0"),
2941         PIN_BANK(1, 32, "gpio1"),
2942         PIN_BANK(2, 32, "gpio2"),
2943         PIN_BANK(3, 32, "gpio3"),
2944         PIN_BANK(4, 32, "gpio4"),
2945         PIN_BANK(6, 16, "gpio6"),
2946 };
2947
2948 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
2949                 .pin_banks              = rk3066a_pin_banks,
2950                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
2951                 .label                  = "RK3066a-GPIO",
2952                 .type                   = RK2928,
2953                 .grf_mux_offset         = 0xa8,
2954                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2955 };
2956
2957 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
2958         PIN_BANK(0, 32, "gpio0"),
2959         PIN_BANK(1, 32, "gpio1"),
2960         PIN_BANK(2, 32, "gpio2"),
2961         PIN_BANK(3, 32, "gpio3"),
2962 };
2963
2964 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2965                 .pin_banks      = rk3066b_pin_banks,
2966                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
2967                 .label          = "RK3066b-GPIO",
2968                 .type           = RK3066B,
2969                 .grf_mux_offset = 0x60,
2970 };
2971
2972 static struct rockchip_pin_bank rk3188_pin_banks[] = {
2973         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
2974         PIN_BANK(1, 32, "gpio1"),
2975         PIN_BANK(2, 32, "gpio2"),
2976         PIN_BANK(3, 32, "gpio3"),
2977 };
2978
2979 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
2980                 .pin_banks              = rk3188_pin_banks,
2981                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
2982                 .label                  = "RK3188-GPIO",
2983                 .type                   = RK3188,
2984                 .grf_mux_offset         = 0x60,
2985                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
2986 };
2987
2988 static struct rockchip_pin_bank rk3228_pin_banks[] = {
2989         PIN_BANK(0, 32, "gpio0"),
2990         PIN_BANK(1, 32, "gpio1"),
2991         PIN_BANK(2, 32, "gpio2"),
2992         PIN_BANK(3, 32, "gpio3"),
2993 };
2994
2995 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
2996                 .pin_banks              = rk3228_pin_banks,
2997                 .nr_banks               = ARRAY_SIZE(rk3228_pin_banks),
2998                 .label                  = "RK3228-GPIO",
2999                 .type                   = RK3288,
3000                 .grf_mux_offset         = 0x0,
3001                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
3002                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
3003 };
3004
3005 static struct rockchip_pin_bank rk3288_pin_banks[] = {
3006         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
3007                                              IOMUX_SOURCE_PMU,
3008                                              IOMUX_SOURCE_PMU,
3009                                              IOMUX_UNROUTED
3010                             ),
3011         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
3012                                              IOMUX_UNROUTED,
3013                                              IOMUX_UNROUTED,
3014                                              0
3015                             ),
3016         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3017         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3018         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3019                                              IOMUX_WIDTH_4BIT,
3020                                              0,
3021                                              0
3022                             ),
3023         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
3024                                              0,
3025                                              0,
3026                                              IOMUX_UNROUTED
3027                             ),
3028         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3029         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3030                                              0,
3031                                              IOMUX_WIDTH_4BIT,
3032                                              IOMUX_UNROUTED
3033                             ),
3034         PIN_BANK(8, 16, "gpio8"),
3035 };
3036
3037 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3038                 .pin_banks              = rk3288_pin_banks,
3039                 .nr_banks               = ARRAY_SIZE(rk3288_pin_banks),
3040                 .label                  = "RK3288-GPIO",
3041                 .type                   = RK3288,
3042                 .grf_mux_offset         = 0x0,
3043                 .pmu_mux_offset         = 0x84,
3044                 .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
3045                 .drv_calc_reg           = rk3288_calc_drv_reg_and_bit,
3046 };
3047
3048 static struct rockchip_pin_bank rk3328_pin_banks[] = {
3049         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3050         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3051         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3052                              IOMUX_WIDTH_3BIT | IOMUX_RECALCED_FLAG,
3053                              IOMUX_WIDTH_3BIT | IOMUX_RECALCED_FLAG,
3054                              0),
3055         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3056                              IOMUX_WIDTH_3BIT,
3057                              IOMUX_WIDTH_3BIT | IOMUX_RECALCED_FLAG,
3058                              0,
3059                              0),
3060 };
3061
3062 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3063                 .pin_banks              = rk3328_pin_banks,
3064                 .nr_banks               = ARRAY_SIZE(rk3328_pin_banks),
3065                 .label                  = "RK3328-GPIO",
3066                 .type                   = RK3288,
3067                 .grf_mux_offset         = 0x0,
3068                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
3069                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
3070                 .iomux_recalc           = rk3328_recalc_mux,
3071 };
3072
3073 static struct rockchip_pin_bank rk3366_pin_banks[] = {
3074         PIN_BANK_IOMUX_DRV_FLAGS(0, 32, "gpio0",
3075                                  IOMUX_SOURCE_PMU,
3076                                  IOMUX_SOURCE_PMU,
3077                                  IOMUX_SOURCE_PMU,
3078                                  IOMUX_SOURCE_PMU,
3079                                  DRV_TYPE_IO_NARROW_LEVEL,
3080                                  DRV_TYPE_IO_NARROW_LEVEL,
3081                                  DRV_TYPE_IO_NARROW_LEVEL,
3082                                  DRV_TYPE_IO_NARROW_LEVEL
3083                                  ),
3084         PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(1, 32, "gpio1",
3085                                               IOMUX_SOURCE_PMU,
3086                                               IOMUX_SOURCE_PMU,
3087                                               IOMUX_SOURCE_PMU,
3088                                               IOMUX_SOURCE_PMU,
3089                                               0x30,
3090                                               0x34,
3091                                               0x38,
3092                                               0x3c,
3093                                               DRV_TYPE_IO_NARROW_LEVEL,
3094                                               DRV_TYPE_IO_NARROW_LEVEL,
3095                                               DRV_TYPE_IO_NARROW_LEVEL,
3096                                               DRV_TYPE_IO_NARROW_LEVEL
3097                                               ),
3098         PIN_BANK_DRV_FLAGS(2, 32, "gpio2",
3099                            DRV_TYPE_IO_WIDE_LEVEL,
3100                            DRV_TYPE_IO_NARROW_LEVEL,
3101                            DRV_TYPE_IO_WIDE_LEVEL,
3102                            DRV_TYPE_IO_NARROW_LEVEL
3103                            ),
3104         PIN_BANK_DRV_FLAGS(3, 32, "gpio3",
3105                            DRV_TYPE_IO_NARROW_LEVEL,
3106                            DRV_TYPE_IO_NARROW_LEVEL,
3107                            DRV_TYPE_IO_NARROW_LEVEL,
3108                            DRV_TYPE_IO_NARROW_LEVEL
3109                            ),
3110         PIN_BANK_DRV_FLAGS(4, 32, "gpio4",
3111                            DRV_TYPE_IO_NARROW_LEVEL,
3112                            DRV_TYPE_IO_NARROW_LEVEL,
3113                            DRV_TYPE_IO_NARROW_LEVEL,
3114                            DRV_TYPE_IO_NARROW_LEVEL
3115                            ),
3116         PIN_BANK_DRV_FLAGS(5, 32, "gpio5",
3117                            DRV_TYPE_IO_NARROW_LEVEL,
3118                            DRV_TYPE_IO_NARROW_LEVEL,
3119                            DRV_TYPE_IO_NARROW_LEVEL,
3120                            DRV_TYPE_IO_NARROW_LEVEL
3121                            ),
3122 };
3123
3124 static struct rockchip_pin_ctrl rk3366_pin_ctrl = {
3125                 .pin_banks              = rk3366_pin_banks,
3126                 .nr_banks               = ARRAY_SIZE(rk3366_pin_banks),
3127                 .label                  = "RK3366-GPIO",
3128                 .type                   = RK3366,
3129                 .grf_mux_offset         = 0x10,
3130                 .pmu_mux_offset         = 0x0,
3131                 .pull_calc_reg          = rk3366_calc_pull_reg_and_bit,
3132                 .drv_calc_reg           = rk3366_calc_drv_reg_and_bit,
3133                 .drv_calc_extra_reg     = rk3366_calc_drv_extra_reg_and_bit,
3134 };
3135
3136 static struct rockchip_pin_bank rk3368_pin_banks[] = {
3137         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3138                                              IOMUX_SOURCE_PMU,
3139                                              IOMUX_SOURCE_PMU,
3140                                              IOMUX_SOURCE_PMU
3141                             ),
3142         PIN_BANK(1, 32, "gpio1"),
3143         PIN_BANK(2, 32, "gpio2"),
3144         PIN_BANK(3, 32, "gpio3"),
3145 };
3146
3147 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3148                 .pin_banks              = rk3368_pin_banks,
3149                 .nr_banks               = ARRAY_SIZE(rk3368_pin_banks),
3150                 .label                  = "RK3368-GPIO",
3151                 .type                   = RK3368,
3152                 .grf_mux_offset         = 0x0,
3153                 .pmu_mux_offset         = 0x0,
3154                 .pull_calc_reg          = rk3368_calc_pull_reg_and_bit,
3155                 .drv_calc_reg           = rk3368_calc_drv_reg_and_bit,
3156 };
3157
3158 static struct rockchip_pin_bank rk3399_pin_banks[] = {
3159         PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3160                                                          IOMUX_SOURCE_PMU,
3161                                                          IOMUX_SOURCE_PMU,
3162                                                          IOMUX_SOURCE_PMU,
3163                                                          IOMUX_SOURCE_PMU,
3164                                                          DRV_TYPE_IO_1V8_ONLY,
3165                                                          DRV_TYPE_IO_1V8_ONLY,
3166                                                          DRV_TYPE_IO_DEFAULT,
3167                                                          DRV_TYPE_IO_DEFAULT,
3168                                                          0x0,
3169                                                          0x8,
3170                                                          -1,
3171                                                          -1,
3172                                                          PULL_TYPE_IO_1V8_ONLY,
3173                                                          PULL_TYPE_IO_1V8_ONLY,
3174                                                          PULL_TYPE_IO_DEFAULT,
3175                                                          PULL_TYPE_IO_DEFAULT),
3176         PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3177                                               IOMUX_SOURCE_PMU,
3178                                               IOMUX_SOURCE_PMU,
3179                                               IOMUX_SOURCE_PMU,
3180                                               DRV_TYPE_IO_1V8_OR_3V0,
3181                                               DRV_TYPE_IO_1V8_OR_3V0,
3182                                               DRV_TYPE_IO_1V8_OR_3V0,
3183                                               DRV_TYPE_IO_1V8_OR_3V0,
3184                                               0x20,
3185                                               0x28,
3186                                               0x30,
3187                                               0x38
3188                                               ),
3189         PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3190                                       DRV_TYPE_IO_1V8_OR_3V0,
3191                                       DRV_TYPE_IO_1V8_ONLY,
3192                                       DRV_TYPE_IO_1V8_ONLY,
3193                                       PULL_TYPE_IO_DEFAULT,
3194                                       PULL_TYPE_IO_DEFAULT,
3195                                       PULL_TYPE_IO_1V8_ONLY,
3196                                       PULL_TYPE_IO_1V8_ONLY
3197                                       ),
3198         PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3199                            DRV_TYPE_IO_3V3_ONLY,
3200                            DRV_TYPE_IO_3V3_ONLY,
3201                            DRV_TYPE_IO_1V8_OR_3V0
3202                            ),
3203         PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3204                            DRV_TYPE_IO_1V8_3V0_AUTO,
3205                            DRV_TYPE_IO_1V8_OR_3V0,
3206                            DRV_TYPE_IO_1V8_OR_3V0
3207                            ),
3208 };
3209
3210 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3211                 .pin_banks              = rk3399_pin_banks,
3212                 .nr_banks               = ARRAY_SIZE(rk3399_pin_banks),
3213                 .label                  = "RK3399-GPIO",
3214                 .type                   = RK3399,
3215                 .grf_mux_offset         = 0xe000,
3216                 .pmu_mux_offset         = 0x0,
3217                 .grf_drv_offset         = 0xe100,
3218                 .pmu_drv_offset         = 0x80,
3219                 .pull_calc_reg          = rk3399_calc_pull_reg_and_bit,
3220                 .drv_calc_reg           = rk3399_calc_drv_reg_and_bit,
3221 };
3222
3223 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3224         { .compatible = "rockchip,rk2928-pinctrl",
3225                 .data = (void *)&rk2928_pin_ctrl },
3226         { .compatible = "rockchip,rk3036-pinctrl",
3227                 .data = (void *)&rk3036_pin_ctrl },
3228         { .compatible = "rockchip,rk3066a-pinctrl",
3229                 .data = (void *)&rk3066a_pin_ctrl },
3230         { .compatible = "rockchip,rk3066b-pinctrl",
3231                 .data = (void *)&rk3066b_pin_ctrl },
3232         { .compatible = "rockchip,rk3188-pinctrl",
3233                 .data = (void *)&rk3188_pin_ctrl },
3234         { .compatible = "rockchip,rk3228-pinctrl",
3235                 .data = (void *)&rk3228_pin_ctrl },
3236         { .compatible = "rockchip,rk3288-pinctrl",
3237                 .data = (void *)&rk3288_pin_ctrl },
3238         { .compatible = "rockchip,rk3328-pinctrl",
3239                 .data = (void *)&rk3328_pin_ctrl },
3240         { .compatible = "rockchip,rk3366-pinctrl",
3241                 .data = (void *)&rk3366_pin_ctrl },
3242         { .compatible = "rockchip,rk3368-pinctrl",
3243                 .data = (void *)&rk3368_pin_ctrl },
3244         { .compatible = "rockchip,rk3399-pinctrl",
3245                 .data = (void *)&rk3399_pin_ctrl },
3246         {},
3247 };
3248 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
3249
3250 static struct platform_driver rockchip_pinctrl_driver = {
3251         .probe          = rockchip_pinctrl_probe,
3252         .driver = {
3253                 .name   = "rockchip-pinctrl",
3254                 .pm = &rockchip_pinctrl_dev_pm_ops,
3255                 .of_match_table = rockchip_pinctrl_dt_match,
3256         },
3257 };
3258
3259 static int __init rockchip_pinctrl_drv_register(void)
3260 {
3261         return platform_driver_register(&rockchip_pinctrl_driver);
3262 }
3263 postcore_initcall(rockchip_pinctrl_drv_register);
3264
3265 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
3266 MODULE_DESCRIPTION("Rockchip pinctrl driver");
3267 MODULE_LICENSE("GPL v2");