drivers/pinctrl/pinctrl-rockchip.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2013 MundoReader S.L.
   5  * Author: Heiko Stuebner <heiko@sntech.de>
   6  *
   7  * With some ideas taken from pinctrl-samsung:
   8  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9  *              http://www.samsung.com
  10  * Copyright (c) 2012 Linaro Ltd
  11  *              http://www.linaro.org
  12  *
  13  * and pinctrl-at91:
  14  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as published
  18  * by the Free Software Foundation.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/bitops.h>
  30 #include <linux/gpio.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/pinctrl/machine.h>
  34 #include <linux/pinctrl/pinconf.h>
  35 #include <linux/pinctrl/pinctrl.h>
  36 #include <linux/pinctrl/pinmux.h>
  37 #include <linux/pinctrl/pinconf-generic.h>
  38 #include <linux/irqchip/chained_irq.h>
  39 #include <linux/clk.h>
  40 #include <linux/regmap.h>
  41 #include <linux/mfd/syscon.h>
  42 #include <dt-bindings/pinctrl/rockchip.h>
  43
  44 #include "core.h"
  45 #include "pinconf.h"
  46
  47 /* GPIO control registers */
  48 #define GPIO_SWPORT_DR          0x00
  49 #define GPIO_SWPORT_DDR         0x04
  50 #define GPIO_INTEN              0x30
  51 #define GPIO_INTMASK            0x34
  52 #define GPIO_INTTYPE_LEVEL      0x38
  53 #define GPIO_INT_POLARITY       0x3c
  54 #define GPIO_INT_STATUS         0x40
  55 #define GPIO_INT_RAWSTATUS      0x44
  56 #define GPIO_DEBOUNCE           0x48
  57 #define GPIO_PORTS_EOI          0x4c
  58 #define GPIO_EXT_PORT           0x50
  59 #define GPIO_LS_SYNC            0x60
  60
  61 enum rockchip_pinctrl_type {
  62         RK2928,
  63         RK3066B,
  64         RK3188,
  65         RK3288,
  66         RK3366,
  67         RK3368,
  68         RK3399,
  69 };
  70
  71 /**
  72  * Encode variants of iomux registers into a type variable
  73  */
  74 #define IOMUX_GPIO_ONLY         BIT(0)
  75 #define IOMUX_WIDTH_4BIT        BIT(1)
  76 #define IOMUX_SOURCE_PMU        BIT(2)
  77 #define IOMUX_UNROUTED          BIT(3)
  78
  79 /**
  80  * @type: iomux variant using IOMUX_* constants
  81  * @offset: if initialized to -1 it will be autocalculated, by specifying
  82  *          an initial offset value the relevant source offset can be reset
  83  *          to a new value for autocalculating the following iomux registers.
  84  */
  85 struct rockchip_iomux {
  86         int                             type;
  87         int                             offset;
  88 };
  89
  90 /**
  91  * enum type index corresponding to rockchip_perpin_drv_list arrays index.
  92  */
  93 enum rockchip_pin_drv_type {
  94         DRV_TYPE_IO_DEFAULT = 0,
  95         DRV_TYPE_IO_1V8_OR_3V0,
  96         DRV_TYPE_IO_1V8_ONLY,
  97         DRV_TYPE_IO_1V8_3V0_AUTO,
  98         DRV_TYPE_IO_3V3_ONLY,
  99         DRV_TYPE_IO_WIDE_LEVEL,
 100         DRV_TYPE_IO_NARROW_LEVEL,
 101         DRV_TYPE_MAX
 102 };
 103
 104 /**
 105  * enum type index corresponding to rockchip_pull_list arrays index.
 106  */
 107 enum rockchip_pin_pull_type {
 108         PULL_TYPE_IO_DEFAULT = 0,
 109         PULL_TYPE_IO_1V8_ONLY,
 110         PULL_TYPE_MAX
 111 };
 112
 113 /**
 114  * enum type of pin extra drive alignment.
 115  */
 116 enum rockchip_pin_extra_drv_type {
 117         DRV_TYPE_EXTRA_DEFAULT = 0,
 118         DRV_TYPE_EXTRA_SAME_OFFSET,
 119         DRV_TYPE_EXTRA_SAME_BITS
 120 };
 121
 122 /**
 123  * @drv_type: drive strength variant using rockchip_pin_drv_type
 124  * @offset: if initialized to -1 it will be autocalculated, by specifying
 125  *          an initial offset value the relevant source offset can be reset
 126  *          to a new value for autocalculating the following drive strength
 127  *          registers. if used chips own cal_drv func instead to calculate
 128  *          registers offset, the variant could be ignored.
 129  */
 130 struct rockchip_drv {
 131         enum rockchip_pin_drv_type      drv_type;
 132         int                             offset;
 133 };
 134
 135 /**
 136  * @reg_base: register base of the gpio bank
 137  * @reg_pull: optional separate register for additional pull settings
 138  * @clk: clock of the gpio bank
 139  * @irq: interrupt of the gpio bank
 140  * @saved_masks: Saved content of GPIO_INTEN at suspend time.
 141  * @pin_base: first pin number
 142  * @nr_pins: number of pins in this bank
 143  * @name: name of the bank
 144  * @bank_num: number of the bank, to account for holes
 145  * @iomux: array describing the 4 iomux sources of the bank
 146  * @drv: array describing the 4 drive strength sources of the bank
 147  * @pull_type: array describing the 4 pull type sources of the bank
 148  * @valid: are all necessary informations present
 149  * @of_node: dt node of this bank
 150  * @drvdata: common pinctrl basedata
 151  * @domain: irqdomain of the gpio bank
 152  * @gpio_chip: gpiolib chip
 153  * @grange: gpio range
 154  * @slock: spinlock for the gpio bank
 155  */
 156 struct rockchip_pin_bank {
 157         void __iomem                    *reg_base;
 158         struct regmap                   *regmap_pull;
 159         struct clk                      *clk;
 160         int                             irq;
 161         u32                             saved_masks;
 162         u32                             pin_base;
 163         u8                              nr_pins;
 164         char                            *name;
 165         u8                              bank_num;
 166         struct rockchip_iomux           iomux[4];
 167         struct rockchip_drv             drv[4];
 168         enum rockchip_pin_pull_type     pull_type[4];
 169         bool                            valid;
 170         struct device_node              *of_node;
 171         struct rockchip_pinctrl         *drvdata;
 172         struct irq_domain               *domain;
 173         struct gpio_chip                gpio_chip;
 174         struct pinctrl_gpio_range       grange;
 175         spinlock_t                      slock;
 176         u32                             toggle_edge_mode;
 177 };
 178
 179 #define PIN_BANK(id, pins, label)                       \
 180         {                                               \
 181                 .bank_num       = id,                   \
 182                 .nr_pins        = pins,                 \
 183                 .name           = label,                \
 184                 .iomux          = {                     \
 185                         { .offset = -1 },               \
 186                         { .offset = -1 },               \
 187                         { .offset = -1 },               \
 188                         { .offset = -1 },               \
 189                 },                                      \
 190         }
 191
 192 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
 193         {                                                               \
 194                 .bank_num       = id,                                   \
 195                 .nr_pins        = pins,                                 \
 196                 .name           = label,                                \
 197                 .iomux          = {                                     \
 198                         { .type = iom0, .offset = -1 },                 \
 199                         { .type = iom1, .offset = -1 },                 \
 200                         { .type = iom2, .offset = -1 },                 \
 201                         { .type = iom3, .offset = -1 },                 \
 202                 },                                                      \
 203         }
 204
 205 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
 206         {                                                               \
 207                 .bank_num       = id,                                   \
 208                 .nr_pins        = pins,                                 \
 209                 .name           = label,                                \
 210                 .iomux          = {                                     \
 211                         { .offset = -1 },                               \
 212                         { .offset = -1 },                               \
 213                         { .offset = -1 },                               \
 214                         { .offset = -1 },                               \
 215                 },                                                      \
 216                 .drv            = {                                     \
 217                         { .drv_type = type0, .offset = -1 },            \
 218                         { .drv_type = type1, .offset = -1 },            \
 219                         { .drv_type = type2, .offset = -1 },            \
 220                         { .drv_type = type3, .offset = -1 },            \
 221                 },                                                      \
 222         }
 223
 224 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, drv2,\
 225                                       drv3, pull0, pull1, pull2, pull3) \
 226         {                                                               \
 227                 .bank_num       = id,                                   \
 228                 .nr_pins        = pins,                                 \
 229                 .name           = label,                                \
 230                 .iomux          = {                                     \
 231                         { .offset = -1 },                               \
 232                         { .offset = -1 },                               \
 233                         { .offset = -1 },                               \
 234                         { .offset = -1 },                               \
 235                 },                                                      \
 236                 .drv            = {                                     \
 237                         { .drv_type = drv0, .offset = -1 },             \
 238                         { .drv_type = drv1, .offset = -1 },             \
 239                         { .drv_type = drv2, .offset = -1 },             \
 240                         { .drv_type = drv3, .offset = -1 },             \
 241                 },                                                      \
 242                 .pull_type[0] = pull0,                                  \
 243                 .pull_type[1] = pull1,                                  \
 244                 .pull_type[2] = pull2,                                  \
 245                 .pull_type[3] = pull3,                                  \
 246         }
 247
 248 #define PIN_BANK_IOMUX_DRV_FLAGS(id, pins, label, iom0, iom1, iom2,     \
 249                                 iom3, drv0, drv1, drv2, drv3)           \
 250         {                                                               \
 251                 .bank_num       = id,                                   \
 252                 .nr_pins        = pins,                                 \
 253                 .name           = label,                                \
 254                 .iomux          = {                                     \
 255                         { .type = iom0, .offset = -1 },                 \
 256                         { .type = iom1, .offset = -1 },                 \
 257                         { .type = iom2, .offset = -1 },                 \
 258                         { .type = iom3, .offset = -1 },                 \
 259                 },                                                      \
 260                 .drv            = {                                     \
 261                         { .drv_type = drv0, .offset = -1 },             \
 262                         { .drv_type = drv1, .offset = -1 },             \
 263                         { .drv_type = drv2, .offset = -1 },             \
 264                         { .drv_type = drv3, .offset = -1 },             \
 265                 },                                                      \
 266         }
 267
 268 #define PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(id, pins, label, iom0,    \
 269                                              iom1, iom2, iom3, offset0, \
 270                                              offset1, offset2, offset3, \
 271                                              drv0, drv1, drv2, drv3)    \
 272         {                                                               \
 273                 .bank_num       = id,                                   \
 274                 .nr_pins        = pins,                                 \
 275                 .name           = label,                                \
 276                 .iomux          = {                                     \
 277                         { .type = iom0, .offset = offset0 },            \
 278                         { .type = iom1, .offset = offset1 },            \
 279                         { .type = iom2, .offset = offset2 },            \
 280                         { .type = iom3, .offset = offset3 },            \
 281                 },                                                      \
 282                 .drv            = {                                     \
 283                         { .drv_type = drv0, .offset = -1 },             \
 284                         { .drv_type = drv1, .offset = -1 },             \
 285                         { .drv_type = drv2, .offset = -1 },             \
 286                         { .drv_type = drv3, .offset = -1 },             \
 287                 },                                                      \
 288         }
 289
 290 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET(id, pins, label, iom0,    \
 291                                               iom1, iom2, iom3, drv0,   \
 292                                               drv1, drv2, drv3, offset0,\
 293                                               offset1, offset2, offset3)\
 294         {                                                               \
 295                 .bank_num       = id,                                   \
 296                 .nr_pins        = pins,                                 \
 297                 .name           = label,                                \
 298                 .iomux          = {                                     \
 299                         { .type = iom0, .offset = -1 },                 \
 300                         { .type = iom1, .offset = -1 },                 \
 301                         { .type = iom2, .offset = -1 },                 \
 302                         { .type = iom3, .offset = -1 },                 \
 303                 },                                                      \
 304                 .drv            = {                                     \
 305                         { .drv_type = drv0, .offset = offset0 },        \
 306                         { .drv_type = drv1, .offset = offset1 },        \
 307                         { .drv_type = drv2, .offset = offset2 },        \
 308                         { .drv_type = drv3, .offset = offset3 },        \
 309                 },                                                      \
 310         }
 311
 312 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins,      \
 313                                               label, iom0, iom1, iom2,  \
 314                                               iom3, drv0, drv1, drv2,   \
 315                                               drv3, offset0, offset1,   \
 316                                               offset2, offset3, pull0,  \
 317                                               pull1, pull2, pull3)      \
 318         {                                                               \
 319                 .bank_num       = id,                                   \
 320                 .nr_pins        = pins,                                 \
 321                 .name           = label,                                \
 322                 .iomux          = {                                     \
 323                         { .type = iom0, .offset = -1 },                 \
 324                         { .type = iom1, .offset = -1 },                 \
 325                         { .type = iom2, .offset = -1 },                 \
 326                         { .type = iom3, .offset = -1 },                 \
 327                 },                                                      \
 328                 .drv            = {                                     \
 329                         { .drv_type = drv0, .offset = offset0 },        \
 330                         { .drv_type = drv1, .offset = offset1 },        \
 331                         { .drv_type = drv2, .offset = offset2 },        \
 332                         { .drv_type = drv3, .offset = offset3 },        \
 333                 },                                                      \
 334                 .pull_type[0] = pull0,                                  \
 335                 .pull_type[1] = pull1,                                  \
 336                 .pull_type[2] = pull2,                                  \
 337                 .pull_type[3] = pull3,                                  \
 338         }
 339
 340 /**
 341  */
 342 struct rockchip_pin_ctrl {
 343         struct rockchip_pin_bank        *pin_banks;
 344         u32                             nr_banks;
 345         u32                             nr_pins;
 346         char                            *label;
 347         enum rockchip_pinctrl_type      type;
 348         int                             grf_mux_offset;
 349         int                             pmu_mux_offset;
 350         int                             grf_drv_offset;
 351         int                             pmu_drv_offset;
 352
 353         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank,
 354                                  int pin_num, struct regmap **regmap,
 355                                  int *reg, u8 *bit);
 356         enum rockchip_pin_drv_type (*drv_calc_reg)(
 357                                 struct rockchip_pin_bank *bank,
 358                                 int pin_num, struct regmap **regmap,
 359                                 int *reg, u8 *bit);
 360         enum rockchip_pin_extra_drv_type (*drv_calc_extra_reg)(
 361                                       struct rockchip_pin_bank *bank,
 362                                       int pin_num, struct regmap **regmap,
 363                                       int *reg, u8 *bit);
 364 };
 365
 366 struct rockchip_pin_config {
 367         unsigned int            func;
 368         unsigned long           *configs;
 369         unsigned int            nconfigs;
 370 };
 371
 372 /**
 373  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 374  * @name: name of the pin group, used to lookup the group.
 375  * @pins: the pins included in this group.
 376  * @npins: number of pins included in this group.
 377  * @func: the mux function number to be programmed when selected.
 378  * @configs: the config values to be set for each pin
 379  * @nconfigs: number of configs for each pin
 380  */
 381 struct rockchip_pin_group {
 382         const char                      *name;
 383         unsigned int                    npins;
 384         unsigned int                    *pins;
 385         struct rockchip_pin_config      *data;
 386 };
 387
 388 /**
 389  * struct rockchip_pmx_func: represent a pin function.
 390  * @name: name of the pin function, used to lookup the function.
 391  * @groups: one or more names of pin groups that provide this function.
 392  * @num_groups: number of groups included in @groups.
 393  */
 394 struct rockchip_pmx_func {
 395         const char              *name;
 396         const char              **groups;
 397         u8                      ngroups;
 398 };
 399
 400 struct rockchip_pinctrl {
 401         struct regmap                   *regmap_base;
 402         int                             reg_size;
 403         struct regmap                   *regmap_pull;
 404         struct regmap                   *regmap_pmu;
 405         struct device                   *dev;
 406         struct rockchip_pin_ctrl        *ctrl;
 407         struct pinctrl_desc             pctl;
 408         struct pinctrl_dev              *pctl_dev;
 409         struct rockchip_pin_group       *groups;
 410         unsigned int                    ngroups;
 411         struct rockchip_pmx_func        *functions;
 412         unsigned int                    nfunctions;
 413 };
 414
 415 static struct regmap_config rockchip_regmap_config = {
 416         .reg_bits = 32,
 417         .val_bits = 32,
 418         .reg_stride = 4,
 419 };
 420
 421 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
 422 {
 423         return container_of(gc, struct rockchip_pin_bank, gpio_chip);
 424 }
 425
 426 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
 427                                         const struct rockchip_pinctrl *info,
 428                                         const char *name)
 429 {
 430         int i;
 431
 432         for (i = 0; i < info->ngroups; i++) {
 433                 if (!strcmp(info->groups[i].name, name))
 434                         return &info->groups[i];
 435         }
 436
 437         return NULL;
 438 }
 439
 440 /*
 441  * given a pin number that is local to a pin controller, find out the pin bank
 442  * and the register base of the pin bank.
 443  */
 444 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 445                                                                 unsigned pin)
 446 {
 447         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 448
 449         while (pin >= (b->pin_base + b->nr_pins))
 450                 b++;
 451
 452         return b;
 453 }
 454
 455 static struct rockchip_pin_bank *bank_num_to_bank(
 456                                         struct rockchip_pinctrl *info,
 457                                         unsigned num)
 458 {
 459         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 460         int i;
 461
 462         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 463                 if (b->bank_num == num)
 464                         return b;
 465         }
 466
 467         return ERR_PTR(-EINVAL);
 468 }
 469
 470 /*
 471  * Pinctrl_ops handling
 472  */
 473
 474 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 475 {
 476         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 477
 478         return info->ngroups;
 479 }
 480
 481 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 482                                                         unsigned selector)
 483 {
 484         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 485
 486         return info->groups[selector].name;
 487 }
 488
 489 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 490                                       unsigned selector, const unsigned **pins,
 491                                       unsigned *npins)
 492 {
 493         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 494
 495         if (selector >= info->ngroups)
 496                 return -EINVAL;
 497
 498         *pins = info->groups[selector].pins;
 499         *npins = info->groups[selector].npins;
 500
 501         return 0;
 502 }
 503
 504 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 505                                  struct device_node *np,
 506                                  struct pinctrl_map **map, unsigned *num_maps)
 507 {
 508         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 509         const struct rockchip_pin_group *grp;
 510         struct pinctrl_map *new_map;
 511         struct device_node *parent;
 512         int map_num = 1;
 513         int i;
 514
 515         /*
 516          * first find the group of this node and check if we need to create
 517          * config maps for pins
 518          */
 519         grp = pinctrl_name_to_group(info, np->name);
 520         if (!grp) {
 521                 dev_err(info->dev, "unable to find group for node %s\n",
 522                         np->name);
 523                 return -EINVAL;
 524         }
 525
 526         map_num += grp->npins;
 527         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 528                                                                 GFP_KERNEL);
 529         if (!new_map)
 530                 return -ENOMEM;
 531
 532         *map = new_map;
 533         *num_maps = map_num;
 534
 535         /* create mux map */
 536         parent = of_get_parent(np);
 537         if (!parent) {
 538                 devm_kfree(pctldev->dev, new_map);
 539                 return -EINVAL;
 540         }
 541         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 542         new_map[0].data.mux.function = parent->name;
 543         new_map[0].data.mux.group = np->name;
 544         of_node_put(parent);
 545
 546         /* create config map */
 547         new_map++;
 548         for (i = 0; i < grp->npins; i++) {
 549                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 550                 new_map[i].data.configs.group_or_pin =
 551                                 pin_get_name(pctldev, grp->pins[i]);
 552                 new_map[i].data.configs.configs = grp->data[i].configs;
 553                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 554         }
 555
 556         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 557                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 558
 559         return 0;
 560 }
 561
 562 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 563                                     struct pinctrl_map *map, unsigned num_maps)
 564 {
 565 }
 566
 567 static const struct pinctrl_ops rockchip_pctrl_ops = {
 568         .get_groups_count       = rockchip_get_groups_count,
 569         .get_group_name         = rockchip_get_group_name,
 570         .get_group_pins         = rockchip_get_group_pins,
 571         .dt_node_to_map         = rockchip_dt_node_to_map,
 572         .dt_free_map            = rockchip_dt_free_map,
 573 };
 574
 575 /*
 576  * Hardware access
 577  */
 578
 579 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
 580 {
 581         struct rockchip_pinctrl *info = bank->drvdata;
 582         int iomux_num = (pin / 8);
 583         struct regmap *regmap;
 584         unsigned int val;
 585         int reg, ret, mask;
 586         u8 bit;
 587
 588         if (iomux_num > 3)
 589                 return -EINVAL;
 590
 591         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 592                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 593                 return -EINVAL;
 594         }
 595
 596         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
 597                 return RK_FUNC_GPIO;
 598
 599         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 600                                 ? info->regmap_pmu : info->regmap_base;
 601
 602         /* get basic quadrupel of mux registers and the correct reg inside */
 603         mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
 604         reg = bank->iomux[iomux_num].offset;
 605         if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
 606                 if ((pin % 8) >= 4)
 607                         reg += 0x4;
 608                 bit = (pin % 4) * 4;
 609         } else {
 610                 bit = (pin % 8) * 2;
 611         }
 612
 613         ret = regmap_read(regmap, reg, &val);
 614         if (ret)
 615                 return ret;
 616
 617         return ((val >> bit) & mask);
 618 }
 619
 620 /*
 621  * Set a new mux function for a pin.
 622  *
 623  * The register is divided into the upper and lower 16 bit. When changing
 624  * a value, the previous register value is not read and changed. Instead
 625  * it seems the changed bits are marked in the upper 16 bit, while the
 626  * changed value gets set in the same offset in the lower 16 bit.
 627  * All pin settings seem to be 2 bit wide in both the upper and lower
 628  * parts.
 629  * @bank: pin bank to change
 630  * @pin: pin to change
 631  * @mux: new mux function to set
 632  */
 633 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 634 {
 635         struct rockchip_pinctrl *info = bank->drvdata;
 636         int iomux_num = (pin / 8);
 637         struct regmap *regmap;
 638         int reg, ret, mask;
 639         unsigned long flags;
 640         u8 bit;
 641         u32 data, rmask;
 642
 643         if (iomux_num > 3)
 644                 return -EINVAL;
 645
 646         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 647                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 648                 return -EINVAL;
 649         }
 650
 651         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
 652                 if (mux != RK_FUNC_GPIO) {
 653                         dev_err(info->dev,
 654                                 "pin %d only supports a gpio mux\n", pin);
 655                         return -ENOTSUPP;
 656                 } else {
 657                         return 0;
 658                 }
 659         }
 660
 661         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
 662                                                 bank->bank_num, pin, mux);
 663
 664         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 665                                 ? info->regmap_pmu : info->regmap_base;
 666
 667         /* get basic quadrupel of mux registers and the correct reg inside */
 668         mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
 669         reg = bank->iomux[iomux_num].offset;
 670         if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
 671                 if ((pin % 8) >= 4)
 672                         reg += 0x4;
 673                 bit = (pin % 4) * 4;
 674         } else {
 675                 bit = (pin % 8) * 2;
 676         }
 677
 678         spin_lock_irqsave(&bank->slock, flags);
 679
 680         data = (mask << (bit + 16));
 681         rmask = data | (data >> 16);
 682         data |= (mux & mask) << bit;
 683         ret = regmap_update_bits(regmap, reg, rmask, data);
 684
 685         spin_unlock_irqrestore(&bank->slock, flags);
 686
 687         return ret;
 688 }
 689
 690 #define RK2928_PULL_OFFSET              0x118
 691 #define RK2928_PULL_PINS_PER_REG        16
 692 #define RK2928_PULL_BANK_STRIDE         8
 693
 694 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 695                                     int pin_num, struct regmap **regmap,
 696                                     int *reg, u8 *bit)
 697 {
 698         struct rockchip_pinctrl *info = bank->drvdata;
 699
 700         *regmap = info->regmap_base;
 701         *reg = RK2928_PULL_OFFSET;
 702         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
 703         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
 704
 705         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
 706 };
 707
 708 #define RK3188_PULL_OFFSET              0x164
 709 #define RK3188_PULL_BITS_PER_PIN        2
 710 #define RK3188_PULL_PINS_PER_REG        8
 711 #define RK3188_PULL_BANK_STRIDE         16
 712 #define RK3188_PULL_PMU_OFFSET          0x64
 713
 714 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 715                                     int pin_num, struct regmap **regmap,
 716                                     int *reg, u8 *bit)
 717 {
 718         struct rockchip_pinctrl *info = bank->drvdata;
 719
 720         /* The first 12 pins of the first bank are located elsewhere */
 721         if (bank->bank_num == 0 && pin_num < 12) {
 722                 *regmap = info->regmap_pmu ? info->regmap_pmu
 723                                            : bank->regmap_pull;
 724                 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
 725                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 726                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 727                 *bit *= RK3188_PULL_BITS_PER_PIN;
 728         } else {
 729                 *regmap = info->regmap_pull ? info->regmap_pull
 730                                             : info->regmap_base;
 731                 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
 732
 733                 /* correct the offset, as it is the 2nd pull register */
 734                 *reg -= 4;
 735                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 736                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 737
 738                 /*
 739                  * The bits in these registers have an inverse ordering
 740                  * with the lowest pin being in bits 15:14 and the highest
 741                  * pin in bits 1:0
 742                  */
 743                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
 744                 *bit *= RK3188_PULL_BITS_PER_PIN;
 745         }
 746 }
 747
 748 #define RK3288_PULL_OFFSET              0x140
 749 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 750                                     int pin_num, struct regmap **regmap,
 751                                     int *reg, u8 *bit)
 752 {
 753         struct rockchip_pinctrl *info = bank->drvdata;
 754
 755         /* The first 24 pins of the first bank are located in PMU */
 756         if (bank->bank_num == 0) {
 757                 *regmap = info->regmap_pmu;
 758                 *reg = RK3188_PULL_PMU_OFFSET;
 759
 760                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 761                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 762                 *bit *= RK3188_PULL_BITS_PER_PIN;
 763         } else {
 764                 *regmap = info->regmap_base;
 765                 *reg = RK3288_PULL_OFFSET;
 766
 767                 /* correct the offset, as we're starting with the 2nd bank */
 768                 *reg -= 0x10;
 769                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 770                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 771
 772                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
 773                 *bit *= RK3188_PULL_BITS_PER_PIN;
 774         }
 775 }
 776
 777 #define RK3288_DRV_PMU_OFFSET           0x70
 778 #define RK3288_DRV_GRF_OFFSET           0x1c0
 779 #define RK3288_DRV_BITS_PER_PIN         2
 780 #define RK3288_DRV_PINS_PER_REG         8
 781 #define RK3288_DRV_BANK_STRIDE          16
 782
 783 static enum rockchip_pin_drv_type rk3288_calc_drv_reg_and_bit(
 784                                        struct rockchip_pin_bank *bank,
 785                                        int pin_num, struct regmap **regmap,
 786                                        int *reg, u8 *bit)
 787 {
 788         struct rockchip_pinctrl *info = bank->drvdata;
 789
 790         /* The first 24 pins of the first bank are located in PMU */
 791         if (bank->bank_num == 0) {
 792                 *regmap = info->regmap_pmu;
 793                 *reg = RK3288_DRV_PMU_OFFSET;
 794
 795                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 796                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
 797                 *bit *= RK3288_DRV_BITS_PER_PIN;
 798         } else {
 799                 *regmap = info->regmap_base;
 800                 *reg = RK3288_DRV_GRF_OFFSET;
 801
 802                 /* correct the offset, as we're starting with the 2nd bank */
 803                 *reg -= 0x10;
 804                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
 805                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 806
 807                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
 808                 *bit *= RK3288_DRV_BITS_PER_PIN;
 809         }
 810
 811         return DRV_TYPE_IO_DEFAULT;
 812 }
 813
 814 #define RK3228_PULL_OFFSET              0x100
 815
 816 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 817                                     int pin_num, struct regmap **regmap,
 818                                     int *reg, u8 *bit)
 819 {
 820         struct rockchip_pinctrl *info = bank->drvdata;
 821
 822         *regmap = info->regmap_base;
 823         *reg = RK3228_PULL_OFFSET;
 824         *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 825         *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 826
 827         *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
 828         *bit *= RK3188_PULL_BITS_PER_PIN;
 829 }
 830
 831 #define RK3228_DRV_GRF_OFFSET           0x200
 832
 833 static enum rockchip_pin_drv_type rk3228_calc_drv_reg_and_bit(
 834                                        struct rockchip_pin_bank *bank,
 835                                        int pin_num, struct regmap **regmap,
 836                                        int *reg, u8 *bit)
 837 {
 838         struct rockchip_pinctrl *info = bank->drvdata;
 839
 840         *regmap = info->regmap_base;
 841         *reg = RK3228_DRV_GRF_OFFSET;
 842         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
 843         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 844
 845         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
 846         *bit *= RK3288_DRV_BITS_PER_PIN;
 847
 848         return DRV_TYPE_IO_DEFAULT;
 849 }
 850
 851 #define RK3366_PULL_GRF_OFFSET          0x110
 852 #define RK3366_PULL_PMU_OFFSET          0x10
 853
 854 static void rk3366_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 855                                          int pin_num, struct regmap **regmap,
 856                                          int *reg, u8 *bit)
 857 {
 858         struct rockchip_pinctrl *info = bank->drvdata;
 859
 860         /* The bank0:32 and bank1:16 pins are located in PMU */
 861         if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
 862                 *regmap = info->regmap_pmu;
 863                 *reg = RK3366_PULL_PMU_OFFSET + bank->bank_num * 0x30;
 864
 865                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 866                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 867                 *bit *= RK3188_PULL_BITS_PER_PIN;
 868         } else {
 869                 *regmap = info->regmap_base;
 870                 *reg = RK3366_PULL_GRF_OFFSET;
 871
 872                 /* correct the offset, as we're starting with the 2nd bank */
 873                 *reg -= 0x20;
 874                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 875                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 876
 877                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
 878                 *bit *= RK3188_PULL_BITS_PER_PIN;
 879         }
 880 }
 881
 882 #define RK3366_DRV_PMU_OFFSET           0x20
 883 #define RK3366_DRV_GRF_OFFSET           0x210
 884
 885 #define RK3366_DRV_GPIO2B3_OFFSET       0x378
 886 #define RK3366_DRV_GPIO2B3_BITS         4
 887
 888 #define RK3366_DRV_GPIO3A4_OFFSET       0x37c
 889 #define RK3366_DRV_GPIO3A4_BITS         4
 890
 891 static enum rockchip_pin_drv_type rk3366_calc_drv_reg_and_bit(
 892                                        struct rockchip_pin_bank *bank,
 893                                        int pin_num, struct regmap **regmap,
 894                                        int *reg, u8 *bit)
 895 {
 896         struct rockchip_pinctrl *info = bank->drvdata;
 897
 898         /* The bank0:32 and bank1:16 pins are located in PMU */
 899         if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
 900                 *regmap = info->regmap_pmu;
 901                 *reg = RK3366_DRV_PMU_OFFSET + bank->bank_num * 0x30;
 902
 903                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 904                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
 905                 *bit *= RK3288_DRV_BITS_PER_PIN;
 906
 907                 return DRV_TYPE_IO_DEFAULT;
 908         } else if ((bank->bank_num == 2) && (pin_num == 11)) {
 909                 /* GPIO2B3 is a special case in bank2 */
 910                 *regmap = info->regmap_base;
 911                 *reg = RK3366_DRV_GPIO2B3_OFFSET;
 912                 *bit = RK3366_DRV_GPIO2B3_BITS;
 913
 914                 return DRV_TYPE_IO_WIDE_LEVEL;
 915         } else if ((bank->bank_num == 3) && (pin_num == 4)) {
 916                 /* GPIO3A4 is a special case in bank3 */
 917                 *regmap = info->regmap_base;
 918                 *reg = RK3366_DRV_GPIO3A4_OFFSET;
 919                 *bit = RK3366_DRV_GPIO3A4_BITS;
 920
 921                 return DRV_TYPE_IO_WIDE_LEVEL;
 922         }
 923
 924         *regmap = info->regmap_base;
 925         *reg = RK3366_DRV_GRF_OFFSET;
 926
 927         /* correct the offset, as we're starting with the 2nd bank */
 928         *reg -= 0x20;
 929         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
 930         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 931
 932         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
 933         *bit *= RK3288_DRV_BITS_PER_PIN;
 934
 935         /* special cases need special handle */
 936         if ((bank->bank_num == 2) && (pin_num == 14))
 937                 return DRV_TYPE_IO_WIDE_LEVEL;
 938         else if ((bank->bank_num == 2) && (pin_num == 16))
 939                 return DRV_TYPE_IO_NARROW_LEVEL;
 940         else if ((bank->bank_num == 2) && (pin_num >= 24) && (pin_num <= 26))
 941                 return DRV_TYPE_IO_WIDE_LEVEL;
 942
 943         return DRV_TYPE_IO_DEFAULT;
 944 }
 945
 946 #define RK3366_DRV_GPIO2A_EN_OFFSET     0x360
 947 #define RK3366_DRV_GPIO2A_EP_OFFSET     0x364
 948
 949 #define RK3366_DRV_GPIO2C_EN_OFFSET     0x368
 950 #define RK3366_DRV_GPIO2C_EP_OFFSET     0x36C
 951
 952 #define RK3366_DRV_GPIO2D_EN_OFFSET     0x370
 953 #define RK3366_DRV_GPIO2D_EP_OFFSET     0x374
 954
 955 #define RK3366_DRV_GPIO2B3_E_OFFSET     0x378
 956 #define RK3366_DRV_GPIO2B3_EN_BIT       0
 957 #define RK3366_DRV_GPIO2B3_EP_BIT       2
 958
 959 #define RK3366_DRV_GPIO3A4_E_OFFSET     0x37c
 960 #define RK3366_DRV_GPIO3A4_EN_BIT       0
 961 #define RK3366_DRV_GPIO3A4_EP_BIT       2
 962
 963 #define RK3366_DRV_GPIO2B6_E_OFFSET     0x404
 964 #define RK3366_DRV_GPIO2B6_EN_BIT       12
 965 #define RK3366_DRV_GPIO2B6_EP_BIT       14
 966
 967 static enum rockchip_pin_extra_drv_type rk3366_calc_drv_extra_reg_and_bit(
 968                                              struct rockchip_pin_bank *bank,
 969                                              int pin_num,
 970                                              struct regmap **regmap,
 971                                              int *reg, u8 *bit)
 972 {
 973         struct rockchip_pinctrl *info = bank->drvdata;
 974
 975         *regmap = info->regmap_base;
 976         if (bank->bank_num == 2) {
 977                 switch (pin_num / 8) {
 978                 case 0:
 979                         *reg = RK3366_DRV_GPIO2A_EN_OFFSET;
 980                         break;
 981                 case 1:
 982                         /* special cases need special handle */
 983                         if (pin_num == 11) {
 984                                 *reg = RK3366_DRV_GPIO2B3_E_OFFSET;
 985                                 *bit = RK3366_DRV_GPIO2B3_EN_BIT;
 986                         } else if (pin_num == 14) {
 987                                 *reg = RK3366_DRV_GPIO2B6_E_OFFSET;
 988                                 *bit = RK3366_DRV_GPIO2B6_EN_BIT;
 989                         } else {
 990                                 return -1;
 991                         }
 992
 993                         return DRV_TYPE_EXTRA_SAME_OFFSET;
 994                 case 2:
 995                         *reg = RK3366_DRV_GPIO2C_EN_OFFSET;
 996                         break;
 997                 case 3:
 998                         *reg = RK3366_DRV_GPIO2D_EN_OFFSET;
 999                         break;
1000                 default:
1001                         return -1;
1002                 }
1003
1004                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1005                 *bit *= RK3288_DRV_BITS_PER_PIN;
1006
1007                 return DRV_TYPE_EXTRA_SAME_BITS;
1008         }
1009
1010         /* GPIO3A4 is a special case */
1011         if ((pin_num != 4) && (bank->bank_num != 3))
1012                 return -1;
1013
1014         *reg = RK3366_DRV_GPIO3A4_E_OFFSET;
1015         *bit = RK3366_DRV_GPIO3A4_EN_BIT;
1016
1017         return DRV_TYPE_EXTRA_SAME_OFFSET;
1018 }
1019
1020 #define RK3368_PULL_GRF_OFFSET          0x100
1021 #define RK3368_PULL_PMU_OFFSET          0x10
1022
1023 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1024                                          int pin_num, struct regmap **regmap,
1025                                          int *reg, u8 *bit)
1026 {
1027         struct rockchip_pinctrl *info = bank->drvdata;
1028
1029         /* The first 32 pins of the first bank are located in PMU */
1030         if (bank->bank_num == 0) {
1031                 *regmap = info->regmap_pmu;
1032                 *reg = RK3368_PULL_PMU_OFFSET;
1033
1034                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1035                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1036                 *bit *= RK3188_PULL_BITS_PER_PIN;
1037         } else {
1038                 *regmap = info->regmap_base;
1039                 *reg = RK3368_PULL_GRF_OFFSET;
1040
1041                 /* correct the offset, as we're starting with the 2nd bank */
1042                 *reg -= 0x10;
1043                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1044                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1045
1046                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1047                 *bit *= RK3188_PULL_BITS_PER_PIN;
1048         }
1049 }
1050
1051 #define RK3368_DRV_PMU_OFFSET           0x20
1052 #define RK3368_DRV_GRF_OFFSET           0x200
1053
1054 static enum rockchip_pin_drv_type rk3368_calc_drv_reg_and_bit(
1055                                        struct rockchip_pin_bank *bank,
1056                                        int pin_num, struct regmap **regmap,
1057                                        int *reg, u8 *bit)
1058 {
1059         struct rockchip_pinctrl *info = bank->drvdata;
1060
1061         /* The first 32 pins of the first bank are located in PMU */
1062         if (bank->bank_num == 0) {
1063                 *regmap = info->regmap_pmu;
1064                 *reg = RK3368_DRV_PMU_OFFSET;
1065
1066                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1067                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1068                 *bit *= RK3288_DRV_BITS_PER_PIN;
1069         } else {
1070                 *regmap = info->regmap_base;
1071                 *reg = RK3368_DRV_GRF_OFFSET;
1072
1073                 /* correct the offset, as we're starting with the 2nd bank */
1074                 *reg -= 0x10;
1075                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1076                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1077
1078                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1079                 *bit *= RK3288_DRV_BITS_PER_PIN;
1080         }
1081
1082         return DRV_TYPE_IO_DEFAULT;
1083 }
1084
1085 #define RK3399_PULL_GRF_OFFSET          0xe040
1086 #define RK3399_PULL_PMU_OFFSET          0x40
1087 #define RK3399_DRV_3BITS_PER_PIN        3
1088
1089 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1090                                          int pin_num, struct regmap **regmap,
1091                                          int *reg, u8 *bit)
1092 {
1093         struct rockchip_pinctrl *info = bank->drvdata;
1094
1095         /* The bank0:16 and bank1:32 pins are located in PMU */
1096         if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1097                 *regmap = info->regmap_pmu;
1098                 *reg = RK3399_PULL_PMU_OFFSET;
1099
1100                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1101
1102                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1103                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1104                 *bit *= RK3188_PULL_BITS_PER_PIN;
1105         } else {
1106                 *regmap = info->regmap_base;
1107                 *reg = RK3399_PULL_GRF_OFFSET;
1108
1109                 /* correct the offset, as we're starting with the 3rd bank */
1110                 *reg -= 0x20;
1111                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1112                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1113
1114                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1115                 *bit *= RK3188_PULL_BITS_PER_PIN;
1116         }
1117 }
1118
1119 static enum rockchip_pin_drv_type rk3399_calc_drv_reg_and_bit(
1120                                        struct rockchip_pin_bank *bank,
1121                                        int pin_num, struct regmap **regmap,
1122                                        int *reg, u8 *bit)
1123 {
1124         struct rockchip_pinctrl *info = bank->drvdata;
1125         int drv_num = (pin_num / 8);
1126
1127         /*  The bank0:16 and bank1:32 pins are located in PMU */
1128         if ((bank->bank_num == 0) || (bank->bank_num == 1))
1129                 *regmap = info->regmap_pmu;
1130         else
1131                 *regmap = info->regmap_base;
1132
1133         *reg = bank->drv[drv_num].offset;
1134         if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1135             (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1136                 *bit = (pin_num % 8) * 3;
1137         else
1138                 *bit = (pin_num % 8) * 2;
1139
1140         return DRV_TYPE_IO_DEFAULT;
1141 }
1142
1143 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1144         { 2, 4, 8, 12, -1, -1, -1, -1 },
1145         { 3, 6, 9, 12, -1, -1, -1, -1 },
1146         { 5, 10, 15, 20, -1, -1, -1, -1 },
1147         { 4, 6, 8, 10, 12, 14, 16, 18 },
1148         { 4, 7, 10, 13, 16, 19, 22, 26 },
1149         { 0, 6, 12, 18, -1, -1, -1, -1 },
1150         { 4, 8, 12, 16, -1, -1, -1, -1 }
1151 };
1152
1153 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1154                                      int pin_num)
1155 {
1156         struct rockchip_pinctrl *info = bank->drvdata;
1157         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1158         struct regmap *regmap, *extra_regmap;
1159         int reg, ret, extra_reg;
1160         u32 data, temp, rmask_bits;
1161         u8 bit, extra_bit;
1162         int drv_type;
1163
1164         drv_type = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1165         if (!drv_type)
1166                 drv_type = bank->drv[pin_num / 8].drv_type;
1167
1168         switch (drv_type) {
1169         case DRV_TYPE_IO_1V8_3V0_AUTO:
1170         case DRV_TYPE_IO_3V3_ONLY:
1171                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1172                 switch (bit) {
1173                 case 0 ... 12:
1174                         /* regular case, nothing to do */
1175                         break;
1176                 case 15:
1177                         /*
1178                          * drive-strength offset is special, as it is
1179                          * spread over 2 registers
1180                          */
1181                         ret = regmap_read(regmap, reg, &data);
1182                         if (ret)
1183                                 return ret;
1184
1185                         ret = regmap_read(regmap, reg + 0x4, &temp);
1186                         if (ret)
1187                                 return ret;
1188
1189                         /*
1190                          * the bit data[15] contains bit 0 of the value
1191                          * while temp[1:0] contains bits 2 and 1
1192                          */
1193                         data >>= 15;
1194                         temp &= 0x3;
1195                         temp <<= 1;
1196                         data |= temp;
1197
1198                         return rockchip_perpin_drv_list[drv_type][data];
1199                 case 18 ... 21:
1200                         /* setting fully enclosed in the second register */
1201                         reg += 4;
1202                         bit -= 16;
1203                         break;
1204                 default:
1205                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1206                                 bit, drv_type);
1207                         return -EINVAL;
1208                 }
1209
1210                 break;
1211         case DRV_TYPE_IO_WIDE_LEVEL:
1212                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1213                 /* enable the write to the equivalent lower bits */
1214                 ret = regmap_read(regmap, reg, &data);
1215                 if (ret)
1216                         return ret;
1217                 data >>= bit;
1218                 data &= (1 << rmask_bits) - 1;
1219
1220                 /*
1221                  * assume the drive strength of N channel and
1222                  * P channel are the same.
1223                  */
1224                 if (ctrl->drv_calc_extra_reg)
1225                         ctrl->drv_calc_extra_reg(bank, pin_num,
1226                                                  &extra_regmap,
1227                                                  &extra_reg,
1228                                                  &extra_bit);
1229
1230                 /*
1231                  * It is enough to read one channel drive strength,
1232                  * this is N channel.
1233                  */
1234                 ret = regmap_read(extra_regmap, extra_reg, &temp);
1235                 if (ret)
1236                         return ret;
1237
1238                 temp >>= extra_bit;
1239                 temp &= (1 << rmask_bits) - 1;
1240
1241                 return (rockchip_perpin_drv_list[drv_type][data]) + (temp * 2);
1242         case DRV_TYPE_IO_DEFAULT:
1243         case DRV_TYPE_IO_1V8_OR_3V0:
1244         case DRV_TYPE_IO_1V8_ONLY:
1245         case DRV_TYPE_IO_NARROW_LEVEL:
1246                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1247                 break;
1248         default:
1249                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1250                         drv_type);
1251                 return -EINVAL;
1252         }
1253
1254         ret = regmap_read(regmap, reg, &data);
1255         if (ret)
1256                 return ret;
1257
1258         data >>= bit;
1259         data &= (1 << rmask_bits) - 1;
1260
1261         return rockchip_perpin_drv_list[drv_type][data];
1262 }
1263
1264 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1265                                      int pin_num, int strength)
1266 {
1267         struct rockchip_pinctrl *info = bank->drvdata;
1268         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1269         struct regmap *regmap, *extra_regmap;
1270         unsigned long flags;
1271         int reg, ret, i;
1272         u32 data, temp, rmask, rmask_bits;
1273         u8 bit, extra_bit;
1274         int drv_type, extra_drv_type = 0;
1275         int extra_value, extra_reg;
1276
1277         dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
1278                 bank->bank_num, pin_num, strength);
1279
1280         drv_type = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1281         if (!drv_type)
1282                 drv_type = bank->drv[pin_num / 8].drv_type;
1283
1284         ret = -EINVAL;
1285
1286         if (drv_type == DRV_TYPE_IO_WIDE_LEVEL) {
1287                 if ((strength % 2 == 0) && (strength <= 24))
1288                         ret = ((strength > 18) ? 18 : strength) / 6;
1289         } else {
1290                 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]);
1291                      i++) {
1292                         if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1293                                 ret = rockchip_perpin_drv_list[drv_type][i];
1294                                 break;
1295                         } else if (rockchip_perpin_drv_list[drv_type][i] ==
1296                                    strength) {
1297                                 ret = i;
1298                                 break;
1299                         }
1300                 }
1301         }
1302
1303         if (ret < 0) {
1304                 dev_err(info->dev, "unsupported driver strength %d\n",
1305                         strength);
1306                 return ret;
1307         }
1308
1309         spin_lock_irqsave(&bank->slock, flags);
1310
1311         switch (drv_type) {
1312         case DRV_TYPE_IO_1V8_3V0_AUTO:
1313         case DRV_TYPE_IO_3V3_ONLY:
1314                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1315                 switch (bit) {
1316                 case 0 ... 12:
1317                         /* regular case, nothing to do */
1318                         break;
1319                 case 15:
1320                         /*
1321                          * drive-strength offset is special, as it is spread
1322                          * over 2 registers, the bit data[15] contains bit 0
1323                          * of the value while temp[1:0] contains bits 2 and 1
1324                          */
1325                         data = (ret & 0x1) << 15;
1326                         temp = (ret >> 0x1) & 0x3;
1327
1328                         rmask = BIT(15) | BIT(31);
1329                         data |= BIT(31);
1330                         ret = regmap_update_bits(regmap, reg, rmask, data);
1331                         if (ret) {
1332                                 spin_unlock_irqrestore(&bank->slock, flags);
1333                                 return ret;
1334                         }
1335
1336                         rmask = 0x3 | (0x3 << 16);
1337                         temp |= (0x3 << 16);
1338                         reg += 0x4;
1339                         ret = regmap_update_bits(regmap, reg, rmask, temp);
1340
1341                         spin_unlock_irqrestore(&bank->slock, flags);
1342                         return ret;
1343                 case 18 ... 21:
1344                         /* setting fully enclosed in the second register */
1345                         reg += 4;
1346                         bit -= 16;
1347                         break;
1348                 default:
1349                         spin_unlock_irqrestore(&bank->slock, flags);
1350                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1351                                 bit, drv_type);
1352                         return -EINVAL;
1353                 }
1354                 break;
1355         case DRV_TYPE_IO_WIDE_LEVEL:
1356                 extra_value = ((strength -
1357                                 rockchip_perpin_drv_list[drv_type][ret])) >> 1;
1358                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1359
1360                 /*
1361                  * assume the drive strength of N channel and
1362                  * P channel are the same.
1363                  */
1364                 if (ctrl->drv_calc_extra_reg)
1365                         extra_drv_type = ctrl->drv_calc_extra_reg(bank, pin_num,
1366                                                                   &extra_regmap,
1367                                                                   &extra_reg,
1368                                                                   &extra_bit);
1369
1370                 /* enable the write to the equivalent lower bits */
1371                 data = ((1 << rmask_bits) - 1) << (extra_bit + 16);
1372                 rmask = data | (data >> 16);
1373                 data |= (extra_value << extra_bit);
1374
1375                 /* write drive strength of N channel */
1376                 if (regmap_update_bits(extra_regmap, extra_reg, rmask, data)) {
1377                         spin_unlock_irqrestore(&bank->slock, flags);
1378                         return -EINVAL;
1379                 }
1380
1381                 if (extra_drv_type == DRV_TYPE_EXTRA_SAME_OFFSET) {
1382                         extra_bit += 2;
1383                 } else if (extra_drv_type == DRV_TYPE_EXTRA_SAME_BITS) {
1384                         extra_reg += 0x4;
1385                 } else {
1386                         spin_unlock_irqrestore(&bank->slock, flags);
1387                         return -EINVAL;
1388                 }
1389
1390                 /* enable the write to the equivalent lower bits */
1391                 data = ((1 << rmask_bits) - 1) << (extra_bit + 16);
1392                 rmask = data | (data >> 16);
1393                 data |= (extra_value << extra_bit);
1394
1395                 /* write drive strength of P channel */
1396                 if (regmap_update_bits(extra_regmap, extra_reg, rmask, data)) {
1397                         spin_unlock_irqrestore(&bank->slock, flags);
1398                         return -EINVAL;
1399                 }
1400
1401                 break;
1402         case DRV_TYPE_IO_DEFAULT:
1403         case DRV_TYPE_IO_1V8_OR_3V0:
1404         case DRV_TYPE_IO_1V8_ONLY:
1405         case DRV_TYPE_IO_NARROW_LEVEL:
1406                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1407                 break;
1408         default:
1409                 spin_unlock_irqrestore(&bank->slock, flags);
1410                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1411                         drv_type);
1412                 return -EINVAL;
1413         }
1414
1415         /* enable the write to the equivalent lower bits */
1416         data = ((1 << rmask_bits) - 1) << (bit + 16);
1417         rmask = data | (data >> 16);
1418         data |= (ret << bit);
1419
1420         ret = regmap_update_bits(regmap, reg, rmask, data);
1421         spin_unlock_irqrestore(&bank->slock, flags);
1422
1423         return ret;
1424 }
1425
1426 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1427         {
1428                 PIN_CONFIG_BIAS_DISABLE,
1429                 PIN_CONFIG_BIAS_PULL_UP,
1430                 PIN_CONFIG_BIAS_PULL_DOWN,
1431                 PIN_CONFIG_BIAS_BUS_HOLD
1432         },
1433         {
1434                 PIN_CONFIG_BIAS_DISABLE,
1435                 PIN_CONFIG_BIAS_PULL_DOWN,
1436                 PIN_CONFIG_BIAS_DISABLE,
1437                 PIN_CONFIG_BIAS_PULL_UP
1438         },
1439 };
1440
1441 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1442 {
1443         struct rockchip_pinctrl *info = bank->drvdata;
1444         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1445         struct regmap *regmap;
1446         int reg, ret, pull_type;
1447         u8 bit;
1448         u32 data;
1449
1450         /* rk3066b does support any pulls */
1451         if (ctrl->type == RK3066B)
1452                 return PIN_CONFIG_BIAS_DISABLE;
1453
1454         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1455
1456         ret = regmap_read(regmap, reg, &data);
1457         if (ret)
1458                 return ret;
1459
1460         switch (ctrl->type) {
1461         case RK2928:
1462                 return !(data & BIT(bit))
1463                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1464                                 : PIN_CONFIG_BIAS_DISABLE;
1465         case RK3188:
1466         case RK3288:
1467         case RK3366:
1468         case RK3368:
1469         case RK3399:
1470                 pull_type = bank->pull_type[pin_num / 8];
1471                 data >>= bit;
1472                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1473
1474                 return rockchip_pull_list[pull_type][data];
1475         default:
1476                 dev_err(info->dev, "unsupported pinctrl type\n");
1477                 return -EINVAL;
1478         };
1479 }
1480
1481 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1482                                         int pin_num, int pull)
1483 {
1484         struct rockchip_pinctrl *info = bank->drvdata;
1485         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1486         struct regmap *regmap;
1487         int reg, ret, i, pull_type;
1488         unsigned long flags;
1489         u8 bit;
1490         u32 data, rmask;
1491
1492         dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
1493                  bank->bank_num, pin_num, pull);
1494
1495         /* rk3066b does support any pulls */
1496         if (ctrl->type == RK3066B)
1497                 return pull ? -EINVAL : 0;
1498
1499         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1500
1501         switch (ctrl->type) {
1502         case RK2928:
1503                 spin_lock_irqsave(&bank->slock, flags);
1504
1505                 data = BIT(bit + 16);
1506                 if (pull == PIN_CONFIG_BIAS_DISABLE)
1507                         data |= BIT(bit);
1508                 ret = regmap_write(regmap, reg, data);
1509
1510                 spin_unlock_irqrestore(&bank->slock, flags);
1511                 break;
1512         case RK3188:
1513         case RK3288:
1514         case RK3366:
1515         case RK3368:
1516         case RK3399:
1517                 pull_type = bank->pull_type[pin_num / 8];
1518                 ret = -EINVAL;
1519                 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
1520                         i++) {
1521                         if (rockchip_pull_list[pull_type][i] == pull) {
1522                                 ret = i;
1523                                 break;
1524                         }
1525                 }
1526
1527                 if (ret < 0) {
1528                         dev_err(info->dev, "unknown pull setting %d\n", pull);
1529                         return ret;
1530                 }
1531
1532                 spin_lock_irqsave(&bank->slock, flags);
1533
1534                 /* enable the write to the equivalent lower bits */
1535                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
1536                 rmask = data | (data >> 16);
1537                 data |= (ret << bit);
1538
1539                 ret = regmap_update_bits(regmap, reg, rmask, data);
1540
1541                 spin_unlock_irqrestore(&bank->slock, flags);
1542                 break;
1543         default:
1544                 dev_err(info->dev, "unsupported pinctrl type\n");
1545                 return -EINVAL;
1546         }
1547
1548         return ret;
1549 }
1550
1551 /*
1552  * Pinmux_ops handling
1553  */
1554
1555 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
1556 {
1557         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1558
1559         return info->nfunctions;
1560 }
1561
1562 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
1563                                           unsigned selector)
1564 {
1565         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1566
1567         return info->functions[selector].name;
1568 }
1569
1570 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
1571                                 unsigned selector, const char * const **groups,
1572                                 unsigned * const num_groups)
1573 {
1574         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1575
1576         *groups = info->functions[selector].groups;
1577         *num_groups = info->functions[selector].ngroups;
1578
1579         return 0;
1580 }
1581
1582 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
1583                             unsigned group)
1584 {
1585         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1586         const unsigned int *pins = info->groups[group].pins;
1587         const struct rockchip_pin_config *data = info->groups[group].data;
1588         struct rockchip_pin_bank *bank;
1589         int cnt, ret = 0;
1590
1591         dev_dbg(info->dev, "enable function %s group %s\n",
1592                 info->functions[selector].name, info->groups[group].name);
1593
1594         /*
1595          * for each pin in the pin group selected, program the correspoding pin
1596          * pin function number in the config register.
1597          */
1598         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
1599                 bank = pin_to_bank(info, pins[cnt]);
1600                 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
1601                                        data[cnt].func);
1602                 if (ret)
1603                         break;
1604         }
1605
1606         if (ret) {
1607                 /* revert the already done pin settings */
1608                 for (cnt--; cnt >= 0; cnt--)
1609                         rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
1610
1611                 return ret;
1612         }
1613
1614         return 0;
1615 }
1616
1617 /*
1618  * The calls to gpio_direction_output() and gpio_direction_input()
1619  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
1620  * function called from the gpiolib interface).
1621  */
1622 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
1623                                             int pin, bool input)
1624 {
1625         struct rockchip_pin_bank *bank;
1626         int ret;
1627         unsigned long flags;
1628         u32 data;
1629
1630         bank = gc_to_pin_bank(chip);
1631
1632         ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
1633         if (ret < 0)
1634                 return ret;
1635
1636         clk_enable(bank->clk);
1637         spin_lock_irqsave(&bank->slock, flags);
1638
1639         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1640         /* set bit to 1 for output, 0 for input */
1641         if (!input)
1642                 data |= BIT(pin);
1643         else
1644                 data &= ~BIT(pin);
1645         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1646
1647         spin_unlock_irqrestore(&bank->slock, flags);
1648         clk_disable(bank->clk);
1649
1650         return 0;
1651 }
1652
1653 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
1654                                               struct pinctrl_gpio_range *range,
1655                                               unsigned offset, bool input)
1656 {
1657         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1658         struct gpio_chip *chip;
1659         int pin;
1660
1661         chip = range->gc;
1662         pin = offset - chip->base;
1663         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
1664                  offset, range->name, pin, input ? "input" : "output");
1665
1666         return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
1667                                                 input);
1668 }
1669
1670 static const struct pinmux_ops rockchip_pmx_ops = {
1671         .get_functions_count    = rockchip_pmx_get_funcs_count,
1672         .get_function_name      = rockchip_pmx_get_func_name,
1673         .get_function_groups    = rockchip_pmx_get_groups,
1674         .set_mux                = rockchip_pmx_set,
1675         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
1676 };
1677
1678 /*
1679  * Pinconf_ops handling
1680  */
1681
1682 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
1683                                         enum pin_config_param pull)
1684 {
1685         switch (ctrl->type) {
1686         case RK2928:
1687                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
1688                                         pull == PIN_CONFIG_BIAS_DISABLE);
1689         case RK3066B:
1690                 return pull ? false : true;
1691         case RK3188:
1692         case RK3288:
1693         case RK3366:
1694         case RK3368:
1695         case RK3399:
1696                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
1697         }
1698
1699         return false;
1700 }
1701
1702 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
1703 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
1704
1705 /* set the pin config settings for a specified pin */
1706 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1707                                 unsigned long *configs, unsigned num_configs)
1708 {
1709         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1710         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1711         enum pin_config_param param;
1712         u16 arg;
1713         int i;
1714         int rc;
1715
1716         for (i = 0; i < num_configs; i++) {
1717                 param = pinconf_to_config_param(configs[i]);
1718                 arg = pinconf_to_config_argument(configs[i]);
1719
1720                 switch (param) {
1721                 case PIN_CONFIG_BIAS_DISABLE:
1722                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
1723                                 param);
1724                         if (rc)
1725                                 return rc;
1726                         break;
1727                 case PIN_CONFIG_BIAS_PULL_UP:
1728                 case PIN_CONFIG_BIAS_PULL_DOWN:
1729                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1730                 case PIN_CONFIG_BIAS_BUS_HOLD:
1731                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1732                                 return -ENOTSUPP;
1733
1734                         if (!arg)
1735                                 return -EINVAL;
1736
1737                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
1738                                 param);
1739                         if (rc)
1740                                 return rc;
1741                         break;
1742                 case PIN_CONFIG_OUTPUT:
1743                         rockchip_gpio_set(&bank->gpio_chip,
1744                                           pin - bank->pin_base, arg);
1745                         rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
1746                                           pin - bank->pin_base, false);
1747                         if (rc)
1748                                 return rc;
1749                         break;
1750                 case PIN_CONFIG_DRIVE_STRENGTH:
1751                         /* rk3288 is the first with per-pin drive-strength */
1752                         if (!info->ctrl->drv_calc_reg)
1753                                 return -ENOTSUPP;
1754
1755                         rc = rockchip_set_drive_perpin(bank,
1756                                                 pin - bank->pin_base, arg);
1757                         if (rc < 0)
1758                                 return rc;
1759                         break;
1760                 default:
1761                         return -ENOTSUPP;
1762                         break;
1763                 }
1764         } /* for each config */
1765
1766         return 0;
1767 }
1768
1769 /* get the pin config settings for a specified pin */
1770 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1771                                                         unsigned long *config)
1772 {
1773         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1774         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1775         enum pin_config_param param = pinconf_to_config_param(*config);
1776         u16 arg;
1777         int rc;
1778
1779         switch (param) {
1780         case PIN_CONFIG_BIAS_DISABLE:
1781                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1782                         return -EINVAL;
1783
1784                 arg = 0;
1785                 break;
1786         case PIN_CONFIG_BIAS_PULL_UP:
1787         case PIN_CONFIG_BIAS_PULL_DOWN:
1788         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1789         case PIN_CONFIG_BIAS_BUS_HOLD:
1790                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1791                         return -ENOTSUPP;
1792
1793                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1794                         return -EINVAL;
1795
1796                 arg = 1;
1797                 break;
1798         case PIN_CONFIG_OUTPUT:
1799                 rc = rockchip_get_mux(bank, pin - bank->pin_base);
1800                 if (rc != RK_FUNC_GPIO)
1801                         return -EINVAL;
1802
1803                 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
1804                 if (rc < 0)
1805                         return rc;
1806
1807                 arg = rc ? 1 : 0;
1808                 break;
1809         case PIN_CONFIG_DRIVE_STRENGTH:
1810                 /* rk3288 is the first with per-pin drive-strength */
1811                 if (!info->ctrl->drv_calc_reg)
1812                         return -ENOTSUPP;
1813
1814                 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
1815                 if (rc < 0)
1816                         return rc;
1817
1818                 arg = rc;
1819                 break;
1820         default:
1821                 return -ENOTSUPP;
1822                 break;
1823         }
1824
1825         *config = pinconf_to_config_packed(param, arg);
1826
1827         return 0;
1828 }
1829
1830 static const struct pinconf_ops rockchip_pinconf_ops = {
1831         .pin_config_get                 = rockchip_pinconf_get,
1832         .pin_config_set                 = rockchip_pinconf_set,
1833         .is_generic                     = true,
1834 };
1835
1836 static const struct of_device_id rockchip_bank_match[] = {
1837         { .compatible = "rockchip,gpio-bank" },
1838         { .compatible = "rockchip,rk3188-gpio-bank0" },
1839         {},
1840 };
1841
1842 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
1843                                                 struct device_node *np)
1844 {
1845         struct device_node *child;
1846
1847         for_each_child_of_node(np, child) {
1848                 if (of_match_node(rockchip_bank_match, child))
1849                         continue;
1850
1851                 info->nfunctions++;
1852                 info->ngroups += of_get_child_count(child);
1853         }
1854 }
1855
1856 static int rockchip_pinctrl_parse_groups(struct device_node *np,
1857                                               struct rockchip_pin_group *grp,
1858                                               struct rockchip_pinctrl *info,
1859                                               u32 index)
1860 {
1861         struct rockchip_pin_bank *bank;
1862         int size;
1863         const __be32 *list;
1864         int num;
1865         int i, j;
1866         int ret;
1867
1868         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1869
1870         /* Initialise group */
1871         grp->name = np->name;
1872
1873         /*
1874          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
1875          * do sanity check and calculate pins number
1876          */
1877         list = of_get_property(np, "rockchip,pins", &size);
1878         /* we do not check return since it's safe node passed down */
1879         size /= sizeof(*list);
1880         if (!size || size % 4) {
1881                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1882                 return -EINVAL;
1883         }
1884
1885         grp->npins = size / 4;
1886
1887         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1888                                                 GFP_KERNEL);
1889         grp->data = devm_kzalloc(info->dev, grp->npins *
1890                                           sizeof(struct rockchip_pin_config),
1891                                         GFP_KERNEL);
1892         if (!grp->pins || !grp->data)
1893                 return -ENOMEM;
1894
1895         for (i = 0, j = 0; i < size; i += 4, j++) {
1896                 const __be32 *phandle;
1897                 struct device_node *np_config;
1898
1899                 num = be32_to_cpu(*list++);
1900                 bank = bank_num_to_bank(info, num);
1901                 if (IS_ERR(bank))
1902                         return PTR_ERR(bank);
1903
1904                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
1905                 grp->data[j].func = be32_to_cpu(*list++);
1906
1907                 phandle = list++;
1908                 if (!phandle)
1909                         return -EINVAL;
1910
1911                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
1912                 ret = pinconf_generic_parse_dt_config(np_config, NULL,
1913                                 &grp->data[j].configs, &grp->data[j].nconfigs);
1914                 if (ret)
1915                         return ret;
1916         }
1917
1918         return 0;
1919 }
1920
1921 static int rockchip_pinctrl_parse_functions(struct device_node *np,
1922                                                 struct rockchip_pinctrl *info,
1923                                                 u32 index)
1924 {
1925         struct device_node *child;
1926         struct rockchip_pmx_func *func;
1927         struct rockchip_pin_group *grp;
1928         int ret;
1929         static u32 grp_index;
1930         u32 i = 0;
1931
1932         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1933
1934         func = &info->functions[index];
1935
1936         /* Initialise function */
1937         func->name = np->name;
1938         func->ngroups = of_get_child_count(np);
1939         if (func->ngroups <= 0)
1940                 return 0;
1941
1942         func->groups = devm_kzalloc(info->dev,
1943                         func->ngroups * sizeof(char *), GFP_KERNEL);
1944         if (!func->groups)
1945                 return -ENOMEM;
1946
1947         for_each_child_of_node(np, child) {
1948                 func->groups[i] = child->name;
1949                 grp = &info->groups[grp_index++];
1950                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
1951                 if (ret) {
1952                         of_node_put(child);
1953                         return ret;
1954                 }
1955         }
1956
1957         return 0;
1958 }
1959
1960 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1961                                               struct rockchip_pinctrl *info)
1962 {
1963         struct device *dev = &pdev->dev;
1964         struct device_node *np = dev->of_node;
1965         struct device_node *child;
1966         int ret;
1967         int i;
1968
1969         rockchip_pinctrl_child_count(info, np);
1970
1971         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1972         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1973
1974         info->functions = devm_kzalloc(dev, info->nfunctions *
1975                                               sizeof(struct rockchip_pmx_func),
1976                                               GFP_KERNEL);
1977         if (!info->functions) {
1978                 dev_err(dev, "failed to allocate memory for function list\n");
1979                 return -EINVAL;
1980         }
1981
1982         info->groups = devm_kzalloc(dev, info->ngroups *
1983                                             sizeof(struct rockchip_pin_group),
1984                                             GFP_KERNEL);
1985         if (!info->groups) {
1986                 dev_err(dev, "failed allocate memory for ping group list\n");
1987                 return -EINVAL;
1988         }
1989
1990         i = 0;
1991
1992         for_each_child_of_node(np, child) {
1993                 if (of_match_node(rockchip_bank_match, child))
1994                         continue;
1995
1996                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1997                 if (ret) {
1998                         dev_err(&pdev->dev, "failed to parse function\n");
1999                         of_node_put(child);
2000                         return ret;
2001                 }
2002         }
2003
2004         return 0;
2005 }
2006
2007 static int rockchip_pinctrl_register(struct platform_device *pdev,
2008                                         struct rockchip_pinctrl *info)
2009 {
2010         struct pinctrl_desc *ctrldesc = &info->pctl;
2011         struct pinctrl_pin_desc *pindesc, *pdesc;
2012         struct rockchip_pin_bank *pin_bank;
2013         int pin, bank, ret;
2014         int k;
2015
2016         ctrldesc->name = "rockchip-pinctrl";
2017         ctrldesc->owner = THIS_MODULE;
2018         ctrldesc->pctlops = &rockchip_pctrl_ops;
2019         ctrldesc->pmxops = &rockchip_pmx_ops;
2020         ctrldesc->confops = &rockchip_pinconf_ops;
2021
2022         pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
2023                         info->ctrl->nr_pins, GFP_KERNEL);
2024         if (!pindesc) {
2025                 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
2026                 return -ENOMEM;
2027         }
2028         ctrldesc->pins = pindesc;
2029         ctrldesc->npins = info->ctrl->nr_pins;
2030
2031         pdesc = pindesc;
2032         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
2033                 pin_bank = &info->ctrl->pin_banks[bank];
2034                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2035                         pdesc->number = k;
2036                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
2037                                                 pin_bank->name, pin);
2038                         pdesc++;
2039                 }
2040         }
2041
2042         ret = rockchip_pinctrl_parse_dt(pdev, info);
2043         if (ret)
2044                 return ret;
2045
2046         info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
2047         if (IS_ERR(info->pctl_dev)) {
2048                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
2049                 return PTR_ERR(info->pctl_dev);
2050         }
2051
2052         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
2053                 pin_bank = &info->ctrl->pin_banks[bank];
2054                 pin_bank->grange.name = pin_bank->name;
2055                 pin_bank->grange.id = bank;
2056                 pin_bank->grange.pin_base = pin_bank->pin_base;
2057                 pin_bank->grange.base = pin_bank->gpio_chip.base;
2058                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
2059                 pin_bank->grange.gc = &pin_bank->gpio_chip;
2060                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
2061         }
2062
2063         return 0;
2064 }
2065
2066 /*
2067  * GPIO handling
2068  */
2069
2070 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2071 {
2072         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2073         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
2074         unsigned long flags;
2075         u32 data;
2076
2077         clk_enable(bank->clk);
2078         spin_lock_irqsave(&bank->slock, flags);
2079
2080         data = readl(reg);
2081         data &= ~BIT(offset);
2082         if (value)
2083                 data |= BIT(offset);
2084         writel(data, reg);
2085
2086         spin_unlock_irqrestore(&bank->slock, flags);
2087         clk_disable(bank->clk);
2088 }
2089
2090 /*
2091  * Returns the level of the pin for input direction and setting of the DR
2092  * register for output gpios.
2093  */
2094 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
2095 {
2096         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2097         u32 data;
2098
2099         clk_enable(bank->clk);
2100         data = readl(bank->reg_base + GPIO_EXT_PORT);
2101         clk_disable(bank->clk);
2102         data >>= offset;
2103         data &= 1;
2104         return data;
2105 }
2106
2107 /*
2108  * gpiolib gpio_direction_input callback function. The setting of the pin
2109  * mux function as 'gpio input' will be handled by the pinctrl susbsystem
2110  * interface.
2111  */
2112 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2113 {
2114         return pinctrl_gpio_direction_input(gc->base + offset);
2115 }
2116
2117 /*
2118  * gpiolib gpio_direction_output callback function. The setting of the pin
2119  * mux function as 'gpio output' will be handled by the pinctrl susbsystem
2120  * interface.
2121  */
2122 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
2123                                           unsigned offset, int value)
2124 {
2125         rockchip_gpio_set(gc, offset, value);
2126         return pinctrl_gpio_direction_output(gc->base + offset);
2127 }
2128
2129 /*
2130  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
2131  * and a virtual IRQ, if not already present.
2132  */
2133 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2134 {
2135         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2136         unsigned int virq;
2137
2138         if (!bank->domain)
2139                 return -ENXIO;
2140
2141         virq = irq_create_mapping(bank->domain, offset);
2142
2143         return (virq) ? : -ENXIO;
2144 }
2145
2146 static const struct gpio_chip rockchip_gpiolib_chip = {
2147         .request = gpiochip_generic_request,
2148         .free = gpiochip_generic_free,
2149         .set = rockchip_gpio_set,
2150         .get = rockchip_gpio_get,
2151         .direction_input = rockchip_gpio_direction_input,
2152         .direction_output = rockchip_gpio_direction_output,
2153         .to_irq = rockchip_gpio_to_irq,
2154         .owner = THIS_MODULE,
2155 };
2156
2157 /*
2158  * Interrupt handling
2159  */
2160
2161 static void rockchip_irq_demux(struct irq_desc *desc)
2162 {
2163         struct irq_chip *chip = irq_desc_get_chip(desc);
2164         struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
2165         u32 pend;
2166
2167         dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
2168
2169         chained_irq_enter(chip, desc);
2170
2171         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2172
2173         while (pend) {
2174                 unsigned int irq, virq;
2175
2176                 irq = __ffs(pend);
2177                 pend &= ~BIT(irq);
2178                 virq = irq_linear_revmap(bank->domain, irq);
2179
2180                 if (!virq) {
2181                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2182                         continue;
2183                 }
2184
2185                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2186
2187                 /*
2188                  * Triggering IRQ on both rising and falling edge
2189                  * needs manual intervention.
2190                  */
2191                 if (bank->toggle_edge_mode & BIT(irq)) {
2192                         u32 data, data_old, polarity;
2193                         unsigned long flags;
2194
2195                         data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
2196                         do {
2197                                 spin_lock_irqsave(&bank->slock, flags);
2198
2199                                 polarity = readl_relaxed(bank->reg_base +
2200                                                          GPIO_INT_POLARITY);
2201                                 if (data & BIT(irq))
2202                                         polarity &= ~BIT(irq);
2203                                 else
2204                                         polarity |= BIT(irq);
2205                                 writel(polarity,
2206                                        bank->reg_base + GPIO_INT_POLARITY);
2207
2208                                 spin_unlock_irqrestore(&bank->slock, flags);
2209
2210                                 data_old = data;
2211                                 data = readl_relaxed(bank->reg_base +
2212                                                      GPIO_EXT_PORT);
2213                         } while ((data & BIT(irq)) != (data_old & BIT(irq)));
2214                 }
2215
2216                 generic_handle_irq(virq);
2217         }
2218
2219         chained_irq_exit(chip, desc);
2220 }
2221
2222 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
2223 {
2224         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2225         struct rockchip_pin_bank *bank = gc->private;
2226         u32 mask = BIT(d->hwirq);
2227         u32 polarity;
2228         u32 level;
2229         u32 data;
2230         unsigned long flags;
2231         int ret;
2232
2233         /* make sure the pin is configured as gpio input */
2234         ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
2235         if (ret < 0)
2236                 return ret;
2237
2238         clk_enable(bank->clk);
2239         spin_lock_irqsave(&bank->slock, flags);
2240
2241         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2242         data &= ~mask;
2243         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2244
2245         spin_unlock_irqrestore(&bank->slock, flags);
2246
2247         if (type & IRQ_TYPE_EDGE_BOTH)
2248                 irq_set_handler_locked(d, handle_edge_irq);
2249         else
2250                 irq_set_handler_locked(d, handle_level_irq);
2251
2252         spin_lock_irqsave(&bank->slock, flags);
2253         irq_gc_lock(gc);
2254
2255         level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
2256         polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
2257
2258         switch (type) {
2259         case IRQ_TYPE_EDGE_BOTH:
2260                 bank->toggle_edge_mode |= mask;
2261                 level |= mask;
2262
2263                 /*
2264                  * Determine gpio state. If 1 next interrupt should be falling
2265                  * otherwise rising.
2266                  */
2267                 data = readl(bank->reg_base + GPIO_EXT_PORT);
2268                 if (data & mask)
2269                         polarity &= ~mask;
2270                 else
2271                         polarity |= mask;
2272                 break;
2273         case IRQ_TYPE_EDGE_RISING:
2274                 bank->toggle_edge_mode &= ~mask;
2275                 level |= mask;
2276                 polarity |= mask;
2277                 break;
2278         case IRQ_TYPE_EDGE_FALLING:
2279                 bank->toggle_edge_mode &= ~mask;
2280                 level |= mask;
2281                 polarity &= ~mask;
2282                 break;
2283         case IRQ_TYPE_LEVEL_HIGH:
2284                 bank->toggle_edge_mode &= ~mask;
2285                 level &= ~mask;
2286                 polarity |= mask;
2287                 break;
2288         case IRQ_TYPE_LEVEL_LOW:
2289                 bank->toggle_edge_mode &= ~mask;
2290                 level &= ~mask;
2291                 polarity &= ~mask;
2292                 break;
2293         default:
2294                 irq_gc_unlock(gc);
2295                 spin_unlock_irqrestore(&bank->slock, flags);
2296                 clk_disable(bank->clk);
2297                 return -EINVAL;
2298         }
2299
2300         writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
2301         writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
2302
2303         irq_gc_unlock(gc);
2304         spin_unlock_irqrestore(&bank->slock, flags);
2305         clk_disable(bank->clk);
2306
2307         return 0;
2308 }
2309
2310 static void rockchip_irq_suspend(struct irq_data *d)
2311 {
2312         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2313         struct rockchip_pin_bank *bank = gc->private;
2314
2315         clk_enable(bank->clk);
2316         bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
2317         irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
2318         clk_disable(bank->clk);
2319 }
2320
2321 static void rockchip_irq_resume(struct irq_data *d)
2322 {
2323         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2324         struct rockchip_pin_bank *bank = gc->private;
2325
2326         clk_enable(bank->clk);
2327         irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
2328         clk_disable(bank->clk);
2329 }
2330
2331 static void rockchip_irq_gc_mask_clr_bit(struct irq_data *d)
2332 {
2333         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2334         struct rockchip_pin_bank *bank = gc->private;
2335
2336         clk_enable(bank->clk);
2337         irq_gc_mask_clr_bit(d);
2338 }
2339
2340 void rockchip_irq_gc_mask_set_bit(struct irq_data *d)
2341 {
2342         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2343         struct rockchip_pin_bank *bank = gc->private;
2344
2345         irq_gc_mask_set_bit(d);
2346         clk_disable(bank->clk);
2347 }
2348
2349 static int rockchip_interrupts_register(struct platform_device *pdev,
2350                                                 struct rockchip_pinctrl *info)
2351 {
2352         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2353         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2354         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
2355         struct irq_chip_generic *gc;
2356         int ret;
2357         int i, j;
2358
2359         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2360                 if (!bank->valid) {
2361                         dev_warn(&pdev->dev, "bank %s is not valid\n",
2362                                  bank->name);
2363                         continue;
2364                 }
2365
2366                 ret = clk_enable(bank->clk);
2367                 if (ret) {
2368                         dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
2369                                 bank->name);
2370                         continue;
2371                 }
2372
2373                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
2374                                                 &irq_generic_chip_ops, NULL);
2375                 if (!bank->domain) {
2376                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
2377                                  bank->name);
2378                         clk_disable(bank->clk);
2379                         continue;
2380                 }
2381
2382                 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
2383                                          bank->name, handle_level_irq,
2384                                          clr, 0, IRQ_GC_INIT_MASK_CACHE);
2385                 if (ret) {
2386                         dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
2387                                 bank->name);
2388                         irq_domain_remove(bank->domain);
2389                         clk_disable(bank->clk);
2390                         continue;
2391                 }
2392
2393                 /*
2394                  * Linux assumes that all interrupts start out disabled/masked.
2395                  * Our driver only uses the concept of masked and always keeps
2396                  * things enabled, so for us that's all masked and all enabled.
2397                  */
2398                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
2399                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
2400
2401                 gc = irq_get_domain_generic_chip(bank->domain, 0);
2402                 gc->reg_base = bank->reg_base;
2403                 gc->private = bank;
2404                 gc->chip_types[0].regs.mask = GPIO_INTMASK;
2405                 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
2406                 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
2407                 gc->chip_types[0].chip.irq_mask = rockchip_irq_gc_mask_set_bit;
2408                 gc->chip_types[0].chip.irq_unmask =
2409                                                   rockchip_irq_gc_mask_clr_bit;
2410                 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
2411                 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
2412                 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
2413                 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
2414                 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
2415
2416                 irq_set_chained_handler_and_data(bank->irq,
2417                                                  rockchip_irq_demux, bank);
2418
2419                 /* map the gpio irqs here, when the clock is still running */
2420                 for (j = 0 ; j < 32 ; j++)
2421                         irq_create_mapping(bank->domain, j);
2422
2423                 clk_disable(bank->clk);
2424         }
2425
2426         return 0;
2427 }
2428
2429 static int rockchip_gpiolib_register(struct platform_device *pdev,
2430                                                 struct rockchip_pinctrl *info)
2431 {
2432         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2433         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2434         struct gpio_chip *gc;
2435         int ret;
2436         int i;
2437
2438         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2439                 if (!bank->valid) {
2440                         dev_warn(&pdev->dev, "bank %s is not valid\n",
2441                                  bank->name);
2442                         continue;
2443                 }
2444
2445                 bank->gpio_chip = rockchip_gpiolib_chip;
2446
2447                 gc = &bank->gpio_chip;
2448                 gc->base = bank->pin_base;
2449                 gc->ngpio = bank->nr_pins;
2450                 gc->dev = &pdev->dev;
2451                 gc->of_node = bank->of_node;
2452                 gc->label = bank->name;
2453
2454                 ret = gpiochip_add(gc);
2455                 if (ret) {
2456                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
2457                                                         gc->label, ret);
2458                         goto fail;
2459                 }
2460         }
2461
2462         rockchip_interrupts_register(pdev, info);
2463
2464         return 0;
2465
2466 fail:
2467         for (--i, --bank; i >= 0; --i, --bank) {
2468                 if (!bank->valid)
2469                         continue;
2470                 gpiochip_remove(&bank->gpio_chip);
2471         }
2472         return ret;
2473 }
2474
2475 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
2476                                                 struct rockchip_pinctrl *info)
2477 {
2478         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2479         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2480         int i;
2481
2482         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2483                 if (!bank->valid)
2484                         continue;
2485                 gpiochip_remove(&bank->gpio_chip);
2486         }
2487
2488         return 0;
2489 }
2490
2491 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
2492                                   struct rockchip_pinctrl *info)
2493 {
2494         struct resource res;
2495         void __iomem *base;
2496
2497         if (of_address_to_resource(bank->of_node, 0, &res)) {
2498                 dev_err(info->dev, "cannot find IO resource for bank\n");
2499                 return -ENOENT;
2500         }
2501
2502         bank->reg_base = devm_ioremap_resource(info->dev, &res);
2503         if (IS_ERR(bank->reg_base))
2504                 return PTR_ERR(bank->reg_base);
2505
2506         /*
2507          * special case, where parts of the pull setting-registers are
2508          * part of the PMU register space
2509          */
2510         if (of_device_is_compatible(bank->of_node,
2511                                     "rockchip,rk3188-gpio-bank0")) {
2512                 struct device_node *node;
2513
2514                 node = of_parse_phandle(bank->of_node->parent,
2515                                         "rockchip,pmu", 0);
2516                 if (!node) {
2517                         if (of_address_to_resource(bank->of_node, 1, &res)) {
2518                                 dev_err(info->dev, "cannot find IO resource for bank\n");
2519                                 return -ENOENT;
2520                         }
2521
2522                         base = devm_ioremap_resource(info->dev, &res);
2523                         if (IS_ERR(base))
2524                                 return PTR_ERR(base);
2525                         rockchip_regmap_config.max_register =
2526                                                     resource_size(&res) - 4;
2527                         rockchip_regmap_config.name =
2528                                             "rockchip,rk3188-gpio-bank0-pull";
2529                         bank->regmap_pull = devm_regmap_init_mmio(info->dev,
2530                                                     base,
2531                                                     &rockchip_regmap_config);
2532                 }
2533         }
2534
2535         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
2536
2537         bank->clk = of_clk_get(bank->of_node, 0);
2538         if (IS_ERR(bank->clk))
2539                 return PTR_ERR(bank->clk);
2540
2541         return clk_prepare(bank->clk);
2542 }
2543
2544 static const struct of_device_id rockchip_pinctrl_dt_match[];
2545
2546 /* retrieve the soc specific data */
2547 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
2548                                                 struct rockchip_pinctrl *d,
2549                                                 struct platform_device *pdev)
2550 {
2551         const struct of_device_id *match;
2552         struct device_node *node = pdev->dev.of_node;
2553         struct device_node *np;
2554         struct rockchip_pin_ctrl *ctrl;
2555         struct rockchip_pin_bank *bank;
2556         int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
2557
2558         match = of_match_node(rockchip_pinctrl_dt_match, node);
2559         ctrl = (struct rockchip_pin_ctrl *)match->data;
2560
2561         for_each_child_of_node(node, np) {
2562                 if (!of_find_property(np, "gpio-controller", NULL))
2563                         continue;
2564
2565                 bank = ctrl->pin_banks;
2566                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2567                         if (!strcmp(bank->name, np->name)) {
2568                                 bank->of_node = np;
2569
2570                                 if (!rockchip_get_bank_data(bank, d))
2571                                         bank->valid = true;
2572
2573                                 break;
2574                         }
2575                 }
2576         }
2577
2578         grf_offs = ctrl->grf_mux_offset;
2579         pmu_offs = ctrl->pmu_mux_offset;
2580         drv_pmu_offs = ctrl->pmu_drv_offset;
2581         drv_grf_offs = ctrl->grf_drv_offset;
2582         bank = ctrl->pin_banks;
2583         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2584                 int bank_pins = 0;
2585
2586                 spin_lock_init(&bank->slock);
2587                 bank->drvdata = d;
2588                 bank->pin_base = ctrl->nr_pins;
2589                 ctrl->nr_pins += bank->nr_pins;
2590
2591                 /* calculate iomux and drv offsets */
2592                 for (j = 0; j < 4; j++) {
2593                         struct rockchip_iomux *iom = &bank->iomux[j];
2594                         struct rockchip_drv *drv = &bank->drv[j];
2595                         int inc;
2596
2597                         if (bank_pins >= bank->nr_pins)
2598                                 break;
2599
2600                         /* preset iomux offset value, set new start value */
2601                         if (iom->offset >= 0) {
2602                                 if (iom->type & IOMUX_SOURCE_PMU)
2603                                         pmu_offs = iom->offset;
2604                                 else
2605                                         grf_offs = iom->offset;
2606                         } else { /* set current iomux offset */
2607                                 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2608                                                         pmu_offs : grf_offs;
2609                         }
2610
2611                         /* preset drv offset value, set new start value */
2612                         if (drv->offset >= 0) {
2613                                 if (iom->type & IOMUX_SOURCE_PMU)
2614                                         drv_pmu_offs = drv->offset;
2615                                 else
2616                                         drv_grf_offs = drv->offset;
2617                         } else { /* set current drv offset */
2618                                 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2619                                                 drv_pmu_offs : drv_grf_offs;
2620                         }
2621
2622                         dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
2623                                 i, j, iom->offset, drv->offset);
2624
2625                         /*
2626                          * Increase offset according to iomux width.
2627                          * 4bit iomux'es are spread over two registers.
2628                          */
2629                         inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4;
2630                         if (iom->type & IOMUX_SOURCE_PMU)
2631                                 pmu_offs += inc;
2632                         else
2633                                 grf_offs += inc;
2634
2635                         /*
2636                          * Increase offset according to drv width.
2637                          * 3bit drive-strenth'es are spread over two registers.
2638                          */
2639                         if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2640                             (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
2641                                 inc = 8;
2642                         else
2643                                 inc = 4;
2644
2645                         if (iom->type & IOMUX_SOURCE_PMU)
2646                                 drv_pmu_offs += inc;
2647                         else
2648                                 drv_grf_offs += inc;
2649
2650                         bank_pins += 8;
2651                 }
2652         }
2653
2654         return ctrl;
2655 }
2656
2657 #define RK3288_GRF_GPIO6C_IOMUX         0x64
2658 #define GPIO6C6_SEL_WRITE_ENABLE        BIT(28)
2659
2660 static u32 rk3288_grf_gpio6c_iomux;
2661
2662 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
2663 {
2664         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2665         int ret = pinctrl_force_sleep(info->pctl_dev);
2666
2667         if (ret)
2668                 return ret;
2669
2670         /*
2671          * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
2672          * the setting here, and restore it at resume.
2673          */
2674         if (info->ctrl->type == RK3288) {
2675                 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2676                                   &rk3288_grf_gpio6c_iomux);
2677                 if (ret) {
2678                         pinctrl_force_default(info->pctl_dev);
2679                         return ret;
2680                 }
2681         }
2682
2683         return 0;
2684 }
2685
2686 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
2687 {
2688         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2689         int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2690                                rk3288_grf_gpio6c_iomux |
2691                                GPIO6C6_SEL_WRITE_ENABLE);
2692
2693         if (ret)
2694                 return ret;
2695
2696         return pinctrl_force_default(info->pctl_dev);
2697 }
2698
2699 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
2700                          rockchip_pinctrl_resume);
2701
2702 static int rockchip_pinctrl_probe(struct platform_device *pdev)
2703 {
2704         struct rockchip_pinctrl *info;
2705         struct device *dev = &pdev->dev;
2706         struct rockchip_pin_ctrl *ctrl;
2707         struct device_node *np = pdev->dev.of_node, *node;
2708         struct resource *res;
2709         void __iomem *base;
2710         int ret;
2711
2712         if (!dev->of_node) {
2713                 dev_err(dev, "device tree node not found\n");
2714                 return -ENODEV;
2715         }
2716
2717         info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
2718         if (!info)
2719                 return -ENOMEM;
2720
2721         info->dev = dev;
2722
2723         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2724         if (!ctrl) {
2725                 dev_err(dev, "driver data not available\n");
2726                 return -EINVAL;
2727         }
2728         info->ctrl = ctrl;
2729
2730         node = of_parse_phandle(np, "rockchip,grf", 0);
2731         if (node) {
2732                 info->regmap_base = syscon_node_to_regmap(node);
2733                 if (IS_ERR(info->regmap_base))
2734                         return PTR_ERR(info->regmap_base);
2735         } else {
2736                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2737                 base = devm_ioremap_resource(&pdev->dev, res);
2738                 if (IS_ERR(base))
2739                         return PTR_ERR(base);
2740
2741                 rockchip_regmap_config.max_register = resource_size(res) - 4;
2742                 rockchip_regmap_config.name = "rockchip,pinctrl";
2743                 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
2744                                                     &rockchip_regmap_config);
2745
2746                 /* to check for the old dt-bindings */
2747                 info->reg_size = resource_size(res);
2748
2749                 /* Honor the old binding, with pull registers as 2nd resource */
2750                 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
2751                         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2752                         base = devm_ioremap_resource(&pdev->dev, res);
2753                         if (IS_ERR(base))
2754                                 return PTR_ERR(base);
2755
2756                         rockchip_regmap_config.max_register =
2757                                                         resource_size(res) - 4;
2758                         rockchip_regmap_config.name = "rockchip,pinctrl-pull";
2759                         info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
2760                                                     base,
2761                                                     &rockchip_regmap_config);
2762                 }
2763         }
2764
2765         /* try to find the optional reference to the pmu syscon */
2766         node = of_parse_phandle(np, "rockchip,pmu", 0);
2767         if (node) {
2768                 info->regmap_pmu = syscon_node_to_regmap(node);
2769                 if (IS_ERR(info->regmap_pmu))
2770                         return PTR_ERR(info->regmap_pmu);
2771         }
2772
2773         ret = rockchip_gpiolib_register(pdev, info);
2774         if (ret)
2775                 return ret;
2776
2777         ret = rockchip_pinctrl_register(pdev, info);
2778         if (ret) {
2779                 rockchip_gpiolib_unregister(pdev, info);
2780                 return ret;
2781         }
2782
2783         platform_set_drvdata(pdev, info);
2784
2785         return 0;
2786 }
2787
2788 static struct rockchip_pin_bank rk2928_pin_banks[] = {
2789         PIN_BANK(0, 32, "gpio0"),
2790         PIN_BANK(1, 32, "gpio1"),
2791         PIN_BANK(2, 32, "gpio2"),
2792         PIN_BANK(3, 32, "gpio3"),
2793 };
2794
2795 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2796                 .pin_banks              = rk2928_pin_banks,
2797                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
2798                 .label                  = "RK2928-GPIO",
2799                 .type                   = RK2928,
2800                 .grf_mux_offset         = 0xa8,
2801                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2802 };
2803
2804 static struct rockchip_pin_bank rk3036_pin_banks[] = {
2805         PIN_BANK(0, 32, "gpio0"),
2806         PIN_BANK(1, 32, "gpio1"),
2807         PIN_BANK(2, 32, "gpio2"),
2808 };
2809
2810 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
2811                 .pin_banks              = rk3036_pin_banks,
2812                 .nr_banks               = ARRAY_SIZE(rk3036_pin_banks),
2813                 .label                  = "RK3036-GPIO",
2814                 .type                   = RK2928,
2815                 .grf_mux_offset         = 0xa8,
2816                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2817 };
2818
2819 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
2820         PIN_BANK(0, 32, "gpio0"),
2821         PIN_BANK(1, 32, "gpio1"),
2822         PIN_BANK(2, 32, "gpio2"),
2823         PIN_BANK(3, 32, "gpio3"),
2824         PIN_BANK(4, 32, "gpio4"),
2825         PIN_BANK(6, 16, "gpio6"),
2826 };
2827
2828 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
2829                 .pin_banks              = rk3066a_pin_banks,
2830                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
2831                 .label                  = "RK3066a-GPIO",
2832                 .type                   = RK2928,
2833                 .grf_mux_offset         = 0xa8,
2834                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2835 };
2836
2837 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
2838         PIN_BANK(0, 32, "gpio0"),
2839         PIN_BANK(1, 32, "gpio1"),
2840         PIN_BANK(2, 32, "gpio2"),
2841         PIN_BANK(3, 32, "gpio3"),
2842 };
2843
2844 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2845                 .pin_banks      = rk3066b_pin_banks,
2846                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
2847                 .label          = "RK3066b-GPIO",
2848                 .type           = RK3066B,
2849                 .grf_mux_offset = 0x60,
2850 };
2851
2852 static struct rockchip_pin_bank rk3188_pin_banks[] = {
2853         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
2854         PIN_BANK(1, 32, "gpio1"),
2855         PIN_BANK(2, 32, "gpio2"),
2856         PIN_BANK(3, 32, "gpio3"),
2857 };
2858
2859 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
2860                 .pin_banks              = rk3188_pin_banks,
2861                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
2862                 .label                  = "RK3188-GPIO",
2863                 .type                   = RK3188,
2864                 .grf_mux_offset         = 0x60,
2865                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
2866 };
2867
2868 static struct rockchip_pin_bank rk3228_pin_banks[] = {
2869         PIN_BANK(0, 32, "gpio0"),
2870         PIN_BANK(1, 32, "gpio1"),
2871         PIN_BANK(2, 32, "gpio2"),
2872         PIN_BANK(3, 32, "gpio3"),
2873 };
2874
2875 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
2876                 .pin_banks              = rk3228_pin_banks,
2877                 .nr_banks               = ARRAY_SIZE(rk3228_pin_banks),
2878                 .label                  = "RK3228-GPIO",
2879                 .type                   = RK3288,
2880                 .grf_mux_offset         = 0x0,
2881                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
2882                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
2883 };
2884
2885 static struct rockchip_pin_bank rk3288_pin_banks[] = {
2886         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
2887                                              IOMUX_SOURCE_PMU,
2888                                              IOMUX_SOURCE_PMU,
2889                                              IOMUX_UNROUTED
2890                             ),
2891         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
2892                                              IOMUX_UNROUTED,
2893                                              IOMUX_UNROUTED,
2894                                              0
2895                             ),
2896         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
2897         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
2898         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
2899                                              IOMUX_WIDTH_4BIT,
2900                                              0,
2901                                              0
2902                             ),
2903         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
2904                                              0,
2905                                              0,
2906                                              IOMUX_UNROUTED
2907                             ),
2908         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
2909         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
2910                                              0,
2911                                              IOMUX_WIDTH_4BIT,
2912                                              IOMUX_UNROUTED
2913                             ),
2914         PIN_BANK(8, 16, "gpio8"),
2915 };
2916
2917 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
2918                 .pin_banks              = rk3288_pin_banks,
2919                 .nr_banks               = ARRAY_SIZE(rk3288_pin_banks),
2920                 .label                  = "RK3288-GPIO",
2921                 .type                   = RK3288,
2922                 .grf_mux_offset         = 0x0,
2923                 .pmu_mux_offset         = 0x84,
2924                 .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
2925                 .drv_calc_reg           = rk3288_calc_drv_reg_and_bit,
2926 };
2927
2928 static struct rockchip_pin_bank rk3366_pin_banks[] = {
2929         PIN_BANK_IOMUX_DRV_FLAGS(0, 32, "gpio0",
2930                                  IOMUX_SOURCE_PMU,
2931                                  IOMUX_SOURCE_PMU,
2932                                  IOMUX_SOURCE_PMU,
2933                                  IOMUX_SOURCE_PMU,
2934                                  DRV_TYPE_IO_NARROW_LEVEL,
2935                                  DRV_TYPE_IO_NARROW_LEVEL,
2936                                  DRV_TYPE_IO_NARROW_LEVEL,
2937                                  DRV_TYPE_IO_NARROW_LEVEL
2938                                  ),
2939         PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(1, 32, "gpio1",
2940                                               IOMUX_SOURCE_PMU,
2941                                               IOMUX_SOURCE_PMU,
2942                                               IOMUX_SOURCE_PMU,
2943                                               IOMUX_SOURCE_PMU,
2944                                               0x30,
2945                                               0x34,
2946                                               0x38,
2947                                               0x3c,
2948                                               DRV_TYPE_IO_NARROW_LEVEL,
2949                                               DRV_TYPE_IO_NARROW_LEVEL,
2950                                               DRV_TYPE_IO_NARROW_LEVEL,
2951                                               DRV_TYPE_IO_NARROW_LEVEL
2952                                               ),
2953         PIN_BANK_DRV_FLAGS(2, 32, "gpio2",
2954                            DRV_TYPE_IO_WIDE_LEVEL,
2955                            DRV_TYPE_IO_NARROW_LEVEL,
2956                            DRV_TYPE_IO_WIDE_LEVEL,
2957                            DRV_TYPE_IO_NARROW_LEVEL
2958                            ),
2959         PIN_BANK_DRV_FLAGS(3, 32, "gpio3",
2960                            DRV_TYPE_IO_NARROW_LEVEL,
2961                            DRV_TYPE_IO_NARROW_LEVEL,
2962                            DRV_TYPE_IO_NARROW_LEVEL,
2963                            DRV_TYPE_IO_NARROW_LEVEL
2964                            ),
2965         PIN_BANK_DRV_FLAGS(4, 32, "gpio4",
2966                            DRV_TYPE_IO_NARROW_LEVEL,
2967                            DRV_TYPE_IO_NARROW_LEVEL,
2968                            DRV_TYPE_IO_NARROW_LEVEL,
2969                            DRV_TYPE_IO_NARROW_LEVEL
2970                            ),
2971         PIN_BANK_DRV_FLAGS(5, 32, "gpio5",
2972                            DRV_TYPE_IO_NARROW_LEVEL,
2973                            DRV_TYPE_IO_NARROW_LEVEL,
2974                            DRV_TYPE_IO_NARROW_LEVEL,
2975                            DRV_TYPE_IO_NARROW_LEVEL
2976                            ),
2977 };
2978
2979 static struct rockchip_pin_ctrl rk3366_pin_ctrl = {
2980                 .pin_banks              = rk3366_pin_banks,
2981                 .nr_banks               = ARRAY_SIZE(rk3366_pin_banks),
2982                 .label                  = "RK3366-GPIO",
2983                 .type                   = RK3366,
2984                 .grf_mux_offset         = 0x10,
2985                 .pmu_mux_offset         = 0x0,
2986                 .pull_calc_reg          = rk3366_calc_pull_reg_and_bit,
2987                 .drv_calc_reg           = rk3366_calc_drv_reg_and_bit,
2988                 .drv_calc_extra_reg     = rk3366_calc_drv_extra_reg_and_bit,
2989 };
2990
2991 static struct rockchip_pin_bank rk3368_pin_banks[] = {
2992         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2993                                              IOMUX_SOURCE_PMU,
2994                                              IOMUX_SOURCE_PMU,
2995                                              IOMUX_SOURCE_PMU
2996                             ),
2997         PIN_BANK(1, 32, "gpio1"),
2998         PIN_BANK(2, 32, "gpio2"),
2999         PIN_BANK(3, 32, "gpio3"),
3000 };
3001
3002 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3003                 .pin_banks              = rk3368_pin_banks,
3004                 .nr_banks               = ARRAY_SIZE(rk3368_pin_banks),
3005                 .label                  = "RK3368-GPIO",
3006                 .type                   = RK3368,
3007                 .grf_mux_offset         = 0x0,
3008                 .pmu_mux_offset         = 0x0,
3009                 .pull_calc_reg          = rk3368_calc_pull_reg_and_bit,
3010                 .drv_calc_reg           = rk3368_calc_drv_reg_and_bit,
3011 };
3012
3013 static struct rockchip_pin_bank rk3399_pin_banks[] = {
3014         PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3015                                                          IOMUX_SOURCE_PMU,
3016                                                          IOMUX_SOURCE_PMU,
3017                                                          IOMUX_SOURCE_PMU,
3018                                                          IOMUX_SOURCE_PMU,
3019                                                          DRV_TYPE_IO_1V8_ONLY,
3020                                                          DRV_TYPE_IO_1V8_ONLY,
3021                                                          DRV_TYPE_IO_DEFAULT,
3022                                                          DRV_TYPE_IO_DEFAULT,
3023                                                          0x0,
3024                                                          0x8,
3025                                                          -1,
3026                                                          -1,
3027                                                          PULL_TYPE_IO_1V8_ONLY,
3028                                                          PULL_TYPE_IO_1V8_ONLY,
3029                                                          PULL_TYPE_IO_DEFAULT,
3030                                                          PULL_TYPE_IO_DEFAULT),
3031         PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3032                                               IOMUX_SOURCE_PMU,
3033                                               IOMUX_SOURCE_PMU,
3034                                               IOMUX_SOURCE_PMU,
3035                                               DRV_TYPE_IO_1V8_OR_3V0,
3036                                               DRV_TYPE_IO_1V8_OR_3V0,
3037                                               DRV_TYPE_IO_1V8_OR_3V0,
3038                                               DRV_TYPE_IO_1V8_OR_3V0,
3039                                               0x20,
3040                                               0x28,
3041                                               0x30,
3042                                               0x38
3043                                               ),
3044         PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3045                                       DRV_TYPE_IO_1V8_OR_3V0,
3046                                       DRV_TYPE_IO_1V8_ONLY,
3047                                       DRV_TYPE_IO_1V8_ONLY,
3048                                       PULL_TYPE_IO_DEFAULT,
3049                                       PULL_TYPE_IO_DEFAULT,
3050                                       PULL_TYPE_IO_1V8_ONLY,
3051                                       PULL_TYPE_IO_1V8_ONLY
3052                                       ),
3053         PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3054                            DRV_TYPE_IO_3V3_ONLY,
3055                            DRV_TYPE_IO_3V3_ONLY,
3056                            DRV_TYPE_IO_1V8_OR_3V0
3057                            ),
3058         PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3059                            DRV_TYPE_IO_1V8_3V0_AUTO,
3060                            DRV_TYPE_IO_1V8_OR_3V0,
3061                            DRV_TYPE_IO_1V8_OR_3V0
3062                            ),
3063 };
3064
3065 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3066                 .pin_banks              = rk3399_pin_banks,
3067                 .nr_banks               = ARRAY_SIZE(rk3399_pin_banks),
3068                 .label                  = "RK3399-GPIO",
3069                 .type                   = RK3399,
3070                 .grf_mux_offset         = 0xe000,
3071                 .pmu_mux_offset         = 0x0,
3072                 .grf_drv_offset         = 0xe100,
3073                 .pmu_drv_offset         = 0x80,
3074                 .pull_calc_reg          = rk3399_calc_pull_reg_and_bit,
3075                 .drv_calc_reg           = rk3399_calc_drv_reg_and_bit,
3076 };
3077
3078 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3079         { .compatible = "rockchip,rk2928-pinctrl",
3080                 .data = (void *)&rk2928_pin_ctrl },
3081         { .compatible = "rockchip,rk3036-pinctrl",
3082                 .data = (void *)&rk3036_pin_ctrl },
3083         { .compatible = "rockchip,rk3066a-pinctrl",
3084                 .data = (void *)&rk3066a_pin_ctrl },
3085         { .compatible = "rockchip,rk3066b-pinctrl",
3086                 .data = (void *)&rk3066b_pin_ctrl },
3087         { .compatible = "rockchip,rk3188-pinctrl",
3088                 .data = (void *)&rk3188_pin_ctrl },
3089         { .compatible = "rockchip,rk3228-pinctrl",
3090                 .data = (void *)&rk3228_pin_ctrl },
3091         { .compatible = "rockchip,rk3288-pinctrl",
3092                 .data = (void *)&rk3288_pin_ctrl },
3093         { .compatible = "rockchip,rk3366-pinctrl",
3094                 .data = (void *)&rk3366_pin_ctrl },
3095         { .compatible = "rockchip,rk3368-pinctrl",
3096                 .data = (void *)&rk3368_pin_ctrl },
3097         { .compatible = "rockchip,rk3399-pinctrl",
3098                 .data = (void *)&rk3399_pin_ctrl },
3099         {},
3100 };
3101 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
3102
3103 static struct platform_driver rockchip_pinctrl_driver = {
3104         .probe          = rockchip_pinctrl_probe,
3105         .driver = {
3106                 .name   = "rockchip-pinctrl",
3107                 .pm = &rockchip_pinctrl_dev_pm_ops,
3108                 .of_match_table = rockchip_pinctrl_dt_match,
3109         },
3110 };
3111
3112 static int __init rockchip_pinctrl_drv_register(void)
3113 {
3114         return platform_driver_register(&rockchip_pinctrl_driver);
3115 }
3116 postcore_initcall(rockchip_pinctrl_drv_register);
3117
3118 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
3119 MODULE_DESCRIPTION("Rockchip pinctrl driver");
3120 MODULE_LICENSE("GPL v2");