drivers/phy/phy-rockchip-inno-usb2.c

   1 /*
   2  * Rockchip USB2.0 PHY with Innosilicon IP block driver
   3  *
   4  * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/delay.h>
  20 #include <linux/extcon.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/gpio/consumer.h>
  24 #include <linux/jiffies.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/mutex.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/phy/phy.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/power_supply.h>
  35 #include <linux/regmap.h>
  36 #include <linux/mfd/syscon.h>
  37 #include <linux/usb/of.h>
  38 #include <linux/usb/otg.h>
  39 #include <linux/wakelock.h>
  40
  41 #define BIT_WRITEABLE_SHIFT     16
  42 #define SCHEDULE_DELAY          (60 * HZ)
  43 #define OTG_SCHEDULE_DELAY      (2 * HZ)
  44
  45 struct rockchip_usb2phy;
  46
  47 enum rockchip_usb2phy_port_id {
  48         USB2PHY_PORT_OTG,
  49         USB2PHY_PORT_HOST,
  50         USB2PHY_NUM_PORTS,
  51 };
  52
  53 enum rockchip_usb2phy_host_state {
  54         PHY_STATE_HS_ONLINE     = 0,
  55         PHY_STATE_DISCONNECT    = 1,
  56         PHY_STATE_CONNECT       = 2,
  57         PHY_STATE_FS_LS_ONLINE  = 4,
  58 };
  59
  60 /**
  61  * Different states involved in USB charger detection.
  62  * USB_CHG_STATE_UNDEFINED      USB charger is not connected or detection
  63  *                              process is not yet started.
  64  * USB_CHG_STATE_WAIT_FOR_DCD   Waiting for Data pins contact.
  65  * USB_CHG_STATE_DCD_DONE       Data pin contact is detected.
  66  * USB_CHG_STATE_PRIMARY_DONE   Primary detection is completed (Detects
  67  *                              between SDP and DCP/CDP).
  68  * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
  69  *                              between DCP and CDP).
  70  * USB_CHG_STATE_DETECTED       USB charger type is determined.
  71  */
  72 enum usb_chg_state {
  73         USB_CHG_STATE_UNDEFINED = 0,
  74         USB_CHG_STATE_WAIT_FOR_DCD,
  75         USB_CHG_STATE_DCD_DONE,
  76         USB_CHG_STATE_PRIMARY_DONE,
  77         USB_CHG_STATE_SECONDARY_DONE,
  78         USB_CHG_STATE_DETECTED,
  79 };
  80
  81 static const unsigned int rockchip_usb2phy_extcon_cable[] = {
  82         EXTCON_USB,
  83         EXTCON_USB_HOST,
  84         EXTCON_USB_VBUS_EN,
  85         EXTCON_CHG_USB_SDP,
  86         EXTCON_CHG_USB_CDP,
  87         EXTCON_CHG_USB_DCP,
  88         EXTCON_CHG_USB_SLOW,
  89         EXTCON_NONE,
  90 };
  91
  92 struct usb2phy_reg {
  93         unsigned int    offset;
  94         unsigned int    bitend;
  95         unsigned int    bitstart;
  96         unsigned int    disable;
  97         unsigned int    enable;
  98 };
  99
 100 /**
 101  * struct rockchip_chg_det_reg: usb charger detect registers
 102  * @cp_det: charging port detected successfully.
 103  * @dcp_det: dedicated charging port detected successfully.
 104  * @dp_det: assert data pin connect successfully.
 105  * @idm_sink_en: open dm sink curren.
 106  * @idp_sink_en: open dp sink current.
 107  * @idp_src_en: open dm source current.
 108  * @rdm_pdwn_en: open dm pull down resistor.
 109  * @vdm_src_en: open dm voltage source.
 110  * @vdp_src_en: open dp voltage source.
 111  * @opmode: utmi operational mode.
 112  */
 113 struct rockchip_chg_det_reg {
 114         struct usb2phy_reg      cp_det;
 115         struct usb2phy_reg      dcp_det;
 116         struct usb2phy_reg      dp_det;
 117         struct usb2phy_reg      idm_sink_en;
 118         struct usb2phy_reg      idp_sink_en;
 119         struct usb2phy_reg      idp_src_en;
 120         struct usb2phy_reg      rdm_pdwn_en;
 121         struct usb2phy_reg      vdm_src_en;
 122         struct usb2phy_reg      vdp_src_en;
 123         struct usb2phy_reg      opmode;
 124 };
 125
 126 /**
 127  * struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
 128  * @phy_sus: phy suspend register.
 129  * @bvalid_det_en: vbus valid rise detection enable register.
 130  * @bvalid_det_st: vbus valid rise detection status register.
 131  * @bvalid_det_clr: vbus valid rise detection clear register.
 132  * @ls_det_en: linestate detection enable register.
 133  * @ls_det_st: linestate detection state register.
 134  * @ls_det_clr: linestate detection clear register.
 135  * @idfall_det_en: id fall detection enable register.
 136  * @idfall_det_st: id fall detection state register.
 137  * @idfall_det_clr: id fall detection clear register.
 138  * @idrise_det_en: id rise detection enable register.
 139  * @idrise_det_st: id rise detection state register.
 140  * @idrise_det_clr: id rise detection clear register.
 141  * @utmi_avalid: utmi vbus avalid status register.
 142  * @utmi_bvalid: utmi vbus bvalid status register.
 143  * @utmi_iddig: otg port id pin status register.
 144  * @utmi_ls: utmi linestate state register.
 145  * @utmi_hstdet: utmi host disconnect register.
 146  * @vbus_det_en: vbus detect function power down register.
 147  */
 148 struct rockchip_usb2phy_port_cfg {
 149         struct usb2phy_reg      phy_sus;
 150         struct usb2phy_reg      bvalid_det_en;
 151         struct usb2phy_reg      bvalid_det_st;
 152         struct usb2phy_reg      bvalid_det_clr;
 153         struct usb2phy_reg      ls_det_en;
 154         struct usb2phy_reg      ls_det_st;
 155         struct usb2phy_reg      ls_det_clr;
 156         struct usb2phy_reg      idfall_det_en;
 157         struct usb2phy_reg      idfall_det_st;
 158         struct usb2phy_reg      idfall_det_clr;
 159         struct usb2phy_reg      idrise_det_en;
 160         struct usb2phy_reg      idrise_det_st;
 161         struct usb2phy_reg      idrise_det_clr;
 162         struct usb2phy_reg      utmi_avalid;
 163         struct usb2phy_reg      utmi_bvalid;
 164         struct usb2phy_reg      utmi_iddig;
 165         struct usb2phy_reg      utmi_ls;
 166         struct usb2phy_reg      utmi_hstdet;
 167         struct usb2phy_reg      vbus_det_en;
 168 };
 169
 170 /**
 171  * struct rockchip_usb2phy_cfg: usb-phy configuration.
 172  * @reg: the address offset of grf for usb-phy config.
 173  * @num_ports: specify how many ports that the phy has.
 174  * @phy_tuning: phy default parameters tunning.
 175  * @clkout_ctl: keep on/turn off output clk of phy.
 176  * @chg_det: charger detection registers.
 177  */
 178 struct rockchip_usb2phy_cfg {
 179         unsigned int    reg;
 180         unsigned int    num_ports;
 181         int (*phy_tuning)(struct rockchip_usb2phy *);
 182         struct usb2phy_reg      clkout_ctl;
 183         const struct rockchip_usb2phy_port_cfg  port_cfgs[USB2PHY_NUM_PORTS];
 184         const struct rockchip_chg_det_reg       chg_det;
 185 };
 186
 187 /**
 188  * struct rockchip_usb2phy_port: usb-phy port data.
 189  * @port_id: flag for otg port or host port.
 190  * @perip_connected: flag for periphyeral connect status.
 191  * @suspended: phy suspended flag.
 192  * @utmi_avalid: utmi avalid status usage flag.
 193  *      true    - use avalid to get vbus status
 194  *      flase   - use bvalid to get vbus status
 195  * @vbus_attached: otg device vbus status.
 196  * @vbus_always_on: otg vbus is always powered on.
 197  * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
 198  * @ls_irq: IRQ number assigned for linestate detection.
 199  * @id_irq: IRQ number assigned for id fall or rise detection.
 200  * @mutex: for register updating in sm_work.
 201  * @chg_work: charge detect work.
 202  * @otg_sm_work: OTG state machine work.
 203  * @sm_work: HOST state machine work.
 204  * @phy_cfg: port register configuration, assigned by driver data.
 205  * @event_nb: hold event notification callback.
 206  * @wakelock: wake lock struct to prevent system suspend
 207  *            when USB is active.
 208  * @state: define OTG enumeration states before device reset.
 209  * @mode: the dr_mode of the controller.
 210  */
 211 struct rockchip_usb2phy_port {
 212         struct phy      *phy;
 213         unsigned int    port_id;
 214         bool            perip_connected;
 215         bool            suspended;
 216         bool            utmi_avalid;
 217         bool            vbus_attached;
 218         bool            vbus_always_on;
 219         int             bvalid_irq;
 220         int             ls_irq;
 221         int             id_irq;
 222         struct mutex    mutex;
 223         struct          delayed_work chg_work;
 224         struct          delayed_work otg_sm_work;
 225         struct          delayed_work sm_work;
 226         const struct    rockchip_usb2phy_port_cfg *port_cfg;
 227         struct notifier_block   event_nb;
 228         struct wake_lock        wakelock;
 229         enum usb_otg_state      state;
 230         enum usb_dr_mode        mode;
 231 };
 232
 233 /**
 234  * struct rockchip_usb2phy: usb2.0 phy driver data.
 235  * @grf: General Register Files regmap.
 236  * @clk: clock struct of phy input clk.
 237  * @clk480m: clock struct of phy output clk.
 238  * @clk_hw: clock struct of phy output clk management.
 239  * @chg_state: states involved in USB charger detection.
 240  * @chg_type: USB charger types.
 241  * @dcd_retries: The retry count used to track Data contact
 242  *               detection process.
 243  * @edev_self: represent the source of extcon.
 244  * @edev: extcon device for notification registration
 245  * @phy_cfg: phy register configuration, assigned by driver data.
 246  * @ports: phy port instance.
 247  */
 248 struct rockchip_usb2phy {
 249         struct device   *dev;
 250         struct regmap   *grf;
 251         struct clk      *clk;
 252         struct clk      *clk480m;
 253         struct clk_hw   clk480m_hw;
 254         enum usb_chg_state      chg_state;
 255         enum power_supply_type  chg_type;
 256         u8                      dcd_retries;
 257         u8                      primary_retries;
 258         bool                    edev_self;
 259         struct extcon_dev       *edev;
 260         const struct rockchip_usb2phy_cfg       *phy_cfg;
 261         struct rockchip_usb2phy_port    ports[USB2PHY_NUM_PORTS];
 262 };
 263
 264 static inline int property_enable(struct rockchip_usb2phy *rphy,
 265                                   const struct usb2phy_reg *reg, bool en)
 266 {
 267         unsigned int val, mask, tmp;
 268
 269         tmp = en ? reg->enable : reg->disable;
 270         mask = GENMASK(reg->bitend, reg->bitstart);
 271         val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
 272
 273         return regmap_write(rphy->grf, reg->offset, val);
 274 }
 275
 276 static inline bool property_enabled(struct rockchip_usb2phy *rphy,
 277                                     const struct usb2phy_reg *reg)
 278 {
 279         int ret;
 280         unsigned int tmp, orig;
 281         unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
 282
 283         ret = regmap_read(rphy->grf, reg->offset, &orig);
 284         if (ret)
 285                 return false;
 286
 287         tmp = (orig & mask) >> reg->bitstart;
 288         return tmp == reg->enable;
 289 }
 290
 291 static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
 292 {
 293         struct rockchip_usb2phy *rphy =
 294                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 295         int ret;
 296
 297         /* turn on 480m clk output if it is off */
 298         if (!property_enabled(rphy, &rphy->phy_cfg->clkout_ctl)) {
 299                 ret = property_enable(rphy, &rphy->phy_cfg->clkout_ctl, true);
 300                 if (ret)
 301                         return ret;
 302
 303                 /* waiting for the clk become stable */
 304                 usleep_range(1200, 1300);
 305         }
 306
 307         return 0;
 308 }
 309
 310 static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw)
 311 {
 312         struct rockchip_usb2phy *rphy =
 313                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 314
 315         /* turn off 480m clk output */
 316         property_enable(rphy, &rphy->phy_cfg->clkout_ctl, false);
 317 }
 318
 319 static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw)
 320 {
 321         struct rockchip_usb2phy *rphy =
 322                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 323
 324         return property_enabled(rphy, &rphy->phy_cfg->clkout_ctl);
 325 }
 326
 327 static unsigned long
 328 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
 329                                      unsigned long parent_rate)
 330 {
 331         return 480000000;
 332 }
 333
 334 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
 335         .prepare = rockchip_usb2phy_clk480m_prepare,
 336         .unprepare = rockchip_usb2phy_clk480m_unprepare,
 337         .is_prepared = rockchip_usb2phy_clk480m_prepared,
 338         .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
 339 };
 340
 341 static void rockchip_usb2phy_clk480m_unregister(void *data)
 342 {
 343         struct rockchip_usb2phy *rphy = data;
 344
 345         of_clk_del_provider(rphy->dev->of_node);
 346         clk_unregister(rphy->clk480m);
 347 }
 348
 349 static int
 350 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
 351 {
 352         struct device_node *node = rphy->dev->of_node;
 353         struct clk_init_data init;
 354         const char *clk_name;
 355         int ret;
 356
 357         init.flags = 0;
 358         init.name = "clk_usbphy_480m";
 359         init.ops = &rockchip_usb2phy_clkout_ops;
 360
 361         /* optional override of the clockname */
 362         of_property_read_string(node, "clock-output-names", &init.name);
 363
 364         if (rphy->clk) {
 365                 clk_name = __clk_get_name(rphy->clk);
 366                 init.parent_names = &clk_name;
 367                 init.num_parents = 1;
 368         } else {
 369                 init.parent_names = NULL;
 370                 init.num_parents = 0;
 371         }
 372
 373         rphy->clk480m_hw.init = &init;
 374
 375         /* register the clock */
 376         rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
 377         if (IS_ERR(rphy->clk480m)) {
 378                 ret = PTR_ERR(rphy->clk480m);
 379                 goto err_ret;
 380         }
 381
 382         ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
 383         if (ret < 0)
 384                 goto err_clk_provider;
 385
 386         ret = devm_add_action(rphy->dev, rockchip_usb2phy_clk480m_unregister,
 387                               rphy);
 388         if (ret < 0)
 389                 goto err_unreg_action;
 390
 391         return 0;
 392
 393 err_unreg_action:
 394         of_clk_del_provider(node);
 395 err_clk_provider:
 396         clk_unregister(rphy->clk480m);
 397 err_ret:
 398         return ret;
 399 }
 400
 401 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
 402 {
 403         int ret;
 404         struct device_node *node = rphy->dev->of_node;
 405         struct extcon_dev *edev;
 406
 407         if (of_property_read_bool(node, "extcon")) {
 408                 edev = extcon_get_edev_by_phandle(rphy->dev, 0);
 409                 if (IS_ERR(edev)) {
 410                         if (PTR_ERR(edev) != -EPROBE_DEFER)
 411                                 dev_err(rphy->dev, "Invalid or missing extcon\n");
 412                         return PTR_ERR(edev);
 413                 }
 414         } else {
 415                 /* Initialize extcon device */
 416                 edev = devm_extcon_dev_allocate(rphy->dev,
 417                                                 rockchip_usb2phy_extcon_cable);
 418
 419                 if (IS_ERR(edev))
 420                         return -ENOMEM;
 421
 422                 ret = devm_extcon_dev_register(rphy->dev, edev);
 423                 if (ret) {
 424                         dev_err(rphy->dev, "failed to register extcon device\n");
 425                         return ret;
 426                 }
 427
 428                 rphy->edev_self = true;
 429         }
 430
 431         rphy->edev = edev;
 432
 433         return 0;
 434 }
 435
 436 static int rockchip_usb2phy_init(struct phy *phy)
 437 {
 438         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 439         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 440         int ret = 0;
 441
 442         mutex_lock(&rport->mutex);
 443
 444         if (rport->port_id == USB2PHY_PORT_OTG) {
 445                 if (rport->mode != USB_DR_MODE_HOST &&
 446                     !rport->vbus_always_on) {
 447                         /* clear bvalid status and enable bvalid detect irq */
 448                         ret = property_enable(rphy,
 449                                               &rport->port_cfg->
 450                                               bvalid_det_clr,
 451                                               true);
 452                         if (ret)
 453                                 goto out;
 454
 455                         ret = property_enable(rphy,
 456                                               &rport->port_cfg->
 457                                               bvalid_det_en,
 458                                               true);
 459                         if (ret)
 460                                 goto out;
 461
 462                         if (rphy->edev_self) {
 463                                 ret = property_enable(rphy,
 464                                                       &rport->port_cfg->
 465                                                       idfall_det_clr,
 466                                                       true);
 467                                 if (ret)
 468                                         goto out;
 469
 470                                 ret = property_enable(rphy,
 471                                                       &rport->port_cfg->
 472                                                       idfall_det_en,
 473                                                       true);
 474                                 if (ret)
 475                                         goto out;
 476
 477                                 ret = property_enable(rphy,
 478                                                       &rport->port_cfg->
 479                                                       idrise_det_clr,
 480                                                       true);
 481                                 if (ret)
 482                                         goto out;
 483
 484                                 ret = property_enable(rphy,
 485                                                       &rport->port_cfg->
 486                                                       idrise_det_en,
 487                                                       true);
 488                                 if (ret)
 489                                         goto out;
 490                         }
 491
 492                         schedule_delayed_work(&rport->otg_sm_work,
 493                                               OTG_SCHEDULE_DELAY);
 494                 } else {
 495                         /* If OTG works in host only mode, do nothing. */
 496                         dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode);
 497                 }
 498         } else if (rport->port_id == USB2PHY_PORT_HOST) {
 499                 /* clear linestate and enable linestate detect irq */
 500                 ret = property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
 501                 if (ret)
 502                         goto out;
 503
 504                 ret = property_enable(rphy, &rport->port_cfg->ls_det_en, true);
 505                 if (ret)
 506                         goto out;
 507
 508                 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
 509         }
 510
 511 out:
 512         mutex_unlock(&rport->mutex);
 513         return ret;
 514 }
 515
 516 static int rockchip_usb2phy_power_on(struct phy *phy)
 517 {
 518         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 519         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 520         int ret;
 521
 522         dev_dbg(&rport->phy->dev, "port power on\n");
 523
 524         if (!rport->suspended)
 525                 return 0;
 526
 527         ret = clk_prepare_enable(rphy->clk480m);
 528         if (ret)
 529                 return ret;
 530
 531         ret = property_enable(rphy, &rport->port_cfg->phy_sus, false);
 532         if (ret)
 533                 return ret;
 534
 535         rport->suspended = false;
 536         return 0;
 537 }
 538
 539 static int rockchip_usb2phy_power_off(struct phy *phy)
 540 {
 541         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 542         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 543         int ret;
 544
 545         dev_dbg(&rport->phy->dev, "port power off\n");
 546
 547         if (rport->suspended)
 548                 return 0;
 549
 550         ret = property_enable(rphy, &rport->port_cfg->phy_sus, true);
 551         if (ret)
 552                 return ret;
 553
 554         rport->suspended = true;
 555         clk_disable_unprepare(rphy->clk480m);
 556
 557         return 0;
 558 }
 559
 560 static int rockchip_usb2phy_exit(struct phy *phy)
 561 {
 562         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 563
 564         if (rport->port_id == USB2PHY_PORT_OTG &&
 565             rport->mode != USB_DR_MODE_HOST &&
 566             !rport->vbus_always_on)
 567                 cancel_delayed_work_sync(&rport->chg_work);
 568         else if (rport->port_id == USB2PHY_PORT_HOST)
 569                 cancel_delayed_work_sync(&rport->sm_work);
 570
 571         return 0;
 572 }
 573
 574 static int rockchip_usb2phy_set_mode(struct phy *phy, enum phy_mode mode)
 575 {
 576         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 577         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 578         bool vbus_det_en;
 579         int ret = 0;
 580
 581         if (rport->port_id != USB2PHY_PORT_OTG ||
 582             !rport->vbus_always_on)
 583                 return ret;
 584
 585         switch (mode) {
 586         case PHY_MODE_USB_OTG:
 587                 /*
 588                  * In case of using vbus to detect connect state by u2phy,
 589                  * enable vbus detect on otg mode.
 590                  *
 591                  * fallthrough
 592                  */
 593         case PHY_MODE_USB_DEVICE:
 594                 vbus_det_en = true;
 595                 break;
 596         case PHY_MODE_USB_HOST:
 597                 /* fallthrough */
 598         case PHY_MODE_INVALID:
 599                 vbus_det_en = false;
 600                 break;
 601         default:
 602                 dev_info(&rport->phy->dev, "illegal mode\n");
 603                 return ret;
 604         }
 605
 606         ret = property_enable(rphy, &rport->port_cfg->vbus_det_en, vbus_det_en);
 607
 608         return ret;
 609 }
 610 static const struct phy_ops rockchip_usb2phy_ops = {
 611         .init           = rockchip_usb2phy_init,
 612         .exit           = rockchip_usb2phy_exit,
 613         .power_on       = rockchip_usb2phy_power_on,
 614         .power_off      = rockchip_usb2phy_power_off,
 615         .set_mode       = rockchip_usb2phy_set_mode,
 616         .owner          = THIS_MODULE,
 617 };
 618
 619 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
 620 {
 621         struct rockchip_usb2phy_port *rport =
 622                 container_of(work, struct rockchip_usb2phy_port,
 623                              otg_sm_work.work);
 624         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 625         static unsigned int cable;
 626         unsigned long delay;
 627         bool sch_work;
 628
 629         if (rport->utmi_avalid)
 630                 rport->vbus_attached =
 631                         property_enabled(rphy, &rport->port_cfg->utmi_avalid);
 632         else
 633                 rport->vbus_attached =
 634                         property_enabled(rphy, &rport->port_cfg->utmi_bvalid);
 635
 636         sch_work = false;
 637         delay = OTG_SCHEDULE_DELAY;
 638
 639         dev_dbg(&rport->phy->dev, "%s otg sm work\n",
 640                 usb_otg_state_string(rport->state));
 641
 642         switch (rport->state) {
 643         case OTG_STATE_UNDEFINED:
 644                 rport->state = OTG_STATE_B_IDLE;
 645                 if (!rport->vbus_attached)
 646                         rockchip_usb2phy_power_off(rport->phy);
 647                 /* fall through */
 648         case OTG_STATE_B_IDLE:
 649                 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) > 0 ||
 650                     extcon_get_cable_state_(rphy->edev,
 651                                             EXTCON_USB_VBUS_EN) > 0) {
 652                         dev_dbg(&rport->phy->dev, "usb otg host connect\n");
 653                         rport->state = OTG_STATE_A_HOST;
 654                         rockchip_usb2phy_power_on(rport->phy);
 655                         return;
 656                 } else if (rport->vbus_attached) {
 657                         dev_dbg(&rport->phy->dev, "vbus_attach\n");
 658                         switch (rphy->chg_state) {
 659                         case USB_CHG_STATE_UNDEFINED:
 660                                 schedule_delayed_work(&rport->chg_work, 0);
 661                                 return;
 662                         case USB_CHG_STATE_DETECTED:
 663                                 switch (rphy->chg_type) {
 664                                 case POWER_SUPPLY_TYPE_USB:
 665                                         dev_dbg(&rport->phy->dev,
 666                                                 "sdp cable is connecetd\n");
 667                                         wake_lock(&rport->wakelock);
 668                                         cable = EXTCON_CHG_USB_SDP;
 669                                         rockchip_usb2phy_power_on(rport->phy);
 670                                         rport->state = OTG_STATE_B_PERIPHERAL;
 671                                         rport->perip_connected = true;
 672                                         sch_work = true;
 673                                         break;
 674                                 case POWER_SUPPLY_TYPE_USB_DCP:
 675                                         dev_dbg(&rport->phy->dev,
 676                                                 "dcp cable is connecetd\n");
 677                                         cable = EXTCON_CHG_USB_DCP;
 678                                         rockchip_usb2phy_power_off(rport->phy);
 679                                         sch_work = true;
 680                                         break;
 681                                 case POWER_SUPPLY_TYPE_USB_CDP:
 682                                         dev_dbg(&rport->phy->dev,
 683                                                 "cdp cable is connecetd\n");
 684                                         wake_lock(&rport->wakelock);
 685                                         cable = EXTCON_CHG_USB_CDP;
 686                                         rockchip_usb2phy_power_on(rport->phy);
 687                                         rport->state = OTG_STATE_B_PERIPHERAL;
 688                                         rport->perip_connected = true;
 689                                         sch_work = true;
 690                                         break;
 691                                 case POWER_SUPPLY_TYPE_USB_FLOATING:
 692                                         dev_dbg(&rport->phy->dev,
 693                                                 "floating cable is connecetd\n");
 694                                         cable = EXTCON_CHG_USB_DCP;
 695                                         rockchip_usb2phy_power_off(rport->phy);
 696                                         sch_work = true;
 697                                         break;
 698                                 default:
 699                                         break;
 700                                 }
 701                                 break;
 702                         default:
 703                                 break;
 704                         }
 705                 } else {
 706                         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
 707                         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
 708                 }
 709                 break;
 710         case OTG_STATE_B_PERIPHERAL:
 711                 if (!rport->vbus_attached) {
 712                         dev_dbg(&rport->phy->dev, "usb disconnect\n");
 713                         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
 714                         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
 715                         rport->state = OTG_STATE_B_IDLE;
 716                         rport->perip_connected = false;
 717                         delay = 0;
 718                         rockchip_usb2phy_power_off(rport->phy);
 719                         wake_unlock(&rport->wakelock);
 720                 } else {
 721                         sch_work = true;
 722                 }
 723                 break;
 724         case OTG_STATE_A_HOST:
 725                 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) == 0) {
 726                         dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
 727                         rport->state = OTG_STATE_B_IDLE;
 728                         rockchip_usb2phy_power_off(rport->phy);
 729                 }
 730                 return;
 731         default:
 732                 return;
 733         }
 734
 735         if (extcon_get_state(rphy->edev, cable) != rport->vbus_attached)
 736                 extcon_set_cable_state_(rphy->edev,
 737                                         cable, rport->vbus_attached);
 738
 739         if (rphy->edev_self &&
 740             (extcon_get_state(rphy->edev, EXTCON_USB) !=
 741              rport->perip_connected))
 742                 extcon_set_cable_state_(rphy->edev,
 743                                         EXTCON_USB,
 744                                         rport->perip_connected);
 745
 746         if (sch_work)
 747                 schedule_delayed_work(&rport->otg_sm_work, delay);
 748 }
 749
 750 static const char *chg_to_string(enum power_supply_type chg_type)
 751 {
 752         switch (chg_type) {
 753         case POWER_SUPPLY_TYPE_USB:
 754                 return "USB_SDP_CHARGER";
 755         case POWER_SUPPLY_TYPE_USB_DCP:
 756                 return "USB_DCP_CHARGER";
 757         case POWER_SUPPLY_TYPE_USB_CDP:
 758                 return "USB_CDP_CHARGER";
 759         case POWER_SUPPLY_TYPE_USB_FLOATING:
 760                 return "USB_FLOATING_CHARGER";
 761         default:
 762                 return "INVALID_CHARGER";
 763         }
 764 }
 765
 766 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
 767                                     bool en)
 768 {
 769         property_enable(rphy, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
 770         property_enable(rphy, &rphy->phy_cfg->chg_det.idp_src_en, en);
 771 }
 772
 773 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
 774                                             bool en)
 775 {
 776         property_enable(rphy, &rphy->phy_cfg->chg_det.vdp_src_en, en);
 777         property_enable(rphy, &rphy->phy_cfg->chg_det.idm_sink_en, en);
 778 }
 779
 780 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
 781                                               bool en)
 782 {
 783         property_enable(rphy, &rphy->phy_cfg->chg_det.vdm_src_en, en);
 784         property_enable(rphy, &rphy->phy_cfg->chg_det.idp_sink_en, en);
 785 }
 786
 787 #define CHG_DCD_POLL_TIME       (100 * HZ / 1000)
 788 #define CHG_DCD_MAX_RETRIES     6
 789 #define CHG_PRIMARY_DET_TIME    (40 * HZ / 1000)
 790 #define CHG_SECONDARY_DET_TIME  (40 * HZ / 1000)
 791 static void rockchip_chg_detect_work(struct work_struct *work)
 792 {
 793         struct rockchip_usb2phy_port *rport =
 794                 container_of(work, struct rockchip_usb2phy_port, chg_work.work);
 795         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 796         bool is_dcd, tmout, vout;
 797         unsigned long delay;
 798
 799         dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
 800                 rphy->chg_state);
 801         switch (rphy->chg_state) {
 802         case USB_CHG_STATE_UNDEFINED:
 803                 if (!rport->suspended)
 804                         rockchip_usb2phy_power_off(rport->phy);
 805                 /* put the controller in non-driving mode */
 806                 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, false);
 807                 /* Start DCD processing stage 1 */
 808                 rockchip_chg_enable_dcd(rphy, true);
 809                 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
 810                 rphy->dcd_retries = 0;
 811                 rphy->primary_retries = 0;
 812                 delay = CHG_DCD_POLL_TIME;
 813                 break;
 814         case USB_CHG_STATE_WAIT_FOR_DCD:
 815                 /* get data contact detection status */
 816                 is_dcd = property_enabled(rphy, &rphy->phy_cfg->chg_det.dp_det);
 817                 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
 818                 /* stage 2 */
 819                 if (is_dcd || tmout) {
 820                         /* stage 4 */
 821                         /* Turn off DCD circuitry */
 822                         rockchip_chg_enable_dcd(rphy, false);
 823                         /* Voltage Source on DP, Probe on DM */
 824                         rockchip_chg_enable_primary_det(rphy, true);
 825                         delay = CHG_PRIMARY_DET_TIME;
 826                         rphy->chg_state = USB_CHG_STATE_DCD_DONE;
 827                 } else {
 828                         /* stage 3 */
 829                         delay = CHG_DCD_POLL_TIME;
 830                 }
 831                 break;
 832         case USB_CHG_STATE_DCD_DONE:
 833                 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.cp_det);
 834                 rockchip_chg_enable_primary_det(rphy, false);
 835                 if (vout) {
 836                         /* Voltage Source on DM, Probe on DP  */
 837                         rockchip_chg_enable_secondary_det(rphy, true);
 838                         delay = CHG_SECONDARY_DET_TIME;
 839                         rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
 840                 } else {
 841                         if (rphy->dcd_retries == CHG_DCD_MAX_RETRIES) {
 842                                 /* floating charger found */
 843                                 rphy->chg_type = POWER_SUPPLY_TYPE_USB_FLOATING;
 844                                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 845                                 delay = 0;
 846                         } else {
 847                                 if (rphy->primary_retries < 2) {
 848                                         /* Turn off DCD circuitry */
 849                                         rockchip_chg_enable_dcd(rphy, false);
 850                                         /* Voltage Source on DP, Probe on DM */
 851                                         rockchip_chg_enable_primary_det(rphy,
 852                                                                         true);
 853                                         delay = CHG_PRIMARY_DET_TIME;
 854                                         rphy->chg_state =
 855                                                 USB_CHG_STATE_DCD_DONE;
 856                                         rphy->primary_retries++;
 857                                         /* break USB_CHG_STATE_DCD_DONE */
 858                                         break;
 859                                 }
 860                                 rphy->chg_type = POWER_SUPPLY_TYPE_USB;
 861                                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 862                                 delay = 0;
 863                         }
 864                 }
 865                 break;
 866         case USB_CHG_STATE_PRIMARY_DONE:
 867                 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.dcp_det);
 868                 /* Turn off voltage source */
 869                 rockchip_chg_enable_secondary_det(rphy, false);
 870                 if (vout)
 871                         rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
 872                 else
 873                         rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
 874                 /* fall through */
 875         case USB_CHG_STATE_SECONDARY_DONE:
 876                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 877                 delay = 0;
 878                 /* fall through */
 879         case USB_CHG_STATE_DETECTED:
 880                 /* put the controller in normal mode */
 881                 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, true);
 882                 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
 883                 dev_info(&rport->phy->dev, "charger = %s\n",
 884                          chg_to_string(rphy->chg_type));
 885                 return;
 886         default:
 887                 return;
 888         }
 889
 890         schedule_delayed_work(&rport->chg_work, delay);
 891 }
 892
 893 /*
 894  * The function manage host-phy port state and suspend/resume phy port
 895  * to save power.
 896  *
 897  * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
 898  * devices is disconnect or not. Besides, we do not need care it is FS/LS
 899  * disconnected or HS disconnected, actually, we just only need get the
 900  * device is disconnected at last through rearm the delayed work,
 901  * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
 902  *
 903  * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
 904  * some clk related APIs, so do not invoke it from interrupt context directly.
 905  */
 906 static void rockchip_usb2phy_sm_work(struct work_struct *work)
 907 {
 908         struct rockchip_usb2phy_port *rport =
 909                 container_of(work, struct rockchip_usb2phy_port, sm_work.work);
 910         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 911         unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
 912                           rport->port_cfg->utmi_hstdet.bitstart + 1;
 913         unsigned int ul, uhd, state;
 914         unsigned int ul_mask, uhd_mask;
 915         int ret;
 916
 917         mutex_lock(&rport->mutex);
 918
 919         ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
 920         if (ret < 0)
 921                 goto next_schedule;
 922
 923         ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset,
 924                           &uhd);
 925         if (ret < 0)
 926                 goto next_schedule;
 927
 928         uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
 929                            rport->port_cfg->utmi_hstdet.bitstart);
 930         ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
 931                           rport->port_cfg->utmi_ls.bitstart);
 932
 933         /* stitch on utmi_ls and utmi_hstdet as phy state */
 934         state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
 935                 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
 936
 937         switch (state) {
 938         case PHY_STATE_HS_ONLINE:
 939                 dev_dbg(&rport->phy->dev, "HS online\n");
 940                 break;
 941         case PHY_STATE_FS_LS_ONLINE:
 942                 /*
 943                  * For FS/LS device, the online state share with connect state
 944                  * from utmi_ls and utmi_hstdet register, so we distinguish
 945                  * them via suspended flag.
 946                  *
 947                  * Plus, there are two cases, one is D- Line pull-up, and D+
 948                  * line pull-down, the state is 4; another is D+ line pull-up,
 949                  * and D- line pull-down, the state is 2.
 950                  */
 951                 if (!rport->suspended) {
 952                         /* D- line pull-up, D+ line pull-down */
 953                         dev_dbg(&rport->phy->dev, "FS/LS online\n");
 954                         break;
 955                 }
 956                 /* fall through */
 957         case PHY_STATE_CONNECT:
 958                 if (rport->suspended) {
 959                         dev_dbg(&rport->phy->dev, "Connected\n");
 960                         rockchip_usb2phy_power_on(rport->phy);
 961                         rport->suspended = false;
 962                 } else {
 963                         /* D+ line pull-up, D- line pull-down */
 964                         dev_dbg(&rport->phy->dev, "FS/LS online\n");
 965                 }
 966                 break;
 967         case PHY_STATE_DISCONNECT:
 968                 if (!rport->suspended) {
 969                         dev_dbg(&rport->phy->dev, "Disconnected\n");
 970                         rockchip_usb2phy_power_off(rport->phy);
 971                         rport->suspended = true;
 972                 }
 973
 974                 /*
 975                  * activate the linestate detection to get the next device
 976                  * plug-in irq.
 977                  */
 978                 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
 979                 property_enable(rphy, &rport->port_cfg->ls_det_en, true);
 980
 981                 /*
 982                  * we don't need to rearm the delayed work when the phy port
 983                  * is suspended.
 984                  */
 985                 mutex_unlock(&rport->mutex);
 986                 return;
 987         default:
 988                 dev_dbg(&rport->phy->dev, "unknown phy state\n");
 989                 break;
 990         }
 991
 992 next_schedule:
 993         mutex_unlock(&rport->mutex);
 994         schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
 995 }
 996
 997 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
 998 {
 999         struct rockchip_usb2phy_port *rport = data;
1000         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1001
1002         if (!property_enabled(rphy, &rport->port_cfg->ls_det_st))
1003                 return IRQ_NONE;
1004
1005         dev_dbg(&rport->phy->dev, "linestate interrupt\n");
1006
1007         mutex_lock(&rport->mutex);
1008
1009         /* disable linestate detect irq and clear its status */
1010         property_enable(rphy, &rport->port_cfg->ls_det_en, false);
1011         property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
1012
1013         mutex_unlock(&rport->mutex);
1014
1015         /*
1016          * In this case for host phy port, a new device is plugged in,
1017          * meanwhile, if the phy port is suspended, we need rearm the work to
1018          * resume it and mange its states; otherwise, we do nothing about that.
1019          */
1020         if (rport->suspended) {
1021                 if (rport->port_id == USB2PHY_PORT_HOST)
1022                         rockchip_usb2phy_sm_work(&rport->sm_work.work);
1023                 else
1024                         rockchip_usb2phy_power_on(rport->phy);
1025         }
1026
1027         return IRQ_HANDLED;
1028 }
1029
1030 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
1031 {
1032         struct rockchip_usb2phy_port *rport = data;
1033         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1034
1035         if (!property_enabled(rphy, &rport->port_cfg->bvalid_det_st))
1036                 return IRQ_NONE;
1037
1038         mutex_lock(&rport->mutex);
1039
1040         /* clear bvalid detect irq pending status */
1041         property_enable(rphy, &rport->port_cfg->bvalid_det_clr, true);
1042
1043         mutex_unlock(&rport->mutex);
1044
1045         rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
1046
1047         return IRQ_HANDLED;
1048 }
1049
1050 static irqreturn_t rockchip_usb2phy_id_irq(int irq, void *data)
1051 {
1052         struct rockchip_usb2phy_port *rport = data;
1053         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1054
1055         if (!property_enabled(rphy, &rport->port_cfg->idfall_det_st) &&
1056             !property_enabled(rphy, &rport->port_cfg->idrise_det_st))
1057                 return IRQ_NONE;
1058
1059         mutex_lock(&rport->mutex);
1060
1061         /* clear id fall or rise detect irq pending status */
1062         if (property_enabled(rphy, &rport->port_cfg->idfall_det_st)) {
1063                 property_enable(rphy, &rport->port_cfg->idfall_det_clr,
1064                                 true);
1065                 extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
1066                 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, true);
1067         } else if (property_enabled(rphy, &rport->port_cfg->idrise_det_st)) {
1068                 property_enable(rphy, &rport->port_cfg->idrise_det_clr,
1069                                 true);
1070                 extcon_set_state(rphy->edev, EXTCON_USB_HOST, false);
1071                 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, false);
1072         }
1073
1074         extcon_sync(rphy->edev, EXTCON_USB_HOST);
1075         extcon_sync(rphy->edev, EXTCON_USB_VBUS_EN);
1076
1077         mutex_unlock(&rport->mutex);
1078
1079         return IRQ_HANDLED;
1080 }
1081
1082 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
1083                                            struct rockchip_usb2phy_port *rport,
1084                                            struct device_node *child_np)
1085 {
1086         int ret;
1087
1088         rport->port_id = USB2PHY_PORT_HOST;
1089         rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
1090         rport->suspended = true;
1091
1092         mutex_init(&rport->mutex);
1093         INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
1094
1095         rport->ls_irq = of_irq_get_byname(child_np, "linestate");
1096         if (rport->ls_irq < 0) {
1097                 dev_err(rphy->dev, "no linestate irq provided\n");
1098                 return rport->ls_irq;
1099         }
1100
1101         ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
1102                                         rockchip_usb2phy_linestate_irq,
1103                                         IRQF_ONESHOT,
1104                                         "rockchip_usb2phy", rport);
1105         if (ret) {
1106                 dev_err(rphy->dev, "failed to request linestate irq handle\n");
1107                 return ret;
1108         }
1109
1110         return 0;
1111 }
1112
1113 static int rockchip_otg_event(struct notifier_block *nb,
1114                               unsigned long event, void *ptr)
1115 {
1116         struct rockchip_usb2phy_port *rport =
1117                 container_of(nb, struct rockchip_usb2phy_port, event_nb);
1118
1119         schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
1120
1121         return NOTIFY_DONE;
1122 }
1123
1124 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
1125                                           struct rockchip_usb2phy_port *rport,
1126                                           struct device_node *child_np)
1127 {
1128         int ret;
1129         int iddig;
1130
1131         rport->port_id = USB2PHY_PORT_OTG;
1132         rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
1133         rport->state = OTG_STATE_UNDEFINED;
1134
1135         /*
1136          * set suspended flag to true, but actually don't
1137          * put phy in suspend mode, it aims to enable usb
1138          * phy and clock in power_on() called by usb controller
1139          * driver during probe.
1140          */
1141         rport->suspended = true;
1142         rport->vbus_attached = false;
1143         rport->perip_connected = false;
1144
1145         mutex_init(&rport->mutex);
1146
1147         rport->ls_irq = of_irq_get_byname(child_np, "linestate");
1148         if (rport->ls_irq < 0) {
1149                 dev_err(rphy->dev, "no linestate irq provided\n");
1150                 return rport->ls_irq;
1151         }
1152
1153         ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
1154                                         rockchip_usb2phy_linestate_irq,
1155                                         IRQF_ONESHOT,
1156                                         "rockchip_usb2phy", rport);
1157         if (ret) {
1158                 dev_err(rphy->dev, "failed to request linestate irq handle\n");
1159                 return ret;
1160         }
1161
1162         rport->vbus_always_on =
1163                 of_property_read_bool(child_np, "rockchip,vbus-always-on");
1164
1165         rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
1166         if (rport->mode == USB_DR_MODE_HOST || rport->vbus_always_on)
1167                 return 0;
1168
1169         wake_lock_init(&rport->wakelock, WAKE_LOCK_SUSPEND, "rockchip_otg");
1170         INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
1171         INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
1172
1173         rport->utmi_avalid =
1174                 of_property_read_bool(child_np, "rockchip,utmi-avalid");
1175
1176         rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
1177         if (rport->bvalid_irq < 0) {
1178                 dev_err(rphy->dev, "no vbus valid irq provided\n");
1179                 return rport->bvalid_irq;
1180         }
1181
1182         ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, NULL,
1183                                         rockchip_usb2phy_bvalid_irq,
1184                                         IRQF_ONESHOT,
1185                                         "rockchip_usb2phy_bvalid", rport);
1186         if (ret) {
1187                 dev_err(rphy->dev, "failed to request otg-bvalid irq handle\n");
1188                 return ret;
1189         }
1190
1191         if (rphy->edev_self) {
1192                 rport->id_irq = of_irq_get_byname(child_np, "otg-id");
1193                 if (rport->id_irq < 0) {
1194                         dev_err(rphy->dev, "no otg id irq provided\n");
1195                         return rport->id_irq;
1196                 }
1197
1198                 ret = devm_request_threaded_irq(rphy->dev, rport->id_irq, NULL,
1199                                                 rockchip_usb2phy_id_irq,
1200                                                 IRQF_ONESHOT,
1201                                                 "rockchip_usb2phy_id", rport);
1202                 if (ret) {
1203                         dev_err(rphy->dev, "failed to request otg-id irq handle\n");
1204                         return ret;
1205                 }
1206
1207                 iddig = property_enabled(rphy, &rport->port_cfg->utmi_iddig);
1208                 if (!iddig) {
1209                         extcon_set_state(rphy->edev, EXTCON_USB, false);
1210                         extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
1211                         extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, true);
1212                 } else {
1213                         extcon_set_state(rphy->edev, EXTCON_USB_HOST, false);
1214                         extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, false);
1215                 }
1216         }
1217
1218         if (!IS_ERR(rphy->edev)) {
1219                 rport->event_nb.notifier_call = rockchip_otg_event;
1220
1221                 ret = extcon_register_notifier(rphy->edev, EXTCON_USB_HOST,
1222                                                &rport->event_nb);
1223                 if (ret < 0) {
1224                         dev_err(rphy->dev, "register USB HOST notifier failed\n");
1225                         return ret;
1226                 }
1227         }
1228
1229         return 0;
1230 }
1231
1232 static int rockchip_usb2phy_probe(struct platform_device *pdev)
1233 {
1234         struct device *dev = &pdev->dev;
1235         struct device_node *np = dev->of_node;
1236         struct device_node *child_np;
1237         struct phy_provider *provider;
1238         struct rockchip_usb2phy *rphy;
1239         const struct rockchip_usb2phy_cfg *phy_cfgs;
1240         const struct of_device_id *match;
1241         unsigned int reg;
1242         int index, ret;
1243
1244         rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
1245         if (!rphy)
1246                 return -ENOMEM;
1247
1248         match = of_match_device(dev->driver->of_match_table, dev);
1249         if (!match || !match->data) {
1250                 dev_err(dev, "phy configs are not assigned!\n");
1251                 return -EINVAL;
1252         }
1253
1254         if (!dev->parent || !dev->parent->of_node)
1255                 return -EINVAL;
1256
1257         rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
1258         if (IS_ERR(rphy->grf))
1259                 return PTR_ERR(rphy->grf);
1260
1261         if (of_property_read_u32(np, "reg", &reg)) {
1262                 dev_err(dev, "the reg property is not assigned in %s node\n",
1263                         np->name);
1264                 return -EINVAL;
1265         }
1266
1267         rphy->dev = dev;
1268         phy_cfgs = match->data;
1269         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1270         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1271         rphy->edev_self = false;
1272         platform_set_drvdata(pdev, rphy);
1273
1274         ret = rockchip_usb2phy_extcon_register(rphy);
1275         if (ret)
1276                 return ret;
1277
1278         /* find out a proper config which can be matched with dt. */
1279         index = 0;
1280         while (phy_cfgs[index].reg) {
1281                 if (phy_cfgs[index].reg == reg) {
1282                         rphy->phy_cfg = &phy_cfgs[index];
1283                         break;
1284                 }
1285
1286                 ++index;
1287         }
1288
1289         if (!rphy->phy_cfg) {
1290                 dev_err(dev, "no phy-config can be matched with %s node\n",
1291                         np->name);
1292                 return -EINVAL;
1293         }
1294
1295         rphy->clk = of_clk_get_by_name(np, "phyclk");
1296         if (!IS_ERR(rphy->clk)) {
1297                 clk_prepare_enable(rphy->clk);
1298         } else {
1299                 dev_info(&pdev->dev, "no phyclk specified\n");
1300                 rphy->clk = NULL;
1301         }
1302
1303         ret = rockchip_usb2phy_clk480m_register(rphy);
1304         if (ret) {
1305                 dev_err(dev, "failed to register 480m output clock\n");
1306                 goto disable_clks;
1307         }
1308
1309         if (rphy->phy_cfg->phy_tuning) {
1310                 ret = rphy->phy_cfg->phy_tuning(rphy);
1311                 if (ret)
1312                         goto disable_clks;
1313         }
1314
1315         index = 0;
1316         for_each_available_child_of_node(np, child_np) {
1317                 struct rockchip_usb2phy_port *rport = &rphy->ports[index];
1318                 struct phy *phy;
1319
1320                 /* This driver aims to support both otg-port and host-port */
1321                 if (of_node_cmp(child_np->name, "host-port") &&
1322                     of_node_cmp(child_np->name, "otg-port"))
1323                         goto next_child;
1324
1325                 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
1326                 if (IS_ERR(phy)) {
1327                         dev_err(dev, "failed to create phy\n");
1328                         ret = PTR_ERR(phy);
1329                         goto put_child;
1330                 }
1331
1332                 rport->phy = phy;
1333                 phy_set_drvdata(rport->phy, rport);
1334
1335                 /* initialize otg/host port separately */
1336                 if (!of_node_cmp(child_np->name, "host-port")) {
1337                         ret = rockchip_usb2phy_host_port_init(rphy, rport,
1338                                                               child_np);
1339                         if (ret)
1340                                 goto put_child;
1341                 } else {
1342                         ret = rockchip_usb2phy_otg_port_init(rphy, rport,
1343                                                              child_np);
1344                         if (ret)
1345                                 goto put_child;
1346                 }
1347
1348 next_child:
1349                 /* to prevent out of boundary */
1350                 if (++index >= rphy->phy_cfg->num_ports)
1351                         break;
1352         }
1353
1354         provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1355         return PTR_ERR_OR_ZERO(provider);
1356
1357 put_child:
1358         of_node_put(child_np);
1359 disable_clks:
1360         if (rphy->clk) {
1361                 clk_disable_unprepare(rphy->clk);
1362                 clk_put(rphy->clk);
1363         }
1364         return ret;
1365 }
1366
1367 static int rk3366_usb2phy_tuning(struct rockchip_usb2phy *rphy)
1368 {
1369         unsigned int open_pre_emphasize = 0xffff851f;
1370         unsigned int eye_height_tuning = 0xffff68c8;
1371         unsigned int compensation_tuning = 0xffff026e;
1372         int ret = 0;
1373
1374         /* open HS pre-emphasize to expand HS slew rate for each port. */
1375         ret |= regmap_write(rphy->grf, 0x0780, open_pre_emphasize);
1376         ret |= regmap_write(rphy->grf, 0x079c, eye_height_tuning);
1377         ret |= regmap_write(rphy->grf, 0x07b0, open_pre_emphasize);
1378         ret |= regmap_write(rphy->grf, 0x07cc, eye_height_tuning);
1379
1380         /* compensate default tuning reference relate to ODT and etc. */
1381         ret |= regmap_write(rphy->grf, 0x078c, compensation_tuning);
1382
1383         return ret;
1384 }
1385
1386 static int rk3399_usb2phy_tuning(struct rockchip_usb2phy *rphy)
1387 {
1388         struct device_node *node = rphy->dev->of_node;
1389         int ret = 0;
1390
1391         if (!of_property_read_bool(node, "rockchip,u2phy-tuning"))
1392                 return ret;
1393
1394         if (rphy->phy_cfg->reg == 0xe450) {
1395                 /*
1396                  * Set max ODT compensation voltage and
1397                  * current tuning reference for PHY0.
1398                  */
1399                 ret |= regmap_write(rphy->grf, 0x448c,
1400                                     GENMASK(23, 16) | 0xe3);
1401
1402                 /* Set max pre-emphasis level for PHY0 */
1403                 ret |= regmap_write(rphy->grf, 0x44b0,
1404                                     GENMASK(18, 16) | 0x07);
1405
1406                 /*
1407                  * Disable the pre-emphasize in eop state
1408                  * and chirp state to avoid mis-trigger the
1409                  * disconnect detection and also avoid hs
1410                  * handshake fail for PHY0.
1411                  */
1412                 ret |= regmap_write(rphy->grf, 0x4480,
1413                                     GENMASK(17, 16) | 0x0);
1414                 ret |= regmap_write(rphy->grf, 0x44b4,
1415                                     GENMASK(17, 16) | 0x0);
1416         } else {
1417                 /*
1418                  * Set max ODT compensation voltage and
1419                  * current tuning reference for PHY1.
1420                  */
1421                 ret |= regmap_write(rphy->grf, 0x450c,
1422                                     GENMASK(23, 16) | 0xe3);
1423
1424                 /* Set max pre-emphasis level for PHY1 */
1425                 ret |= regmap_write(rphy->grf, 0x4530,
1426                                     GENMASK(18, 16) | 0x07);
1427
1428                 /*
1429                  * Disable the pre-emphasize in eop state
1430                  * and chirp state to avoid mis-trigger the
1431                  * disconnect detection and also avoid hs
1432                  * handshake fail for PHY1.
1433                  */
1434                 ret |= regmap_write(rphy->grf, 0x4500,
1435                                     GENMASK(17, 16) | 0x0);
1436                 ret |= regmap_write(rphy->grf, 0x4534,
1437                                     GENMASK(17, 16) | 0x0);
1438         }
1439
1440         return ret;
1441 }
1442
1443 #ifdef CONFIG_PM_SLEEP
1444 static int rockchip_usb2phy_pm_suspend(struct device *dev)
1445 {
1446         struct rockchip_usb2phy *rphy = dev_get_drvdata(dev);
1447         struct rockchip_usb2phy_port *rport;
1448         int index;
1449
1450         for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
1451                 rport = &rphy->ports[index];
1452                 if (!rport->phy)
1453                         continue;
1454
1455                 /* activate the linestate to detect the next interrupt. */
1456                 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
1457                 property_enable(rphy, &rport->port_cfg->ls_det_en, true);
1458         }
1459
1460         return 0;
1461 }
1462
1463 static int rockchip_usb2phy_pm_resume(struct device *dev)
1464 {
1465         return 0;
1466 }
1467
1468 static const struct dev_pm_ops rockchip_usb2phy_dev_pm_ops = {
1469         SET_SYSTEM_SLEEP_PM_OPS(rockchip_usb2phy_pm_suspend,
1470                                 rockchip_usb2phy_pm_resume)
1471 };
1472
1473 #define ROCKCHIP_USB2PHY_DEV_PM (&rockchip_usb2phy_dev_pm_ops)
1474 #else
1475 #define ROCKCHIP_USB2PHY_DEV_PM NULL
1476 #endif /* CONFIG_PM_SLEEP */
1477
1478 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
1479         {
1480                 .reg = 0x700,
1481                 .num_ports      = 2,
1482                 .phy_tuning     = rk3366_usb2phy_tuning,
1483                 .clkout_ctl     = { 0x0724, 15, 15, 1, 0 },
1484                 .port_cfgs      = {
1485                         [USB2PHY_PORT_HOST] = {
1486                                 .phy_sus        = { 0x0728, 15, 0, 0, 0x1d1 },
1487                                 .ls_det_en      = { 0x0680, 4, 4, 0, 1 },
1488                                 .ls_det_st      = { 0x0690, 4, 4, 0, 1 },
1489                                 .ls_det_clr     = { 0x06a0, 4, 4, 0, 1 },
1490                                 .utmi_ls        = { 0x049c, 14, 13, 0, 1 },
1491                                 .utmi_hstdet    = { 0x049c, 12, 12, 0, 1 }
1492                         }
1493                 },
1494         },
1495         { /* sentinel */ }
1496 };
1497
1498 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1499         {
1500                 .reg            = 0xe450,
1501                 .num_ports      = 2,
1502                 .phy_tuning     = rk3399_usb2phy_tuning,
1503                 .clkout_ctl     = { 0xe450, 4, 4, 1, 0 },
1504                 .port_cfgs      = {
1505                         [USB2PHY_PORT_OTG] = {
1506                                 .phy_sus = { 0xe454, 15, 0, 0x1452, 0x15d1 },
1507                                 .bvalid_det_en  = { 0xe3c0, 3, 3, 0, 1 },
1508                                 .bvalid_det_st  = { 0xe3e0, 3, 3, 0, 1 },
1509                                 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
1510                                 .idfall_det_en  = { 0xe3c0, 5, 5, 0, 1 },
1511                                 .idfall_det_st  = { 0xe3e0, 5, 5, 0, 1 },
1512                                 .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 },
1513                                 .idrise_det_en  = { 0xe3c0, 4, 4, 0, 1 },
1514                                 .idrise_det_st  = { 0xe3e0, 4, 4, 0, 1 },
1515                                 .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 },
1516                                 .ls_det_en      = { 0xe3c0, 2, 2, 0, 1 },
1517                                 .ls_det_st      = { 0xe3e0, 2, 2, 0, 1 },
1518                                 .ls_det_clr     = { 0xe3d0, 2, 2, 0, 1 },
1519                                 .utmi_avalid    = { 0xe2ac, 7, 7, 0, 1 },
1520                                 .utmi_bvalid    = { 0xe2ac, 12, 12, 0, 1 },
1521                                 .utmi_iddig     = { 0xe2ac, 8, 8, 0, 1 },
1522                                 .utmi_ls        = { 0xe2ac, 14, 13, 0, 1 },
1523                                 .vbus_det_en    = { 0x449c, 15, 15, 1, 0 },
1524                         },
1525                         [USB2PHY_PORT_HOST] = {
1526                                 .phy_sus        = { 0xe458, 1, 0, 0x2, 0x1 },
1527                                 .ls_det_en      = { 0xe3c0, 6, 6, 0, 1 },
1528                                 .ls_det_st      = { 0xe3e0, 6, 6, 0, 1 },
1529                                 .ls_det_clr     = { 0xe3d0, 6, 6, 0, 1 },
1530                                 .utmi_ls        = { 0xe2ac, 22, 21, 0, 1 },
1531                                 .utmi_hstdet    = { 0xe2ac, 23, 23, 0, 1 }
1532                         }
1533                 },
1534                 .chg_det = {
1535                         .opmode         = { 0xe454, 3, 0, 5, 1 },
1536                         .cp_det         = { 0xe2ac, 2, 2, 0, 1 },
1537                         .dcp_det        = { 0xe2ac, 1, 1, 0, 1 },
1538                         .dp_det         = { 0xe2ac, 0, 0, 0, 1 },
1539                         .idm_sink_en    = { 0xe450, 8, 8, 0, 1 },
1540                         .idp_sink_en    = { 0xe450, 7, 7, 0, 1 },
1541                         .idp_src_en     = { 0xe450, 9, 9, 0, 1 },
1542                         .rdm_pdwn_en    = { 0xe450, 10, 10, 0, 1 },
1543                         .vdm_src_en     = { 0xe450, 12, 12, 0, 1 },
1544                         .vdp_src_en     = { 0xe450, 11, 11, 0, 1 },
1545                 },
1546         },
1547         {
1548                 .reg            = 0xe460,
1549                 .num_ports      = 2,
1550                 .phy_tuning     = rk3399_usb2phy_tuning,
1551                 .clkout_ctl     = { 0xe460, 4, 4, 1, 0 },
1552                 .port_cfgs      = {
1553                         [USB2PHY_PORT_OTG] = {
1554                                 .phy_sus = { 0xe464, 15, 0, 0x1452, 0x15d1 },
1555                                 .bvalid_det_en  = { 0xe3c0, 8, 8, 0, 1 },
1556                                 .bvalid_det_st  = { 0xe3e0, 8, 8, 0, 1 },
1557                                 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
1558                                 .idfall_det_en  = { 0xe3c0, 10, 10, 0, 1 },
1559                                 .idfall_det_st  = { 0xe3e0, 10, 10, 0, 1 },
1560                                 .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 },
1561                                 .idrise_det_en  = { 0xe3c0, 9, 9, 0, 1 },
1562                                 .idrise_det_st  = { 0xe3e0, 9, 9, 0, 1 },
1563                                 .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 },
1564                                 .ls_det_en      = { 0xe3c0, 7, 7, 0, 1 },
1565                                 .ls_det_st      = { 0xe3e0, 7, 7, 0, 1 },
1566                                 .ls_det_clr     = { 0xe3d0, 7, 7, 0, 1 },
1567                                 .utmi_avalid    = { 0xe2ac, 10, 10, 0, 1 },
1568                                 .utmi_bvalid    = { 0xe2ac, 16, 16, 0, 1 },
1569                                 .utmi_iddig     = { 0xe2ac, 11, 11, 0, 1 },
1570                                 .utmi_ls        = { 0xe2ac, 18, 17, 0, 1 },
1571                                 .vbus_det_en    = { 0x451c, 15, 15, 1, 0 },
1572                         },
1573                         [USB2PHY_PORT_HOST] = {
1574                                 .phy_sus        = { 0xe468, 1, 0, 0x2, 0x1 },
1575                                 .ls_det_en      = { 0xe3c0, 11, 11, 0, 1 },
1576                                 .ls_det_st      = { 0xe3e0, 11, 11, 0, 1 },
1577                                 .ls_det_clr     = { 0xe3d0, 11, 11, 0, 1 },
1578                                 .utmi_ls        = { 0xe2ac, 26, 25, 0, 1 },
1579                                 .utmi_hstdet    = { 0xe2ac, 27, 27, 0, 1 }
1580                         }
1581                 },
1582         },
1583         { /* sentinel */ }
1584 };
1585
1586 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
1587         { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
1588         { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
1589         {}
1590 };
1591 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
1592
1593 static struct platform_driver rockchip_usb2phy_driver = {
1594         .probe          = rockchip_usb2phy_probe,
1595         .driver         = {
1596                 .name   = "rockchip-usb2phy",
1597                 .pm     = ROCKCHIP_USB2PHY_DEV_PM,
1598                 .of_match_table = rockchip_usb2phy_dt_match,
1599         },
1600 };
1601 module_platform_driver(rockchip_usb2phy_driver);
1602
1603 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1604 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
1605 MODULE_LICENSE("GPL v2");