drivers/phy/phy-rockchip-inno-usb2.c

   1 /*
   2  * Rockchip USB2.0 PHY with Innosilicon IP block driver
   3  *
   4  * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/delay.h>
  20 #include <linux/extcon.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/gpio/consumer.h>
  24 #include <linux/jiffies.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/mutex.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/phy/phy.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/power_supply.h>
  35 #include <linux/regmap.h>
  36 #include <linux/mfd/syscon.h>
  37 #include <linux/usb/of.h>
  38 #include <linux/usb/otg.h>
  39 #include <linux/wakelock.h>
  40
  41 #define BIT_WRITEABLE_SHIFT     16
  42 #define SCHEDULE_DELAY          (60 * HZ)
  43 #define OTG_SCHEDULE_DELAY      (2 * HZ)
  44
  45 struct rockchip_usb2phy;
  46
  47 enum rockchip_usb2phy_port_id {
  48         USB2PHY_PORT_OTG,
  49         USB2PHY_PORT_HOST,
  50         USB2PHY_NUM_PORTS,
  51 };
  52
  53 enum rockchip_usb2phy_host_state {
  54         PHY_STATE_HS_ONLINE     = 0,
  55         PHY_STATE_DISCONNECT    = 1,
  56         PHY_STATE_CONNECT       = 2,
  57         PHY_STATE_FS_LS_ONLINE  = 4,
  58 };
  59
  60 /**
  61  * Different states involved in USB charger detection.
  62  * USB_CHG_STATE_UNDEFINED      USB charger is not connected or detection
  63  *                              process is not yet started.
  64  * USB_CHG_STATE_WAIT_FOR_DCD   Waiting for Data pins contact.
  65  * USB_CHG_STATE_DCD_DONE       Data pin contact is detected.
  66  * USB_CHG_STATE_PRIMARY_DONE   Primary detection is completed (Detects
  67  *                              between SDP and DCP/CDP).
  68  * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
  69  *                              between DCP and CDP).
  70  * USB_CHG_STATE_DETECTED       USB charger type is determined.
  71  */
  72 enum usb_chg_state {
  73         USB_CHG_STATE_UNDEFINED = 0,
  74         USB_CHG_STATE_WAIT_FOR_DCD,
  75         USB_CHG_STATE_DCD_DONE,
  76         USB_CHG_STATE_PRIMARY_DONE,
  77         USB_CHG_STATE_SECONDARY_DONE,
  78         USB_CHG_STATE_DETECTED,
  79 };
  80
  81 static const unsigned int rockchip_usb2phy_extcon_cable[] = {
  82         EXTCON_USB,
  83         EXTCON_USB_HOST,
  84         EXTCON_USB_VBUS_EN,
  85         EXTCON_CHG_USB_SDP,
  86         EXTCON_CHG_USB_CDP,
  87         EXTCON_CHG_USB_DCP,
  88         EXTCON_CHG_USB_SLOW,
  89         EXTCON_NONE,
  90 };
  91
  92 struct usb2phy_reg {
  93         unsigned int    offset;
  94         unsigned int    bitend;
  95         unsigned int    bitstart;
  96         unsigned int    disable;
  97         unsigned int    enable;
  98 };
  99
 100 /**
 101  * struct rockchip_chg_det_reg: usb charger detect registers
 102  * @cp_det: charging port detected successfully.
 103  * @dcp_det: dedicated charging port detected successfully.
 104  * @dp_det: assert data pin connect successfully.
 105  * @idm_sink_en: open dm sink curren.
 106  * @idp_sink_en: open dp sink current.
 107  * @idp_src_en: open dm source current.
 108  * @rdm_pdwn_en: open dm pull down resistor.
 109  * @vdm_src_en: open dm voltage source.
 110  * @vdp_src_en: open dp voltage source.
 111  * @opmode: utmi operational mode.
 112  */
 113 struct rockchip_chg_det_reg {
 114         struct usb2phy_reg      cp_det;
 115         struct usb2phy_reg      dcp_det;
 116         struct usb2phy_reg      dp_det;
 117         struct usb2phy_reg      idm_sink_en;
 118         struct usb2phy_reg      idp_sink_en;
 119         struct usb2phy_reg      idp_src_en;
 120         struct usb2phy_reg      rdm_pdwn_en;
 121         struct usb2phy_reg      vdm_src_en;
 122         struct usb2phy_reg      vdp_src_en;
 123         struct usb2phy_reg      opmode;
 124 };
 125
 126 /**
 127  * struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
 128  * @phy_sus: phy suspend register.
 129  * @bvalid_det_en: vbus valid rise detection enable register.
 130  * @bvalid_det_st: vbus valid rise detection status register.
 131  * @bvalid_det_clr: vbus valid rise detection clear register.
 132  * @ls_det_en: linestate detection enable register.
 133  * @ls_det_st: linestate detection state register.
 134  * @ls_det_clr: linestate detection clear register.
 135  * @idfall_det_en: id fall detection enable register.
 136  * @idfall_det_st: id fall detection state register.
 137  * @idfall_det_clr: id fall detection clear register.
 138  * @idrise_det_en: id rise detection enable register.
 139  * @idrise_det_st: id rise detection state register.
 140  * @idrise_det_clr: id rise detection clear register.
 141  * @utmi_avalid: utmi vbus avalid status register.
 142  * @utmi_bvalid: utmi vbus bvalid status register.
 143  * @utmi_iddig: otg port id pin status register.
 144  * @utmi_ls: utmi linestate state register.
 145  * @utmi_hstdet: utmi host disconnect register.
 146  */
 147 struct rockchip_usb2phy_port_cfg {
 148         struct usb2phy_reg      phy_sus;
 149         struct usb2phy_reg      bvalid_det_en;
 150         struct usb2phy_reg      bvalid_det_st;
 151         struct usb2phy_reg      bvalid_det_clr;
 152         struct usb2phy_reg      ls_det_en;
 153         struct usb2phy_reg      ls_det_st;
 154         struct usb2phy_reg      ls_det_clr;
 155         struct usb2phy_reg      idfall_det_en;
 156         struct usb2phy_reg      idfall_det_st;
 157         struct usb2phy_reg      idfall_det_clr;
 158         struct usb2phy_reg      idrise_det_en;
 159         struct usb2phy_reg      idrise_det_st;
 160         struct usb2phy_reg      idrise_det_clr;
 161         struct usb2phy_reg      utmi_avalid;
 162         struct usb2phy_reg      utmi_bvalid;
 163         struct usb2phy_reg      utmi_iddig;
 164         struct usb2phy_reg      utmi_ls;
 165         struct usb2phy_reg      utmi_hstdet;
 166 };
 167
 168 /**
 169  * struct rockchip_usb2phy_cfg: usb-phy configuration.
 170  * @reg: the address offset of grf for usb-phy config.
 171  * @num_ports: specify how many ports that the phy has.
 172  * @phy_tuning: phy default parameters tunning.
 173  * @clkout_ctl: keep on/turn off output clk of phy.
 174  * @chg_det: charger detection registers.
 175  */
 176 struct rockchip_usb2phy_cfg {
 177         unsigned int    reg;
 178         unsigned int    num_ports;
 179         int (*phy_tuning)(struct rockchip_usb2phy *);
 180         struct usb2phy_reg      clkout_ctl;
 181         const struct rockchip_usb2phy_port_cfg  port_cfgs[USB2PHY_NUM_PORTS];
 182         const struct rockchip_chg_det_reg       chg_det;
 183 };
 184
 185 /**
 186  * struct rockchip_usb2phy_port: usb-phy port data.
 187  * @port_id: flag for otg port or host port.
 188  * @perip_connected: flag for periphyeral connect status.
 189  * @suspended: phy suspended flag.
 190  * @utmi_avalid: utmi avalid status usage flag.
 191  *      true    - use avalid to get vbus status
 192  *      flase   - use bvalid to get vbus status
 193  * @vbus_attached: otg device vbus status.
 194  * @vbus_always_on: otg vbus is always powered on.
 195  * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
 196  * @ls_irq: IRQ number assigned for linestate detection.
 197  * @id_irq: IRQ number assigned for id fall or rise detection.
 198  * @mutex: for register updating in sm_work.
 199  * @chg_work: charge detect work.
 200  * @otg_sm_work: OTG state machine work.
 201  * @sm_work: HOST state machine work.
 202  * @phy_cfg: port register configuration, assigned by driver data.
 203  * @event_nb: hold event notification callback.
 204  * @wakelock: wake lock struct to prevent system suspend
 205  *            when USB is active.
 206  * @state: define OTG enumeration states before device reset.
 207  * @mode: the dr_mode of the controller.
 208  */
 209 struct rockchip_usb2phy_port {
 210         struct phy      *phy;
 211         unsigned int    port_id;
 212         bool            perip_connected;
 213         bool            suspended;
 214         bool            utmi_avalid;
 215         bool            vbus_attached;
 216         bool            vbus_always_on;
 217         int             bvalid_irq;
 218         int             ls_irq;
 219         int             id_irq;
 220         struct mutex    mutex;
 221         struct          delayed_work chg_work;
 222         struct          delayed_work otg_sm_work;
 223         struct          delayed_work sm_work;
 224         const struct    rockchip_usb2phy_port_cfg *port_cfg;
 225         struct notifier_block   event_nb;
 226         struct wake_lock        wakelock;
 227         enum usb_otg_state      state;
 228         enum usb_dr_mode        mode;
 229 };
 230
 231 /**
 232  * struct rockchip_usb2phy: usb2.0 phy driver data.
 233  * @grf: General Register Files regmap.
 234  * @clk: clock struct of phy input clk.
 235  * @clk480m: clock struct of phy output clk.
 236  * @clk_hw: clock struct of phy output clk management.
 237  * @chg_state: states involved in USB charger detection.
 238  * @chg_type: USB charger types.
 239  * @dcd_retries: The retry count used to track Data contact
 240  *               detection process.
 241  * @edev_self: represent the source of extcon.
 242  * @edev: extcon device for notification registration
 243  * @phy_cfg: phy register configuration, assigned by driver data.
 244  * @ports: phy port instance.
 245  */
 246 struct rockchip_usb2phy {
 247         struct device   *dev;
 248         struct regmap   *grf;
 249         struct clk      *clk;
 250         struct clk      *clk480m;
 251         struct clk_hw   clk480m_hw;
 252         enum usb_chg_state      chg_state;
 253         enum power_supply_type  chg_type;
 254         u8                      dcd_retries;
 255         u8                      primary_retries;
 256         bool                    edev_self;
 257         struct extcon_dev       *edev;
 258         const struct rockchip_usb2phy_cfg       *phy_cfg;
 259         struct rockchip_usb2phy_port    ports[USB2PHY_NUM_PORTS];
 260 };
 261
 262 static inline int property_enable(struct rockchip_usb2phy *rphy,
 263                                   const struct usb2phy_reg *reg, bool en)
 264 {
 265         unsigned int val, mask, tmp;
 266
 267         tmp = en ? reg->enable : reg->disable;
 268         mask = GENMASK(reg->bitend, reg->bitstart);
 269         val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
 270
 271         return regmap_write(rphy->grf, reg->offset, val);
 272 }
 273
 274 static inline bool property_enabled(struct rockchip_usb2phy *rphy,
 275                                     const struct usb2phy_reg *reg)
 276 {
 277         int ret;
 278         unsigned int tmp, orig;
 279         unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
 280
 281         ret = regmap_read(rphy->grf, reg->offset, &orig);
 282         if (ret)
 283                 return false;
 284
 285         tmp = (orig & mask) >> reg->bitstart;
 286         return tmp == reg->enable;
 287 }
 288
 289 static int rockchip_usb2phy_clk480m_enable(struct clk_hw *hw)
 290 {
 291         struct rockchip_usb2phy *rphy =
 292                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 293         int ret;
 294
 295         /* turn on 480m clk output if it is off */
 296         if (!property_enabled(rphy, &rphy->phy_cfg->clkout_ctl)) {
 297                 ret = property_enable(rphy, &rphy->phy_cfg->clkout_ctl, true);
 298                 if (ret)
 299                         return ret;
 300
 301                 /* waitting for the clk become stable */
 302                 udelay(1200);
 303         }
 304
 305         return 0;
 306 }
 307
 308 static void rockchip_usb2phy_clk480m_disable(struct clk_hw *hw)
 309 {
 310         struct rockchip_usb2phy *rphy =
 311                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 312
 313         /* turn off 480m clk output */
 314         property_enable(rphy, &rphy->phy_cfg->clkout_ctl, false);
 315 }
 316
 317 static int rockchip_usb2phy_clk480m_enabled(struct clk_hw *hw)
 318 {
 319         struct rockchip_usb2phy *rphy =
 320                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 321
 322         return property_enabled(rphy, &rphy->phy_cfg->clkout_ctl);
 323 }
 324
 325 static unsigned long
 326 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
 327                                      unsigned long parent_rate)
 328 {
 329         return 480000000;
 330 }
 331
 332 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
 333         .enable = rockchip_usb2phy_clk480m_enable,
 334         .disable = rockchip_usb2phy_clk480m_disable,
 335         .is_enabled = rockchip_usb2phy_clk480m_enabled,
 336         .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
 337 };
 338
 339 static void rockchip_usb2phy_clk480m_unregister(void *data)
 340 {
 341         struct rockchip_usb2phy *rphy = data;
 342
 343         of_clk_del_provider(rphy->dev->of_node);
 344         clk_unregister(rphy->clk480m);
 345 }
 346
 347 static int
 348 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
 349 {
 350         struct device_node *node = rphy->dev->of_node;
 351         struct clk_init_data init;
 352         const char *clk_name;
 353         int ret;
 354
 355         init.flags = 0;
 356         init.name = "clk_usbphy_480m";
 357         init.ops = &rockchip_usb2phy_clkout_ops;
 358
 359         /* optional override of the clockname */
 360         of_property_read_string(node, "clock-output-names", &init.name);
 361
 362         if (rphy->clk) {
 363                 clk_name = __clk_get_name(rphy->clk);
 364                 init.parent_names = &clk_name;
 365                 init.num_parents = 1;
 366         } else {
 367                 init.parent_names = NULL;
 368                 init.num_parents = 0;
 369         }
 370
 371         rphy->clk480m_hw.init = &init;
 372
 373         /* register the clock */
 374         rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
 375         if (IS_ERR(rphy->clk480m)) {
 376                 ret = PTR_ERR(rphy->clk480m);
 377                 goto err_ret;
 378         }
 379
 380         ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
 381         if (ret < 0)
 382                 goto err_clk_provider;
 383
 384         ret = devm_add_action(rphy->dev, rockchip_usb2phy_clk480m_unregister,
 385                               rphy);
 386         if (ret < 0)
 387                 goto err_unreg_action;
 388
 389         return 0;
 390
 391 err_unreg_action:
 392         of_clk_del_provider(node);
 393 err_clk_provider:
 394         clk_unregister(rphy->clk480m);
 395 err_ret:
 396         return ret;
 397 }
 398
 399 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
 400 {
 401         int ret;
 402         struct device_node *node = rphy->dev->of_node;
 403         struct extcon_dev *edev;
 404
 405         if (of_property_read_bool(node, "extcon")) {
 406                 edev = extcon_get_edev_by_phandle(rphy->dev, 0);
 407                 if (IS_ERR(edev)) {
 408                         if (PTR_ERR(edev) != -EPROBE_DEFER)
 409                                 dev_err(rphy->dev, "Invalid or missing extcon\n");
 410                         return PTR_ERR(edev);
 411                 }
 412         } else {
 413                 /* Initialize extcon device */
 414                 edev = devm_extcon_dev_allocate(rphy->dev,
 415                                                 rockchip_usb2phy_extcon_cable);
 416
 417                 if (IS_ERR(edev))
 418                         return -ENOMEM;
 419
 420                 ret = devm_extcon_dev_register(rphy->dev, edev);
 421                 if (ret) {
 422                         dev_err(rphy->dev, "failed to register extcon device\n");
 423                         return ret;
 424                 }
 425
 426                 rphy->edev_self = true;
 427         }
 428
 429         rphy->edev = edev;
 430
 431         return 0;
 432 }
 433
 434 static int rockchip_usb2phy_init(struct phy *phy)
 435 {
 436         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 437         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 438         int ret = 0;
 439
 440         mutex_lock(&rport->mutex);
 441
 442         if (rport->port_id == USB2PHY_PORT_OTG) {
 443                 if (rport->mode != USB_DR_MODE_HOST &&
 444                     !rport->vbus_always_on) {
 445                         /* clear bvalid status and enable bvalid detect irq */
 446                         ret = property_enable(rphy,
 447                                               &rport->port_cfg->
 448                                               bvalid_det_clr,
 449                                               true);
 450                         if (ret)
 451                                 goto out;
 452
 453                         ret = property_enable(rphy,
 454                                               &rport->port_cfg->
 455                                               bvalid_det_en,
 456                                               true);
 457                         if (ret)
 458                                 goto out;
 459
 460                         if (rphy->edev_self) {
 461                                 ret = property_enable(rphy,
 462                                                       &rport->port_cfg->
 463                                                       idfall_det_clr,
 464                                                       true);
 465                                 if (ret)
 466                                         goto out;
 467
 468                                 ret = property_enable(rphy,
 469                                                       &rport->port_cfg->
 470                                                       idfall_det_en,
 471                                                       true);
 472                                 if (ret)
 473                                         goto out;
 474
 475                                 ret = property_enable(rphy,
 476                                                       &rport->port_cfg->
 477                                                       idrise_det_clr,
 478                                                       true);
 479                                 if (ret)
 480                                         goto out;
 481
 482                                 ret = property_enable(rphy,
 483                                                       &rport->port_cfg->
 484                                                       idrise_det_en,
 485                                                       true);
 486                                 if (ret)
 487                                         goto out;
 488                         }
 489
 490                         schedule_delayed_work(&rport->otg_sm_work,
 491                                               OTG_SCHEDULE_DELAY);
 492                 } else {
 493                         /* If OTG works in host only mode, do nothing. */
 494                         dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode);
 495                 }
 496         } else if (rport->port_id == USB2PHY_PORT_HOST) {
 497                 /* clear linestate and enable linestate detect irq */
 498                 ret = property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
 499                 if (ret)
 500                         goto out;
 501
 502                 ret = property_enable(rphy, &rport->port_cfg->ls_det_en, true);
 503                 if (ret)
 504                         goto out;
 505
 506                 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
 507         }
 508
 509 out:
 510         mutex_unlock(&rport->mutex);
 511         return ret;
 512 }
 513
 514 static int rockchip_usb2phy_power_on(struct phy *phy)
 515 {
 516         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 517         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 518         int ret;
 519
 520         dev_dbg(&rport->phy->dev, "port power on\n");
 521
 522         if (!rport->suspended)
 523                 return 0;
 524
 525         ret = clk_prepare_enable(rphy->clk480m);
 526         if (ret)
 527                 return ret;
 528
 529         ret = property_enable(rphy, &rport->port_cfg->phy_sus, false);
 530         if (ret)
 531                 return ret;
 532
 533         rport->suspended = false;
 534         return 0;
 535 }
 536
 537 static int rockchip_usb2phy_power_off(struct phy *phy)
 538 {
 539         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 540         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 541         int ret;
 542
 543         dev_dbg(&rport->phy->dev, "port power off\n");
 544
 545         if (rport->suspended)
 546                 return 0;
 547
 548         ret = property_enable(rphy, &rport->port_cfg->phy_sus, true);
 549         if (ret)
 550                 return ret;
 551
 552         rport->suspended = true;
 553         clk_disable_unprepare(rphy->clk480m);
 554
 555         return 0;
 556 }
 557
 558 static int rockchip_usb2phy_exit(struct phy *phy)
 559 {
 560         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 561
 562         if (rport->port_id == USB2PHY_PORT_OTG &&
 563             rport->mode != USB_DR_MODE_HOST &&
 564             !rport->vbus_always_on)
 565                 cancel_delayed_work_sync(&rport->chg_work);
 566         else if (rport->port_id == USB2PHY_PORT_HOST)
 567                 cancel_delayed_work_sync(&rport->sm_work);
 568
 569         return 0;
 570 }
 571
 572 static const struct phy_ops rockchip_usb2phy_ops = {
 573         .init           = rockchip_usb2phy_init,
 574         .exit           = rockchip_usb2phy_exit,
 575         .power_on       = rockchip_usb2phy_power_on,
 576         .power_off      = rockchip_usb2phy_power_off,
 577         .owner          = THIS_MODULE,
 578 };
 579
 580 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
 581 {
 582         struct rockchip_usb2phy_port *rport =
 583                 container_of(work, struct rockchip_usb2phy_port,
 584                              otg_sm_work.work);
 585         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 586         static unsigned int cable;
 587         unsigned long delay;
 588         bool sch_work;
 589
 590         if (rport->utmi_avalid)
 591                 rport->vbus_attached =
 592                         property_enabled(rphy, &rport->port_cfg->utmi_avalid);
 593         else
 594                 rport->vbus_attached =
 595                         property_enabled(rphy, &rport->port_cfg->utmi_bvalid);
 596
 597         sch_work = false;
 598         delay = OTG_SCHEDULE_DELAY;
 599
 600         dev_dbg(&rport->phy->dev, "%s otg sm work\n",
 601                 usb_otg_state_string(rport->state));
 602
 603         switch (rport->state) {
 604         case OTG_STATE_UNDEFINED:
 605                 rport->state = OTG_STATE_B_IDLE;
 606                 if (!rport->vbus_attached)
 607                         rockchip_usb2phy_power_off(rport->phy);
 608                 /* fall through */
 609         case OTG_STATE_B_IDLE:
 610                 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) > 0 ||
 611                     extcon_get_cable_state_(rphy->edev,
 612                                             EXTCON_USB_VBUS_EN) > 0) {
 613                         dev_dbg(&rport->phy->dev, "usb otg host connect\n");
 614                         rport->state = OTG_STATE_A_HOST;
 615                         rockchip_usb2phy_power_on(rport->phy);
 616                         return;
 617                 } else if (rport->vbus_attached) {
 618                         dev_dbg(&rport->phy->dev, "vbus_attach\n");
 619                         switch (rphy->chg_state) {
 620                         case USB_CHG_STATE_UNDEFINED:
 621                                 schedule_delayed_work(&rport->chg_work, 0);
 622                                 return;
 623                         case USB_CHG_STATE_DETECTED:
 624                                 switch (rphy->chg_type) {
 625                                 case POWER_SUPPLY_TYPE_USB:
 626                                         dev_dbg(&rport->phy->dev,
 627                                                 "sdp cable is connecetd\n");
 628                                         wake_lock(&rport->wakelock);
 629                                         cable = EXTCON_CHG_USB_SDP;
 630                                         rockchip_usb2phy_power_on(rport->phy);
 631                                         rport->state = OTG_STATE_B_PERIPHERAL;
 632                                         rport->perip_connected = true;
 633                                         sch_work = true;
 634                                         break;
 635                                 case POWER_SUPPLY_TYPE_USB_DCP:
 636                                         dev_dbg(&rport->phy->dev,
 637                                                 "dcp cable is connecetd\n");
 638                                         cable = EXTCON_CHG_USB_DCP;
 639                                         rockchip_usb2phy_power_off(rport->phy);
 640                                         sch_work = true;
 641                                         break;
 642                                 case POWER_SUPPLY_TYPE_USB_CDP:
 643                                         dev_dbg(&rport->phy->dev,
 644                                                 "cdp cable is connecetd\n");
 645                                         wake_lock(&rport->wakelock);
 646                                         cable = EXTCON_CHG_USB_CDP;
 647                                         rockchip_usb2phy_power_on(rport->phy);
 648                                         rport->state = OTG_STATE_B_PERIPHERAL;
 649                                         rport->perip_connected = true;
 650                                         sch_work = true;
 651                                         break;
 652                                 case POWER_SUPPLY_TYPE_USB_FLOATING:
 653                                         dev_dbg(&rport->phy->dev,
 654                                                 "floating cable is connecetd\n");
 655                                         cable = EXTCON_CHG_USB_DCP;
 656                                         rockchip_usb2phy_power_off(rport->phy);
 657                                         sch_work = true;
 658                                         break;
 659                                 default:
 660                                         break;
 661                                 }
 662                                 break;
 663                         default:
 664                                 break;
 665                         }
 666                 } else {
 667                         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
 668                         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
 669                 }
 670                 break;
 671         case OTG_STATE_B_PERIPHERAL:
 672                 if (!rport->vbus_attached) {
 673                         dev_dbg(&rport->phy->dev, "usb disconnect\n");
 674                         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
 675                         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
 676                         rport->state = OTG_STATE_B_IDLE;
 677                         rport->perip_connected = false;
 678                         delay = 0;
 679                         rockchip_usb2phy_power_off(rport->phy);
 680                         wake_unlock(&rport->wakelock);
 681                 } else {
 682                         sch_work = true;
 683                 }
 684                 break;
 685         case OTG_STATE_A_HOST:
 686                 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) == 0) {
 687                         dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
 688                         rport->state = OTG_STATE_B_IDLE;
 689                         rockchip_usb2phy_power_off(rport->phy);
 690                 }
 691                 return;
 692         default:
 693                 return;
 694         }
 695
 696         if (extcon_get_state(rphy->edev, cable) != rport->vbus_attached)
 697                 extcon_set_cable_state_(rphy->edev,
 698                                         cable, rport->vbus_attached);
 699
 700         if (rphy->edev_self &&
 701             (extcon_get_state(rphy->edev, EXTCON_USB) !=
 702              rport->perip_connected))
 703                 extcon_set_cable_state_(rphy->edev,
 704                                         EXTCON_USB,
 705                                         rport->perip_connected);
 706
 707         if (sch_work)
 708                 schedule_delayed_work(&rport->otg_sm_work, delay);
 709 }
 710
 711 static const char *chg_to_string(enum power_supply_type chg_type)
 712 {
 713         switch (chg_type) {
 714         case POWER_SUPPLY_TYPE_USB:
 715                 return "USB_SDP_CHARGER";
 716         case POWER_SUPPLY_TYPE_USB_DCP:
 717                 return "USB_DCP_CHARGER";
 718         case POWER_SUPPLY_TYPE_USB_CDP:
 719                 return "USB_CDP_CHARGER";
 720         case POWER_SUPPLY_TYPE_USB_FLOATING:
 721                 return "USB_FLOATING_CHARGER";
 722         default:
 723                 return "INVALID_CHARGER";
 724         }
 725 }
 726
 727 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
 728                                     bool en)
 729 {
 730         property_enable(rphy, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
 731         property_enable(rphy, &rphy->phy_cfg->chg_det.idp_src_en, en);
 732 }
 733
 734 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
 735                                             bool en)
 736 {
 737         property_enable(rphy, &rphy->phy_cfg->chg_det.vdp_src_en, en);
 738         property_enable(rphy, &rphy->phy_cfg->chg_det.idm_sink_en, en);
 739 }
 740
 741 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
 742                                               bool en)
 743 {
 744         property_enable(rphy, &rphy->phy_cfg->chg_det.vdm_src_en, en);
 745         property_enable(rphy, &rphy->phy_cfg->chg_det.idp_sink_en, en);
 746 }
 747
 748 #define CHG_DCD_POLL_TIME       (100 * HZ / 1000)
 749 #define CHG_DCD_MAX_RETRIES     6
 750 #define CHG_PRIMARY_DET_TIME    (40 * HZ / 1000)
 751 #define CHG_SECONDARY_DET_TIME  (40 * HZ / 1000)
 752 static void rockchip_chg_detect_work(struct work_struct *work)
 753 {
 754         struct rockchip_usb2phy_port *rport =
 755                 container_of(work, struct rockchip_usb2phy_port, chg_work.work);
 756         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 757         bool is_dcd, tmout, vout;
 758         unsigned long delay;
 759
 760         dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
 761                 rphy->chg_state);
 762         switch (rphy->chg_state) {
 763         case USB_CHG_STATE_UNDEFINED:
 764                 if (!rport->suspended)
 765                         rockchip_usb2phy_power_off(rport->phy);
 766                 /* put the controller in non-driving mode */
 767                 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, false);
 768                 /* Start DCD processing stage 1 */
 769                 rockchip_chg_enable_dcd(rphy, true);
 770                 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
 771                 rphy->dcd_retries = 0;
 772                 rphy->primary_retries = 0;
 773                 delay = CHG_DCD_POLL_TIME;
 774                 break;
 775         case USB_CHG_STATE_WAIT_FOR_DCD:
 776                 /* get data contact detection status */
 777                 is_dcd = property_enabled(rphy, &rphy->phy_cfg->chg_det.dp_det);
 778                 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
 779                 /* stage 2 */
 780                 if (is_dcd || tmout) {
 781                         /* stage 4 */
 782                         /* Turn off DCD circuitry */
 783                         rockchip_chg_enable_dcd(rphy, false);
 784                         /* Voltage Source on DP, Probe on DM */
 785                         rockchip_chg_enable_primary_det(rphy, true);
 786                         delay = CHG_PRIMARY_DET_TIME;
 787                         rphy->chg_state = USB_CHG_STATE_DCD_DONE;
 788                 } else {
 789                         /* stage 3 */
 790                         delay = CHG_DCD_POLL_TIME;
 791                 }
 792                 break;
 793         case USB_CHG_STATE_DCD_DONE:
 794                 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.cp_det);
 795                 rockchip_chg_enable_primary_det(rphy, false);
 796                 if (vout) {
 797                         /* Voltage Source on DM, Probe on DP  */
 798                         rockchip_chg_enable_secondary_det(rphy, true);
 799                         delay = CHG_SECONDARY_DET_TIME;
 800                         rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
 801                 } else {
 802                         if (rphy->dcd_retries == CHG_DCD_MAX_RETRIES) {
 803                                 /* floating charger found */
 804                                 rphy->chg_type = POWER_SUPPLY_TYPE_USB_FLOATING;
 805                                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 806                                 delay = 0;
 807                         } else {
 808                                 if (rphy->primary_retries < 2) {
 809                                         /* Turn off DCD circuitry */
 810                                         rockchip_chg_enable_dcd(rphy, false);
 811                                         /* Voltage Source on DP, Probe on DM */
 812                                         rockchip_chg_enable_primary_det(rphy,
 813                                                                         true);
 814                                         delay = CHG_PRIMARY_DET_TIME;
 815                                         rphy->chg_state =
 816                                                 USB_CHG_STATE_DCD_DONE;
 817                                         rphy->primary_retries++;
 818                                         /* break USB_CHG_STATE_DCD_DONE */
 819                                         break;
 820                                 }
 821                                 rphy->chg_type = POWER_SUPPLY_TYPE_USB;
 822                                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 823                                 delay = 0;
 824                         }
 825                 }
 826                 break;
 827         case USB_CHG_STATE_PRIMARY_DONE:
 828                 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.dcp_det);
 829                 /* Turn off voltage source */
 830                 rockchip_chg_enable_secondary_det(rphy, false);
 831                 if (vout)
 832                         rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
 833                 else
 834                         rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
 835                 /* fall through */
 836         case USB_CHG_STATE_SECONDARY_DONE:
 837                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 838                 delay = 0;
 839                 /* fall through */
 840         case USB_CHG_STATE_DETECTED:
 841                 /* put the controller in normal mode */
 842                 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, true);
 843                 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
 844                 dev_info(&rport->phy->dev, "charger = %s\n",
 845                          chg_to_string(rphy->chg_type));
 846                 return;
 847         default:
 848                 return;
 849         }
 850
 851         schedule_delayed_work(&rport->chg_work, delay);
 852 }
 853
 854 /*
 855  * The function manage host-phy port state and suspend/resume phy port
 856  * to save power.
 857  *
 858  * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
 859  * devices is disconnect or not. Besides, we do not need care it is FS/LS
 860  * disconnected or HS disconnected, actually, we just only need get the
 861  * device is disconnected at last through rearm the delayed work,
 862  * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
 863  *
 864  * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
 865  * some clk related APIs, so do not invoke it from interrupt context directly.
 866  */
 867 static void rockchip_usb2phy_sm_work(struct work_struct *work)
 868 {
 869         struct rockchip_usb2phy_port *rport =
 870                 container_of(work, struct rockchip_usb2phy_port, sm_work.work);
 871         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 872         unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
 873                           rport->port_cfg->utmi_hstdet.bitstart + 1;
 874         unsigned int ul, uhd, state;
 875         unsigned int ul_mask, uhd_mask;
 876         int ret;
 877
 878         mutex_lock(&rport->mutex);
 879
 880         ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
 881         if (ret < 0)
 882                 goto next_schedule;
 883
 884         ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset,
 885                           &uhd);
 886         if (ret < 0)
 887                 goto next_schedule;
 888
 889         uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
 890                            rport->port_cfg->utmi_hstdet.bitstart);
 891         ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
 892                           rport->port_cfg->utmi_ls.bitstart);
 893
 894         /* stitch on utmi_ls and utmi_hstdet as phy state */
 895         state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
 896                 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
 897
 898         switch (state) {
 899         case PHY_STATE_HS_ONLINE:
 900                 dev_dbg(&rport->phy->dev, "HS online\n");
 901                 break;
 902         case PHY_STATE_FS_LS_ONLINE:
 903                 /*
 904                  * For FS/LS device, the online state share with connect state
 905                  * from utmi_ls and utmi_hstdet register, so we distinguish
 906                  * them via suspended flag.
 907                  *
 908                  * Plus, there are two cases, one is D- Line pull-up, and D+
 909                  * line pull-down, the state is 4; another is D+ line pull-up,
 910                  * and D- line pull-down, the state is 2.
 911                  */
 912                 if (!rport->suspended) {
 913                         /* D- line pull-up, D+ line pull-down */
 914                         dev_dbg(&rport->phy->dev, "FS/LS online\n");
 915                         break;
 916                 }
 917                 /* fall through */
 918         case PHY_STATE_CONNECT:
 919                 if (rport->suspended) {
 920                         dev_dbg(&rport->phy->dev, "Connected\n");
 921                         rockchip_usb2phy_power_on(rport->phy);
 922                         rport->suspended = false;
 923                 } else {
 924                         /* D+ line pull-up, D- line pull-down */
 925                         dev_dbg(&rport->phy->dev, "FS/LS online\n");
 926                 }
 927                 break;
 928         case PHY_STATE_DISCONNECT:
 929                 if (!rport->suspended) {
 930                         dev_dbg(&rport->phy->dev, "Disconnected\n");
 931                         rockchip_usb2phy_power_off(rport->phy);
 932                         rport->suspended = true;
 933                 }
 934
 935                 /*
 936                  * activate the linestate detection to get the next device
 937                  * plug-in irq.
 938                  */
 939                 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
 940                 property_enable(rphy, &rport->port_cfg->ls_det_en, true);
 941
 942                 /*
 943                  * we don't need to rearm the delayed work when the phy port
 944                  * is suspended.
 945                  */
 946                 mutex_unlock(&rport->mutex);
 947                 return;
 948         default:
 949                 dev_dbg(&rport->phy->dev, "unknown phy state\n");
 950                 break;
 951         }
 952
 953 next_schedule:
 954         mutex_unlock(&rport->mutex);
 955         schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
 956 }
 957
 958 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
 959 {
 960         struct rockchip_usb2phy_port *rport = data;
 961         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 962
 963         if (!property_enabled(rphy, &rport->port_cfg->ls_det_st))
 964                 return IRQ_NONE;
 965
 966         dev_dbg(&rport->phy->dev, "linestate interrupt\n");
 967
 968         mutex_lock(&rport->mutex);
 969
 970         /* disable linestate detect irq and clear its status */
 971         property_enable(rphy, &rport->port_cfg->ls_det_en, false);
 972         property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
 973
 974         mutex_unlock(&rport->mutex);
 975
 976         /*
 977          * In this case for host phy port, a new device is plugged in,
 978          * meanwhile, if the phy port is suspended, we need rearm the work to
 979          * resume it and mange its states; otherwise, we do nothing about that.
 980          */
 981         if (rport->suspended) {
 982                 if (rport->port_id == USB2PHY_PORT_HOST)
 983                         rockchip_usb2phy_sm_work(&rport->sm_work.work);
 984                 else
 985                         rockchip_usb2phy_power_on(rport->phy);
 986         }
 987
 988         return IRQ_HANDLED;
 989 }
 990
 991 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
 992 {
 993         struct rockchip_usb2phy_port *rport = data;
 994         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 995
 996         if (!property_enabled(rphy, &rport->port_cfg->bvalid_det_st))
 997                 return IRQ_NONE;
 998
 999         mutex_lock(&rport->mutex);
1000
1001         /* clear bvalid detect irq pending status */
1002         property_enable(rphy, &rport->port_cfg->bvalid_det_clr, true);
1003
1004         mutex_unlock(&rport->mutex);
1005
1006         rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
1007
1008         return IRQ_HANDLED;
1009 }
1010
1011 static irqreturn_t rockchip_usb2phy_id_irq(int irq, void *data)
1012 {
1013         struct rockchip_usb2phy_port *rport = data;
1014         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1015
1016         if (!property_enabled(rphy, &rport->port_cfg->idfall_det_st) &&
1017             !property_enabled(rphy, &rport->port_cfg->idrise_det_st))
1018                 return IRQ_NONE;
1019
1020         mutex_lock(&rport->mutex);
1021
1022         /* clear id fall or rise detect irq pending status */
1023         if (property_enabled(rphy, &rport->port_cfg->idfall_det_st)) {
1024                 property_enable(rphy, &rport->port_cfg->idfall_det_clr,
1025                                 true);
1026                 extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
1027                 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, true);
1028         } else if (property_enabled(rphy, &rport->port_cfg->idrise_det_st)) {
1029                 property_enable(rphy, &rport->port_cfg->idrise_det_clr,
1030                                 true);
1031                 extcon_set_state(rphy->edev, EXTCON_USB_HOST, false);
1032                 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, false);
1033         }
1034
1035         extcon_sync(rphy->edev, EXTCON_USB_HOST);
1036         extcon_sync(rphy->edev, EXTCON_USB_VBUS_EN);
1037
1038         mutex_unlock(&rport->mutex);
1039
1040         return IRQ_HANDLED;
1041 }
1042
1043 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
1044                                            struct rockchip_usb2phy_port *rport,
1045                                            struct device_node *child_np)
1046 {
1047         int ret;
1048
1049         rport->port_id = USB2PHY_PORT_HOST;
1050         rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
1051         rport->suspended = true;
1052
1053         mutex_init(&rport->mutex);
1054         INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
1055
1056         rport->ls_irq = of_irq_get_byname(child_np, "linestate");
1057         if (rport->ls_irq < 0) {
1058                 dev_err(rphy->dev, "no linestate irq provided\n");
1059                 return rport->ls_irq;
1060         }
1061
1062         ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
1063                                         rockchip_usb2phy_linestate_irq,
1064                                         IRQF_ONESHOT,
1065                                         "rockchip_usb2phy", rport);
1066         if (ret) {
1067                 dev_err(rphy->dev, "failed to request linestate irq handle\n");
1068                 return ret;
1069         }
1070
1071         return 0;
1072 }
1073
1074 static int rockchip_otg_event(struct notifier_block *nb,
1075                               unsigned long event, void *ptr)
1076 {
1077         struct rockchip_usb2phy_port *rport =
1078                 container_of(nb, struct rockchip_usb2phy_port, event_nb);
1079
1080         schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
1081
1082         return NOTIFY_DONE;
1083 }
1084
1085 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
1086                                           struct rockchip_usb2phy_port *rport,
1087                                           struct device_node *child_np)
1088 {
1089         int ret;
1090         int iddig;
1091
1092         rport->port_id = USB2PHY_PORT_OTG;
1093         rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
1094         rport->state = OTG_STATE_UNDEFINED;
1095
1096         /*
1097          * set suspended flag to true, but actually don't
1098          * put phy in suspend mode, it aims to enable usb
1099          * phy and clock in power_on() called by usb controller
1100          * driver during probe.
1101          */
1102         rport->suspended = true;
1103         rport->vbus_attached = false;
1104         rport->perip_connected = false;
1105
1106         mutex_init(&rport->mutex);
1107
1108         rport->ls_irq = of_irq_get_byname(child_np, "linestate");
1109         if (rport->ls_irq < 0) {
1110                 dev_err(rphy->dev, "no linestate irq provided\n");
1111                 return rport->ls_irq;
1112         }
1113
1114         ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
1115                                         rockchip_usb2phy_linestate_irq,
1116                                         IRQF_ONESHOT,
1117                                         "rockchip_usb2phy", rport);
1118         if (ret) {
1119                 dev_err(rphy->dev, "failed to request linestate irq handle\n");
1120                 return ret;
1121         }
1122
1123         rport->vbus_always_on =
1124                 of_property_read_bool(child_np, "rockchip,vbus-always-on");
1125
1126         rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
1127         if (rport->mode == USB_DR_MODE_HOST || rport->vbus_always_on)
1128                 return 0;
1129
1130         wake_lock_init(&rport->wakelock, WAKE_LOCK_SUSPEND, "rockchip_otg");
1131         INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
1132         INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
1133
1134         rport->utmi_avalid =
1135                 of_property_read_bool(child_np, "rockchip,utmi-avalid");
1136
1137         rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
1138         if (rport->bvalid_irq < 0) {
1139                 dev_err(rphy->dev, "no vbus valid irq provided\n");
1140                 return rport->bvalid_irq;
1141         }
1142
1143         ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, NULL,
1144                                         rockchip_usb2phy_bvalid_irq,
1145                                         IRQF_ONESHOT,
1146                                         "rockchip_usb2phy_bvalid", rport);
1147         if (ret) {
1148                 dev_err(rphy->dev, "failed to request otg-bvalid irq handle\n");
1149                 return ret;
1150         }
1151
1152         if (rphy->edev_self) {
1153                 rport->id_irq = of_irq_get_byname(child_np, "otg-id");
1154                 if (rport->id_irq < 0) {
1155                         dev_err(rphy->dev, "no otg id irq provided\n");
1156                         return rport->id_irq;
1157                 }
1158
1159                 ret = devm_request_threaded_irq(rphy->dev, rport->id_irq, NULL,
1160                                                 rockchip_usb2phy_id_irq,
1161                                                 IRQF_ONESHOT,
1162                                                 "rockchip_usb2phy_id", rport);
1163                 if (ret) {
1164                         dev_err(rphy->dev, "failed to request otg-id irq handle\n");
1165                         return ret;
1166                 }
1167
1168                 iddig = property_enabled(rphy, &rport->port_cfg->utmi_iddig);
1169                 if (!iddig) {
1170                         extcon_set_state(rphy->edev, EXTCON_USB, false);
1171                         extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
1172                         extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, true);
1173                 } else {
1174                         extcon_set_state(rphy->edev, EXTCON_USB_HOST, false);
1175                         extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, false);
1176                 }
1177         }
1178
1179         if (!IS_ERR(rphy->edev)) {
1180                 rport->event_nb.notifier_call = rockchip_otg_event;
1181
1182                 ret = extcon_register_notifier(rphy->edev, EXTCON_USB_HOST,
1183                                                &rport->event_nb);
1184                 if (ret < 0) {
1185                         dev_err(rphy->dev, "register USB HOST notifier failed\n");
1186                         return ret;
1187                 }
1188         }
1189
1190         return 0;
1191 }
1192
1193 static int rockchip_usb2phy_probe(struct platform_device *pdev)
1194 {
1195         struct device *dev = &pdev->dev;
1196         struct device_node *np = dev->of_node;
1197         struct device_node *child_np;
1198         struct phy_provider *provider;
1199         struct rockchip_usb2phy *rphy;
1200         const struct rockchip_usb2phy_cfg *phy_cfgs;
1201         const struct of_device_id *match;
1202         unsigned int reg;
1203         int index, ret;
1204
1205         rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
1206         if (!rphy)
1207                 return -ENOMEM;
1208
1209         match = of_match_device(dev->driver->of_match_table, dev);
1210         if (!match || !match->data) {
1211                 dev_err(dev, "phy configs are not assigned!\n");
1212                 return -EINVAL;
1213         }
1214
1215         if (!dev->parent || !dev->parent->of_node)
1216                 return -EINVAL;
1217
1218         rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
1219         if (IS_ERR(rphy->grf))
1220                 return PTR_ERR(rphy->grf);
1221
1222         if (of_property_read_u32(np, "reg", &reg)) {
1223                 dev_err(dev, "the reg property is not assigned in %s node\n",
1224                         np->name);
1225                 return -EINVAL;
1226         }
1227
1228         rphy->dev = dev;
1229         phy_cfgs = match->data;
1230         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1231         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1232         rphy->edev_self = false;
1233         platform_set_drvdata(pdev, rphy);
1234
1235         ret = rockchip_usb2phy_extcon_register(rphy);
1236         if (ret)
1237                 return ret;
1238
1239         /* find out a proper config which can be matched with dt. */
1240         index = 0;
1241         while (phy_cfgs[index].reg) {
1242                 if (phy_cfgs[index].reg == reg) {
1243                         rphy->phy_cfg = &phy_cfgs[index];
1244                         break;
1245                 }
1246
1247                 ++index;
1248         }
1249
1250         if (!rphy->phy_cfg) {
1251                 dev_err(dev, "no phy-config can be matched with %s node\n",
1252                         np->name);
1253                 return -EINVAL;
1254         }
1255
1256         rphy->clk = of_clk_get_by_name(np, "phyclk");
1257         if (!IS_ERR(rphy->clk)) {
1258                 clk_prepare_enable(rphy->clk);
1259         } else {
1260                 dev_info(&pdev->dev, "no phyclk specified\n");
1261                 rphy->clk = NULL;
1262         }
1263
1264         ret = rockchip_usb2phy_clk480m_register(rphy);
1265         if (ret) {
1266                 dev_err(dev, "failed to register 480m output clock\n");
1267                 goto disable_clks;
1268         }
1269
1270         if (rphy->phy_cfg->phy_tuning) {
1271                 ret = rphy->phy_cfg->phy_tuning(rphy);
1272                 if (ret)
1273                         goto disable_clks;
1274         }
1275
1276         index = 0;
1277         for_each_available_child_of_node(np, child_np) {
1278                 struct rockchip_usb2phy_port *rport = &rphy->ports[index];
1279                 struct phy *phy;
1280
1281                 /* This driver aims to support both otg-port and host-port */
1282                 if (of_node_cmp(child_np->name, "host-port") &&
1283                     of_node_cmp(child_np->name, "otg-port"))
1284                         goto next_child;
1285
1286                 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
1287                 if (IS_ERR(phy)) {
1288                         dev_err(dev, "failed to create phy\n");
1289                         ret = PTR_ERR(phy);
1290                         goto put_child;
1291                 }
1292
1293                 rport->phy = phy;
1294                 phy_set_drvdata(rport->phy, rport);
1295
1296                 /* initialize otg/host port separately */
1297                 if (!of_node_cmp(child_np->name, "host-port")) {
1298                         ret = rockchip_usb2phy_host_port_init(rphy, rport,
1299                                                               child_np);
1300                         if (ret)
1301                                 goto put_child;
1302                 } else {
1303                         ret = rockchip_usb2phy_otg_port_init(rphy, rport,
1304                                                              child_np);
1305                         if (ret)
1306                                 goto put_child;
1307                 }
1308
1309 next_child:
1310                 /* to prevent out of boundary */
1311                 if (++index >= rphy->phy_cfg->num_ports)
1312                         break;
1313         }
1314
1315         provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1316         return PTR_ERR_OR_ZERO(provider);
1317
1318 put_child:
1319         of_node_put(child_np);
1320 disable_clks:
1321         if (rphy->clk) {
1322                 clk_disable_unprepare(rphy->clk);
1323                 clk_put(rphy->clk);
1324         }
1325         return ret;
1326 }
1327
1328 static int rk3366_usb2phy_tuning(struct rockchip_usb2phy *rphy)
1329 {
1330         unsigned int open_pre_emphasize = 0xffff851f;
1331         unsigned int eye_height_tuning = 0xffff68c8;
1332         unsigned int compensation_tuning = 0xffff026e;
1333         int ret = 0;
1334
1335         /* open HS pre-emphasize to expand HS slew rate for each port. */
1336         ret |= regmap_write(rphy->grf, 0x0780, open_pre_emphasize);
1337         ret |= regmap_write(rphy->grf, 0x079c, eye_height_tuning);
1338         ret |= regmap_write(rphy->grf, 0x07b0, open_pre_emphasize);
1339         ret |= regmap_write(rphy->grf, 0x07cc, eye_height_tuning);
1340
1341         /* compensate default tuning reference relate to ODT and etc. */
1342         ret |= regmap_write(rphy->grf, 0x078c, compensation_tuning);
1343
1344         return ret;
1345 }
1346
1347 #ifdef CONFIG_PM_SLEEP
1348 static int rockchip_usb2phy_pm_suspend(struct device *dev)
1349 {
1350         struct rockchip_usb2phy *rphy = dev_get_drvdata(dev);
1351         struct rockchip_usb2phy_port *rport;
1352         int index;
1353
1354         for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
1355                 rport = &rphy->ports[index];
1356                 if (!rport->phy)
1357                         continue;
1358
1359                 if (!rport->suspended) {
1360                         if (rport->port_id == USB2PHY_PORT_HOST)
1361                                 rockchip_usb2phy_sm_work(&rport->sm_work.work);
1362                         else
1363                                 rockchip_usb2phy_power_off(rport->phy);
1364                 }
1365
1366                 /* activate the linestate to detect the next interrupt. */
1367                 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
1368                 property_enable(rphy, &rport->port_cfg->ls_det_en, true);
1369         }
1370
1371         return 0;
1372 }
1373
1374 static int rockchip_usb2phy_pm_resume(struct device *dev)
1375 {
1376         struct rockchip_usb2phy *rphy = dev_get_drvdata(dev);
1377         struct rockchip_usb2phy_port *rport;
1378         int index;
1379
1380         for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
1381                 rport = &rphy->ports[index];
1382                 if (!rport->phy)
1383                         continue;
1384
1385                 /*
1386                  * Resuming case, for host-port, *_linestate_irq() will take
1387                  * over all actions, but for otg-port, we should invoke
1388                  * *_power_on() to resume the phy-port manually.
1389                  */
1390                 if (rport->suspended && rport->port_id == USB2PHY_PORT_OTG)
1391                         rockchip_usb2phy_power_on(rport->phy);
1392         }
1393
1394         return 0;
1395 }
1396
1397 static const struct dev_pm_ops rockchip_usb2phy_dev_pm_ops = {
1398         SET_SYSTEM_SLEEP_PM_OPS(rockchip_usb2phy_pm_suspend,
1399                                 rockchip_usb2phy_pm_resume)
1400 };
1401
1402 #define ROCKCHIP_USB2PHY_DEV_PM (&rockchip_usb2phy_dev_pm_ops)
1403 #else
1404 #define ROCKCHIP_USB2PHY_DEV_PM NULL
1405 #endif /* CONFIG_PM_SLEEP */
1406
1407 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
1408         {
1409                 .reg = 0x700,
1410                 .num_ports      = 2,
1411                 .phy_tuning     = rk3366_usb2phy_tuning,
1412                 .clkout_ctl     = { 0x0724, 15, 15, 1, 0 },
1413                 .port_cfgs      = {
1414                         [USB2PHY_PORT_HOST] = {
1415                                 .phy_sus        = { 0x0728, 15, 0, 0, 0x1d1 },
1416                                 .ls_det_en      = { 0x0680, 4, 4, 0, 1 },
1417                                 .ls_det_st      = { 0x0690, 4, 4, 0, 1 },
1418                                 .ls_det_clr     = { 0x06a0, 4, 4, 0, 1 },
1419                                 .utmi_ls        = { 0x049c, 14, 13, 0, 1 },
1420                                 .utmi_hstdet    = { 0x049c, 12, 12, 0, 1 }
1421                         }
1422                 },
1423         },
1424         { /* sentinel */ }
1425 };
1426
1427 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1428         {
1429                 .reg            = 0xe450,
1430                 .num_ports      = 2,
1431                 .clkout_ctl     = { 0xe450, 4, 4, 1, 0 },
1432                 .port_cfgs      = {
1433                         [USB2PHY_PORT_OTG] = {
1434                                 .phy_sus = { 0xe454, 15, 0, 0x1452, 0x15d1 },
1435                                 .bvalid_det_en  = { 0xe3c0, 3, 3, 0, 1 },
1436                                 .bvalid_det_st  = { 0xe3e0, 3, 3, 0, 1 },
1437                                 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
1438                                 .idfall_det_en  = { 0xe3c0, 5, 5, 0, 1 },
1439                                 .idfall_det_st  = { 0xe3e0, 5, 5, 0, 1 },
1440                                 .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 },
1441                                 .idrise_det_en  = { 0xe3c0, 4, 4, 0, 1 },
1442                                 .idrise_det_st  = { 0xe3e0, 4, 4, 0, 1 },
1443                                 .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 },
1444                                 .ls_det_en      = { 0xe3c0, 2, 2, 0, 1 },
1445                                 .ls_det_st      = { 0xe3e0, 2, 2, 0, 1 },
1446                                 .ls_det_clr     = { 0xe3d0, 2, 2, 0, 1 },
1447                                 .utmi_avalid    = { 0xe2ac, 7, 7, 0, 1 },
1448                                 .utmi_bvalid    = { 0xe2ac, 12, 12, 0, 1 },
1449                                 .utmi_iddig     = { 0xe2ac, 8, 8, 0, 1 },
1450                                 .utmi_ls        = { 0xe2ac, 14, 13, 0, 1 },
1451                         },
1452                         [USB2PHY_PORT_HOST] = {
1453                                 .phy_sus        = { 0xe458, 1, 0, 0x2, 0x1 },
1454                                 .ls_det_en      = { 0xe3c0, 6, 6, 0, 1 },
1455                                 .ls_det_st      = { 0xe3e0, 6, 6, 0, 1 },
1456                                 .ls_det_clr     = { 0xe3d0, 6, 6, 0, 1 },
1457                                 .utmi_ls        = { 0xe2ac, 22, 21, 0, 1 },
1458                                 .utmi_hstdet    = { 0xe2ac, 23, 23, 0, 1 }
1459                         }
1460                 },
1461                 .chg_det = {
1462                         .opmode         = { 0xe454, 3, 0, 5, 1 },
1463                         .cp_det         = { 0xe2ac, 2, 2, 0, 1 },
1464                         .dcp_det        = { 0xe2ac, 1, 1, 0, 1 },
1465                         .dp_det         = { 0xe2ac, 0, 0, 0, 1 },
1466                         .idm_sink_en    = { 0xe450, 8, 8, 0, 1 },
1467                         .idp_sink_en    = { 0xe450, 7, 7, 0, 1 },
1468                         .idp_src_en     = { 0xe450, 9, 9, 0, 1 },
1469                         .rdm_pdwn_en    = { 0xe450, 10, 10, 0, 1 },
1470                         .vdm_src_en     = { 0xe450, 12, 12, 0, 1 },
1471                         .vdp_src_en     = { 0xe450, 11, 11, 0, 1 },
1472                 },
1473         },
1474         {
1475                 .reg            = 0xe460,
1476                 .num_ports      = 2,
1477                 .clkout_ctl     = { 0xe460, 4, 4, 1, 0 },
1478                 .port_cfgs      = {
1479                         [USB2PHY_PORT_OTG] = {
1480                                 .phy_sus = { 0xe464, 15, 0, 0x1452, 0x15d1 },
1481                                 .bvalid_det_en  = { 0xe3c0, 8, 8, 0, 1 },
1482                                 .bvalid_det_st  = { 0xe3e0, 8, 8, 0, 1 },
1483                                 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
1484                                 .idfall_det_en  = { 0xe3c0, 10, 10, 0, 1 },
1485                                 .idfall_det_st  = { 0xe3e0, 10, 10, 0, 1 },
1486                                 .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 },
1487                                 .idrise_det_en  = { 0xe3c0, 9, 9, 0, 1 },
1488                                 .idrise_det_st  = { 0xe3e0, 9, 9, 0, 1 },
1489                                 .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 },
1490                                 .ls_det_en      = { 0xe3c0, 7, 7, 0, 1 },
1491                                 .ls_det_st      = { 0xe3e0, 7, 7, 0, 1 },
1492                                 .ls_det_clr     = { 0xe3d0, 7, 7, 0, 1 },
1493                                 .utmi_avalid    = { 0xe2ac, 10, 10, 0, 1 },
1494                                 .utmi_bvalid    = { 0xe2ac, 16, 16, 0, 1 },
1495                                 .utmi_iddig     = { 0xe2ac, 11, 11, 0, 1 },
1496                                 .utmi_ls        = { 0xe2ac, 18, 17, 0, 1 },
1497                         },
1498                         [USB2PHY_PORT_HOST] = {
1499                                 .phy_sus        = { 0xe468, 1, 0, 0x2, 0x1 },
1500                                 .ls_det_en      = { 0xe3c0, 11, 11, 0, 1 },
1501                                 .ls_det_st      = { 0xe3e0, 11, 11, 0, 1 },
1502                                 .ls_det_clr     = { 0xe3d0, 11, 11, 0, 1 },
1503                                 .utmi_ls        = { 0xe2ac, 26, 25, 0, 1 },
1504                                 .utmi_hstdet    = { 0xe2ac, 27, 27, 0, 1 }
1505                         }
1506                 },
1507         },
1508         { /* sentinel */ }
1509 };
1510
1511 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
1512         { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
1513         { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
1514         {}
1515 };
1516 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
1517
1518 static struct platform_driver rockchip_usb2phy_driver = {
1519         .probe          = rockchip_usb2phy_probe,
1520         .driver         = {
1521                 .name   = "rockchip-usb2phy",
1522                 .pm     = ROCKCHIP_USB2PHY_DEV_PM,
1523                 .of_match_table = rockchip_usb2phy_dt_match,
1524         },
1525 };
1526 module_platform_driver(rockchip_usb2phy_driver);
1527
1528 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1529 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
1530 MODULE_LICENSE("GPL v2");