2 * Rockchip USB2.0 PHY with Innosilicon IP block driver
4 * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/clk.h>
17 #include <linux/clk-provider.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/jiffies.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/mutex.h>
27 #include <linux/of_address.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_platform.h>
30 #include <linux/phy/phy.h>
31 #include <linux/platform_device.h>
32 #include <linux/regmap.h>
33 #include <linux/mfd/syscon.h>
35 #define BIT_WRITEABLE_SHIFT 16
36 #define SCHEDULE_DELAY (60 * HZ)
38 struct rockchip_usb2phy;
40 enum rockchip_usb2phy_port_id {
46 enum rockchip_usb2phy_host_state {
47 PHY_STATE_HS_ONLINE = 0,
48 PHY_STATE_DISCONNECT = 1,
49 PHY_STATE_HS_CONNECT = 2,
50 PHY_STATE_FS_CONNECT = 4,
56 unsigned int bitstart;
62 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
63 * @phy_sus: phy suspend register.
64 * @ls_det_en: linestate detection enable register.
65 * @ls_det_st: linestate detection state register.
66 * @ls_det_clr: linestate detection clear register.
67 * @utmi_ls: utmi linestate state register.
68 * @utmi_hstdet: utmi host disconnect register.
70 struct rockchip_usb2phy_port_cfg {
71 struct usb2phy_reg phy_sus;
72 struct usb2phy_reg ls_det_en;
73 struct usb2phy_reg ls_det_st;
74 struct usb2phy_reg ls_det_clr;
75 struct usb2phy_reg utmi_ls;
76 struct usb2phy_reg utmi_hstdet;
80 * struct rockchip_usb2phy_cfg: usb-phy configuration.
81 * @num_ports: specify how many ports that the phy has.
82 * @phy_tuning: phy default parameters tunning.
83 * @clkout_ctl: keep on/turn off output clk of phy.
85 struct rockchip_usb2phy_cfg {
86 unsigned int num_ports;
87 int (*phy_tuning)(struct rockchip_usb2phy *);
88 struct usb2phy_reg clkout_ctl;
89 const struct rockchip_usb2phy_port_cfg *port_cfgs;
93 * struct rockchip_usb2phy_port: usb-phy port data.
94 * @port_id: flag for otg port or host port.
95 * @suspended: phy suspended flag.
96 * @ls_irq: IRQ number assigned for linestate detection.
97 * @mutex: for register updating in sm_work.
98 * @sm_work: OTG state machine work.
99 * @phy_cfg: port register configuration, assigned by driver data.
101 struct rockchip_usb2phy_port {
103 unsigned int port_id;
107 struct delayed_work sm_work;
108 const struct rockchip_usb2phy_port_cfg *port_cfg;
112 * struct rockchip_usb2phy: usb2.0 phy driver data.
113 * @grf: General Register Files regmap.
114 * @clk480m: clock struct of phy output clk.
115 * @clk_hw: clock struct of phy output clk management.
116 * @vbus_host_gpio: host VBUS direction output.
117 * @phy_cfg: phy register configuration, assigned by driver data.
118 * @ports: phy port instance.
120 struct rockchip_usb2phy {
124 struct clk_hw clk480m_hw;
125 struct gpio_desc *vbus_host_gpio;
126 const struct rockchip_usb2phy_cfg *phy_cfg;
127 struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS];
130 static inline int property_enable(struct rockchip_usb2phy *rphy,
131 const struct usb2phy_reg *reg, bool en)
133 unsigned int val, mask, tmp;
135 tmp = en ? reg->enable : reg->disable;
136 mask = GENMASK(reg->bitend, reg->bitstart);
137 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
139 return regmap_write(rphy->grf, reg->offset, val);
142 static inline bool property_enabled(struct rockchip_usb2phy *rphy,
143 const struct usb2phy_reg *reg)
146 unsigned int tmp, orig;
147 unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
149 ret = regmap_read(rphy->grf, reg->offset, &orig);
153 tmp = (orig & mask) >> reg->bitstart;
154 return tmp == reg->enable;
157 static int rockchip_usb2phy_clk480m_enable(struct clk_hw *hw)
159 struct rockchip_usb2phy *rphy =
160 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
163 /* turn on 480m clk output if it is off */
164 if (!property_enabled(rphy, &rphy->phy_cfg->clkout_ctl)) {
165 ret = property_enable(rphy, &rphy->phy_cfg->clkout_ctl, true);
169 /* waitting for the clk become stable */
176 static void rockchip_usb2phy_clk480m_disable(struct clk_hw *hw)
178 struct rockchip_usb2phy *rphy =
179 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
182 /* make sure all ports in suspended mode */
183 for (index = 0; index != rphy->phy_cfg->num_ports; index++)
184 if (!rphy->ports[index].suspended)
187 /* turn off 480m clk output */
188 property_enable(rphy, &rphy->phy_cfg->clkout_ctl, false);
191 static int rockchip_usb2phy_clk480m_enabled(struct clk_hw *hw)
193 struct rockchip_usb2phy *rphy =
194 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
196 return property_enabled(rphy, &rphy->phy_cfg->clkout_ctl);
200 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
201 unsigned long parent_rate)
206 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
207 .enable = rockchip_usb2phy_clk480m_enable,
208 .disable = rockchip_usb2phy_clk480m_disable,
209 .is_enabled = rockchip_usb2phy_clk480m_enabled,
210 .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
214 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
216 struct device_node *node = rphy->dev->of_node;
218 struct clk_init_data init;
220 init.name = "clk_usbphy_480m";
221 init.ops = &rockchip_usb2phy_clkout_ops;
222 init.flags = CLK_IS_ROOT;
223 init.parent_names = NULL;
224 init.num_parents = 0;
225 rphy->clk480m_hw.init = &init;
227 /* optional override of the clockname */
228 of_property_read_string(node, "clock-output-names", &init.name);
230 /* register the clock */
231 clk = clk_register(rphy->dev, &rphy->clk480m_hw);
233 of_clk_add_provider(node, of_clk_src_simple_get, clk);
238 static int rockchip_usb2phy_init(struct phy *phy)
240 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
241 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
244 if (rport->port_id == USB2PHY_PORT_HOST) {
245 /* clear linestate and enable linestate detect irq */
246 mutex_lock(&rport->mutex);
248 ret = property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
250 mutex_unlock(&rport->mutex);
254 ret = property_enable(rphy, &rport->port_cfg->ls_det_en, true);
256 mutex_unlock(&rport->mutex);
260 mutex_unlock(&rport->mutex);
261 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
267 static int rockchip_usb2phy_resume(struct phy *phy)
269 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
270 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
273 dev_dbg(&rport->phy->dev, "port resume\n");
275 ret = clk_prepare_enable(rphy->clk480m);
279 ret = property_enable(rphy, &rport->port_cfg->phy_sus, false);
283 rport->suspended = false;
287 static int rockchip_usb2phy_suspend(struct phy *phy)
289 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
290 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
293 dev_dbg(&rport->phy->dev, "port suspend\n");
295 ret = property_enable(rphy, &rport->port_cfg->phy_sus, true);
299 rport->suspended = true;
300 clk_disable_unprepare(rphy->clk480m);
304 static int rockchip_usb2phy_exit(struct phy *phy)
306 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
308 if (rport->port_id == USB2PHY_PORT_HOST)
309 cancel_delayed_work_sync(&rport->sm_work);
314 static const struct phy_ops rockchip_usb2phy_ops = {
315 .init = rockchip_usb2phy_init,
316 .exit = rockchip_usb2phy_exit,
317 .power_on = rockchip_usb2phy_resume,
318 .power_off = rockchip_usb2phy_suspend,
319 .owner = THIS_MODULE,
323 * The function manage host-phy port state and suspend/resume phy port
326 * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
327 * FS/HS is disconnect or not. Besides, we do not need care it is FS
328 * disconnected or HS disconnected, actually, we just only need get the
329 * device is disconnected at last through rearm the delayed work,
330 * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
332 * NOTE: It will invoke some clk related APIs, so do not invoke it from
335 static void rockchip_usb2phy_sm_work(struct work_struct *work)
337 struct rockchip_usb2phy_port *rport =
338 container_of(work, struct rockchip_usb2phy_port, sm_work.work);
339 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
340 unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
341 rport->port_cfg->utmi_hstdet.bitstart + 1;
342 unsigned int ul, uhd, state;
343 unsigned int ul_mask, uhd_mask;
346 mutex_lock(&rport->mutex);
348 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
352 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset,
357 uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
358 rport->port_cfg->utmi_hstdet.bitstart);
359 ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
360 rport->port_cfg->utmi_ls.bitstart);
362 /* stitch on utmi_ls and utmi_hstdet as phy state */
363 state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
364 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
367 case PHY_STATE_HS_ONLINE:
368 dev_dbg(&rport->phy->dev, "HS online\n");
370 case PHY_STATE_FS_CONNECT:
372 * For FS device, the online state share with connect state
373 * from utmi_ls and utmi_hstdet register, so we distinguish
374 * them via suspended flag.
376 if (!rport->suspended) {
377 dev_dbg(&rport->phy->dev, "FS online\n");
381 case PHY_STATE_HS_CONNECT:
382 if (rport->suspended) {
383 dev_dbg(&rport->phy->dev, "HS/FS connected\n");
384 rockchip_usb2phy_resume(rport->phy);
385 rport->suspended = false;
388 case PHY_STATE_DISCONNECT:
389 if (!rport->suspended) {
390 dev_dbg(&rport->phy->dev, "HS/FS disconnected\n");
391 rockchip_usb2phy_suspend(rport->phy);
392 rport->suspended = true;
396 * activate the linestate detection to get the next device
399 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
400 property_enable(rphy, &rport->port_cfg->ls_det_en, true);
403 * we don't need to rearm the delayed work when the phy port
406 mutex_unlock(&rport->mutex);
409 dev_dbg(&rport->phy->dev, "unknown phy state\n");
414 mutex_unlock(&rport->mutex);
415 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
418 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
420 struct rockchip_usb2phy_port *rport = data;
421 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
423 if (!property_enabled(rphy, &rport->port_cfg->ls_det_st))
426 mutex_lock(&rport->mutex);
428 /* disable linestate detect irq and clear its status */
429 property_enable(rphy, &rport->port_cfg->ls_det_en, false);
430 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
432 mutex_unlock(&rport->mutex);
435 * In this case for host phy port, a new device is plugged in,
436 * meanwhile, if the phy port is suspended, we need rearm the work to
437 * resume it and mange its states; otherwise, we do nothing about that.
439 if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST)
440 rockchip_usb2phy_sm_work(&rport->sm_work.work);
445 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
446 struct rockchip_usb2phy_port *rport,
447 struct device_node *child_np)
451 rport->port_id = USB2PHY_PORT_HOST;
452 mutex_init(&rport->mutex);
453 INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
455 rport->ls_irq = of_irq_get_byname(child_np, "linestate");
456 if (rport->ls_irq < 0) {
457 dev_err(rphy->dev, "no linestate irq provided\n");
458 return rport->ls_irq;
461 ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
462 rockchip_usb2phy_linestate_irq,
464 "rockchip_usb2phy", rport);
466 dev_err(rphy->dev, "failed to request irq handle\n");
473 static int rockchip_usb2phy_probe(struct platform_device *pdev)
475 struct device *dev = &pdev->dev;
476 struct device_node *np = dev->of_node;
477 struct device_node *child_np;
478 struct phy_provider *provider;
479 struct rockchip_usb2phy *rphy;
480 const struct of_device_id *match;
483 rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
487 match = of_match_device(dev->driver->of_match_table, dev);
488 if (!match || !match->data) {
489 dev_err(dev, "phy configs are not assigned!\n");
493 if (!dev->parent || !dev->parent->of_node)
496 rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
497 if (IS_ERR(rphy->grf))
498 return PTR_ERR(rphy->grf);
501 rphy->phy_cfg = match->data;
502 platform_set_drvdata(pdev, rphy);
504 rphy->clk480m = rockchip_usb2phy_clk480m_register(rphy);
505 if (IS_ERR(rphy->clk480m))
506 return PTR_ERR(rphy->clk480m);
508 if (rphy->phy_cfg->phy_tuning) {
509 ret = rphy->phy_cfg->phy_tuning(rphy);
514 rphy->vbus_host_gpio =
515 devm_gpiod_get_optional(dev, "vbus_host", GPIOD_OUT_HIGH);
516 if (!rphy->vbus_host_gpio)
517 dev_info(dev, "host_vbus is not assigned!\n");
518 else if (IS_ERR(rphy->vbus_host_gpio))
519 return PTR_ERR(rphy->vbus_host_gpio);
522 for_each_child_of_node(np, child_np) {
523 struct rockchip_usb2phy_port *rport = &rphy->ports[index];
526 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
528 dev_err(dev, "failed to create phy\n");
534 rport->port_cfg = &rphy->phy_cfg->port_cfgs[index];
536 /* initialize otg/host port separately */
537 if (!of_node_cmp(child_np->name, "host-port")) {
538 ret = rockchip_usb2phy_host_port_init(rphy, rport,
544 phy_set_drvdata(rport->phy, rport);
548 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
549 return PTR_ERR_OR_ZERO(provider);
552 of_node_put(child_np);
553 of_clk_del_provider(np);
554 clk_unregister(rphy->clk480m);
558 static int rk3366_usb2phy_tuning(struct rockchip_usb2phy *rphy)
560 unsigned int open_pre_emphasize = 0xffff851f;
561 unsigned int eye_height_tuning = 0xffff68c8;
562 unsigned int compensation_tuning = 0xffff026e;
565 /* open HS pre-emphasize to expand HS slew rate for each port. */
566 ret |= regmap_write(rphy->grf, 0x0780, open_pre_emphasize);
567 ret |= regmap_write(rphy->grf, 0x079c, eye_height_tuning);
568 ret |= regmap_write(rphy->grf, 0x07b0, open_pre_emphasize);
569 ret |= regmap_write(rphy->grf, 0x07cc, eye_height_tuning);
571 /* compensate default tuning reference relate to ODT and etc. */
572 ret |= regmap_write(rphy->grf, 0x078c, compensation_tuning);
577 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs = {
579 .phy_tuning = rk3366_usb2phy_tuning,
580 .clkout_ctl = { 0x0724, 15, 15, 1, 0 },
581 .port_cfgs = (struct rockchip_usb2phy_port_cfg[]) {
583 .phy_sus = { 0x0728, 15, 0, 0, 0x1d1 },
584 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
585 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
586 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 },
587 .utmi_ls = { 0x049c, 14, 13, 0, 1 },
588 .utmi_hstdet = { 0x049c, 12, 12, 0, 1 }
594 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
595 { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
598 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
600 static struct platform_driver rockchip_usb2phy_driver = {
601 .probe = rockchip_usb2phy_probe,
603 .name = "rockchip-usb2phy",
604 .of_match_table = rockchip_usb2phy_dt_match,
607 module_platform_driver(rockchip_usb2phy_driver);
609 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
610 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
611 MODULE_LICENSE("GPL v2");