drivers/phy/phy-rockchip-inno-usb2.c

   1 /*
   2  * Rockchip USB2.0 PHY with Innosilicon IP block driver
   3  *
   4  * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/delay.h>
  20 #include <linux/extcon.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/gpio/consumer.h>
  24 #include <linux/jiffies.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/mutex.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/phy/phy.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/power_supply.h>
  35 #include <linux/regmap.h>
  36 #include <linux/mfd/syscon.h>
  37 #include <linux/usb/of.h>
  38 #include <linux/usb/otg.h>
  39 #include <linux/wakelock.h>
  40
  41 #define BIT_WRITEABLE_SHIFT     16
  42 #define SCHEDULE_DELAY          (60 * HZ)
  43 #define OTG_SCHEDULE_DELAY      (2 * HZ)
  44
  45 struct rockchip_usb2phy;
  46
  47 enum rockchip_usb2phy_port_id {
  48         USB2PHY_PORT_OTG,
  49         USB2PHY_PORT_HOST,
  50         USB2PHY_NUM_PORTS,
  51 };
  52
  53 enum rockchip_usb2phy_host_state {
  54         PHY_STATE_HS_ONLINE     = 0,
  55         PHY_STATE_DISCONNECT    = 1,
  56         PHY_STATE_CONNECT       = 2,
  57         PHY_STATE_FS_LS_ONLINE  = 4,
  58 };
  59
  60 /**
  61  * Different states involved in USB charger detection.
  62  * USB_CHG_STATE_UNDEFINED      USB charger is not connected or detection
  63  *                              process is not yet started.
  64  * USB_CHG_STATE_WAIT_FOR_DCD   Waiting for Data pins contact.
  65  * USB_CHG_STATE_DCD_DONE       Data pin contact is detected.
  66  * USB_CHG_STATE_PRIMARY_DONE   Primary detection is completed (Detects
  67  *                              between SDP and DCP/CDP).
  68  * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
  69  *                              between DCP and CDP).
  70  * USB_CHG_STATE_DETECTED       USB charger type is determined.
  71  */
  72 enum usb_chg_state {
  73         USB_CHG_STATE_UNDEFINED = 0,
  74         USB_CHG_STATE_WAIT_FOR_DCD,
  75         USB_CHG_STATE_DCD_DONE,
  76         USB_CHG_STATE_PRIMARY_DONE,
  77         USB_CHG_STATE_SECONDARY_DONE,
  78         USB_CHG_STATE_DETECTED,
  79 };
  80
  81 static const unsigned int rockchip_usb2phy_extcon_cable[] = {
  82         EXTCON_USB,
  83         EXTCON_USB_HOST,
  84         EXTCON_USB_VBUS_EN,
  85         EXTCON_CHG_USB_SDP,
  86         EXTCON_CHG_USB_CDP,
  87         EXTCON_CHG_USB_DCP,
  88         EXTCON_CHG_USB_SLOW,
  89         EXTCON_NONE,
  90 };
  91
  92 struct usb2phy_reg {
  93         unsigned int    offset;
  94         unsigned int    bitend;
  95         unsigned int    bitstart;
  96         unsigned int    disable;
  97         unsigned int    enable;
  98 };
  99
 100 /**
 101  * struct rockchip_chg_det_reg: usb charger detect registers
 102  * @cp_det: charging port detected successfully.
 103  * @dcp_det: dedicated charging port detected successfully.
 104  * @dp_det: assert data pin connect successfully.
 105  * @idm_sink_en: open dm sink curren.
 106  * @idp_sink_en: open dp sink current.
 107  * @idp_src_en: open dm source current.
 108  * @rdm_pdwn_en: open dm pull down resistor.
 109  * @vdm_src_en: open dm voltage source.
 110  * @vdp_src_en: open dp voltage source.
 111  * @opmode: utmi operational mode.
 112  */
 113 struct rockchip_chg_det_reg {
 114         struct usb2phy_reg      cp_det;
 115         struct usb2phy_reg      dcp_det;
 116         struct usb2phy_reg      dp_det;
 117         struct usb2phy_reg      idm_sink_en;
 118         struct usb2phy_reg      idp_sink_en;
 119         struct usb2phy_reg      idp_src_en;
 120         struct usb2phy_reg      rdm_pdwn_en;
 121         struct usb2phy_reg      vdm_src_en;
 122         struct usb2phy_reg      vdp_src_en;
 123         struct usb2phy_reg      opmode;
 124 };
 125
 126 /**
 127  * struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
 128  * @phy_sus: phy suspend register.
 129  * @bvalid_det_en: vbus valid rise detection enable register.
 130  * @bvalid_det_st: vbus valid rise detection status register.
 131  * @bvalid_det_clr: vbus valid rise detection clear register.
 132  * @ls_det_en: linestate detection enable register.
 133  * @ls_det_st: linestate detection state register.
 134  * @ls_det_clr: linestate detection clear register.
 135  * @idfall_det_en: id fall detection enable register.
 136  * @idfall_det_st: id fall detection state register.
 137  * @idfall_det_clr: id fall detection clear register.
 138  * @idrise_det_en: id rise detection enable register.
 139  * @idrise_det_st: id rise detection state register.
 140  * @idrise_det_clr: id rise detection clear register.
 141  * @utmi_avalid: utmi vbus avalid status register.
 142  * @utmi_bvalid: utmi vbus bvalid status register.
 143  * @utmi_iddig: otg port id pin status register.
 144  * @utmi_ls: utmi linestate state register.
 145  * @utmi_hstdet: utmi host disconnect register.
 146  */
 147 struct rockchip_usb2phy_port_cfg {
 148         struct usb2phy_reg      phy_sus;
 149         struct usb2phy_reg      bvalid_det_en;
 150         struct usb2phy_reg      bvalid_det_st;
 151         struct usb2phy_reg      bvalid_det_clr;
 152         struct usb2phy_reg      ls_det_en;
 153         struct usb2phy_reg      ls_det_st;
 154         struct usb2phy_reg      ls_det_clr;
 155         struct usb2phy_reg      idfall_det_en;
 156         struct usb2phy_reg      idfall_det_st;
 157         struct usb2phy_reg      idfall_det_clr;
 158         struct usb2phy_reg      idrise_det_en;
 159         struct usb2phy_reg      idrise_det_st;
 160         struct usb2phy_reg      idrise_det_clr;
 161         struct usb2phy_reg      utmi_avalid;
 162         struct usb2phy_reg      utmi_bvalid;
 163         struct usb2phy_reg      utmi_iddig;
 164         struct usb2phy_reg      utmi_ls;
 165         struct usb2phy_reg      utmi_hstdet;
 166 };
 167
 168 /**
 169  * struct rockchip_usb2phy_cfg: usb-phy configuration.
 170  * @reg: the address offset of grf for usb-phy config.
 171  * @num_ports: specify how many ports that the phy has.
 172  * @phy_tuning: phy default parameters tunning.
 173  * @clkout_ctl: keep on/turn off output clk of phy.
 174  * @chg_det: charger detection registers.
 175  */
 176 struct rockchip_usb2phy_cfg {
 177         unsigned int    reg;
 178         unsigned int    num_ports;
 179         int (*phy_tuning)(struct rockchip_usb2phy *);
 180         struct usb2phy_reg      clkout_ctl;
 181         const struct rockchip_usb2phy_port_cfg  port_cfgs[USB2PHY_NUM_PORTS];
 182         const struct rockchip_chg_det_reg       chg_det;
 183 };
 184
 185 /**
 186  * struct rockchip_usb2phy_port: usb-phy port data.
 187  * @port_id: flag for otg port or host port.
 188  * @perip_connected: flag for periphyeral connect status.
 189  * @suspended: phy suspended flag.
 190  * @utmi_avalid: utmi avalid status usage flag.
 191  *      true    - use avalid to get vbus status
 192  *      flase   - use bvalid to get vbus status
 193  * @vbus_attached: otg device vbus status.
 194  * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
 195  * @ls_irq: IRQ number assigned for linestate detection.
 196  * @id_irq: IRQ number assigned for id fall or rise detection.
 197  * @mutex: for register updating in sm_work.
 198  * @chg_work: charge detect work.
 199  * @otg_sm_work: OTG state machine work.
 200  * @sm_work: HOST state machine work.
 201  * @phy_cfg: port register configuration, assigned by driver data.
 202  * @event_nb: hold event notification callback.
 203  * @wakelock: wake lock struct to prevent system suspend
 204  *            when USB is active.
 205  * @state: define OTG enumeration states before device reset.
 206  * @mode: the dr_mode of the controller.
 207  */
 208 struct rockchip_usb2phy_port {
 209         struct phy      *phy;
 210         unsigned int    port_id;
 211         bool            perip_connected;
 212         bool            suspended;
 213         bool            utmi_avalid;
 214         bool            vbus_attached;
 215         int             bvalid_irq;
 216         int             ls_irq;
 217         int             id_irq;
 218         struct mutex    mutex;
 219         struct          delayed_work chg_work;
 220         struct          delayed_work otg_sm_work;
 221         struct          delayed_work sm_work;
 222         const struct    rockchip_usb2phy_port_cfg *port_cfg;
 223         struct notifier_block   event_nb;
 224         struct wake_lock        wakelock;
 225         enum usb_otg_state      state;
 226         enum usb_dr_mode        mode;
 227 };
 228
 229 /**
 230  * struct rockchip_usb2phy: usb2.0 phy driver data.
 231  * @grf: General Register Files regmap.
 232  * @clk: clock struct of phy input clk.
 233  * @clk480m: clock struct of phy output clk.
 234  * @clk_hw: clock struct of phy output clk management.
 235  * @chg_state: states involved in USB charger detection.
 236  * @chg_type: USB charger types.
 237  * @dcd_retries: The retry count used to track Data contact
 238  *               detection process.
 239  * @edev_self: represent the source of extcon.
 240  * @edev: extcon device for notification registration
 241  * @phy_cfg: phy register configuration, assigned by driver data.
 242  * @ports: phy port instance.
 243  */
 244 struct rockchip_usb2phy {
 245         struct device   *dev;
 246         struct regmap   *grf;
 247         struct clk      *clk;
 248         struct clk      *clk480m;
 249         struct clk_hw   clk480m_hw;
 250         enum usb_chg_state      chg_state;
 251         enum power_supply_type  chg_type;
 252         u8                      dcd_retries;
 253         u8                      primary_retries;
 254         bool                    edev_self;
 255         struct extcon_dev       *edev;
 256         const struct rockchip_usb2phy_cfg       *phy_cfg;
 257         struct rockchip_usb2phy_port    ports[USB2PHY_NUM_PORTS];
 258 };
 259
 260 static inline int property_enable(struct rockchip_usb2phy *rphy,
 261                                   const struct usb2phy_reg *reg, bool en)
 262 {
 263         unsigned int val, mask, tmp;
 264
 265         tmp = en ? reg->enable : reg->disable;
 266         mask = GENMASK(reg->bitend, reg->bitstart);
 267         val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
 268
 269         return regmap_write(rphy->grf, reg->offset, val);
 270 }
 271
 272 static inline bool property_enabled(struct rockchip_usb2phy *rphy,
 273                                     const struct usb2phy_reg *reg)
 274 {
 275         int ret;
 276         unsigned int tmp, orig;
 277         unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
 278
 279         ret = regmap_read(rphy->grf, reg->offset, &orig);
 280         if (ret)
 281                 return false;
 282
 283         tmp = (orig & mask) >> reg->bitstart;
 284         return tmp == reg->enable;
 285 }
 286
 287 static int rockchip_usb2phy_clk480m_enable(struct clk_hw *hw)
 288 {
 289         struct rockchip_usb2phy *rphy =
 290                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 291         int ret;
 292
 293         /* turn on 480m clk output if it is off */
 294         if (!property_enabled(rphy, &rphy->phy_cfg->clkout_ctl)) {
 295                 ret = property_enable(rphy, &rphy->phy_cfg->clkout_ctl, true);
 296                 if (ret)
 297                         return ret;
 298
 299                 /* waitting for the clk become stable */
 300                 udelay(1200);
 301         }
 302
 303         return 0;
 304 }
 305
 306 static void rockchip_usb2phy_clk480m_disable(struct clk_hw *hw)
 307 {
 308         struct rockchip_usb2phy *rphy =
 309                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 310
 311         /* turn off 480m clk output */
 312         property_enable(rphy, &rphy->phy_cfg->clkout_ctl, false);
 313 }
 314
 315 static int rockchip_usb2phy_clk480m_enabled(struct clk_hw *hw)
 316 {
 317         struct rockchip_usb2phy *rphy =
 318                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 319
 320         return property_enabled(rphy, &rphy->phy_cfg->clkout_ctl);
 321 }
 322
 323 static unsigned long
 324 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
 325                                      unsigned long parent_rate)
 326 {
 327         return 480000000;
 328 }
 329
 330 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
 331         .enable = rockchip_usb2phy_clk480m_enable,
 332         .disable = rockchip_usb2phy_clk480m_disable,
 333         .is_enabled = rockchip_usb2phy_clk480m_enabled,
 334         .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
 335 };
 336
 337 static void rockchip_usb2phy_clk480m_unregister(void *data)
 338 {
 339         struct rockchip_usb2phy *rphy = data;
 340
 341         of_clk_del_provider(rphy->dev->of_node);
 342         clk_unregister(rphy->clk480m);
 343 }
 344
 345 static int
 346 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
 347 {
 348         struct device_node *node = rphy->dev->of_node;
 349         struct clk_init_data init;
 350         const char *clk_name;
 351         int ret;
 352
 353         init.flags = 0;
 354         init.name = "clk_usbphy_480m";
 355         init.ops = &rockchip_usb2phy_clkout_ops;
 356
 357         /* optional override of the clockname */
 358         of_property_read_string(node, "clock-output-names", &init.name);
 359
 360         if (rphy->clk) {
 361                 clk_name = __clk_get_name(rphy->clk);
 362                 init.parent_names = &clk_name;
 363                 init.num_parents = 1;
 364         } else {
 365                 init.parent_names = NULL;
 366                 init.num_parents = 0;
 367         }
 368
 369         rphy->clk480m_hw.init = &init;
 370
 371         /* register the clock */
 372         rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
 373         if (IS_ERR(rphy->clk480m)) {
 374                 ret = PTR_ERR(rphy->clk480m);
 375                 goto err_ret;
 376         }
 377
 378         ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
 379         if (ret < 0)
 380                 goto err_clk_provider;
 381
 382         ret = devm_add_action(rphy->dev, rockchip_usb2phy_clk480m_unregister,
 383                               rphy);
 384         if (ret < 0)
 385                 goto err_unreg_action;
 386
 387         return 0;
 388
 389 err_unreg_action:
 390         of_clk_del_provider(node);
 391 err_clk_provider:
 392         clk_unregister(rphy->clk480m);
 393 err_ret:
 394         return ret;
 395 }
 396
 397 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
 398 {
 399         int ret;
 400         struct device_node *node = rphy->dev->of_node;
 401         struct extcon_dev *edev;
 402
 403         if (of_property_read_bool(node, "extcon")) {
 404                 edev = extcon_get_edev_by_phandle(rphy->dev, 0);
 405                 if (IS_ERR(edev)) {
 406                         if (PTR_ERR(edev) != -EPROBE_DEFER)
 407                                 dev_err(rphy->dev, "Invalid or missing extcon\n");
 408                         return PTR_ERR(edev);
 409                 }
 410         } else {
 411                 /* Initialize extcon device */
 412                 edev = devm_extcon_dev_allocate(rphy->dev,
 413                                                 rockchip_usb2phy_extcon_cable);
 414
 415                 if (IS_ERR(edev))
 416                         return -ENOMEM;
 417
 418                 ret = devm_extcon_dev_register(rphy->dev, edev);
 419                 if (ret) {
 420                         dev_err(rphy->dev, "failed to register extcon device\n");
 421                         return ret;
 422                 }
 423
 424                 rphy->edev_self = true;
 425         }
 426
 427         rphy->edev = edev;
 428
 429         return 0;
 430 }
 431
 432 static int rockchip_usb2phy_init(struct phy *phy)
 433 {
 434         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 435         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 436         int ret = 0;
 437
 438         mutex_lock(&rport->mutex);
 439
 440         if (rport->port_id == USB2PHY_PORT_OTG) {
 441                 if (rport->mode != USB_DR_MODE_HOST) {
 442                         /* clear bvalid status and enable bvalid detect irq */
 443                         ret = property_enable(rphy,
 444                                               &rport->port_cfg->
 445                                               bvalid_det_clr,
 446                                               true);
 447                         if (ret)
 448                                 goto out;
 449
 450                         ret = property_enable(rphy,
 451                                               &rport->port_cfg->
 452                                               bvalid_det_en,
 453                                               true);
 454                         if (ret)
 455                                 goto out;
 456
 457                         if (rphy->edev_self) {
 458                                 ret = property_enable(rphy,
 459                                                       &rport->port_cfg->
 460                                                       idfall_det_clr,
 461                                                       true);
 462                                 if (ret)
 463                                         goto out;
 464
 465                                 ret = property_enable(rphy,
 466                                                       &rport->port_cfg->
 467                                                       idfall_det_en,
 468                                                       true);
 469                                 if (ret)
 470                                         goto out;
 471
 472                                 ret = property_enable(rphy,
 473                                                       &rport->port_cfg->
 474                                                       idrise_det_clr,
 475                                                       true);
 476                                 if (ret)
 477                                         goto out;
 478
 479                                 ret = property_enable(rphy,
 480                                                       &rport->port_cfg->
 481                                                       idrise_det_en,
 482                                                       true);
 483                                 if (ret)
 484                                         goto out;
 485                         }
 486
 487                         schedule_delayed_work(&rport->otg_sm_work,
 488                                               OTG_SCHEDULE_DELAY);
 489                 } else {
 490                         /* If OTG works in host only mode, do nothing. */
 491                         dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode);
 492                 }
 493         } else if (rport->port_id == USB2PHY_PORT_HOST) {
 494                 /* clear linestate and enable linestate detect irq */
 495                 ret = property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
 496                 if (ret)
 497                         goto out;
 498
 499                 ret = property_enable(rphy, &rport->port_cfg->ls_det_en, true);
 500                 if (ret)
 501                         goto out;
 502
 503                 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
 504         }
 505
 506 out:
 507         mutex_unlock(&rport->mutex);
 508         return ret;
 509 }
 510
 511 static int rockchip_usb2phy_power_on(struct phy *phy)
 512 {
 513         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 514         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 515         int ret;
 516
 517         dev_dbg(&rport->phy->dev, "port power on\n");
 518
 519         if (!rport->suspended)
 520                 return 0;
 521
 522         ret = clk_prepare_enable(rphy->clk480m);
 523         if (ret)
 524                 return ret;
 525
 526         ret = property_enable(rphy, &rport->port_cfg->phy_sus, false);
 527         if (ret)
 528                 return ret;
 529
 530         rport->suspended = false;
 531         return 0;
 532 }
 533
 534 static int rockchip_usb2phy_power_off(struct phy *phy)
 535 {
 536         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 537         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 538         int ret;
 539
 540         dev_dbg(&rport->phy->dev, "port power off\n");
 541
 542         if (rport->suspended)
 543                 return 0;
 544
 545         ret = property_enable(rphy, &rport->port_cfg->phy_sus, true);
 546         if (ret)
 547                 return ret;
 548
 549         rport->suspended = true;
 550         clk_disable_unprepare(rphy->clk480m);
 551
 552         return 0;
 553 }
 554
 555 static int rockchip_usb2phy_exit(struct phy *phy)
 556 {
 557         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 558
 559         if (rport->port_id == USB2PHY_PORT_OTG &&
 560             rport->mode != USB_DR_MODE_HOST)
 561                 cancel_delayed_work_sync(&rport->chg_work);
 562         else if (rport->port_id == USB2PHY_PORT_HOST)
 563                 cancel_delayed_work_sync(&rport->sm_work);
 564
 565         return 0;
 566 }
 567
 568 static const struct phy_ops rockchip_usb2phy_ops = {
 569         .init           = rockchip_usb2phy_init,
 570         .exit           = rockchip_usb2phy_exit,
 571         .power_on       = rockchip_usb2phy_power_on,
 572         .power_off      = rockchip_usb2phy_power_off,
 573         .owner          = THIS_MODULE,
 574 };
 575
 576 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
 577 {
 578         struct rockchip_usb2phy_port *rport =
 579                 container_of(work, struct rockchip_usb2phy_port,
 580                              otg_sm_work.work);
 581         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 582         static unsigned int cable;
 583         unsigned long delay;
 584         bool sch_work;
 585
 586         if (rport->utmi_avalid)
 587                 rport->vbus_attached =
 588                         property_enabled(rphy, &rport->port_cfg->utmi_avalid);
 589         else
 590                 rport->vbus_attached =
 591                         property_enabled(rphy, &rport->port_cfg->utmi_bvalid);
 592
 593         sch_work = false;
 594         delay = OTG_SCHEDULE_DELAY;
 595
 596         dev_dbg(&rport->phy->dev, "%s otg sm work\n",
 597                 usb_otg_state_string(rport->state));
 598
 599         switch (rport->state) {
 600         case OTG_STATE_UNDEFINED:
 601                 rport->state = OTG_STATE_B_IDLE;
 602                 if (!rport->vbus_attached)
 603                         rockchip_usb2phy_power_off(rport->phy);
 604                 /* fall through */
 605         case OTG_STATE_B_IDLE:
 606                 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) > 0 ||
 607                     extcon_get_cable_state_(rphy->edev,
 608                                             EXTCON_USB_VBUS_EN) > 0) {
 609                         dev_dbg(&rport->phy->dev, "usb otg host connect\n");
 610                         rport->state = OTG_STATE_A_HOST;
 611                         rockchip_usb2phy_power_on(rport->phy);
 612                         return;
 613                 } else if (rport->vbus_attached) {
 614                         dev_dbg(&rport->phy->dev, "vbus_attach\n");
 615                         switch (rphy->chg_state) {
 616                         case USB_CHG_STATE_UNDEFINED:
 617                                 schedule_delayed_work(&rport->chg_work, 0);
 618                                 return;
 619                         case USB_CHG_STATE_DETECTED:
 620                                 switch (rphy->chg_type) {
 621                                 case POWER_SUPPLY_TYPE_USB:
 622                                         dev_dbg(&rport->phy->dev,
 623                                                 "sdp cable is connecetd\n");
 624                                         wake_lock(&rport->wakelock);
 625                                         cable = EXTCON_CHG_USB_SDP;
 626                                         rockchip_usb2phy_power_on(rport->phy);
 627                                         rport->state = OTG_STATE_B_PERIPHERAL;
 628                                         rport->perip_connected = true;
 629                                         sch_work = true;
 630                                         break;
 631                                 case POWER_SUPPLY_TYPE_USB_DCP:
 632                                         dev_dbg(&rport->phy->dev,
 633                                                 "dcp cable is connecetd\n");
 634                                         cable = EXTCON_CHG_USB_DCP;
 635                                         rockchip_usb2phy_power_off(rport->phy);
 636                                         sch_work = true;
 637                                         break;
 638                                 case POWER_SUPPLY_TYPE_USB_CDP:
 639                                         dev_dbg(&rport->phy->dev,
 640                                                 "cdp cable is connecetd\n");
 641                                         wake_lock(&rport->wakelock);
 642                                         cable = EXTCON_CHG_USB_CDP;
 643                                         rockchip_usb2phy_power_on(rport->phy);
 644                                         rport->state = OTG_STATE_B_PERIPHERAL;
 645                                         rport->perip_connected = true;
 646                                         sch_work = true;
 647                                         break;
 648                                 case POWER_SUPPLY_TYPE_USB_FLOATING:
 649                                         dev_dbg(&rport->phy->dev,
 650                                                 "floating cable is connecetd\n");
 651                                         cable = EXTCON_CHG_USB_SLOW;
 652                                         rockchip_usb2phy_power_off(rport->phy);
 653                                         sch_work = true;
 654                                         break;
 655                                 default:
 656                                         break;
 657                                 }
 658                                 break;
 659                         default:
 660                                 break;
 661                         }
 662                 } else {
 663                         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
 664                         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
 665                 }
 666                 break;
 667         case OTG_STATE_B_PERIPHERAL:
 668                 if (!rport->vbus_attached) {
 669                         dev_dbg(&rport->phy->dev, "usb disconnect\n");
 670                         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
 671                         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
 672                         rport->state = OTG_STATE_B_IDLE;
 673                         rport->perip_connected = false;
 674                         delay = 0;
 675                         rockchip_usb2phy_power_off(rport->phy);
 676                         wake_unlock(&rport->wakelock);
 677                 } else {
 678                         sch_work = true;
 679                 }
 680                 break;
 681         case OTG_STATE_A_HOST:
 682                 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) == 0) {
 683                         dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
 684                         rport->state = OTG_STATE_B_IDLE;
 685                         rockchip_usb2phy_power_off(rport->phy);
 686                 }
 687                 return;
 688         default:
 689                 return;
 690         }
 691
 692         if (extcon_get_state(rphy->edev, cable) != rport->vbus_attached)
 693                 extcon_set_cable_state_(rphy->edev,
 694                                         cable, rport->vbus_attached);
 695
 696         if (rphy->edev_self &&
 697             (extcon_get_state(rphy->edev, EXTCON_USB) !=
 698              rport->perip_connected))
 699                 extcon_set_cable_state_(rphy->edev,
 700                                         EXTCON_USB,
 701                                         rport->perip_connected);
 702
 703         if (sch_work)
 704                 schedule_delayed_work(&rport->otg_sm_work, delay);
 705 }
 706
 707 static const char *chg_to_string(enum power_supply_type chg_type)
 708 {
 709         switch (chg_type) {
 710         case POWER_SUPPLY_TYPE_USB:
 711                 return "USB_SDP_CHARGER";
 712         case POWER_SUPPLY_TYPE_USB_DCP:
 713                 return "USB_DCP_CHARGER";
 714         case POWER_SUPPLY_TYPE_USB_CDP:
 715                 return "USB_CDP_CHARGER";
 716         case POWER_SUPPLY_TYPE_USB_FLOATING:
 717                 return "USB_FLOATING_CHARGER";
 718         default:
 719                 return "INVALID_CHARGER";
 720         }
 721 }
 722
 723 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
 724                                     bool en)
 725 {
 726         property_enable(rphy, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
 727         property_enable(rphy, &rphy->phy_cfg->chg_det.idp_src_en, en);
 728 }
 729
 730 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
 731                                             bool en)
 732 {
 733         property_enable(rphy, &rphy->phy_cfg->chg_det.vdp_src_en, en);
 734         property_enable(rphy, &rphy->phy_cfg->chg_det.idm_sink_en, en);
 735 }
 736
 737 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
 738                                               bool en)
 739 {
 740         property_enable(rphy, &rphy->phy_cfg->chg_det.vdm_src_en, en);
 741         property_enable(rphy, &rphy->phy_cfg->chg_det.idp_sink_en, en);
 742 }
 743
 744 #define CHG_DCD_POLL_TIME       (100 * HZ / 1000)
 745 #define CHG_DCD_MAX_RETRIES     6
 746 #define CHG_PRIMARY_DET_TIME    (40 * HZ / 1000)
 747 #define CHG_SECONDARY_DET_TIME  (40 * HZ / 1000)
 748 static void rockchip_chg_detect_work(struct work_struct *work)
 749 {
 750         struct rockchip_usb2phy_port *rport =
 751                 container_of(work, struct rockchip_usb2phy_port, chg_work.work);
 752         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 753         bool is_dcd, tmout, vout;
 754         unsigned long delay;
 755
 756         dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
 757                 rphy->chg_state);
 758         switch (rphy->chg_state) {
 759         case USB_CHG_STATE_UNDEFINED:
 760                 if (!rport->suspended)
 761                         rockchip_usb2phy_power_off(rport->phy);
 762                 /* put the controller in non-driving mode */
 763                 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, false);
 764                 /* Start DCD processing stage 1 */
 765                 rockchip_chg_enable_dcd(rphy, true);
 766                 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
 767                 rphy->dcd_retries = 0;
 768                 rphy->primary_retries = 0;
 769                 delay = CHG_DCD_POLL_TIME;
 770                 break;
 771         case USB_CHG_STATE_WAIT_FOR_DCD:
 772                 /* get data contact detection status */
 773                 is_dcd = property_enabled(rphy, &rphy->phy_cfg->chg_det.dp_det);
 774                 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
 775                 /* stage 2 */
 776                 if (is_dcd || tmout) {
 777                         /* stage 4 */
 778                         /* Turn off DCD circuitry */
 779                         rockchip_chg_enable_dcd(rphy, false);
 780                         /* Voltage Source on DP, Probe on DM */
 781                         rockchip_chg_enable_primary_det(rphy, true);
 782                         delay = CHG_PRIMARY_DET_TIME;
 783                         rphy->chg_state = USB_CHG_STATE_DCD_DONE;
 784                 } else {
 785                         /* stage 3 */
 786                         delay = CHG_DCD_POLL_TIME;
 787                 }
 788                 break;
 789         case USB_CHG_STATE_DCD_DONE:
 790                 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.cp_det);
 791                 rockchip_chg_enable_primary_det(rphy, false);
 792                 if (vout) {
 793                         /* Voltage Source on DM, Probe on DP  */
 794                         rockchip_chg_enable_secondary_det(rphy, true);
 795                         delay = CHG_SECONDARY_DET_TIME;
 796                         rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
 797                 } else {
 798                         if (tmout) {
 799                                 /* floating charger found */
 800                                 rphy->chg_type = POWER_SUPPLY_TYPE_USB_FLOATING;
 801                                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 802                                 delay = 0;
 803                         } else {
 804                                 if (rphy->primary_retries < 2) {
 805                                         /* Turn off DCD circuitry */
 806                                         rockchip_chg_enable_dcd(rphy, false);
 807                                         /* Voltage Source on DP, Probe on DM */
 808                                         rockchip_chg_enable_primary_det(rphy,
 809                                                                         true);
 810                                         delay = CHG_PRIMARY_DET_TIME;
 811                                         rphy->chg_state =
 812                                                 USB_CHG_STATE_DCD_DONE;
 813                                         rphy->primary_retries++;
 814                                         /* break USB_CHG_STATE_DCD_DONE */
 815                                         break;
 816                                 }
 817                                 rphy->chg_type = POWER_SUPPLY_TYPE_USB;
 818                                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 819                                 delay = 0;
 820                         }
 821                 }
 822                 break;
 823         case USB_CHG_STATE_PRIMARY_DONE:
 824                 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.dcp_det);
 825                 /* Turn off voltage source */
 826                 rockchip_chg_enable_secondary_det(rphy, false);
 827                 if (vout)
 828                         rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
 829                 else
 830                         rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
 831                 /* fall through */
 832         case USB_CHG_STATE_SECONDARY_DONE:
 833                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 834                 delay = 0;
 835                 /* fall through */
 836         case USB_CHG_STATE_DETECTED:
 837                 /* put the controller in normal mode */
 838                 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, true);
 839                 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
 840                 dev_info(&rport->phy->dev, "charger = %s\n",
 841                          chg_to_string(rphy->chg_type));
 842                 return;
 843         default:
 844                 return;
 845         }
 846
 847         schedule_delayed_work(&rport->chg_work, delay);
 848 }
 849
 850 /*
 851  * The function manage host-phy port state and suspend/resume phy port
 852  * to save power.
 853  *
 854  * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
 855  * devices is disconnect or not. Besides, we do not need care it is FS/LS
 856  * disconnected or HS disconnected, actually, we just only need get the
 857  * device is disconnected at last through rearm the delayed work,
 858  * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
 859  *
 860  * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
 861  * some clk related APIs, so do not invoke it from interrupt context directly.
 862  */
 863 static void rockchip_usb2phy_sm_work(struct work_struct *work)
 864 {
 865         struct rockchip_usb2phy_port *rport =
 866                 container_of(work, struct rockchip_usb2phy_port, sm_work.work);
 867         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 868         unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
 869                           rport->port_cfg->utmi_hstdet.bitstart + 1;
 870         unsigned int ul, uhd, state;
 871         unsigned int ul_mask, uhd_mask;
 872         int ret;
 873
 874         mutex_lock(&rport->mutex);
 875
 876         ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
 877         if (ret < 0)
 878                 goto next_schedule;
 879
 880         ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset,
 881                           &uhd);
 882         if (ret < 0)
 883                 goto next_schedule;
 884
 885         uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
 886                            rport->port_cfg->utmi_hstdet.bitstart);
 887         ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
 888                           rport->port_cfg->utmi_ls.bitstart);
 889
 890         /* stitch on utmi_ls and utmi_hstdet as phy state */
 891         state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
 892                 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
 893
 894         switch (state) {
 895         case PHY_STATE_HS_ONLINE:
 896                 dev_dbg(&rport->phy->dev, "HS online\n");
 897                 break;
 898         case PHY_STATE_FS_LS_ONLINE:
 899                 /*
 900                  * For FS/LS device, the online state share with connect state
 901                  * from utmi_ls and utmi_hstdet register, so we distinguish
 902                  * them via suspended flag.
 903                  *
 904                  * Plus, there are two cases, one is D- Line pull-up, and D+
 905                  * line pull-down, the state is 4; another is D+ line pull-up,
 906                  * and D- line pull-down, the state is 2.
 907                  */
 908                 if (!rport->suspended) {
 909                         /* D- line pull-up, D+ line pull-down */
 910                         dev_dbg(&rport->phy->dev, "FS/LS online\n");
 911                         break;
 912                 }
 913                 /* fall through */
 914         case PHY_STATE_CONNECT:
 915                 if (rport->suspended) {
 916                         dev_dbg(&rport->phy->dev, "Connected\n");
 917                         rockchip_usb2phy_power_on(rport->phy);
 918                         rport->suspended = false;
 919                 } else {
 920                         /* D+ line pull-up, D- line pull-down */
 921                         dev_dbg(&rport->phy->dev, "FS/LS online\n");
 922                 }
 923                 break;
 924         case PHY_STATE_DISCONNECT:
 925                 if (!rport->suspended) {
 926                         dev_dbg(&rport->phy->dev, "Disconnected\n");
 927                         rockchip_usb2phy_power_off(rport->phy);
 928                         rport->suspended = true;
 929                 }
 930
 931                 /*
 932                  * activate the linestate detection to get the next device
 933                  * plug-in irq.
 934                  */
 935                 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
 936                 property_enable(rphy, &rport->port_cfg->ls_det_en, true);
 937
 938                 /*
 939                  * we don't need to rearm the delayed work when the phy port
 940                  * is suspended.
 941                  */
 942                 mutex_unlock(&rport->mutex);
 943                 return;
 944         default:
 945                 dev_dbg(&rport->phy->dev, "unknown phy state\n");
 946                 break;
 947         }
 948
 949 next_schedule:
 950         mutex_unlock(&rport->mutex);
 951         schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
 952 }
 953
 954 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
 955 {
 956         struct rockchip_usb2phy_port *rport = data;
 957         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 958
 959         if (!property_enabled(rphy, &rport->port_cfg->ls_det_st))
 960                 return IRQ_NONE;
 961
 962         mutex_lock(&rport->mutex);
 963
 964         /* disable linestate detect irq and clear its status */
 965         property_enable(rphy, &rport->port_cfg->ls_det_en, false);
 966         property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
 967
 968         mutex_unlock(&rport->mutex);
 969
 970         /*
 971          * In this case for host phy port, a new device is plugged in,
 972          * meanwhile, if the phy port is suspended, we need rearm the work to
 973          * resume it and mange its states; otherwise, we do nothing about that.
 974          */
 975         if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST)
 976                 rockchip_usb2phy_sm_work(&rport->sm_work.work);
 977
 978         return IRQ_HANDLED;
 979 }
 980
 981 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
 982 {
 983         struct rockchip_usb2phy_port *rport = data;
 984         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 985
 986         if (!property_enabled(rphy, &rport->port_cfg->bvalid_det_st))
 987                 return IRQ_NONE;
 988
 989         mutex_lock(&rport->mutex);
 990
 991         /* clear bvalid detect irq pending status */
 992         property_enable(rphy, &rport->port_cfg->bvalid_det_clr, true);
 993
 994         mutex_unlock(&rport->mutex);
 995
 996         rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
 997
 998         return IRQ_HANDLED;
 999 }
1000
1001 static irqreturn_t rockchip_usb2phy_id_irq(int irq, void *data)
1002 {
1003         struct rockchip_usb2phy_port *rport = data;
1004         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1005
1006         if (!property_enabled(rphy, &rport->port_cfg->idfall_det_st) &&
1007             !property_enabled(rphy, &rport->port_cfg->idrise_det_st))
1008                 return IRQ_NONE;
1009
1010         mutex_lock(&rport->mutex);
1011
1012         /* clear id fall or rise detect irq pending status */
1013         if (property_enabled(rphy, &rport->port_cfg->idfall_det_st)) {
1014                 property_enable(rphy, &rport->port_cfg->idfall_det_clr,
1015                                 true);
1016                 extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
1017                 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, true);
1018         } else if (property_enabled(rphy, &rport->port_cfg->idrise_det_st)) {
1019                 property_enable(rphy, &rport->port_cfg->idrise_det_clr,
1020                                 true);
1021                 extcon_set_state(rphy->edev, EXTCON_USB_HOST, false);
1022                 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, false);
1023         }
1024
1025         extcon_sync(rphy->edev, EXTCON_USB_HOST);
1026         extcon_sync(rphy->edev, EXTCON_USB_VBUS_EN);
1027
1028         mutex_unlock(&rport->mutex);
1029
1030         return IRQ_HANDLED;
1031 }
1032
1033 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
1034                                            struct rockchip_usb2phy_port *rport,
1035                                            struct device_node *child_np)
1036 {
1037         int ret;
1038
1039         rport->port_id = USB2PHY_PORT_HOST;
1040         rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
1041         rport->suspended = true;
1042
1043         mutex_init(&rport->mutex);
1044         INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
1045
1046         rport->ls_irq = of_irq_get_byname(child_np, "linestate");
1047         if (rport->ls_irq < 0) {
1048                 dev_err(rphy->dev, "no linestate irq provided\n");
1049                 return rport->ls_irq;
1050         }
1051
1052         ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
1053                                         rockchip_usb2phy_linestate_irq,
1054                                         IRQF_ONESHOT,
1055                                         "rockchip_usb2phy", rport);
1056         if (ret) {
1057                 dev_err(rphy->dev, "failed to request linestate irq handle\n");
1058                 return ret;
1059         }
1060
1061         return 0;
1062 }
1063
1064 static int rockchip_otg_event(struct notifier_block *nb,
1065                               unsigned long event, void *ptr)
1066 {
1067         struct rockchip_usb2phy_port *rport =
1068                 container_of(nb, struct rockchip_usb2phy_port, event_nb);
1069
1070         schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
1071
1072         return NOTIFY_DONE;
1073 }
1074
1075 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
1076                                           struct rockchip_usb2phy_port *rport,
1077                                           struct device_node *child_np)
1078 {
1079         int ret;
1080         int iddig;
1081
1082         rport->port_id = USB2PHY_PORT_OTG;
1083         rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
1084         rport->state = OTG_STATE_UNDEFINED;
1085
1086         /*
1087          * set suspended flag to true, but actually don't
1088          * put phy in suspend mode, it aims to enable usb
1089          * phy and clock in power_on() called by usb controller
1090          * driver during probe.
1091          */
1092         rport->suspended = true;
1093         rport->vbus_attached = false;
1094         rport->perip_connected = false;
1095
1096         mutex_init(&rport->mutex);
1097
1098         rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
1099         if (rport->mode == USB_DR_MODE_HOST)
1100                 return 0;
1101
1102         wake_lock_init(&rport->wakelock, WAKE_LOCK_SUSPEND, "rockchip_otg");
1103         INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
1104         INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
1105
1106         rport->utmi_avalid =
1107                 of_property_read_bool(child_np, "rockchip,utmi-avalid");
1108
1109         rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
1110         if (rport->bvalid_irq < 0) {
1111                 dev_err(rphy->dev, "no vbus valid irq provided\n");
1112                 return rport->bvalid_irq;
1113         }
1114
1115         ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, NULL,
1116                                         rockchip_usb2phy_bvalid_irq,
1117                                         IRQF_ONESHOT,
1118                                         "rockchip_usb2phy_bvalid", rport);
1119         if (ret) {
1120                 dev_err(rphy->dev, "failed to request otg-bvalid irq handle\n");
1121                 return ret;
1122         }
1123
1124         if (rphy->edev_self) {
1125                 rport->id_irq = of_irq_get_byname(child_np, "otg-id");
1126                 if (rport->id_irq < 0) {
1127                         dev_err(rphy->dev, "no otg id irq provided\n");
1128                         return rport->id_irq;
1129                 }
1130
1131                 ret = devm_request_threaded_irq(rphy->dev, rport->id_irq, NULL,
1132                                                 rockchip_usb2phy_id_irq,
1133                                                 IRQF_ONESHOT,
1134                                                 "rockchip_usb2phy_id", rport);
1135                 if (ret) {
1136                         dev_err(rphy->dev, "failed to request otg-id irq handle\n");
1137                         return ret;
1138                 }
1139
1140                 iddig = property_enabled(rphy, &rport->port_cfg->utmi_iddig);
1141                 if (!iddig) {
1142                         extcon_set_state(rphy->edev, EXTCON_USB, false);
1143                         extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
1144                         extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, true);
1145                 } else {
1146                         extcon_set_state(rphy->edev, EXTCON_USB_HOST, false);
1147                         extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, false);
1148                 }
1149         }
1150
1151         if (!IS_ERR(rphy->edev)) {
1152                 rport->event_nb.notifier_call = rockchip_otg_event;
1153
1154                 ret = extcon_register_notifier(rphy->edev, EXTCON_USB_HOST,
1155                                                &rport->event_nb);
1156                 if (ret < 0) {
1157                         dev_err(rphy->dev, "register USB HOST notifier failed\n");
1158                         return ret;
1159                 }
1160         }
1161
1162         return 0;
1163 }
1164
1165 static int rockchip_usb2phy_probe(struct platform_device *pdev)
1166 {
1167         struct device *dev = &pdev->dev;
1168         struct device_node *np = dev->of_node;
1169         struct device_node *child_np;
1170         struct phy_provider *provider;
1171         struct rockchip_usb2phy *rphy;
1172         const struct rockchip_usb2phy_cfg *phy_cfgs;
1173         const struct of_device_id *match;
1174         unsigned int reg;
1175         int index, ret;
1176
1177         rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
1178         if (!rphy)
1179                 return -ENOMEM;
1180
1181         match = of_match_device(dev->driver->of_match_table, dev);
1182         if (!match || !match->data) {
1183                 dev_err(dev, "phy configs are not assigned!\n");
1184                 return -EINVAL;
1185         }
1186
1187         if (!dev->parent || !dev->parent->of_node)
1188                 return -EINVAL;
1189
1190         rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
1191         if (IS_ERR(rphy->grf))
1192                 return PTR_ERR(rphy->grf);
1193
1194         if (of_property_read_u32(np, "reg", &reg)) {
1195                 dev_err(dev, "the reg property is not assigned in %s node\n",
1196                         np->name);
1197                 return -EINVAL;
1198         }
1199
1200         rphy->dev = dev;
1201         phy_cfgs = match->data;
1202         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1203         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1204         rphy->edev_self = false;
1205         platform_set_drvdata(pdev, rphy);
1206
1207         ret = rockchip_usb2phy_extcon_register(rphy);
1208         if (ret)
1209                 return ret;
1210
1211         /* find out a proper config which can be matched with dt. */
1212         index = 0;
1213         while (phy_cfgs[index].reg) {
1214                 if (phy_cfgs[index].reg == reg) {
1215                         rphy->phy_cfg = &phy_cfgs[index];
1216                         break;
1217                 }
1218
1219                 ++index;
1220         }
1221
1222         if (!rphy->phy_cfg) {
1223                 dev_err(dev, "no phy-config can be matched with %s node\n",
1224                         np->name);
1225                 return -EINVAL;
1226         }
1227
1228         rphy->clk = of_clk_get_by_name(np, "phyclk");
1229         if (!IS_ERR(rphy->clk)) {
1230                 clk_prepare_enable(rphy->clk);
1231         } else {
1232                 dev_info(&pdev->dev, "no phyclk specified\n");
1233                 rphy->clk = NULL;
1234         }
1235
1236         ret = rockchip_usb2phy_clk480m_register(rphy);
1237         if (ret) {
1238                 dev_err(dev, "failed to register 480m output clock\n");
1239                 goto disable_clks;
1240         }
1241
1242         if (rphy->phy_cfg->phy_tuning) {
1243                 ret = rphy->phy_cfg->phy_tuning(rphy);
1244                 if (ret)
1245                         goto disable_clks;
1246         }
1247
1248         index = 0;
1249         for_each_available_child_of_node(np, child_np) {
1250                 struct rockchip_usb2phy_port *rport = &rphy->ports[index];
1251                 struct phy *phy;
1252
1253                 /* This driver aims to support both otg-port and host-port */
1254                 if (of_node_cmp(child_np->name, "host-port") &&
1255                     of_node_cmp(child_np->name, "otg-port"))
1256                         goto next_child;
1257
1258                 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
1259                 if (IS_ERR(phy)) {
1260                         dev_err(dev, "failed to create phy\n");
1261                         ret = PTR_ERR(phy);
1262                         goto put_child;
1263                 }
1264
1265                 rport->phy = phy;
1266                 phy_set_drvdata(rport->phy, rport);
1267
1268                 /* initialize otg/host port separately */
1269                 if (!of_node_cmp(child_np->name, "host-port")) {
1270                         ret = rockchip_usb2phy_host_port_init(rphy, rport,
1271                                                               child_np);
1272                         if (ret)
1273                                 goto put_child;
1274                 } else {
1275                         ret = rockchip_usb2phy_otg_port_init(rphy, rport,
1276                                                              child_np);
1277                         if (ret)
1278                                 goto put_child;
1279                 }
1280
1281 next_child:
1282                 /* to prevent out of boundary */
1283                 if (++index >= rphy->phy_cfg->num_ports)
1284                         break;
1285         }
1286
1287         provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1288         return PTR_ERR_OR_ZERO(provider);
1289
1290 put_child:
1291         of_node_put(child_np);
1292 disable_clks:
1293         if (rphy->clk) {
1294                 clk_disable_unprepare(rphy->clk);
1295                 clk_put(rphy->clk);
1296         }
1297         return ret;
1298 }
1299
1300 static int rk3366_usb2phy_tuning(struct rockchip_usb2phy *rphy)
1301 {
1302         unsigned int open_pre_emphasize = 0xffff851f;
1303         unsigned int eye_height_tuning = 0xffff68c8;
1304         unsigned int compensation_tuning = 0xffff026e;
1305         int ret = 0;
1306
1307         /* open HS pre-emphasize to expand HS slew rate for each port. */
1308         ret |= regmap_write(rphy->grf, 0x0780, open_pre_emphasize);
1309         ret |= regmap_write(rphy->grf, 0x079c, eye_height_tuning);
1310         ret |= regmap_write(rphy->grf, 0x07b0, open_pre_emphasize);
1311         ret |= regmap_write(rphy->grf, 0x07cc, eye_height_tuning);
1312
1313         /* compensate default tuning reference relate to ODT and etc. */
1314         ret |= regmap_write(rphy->grf, 0x078c, compensation_tuning);
1315
1316         return ret;
1317 }
1318
1319 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
1320         {
1321                 .reg = 0x700,
1322                 .num_ports      = 2,
1323                 .phy_tuning     = rk3366_usb2phy_tuning,
1324                 .clkout_ctl     = { 0x0724, 15, 15, 1, 0 },
1325                 .port_cfgs      = {
1326                         [USB2PHY_PORT_HOST] = {
1327                                 .phy_sus        = { 0x0728, 15, 0, 0, 0x1d1 },
1328                                 .ls_det_en      = { 0x0680, 4, 4, 0, 1 },
1329                                 .ls_det_st      = { 0x0690, 4, 4, 0, 1 },
1330                                 .ls_det_clr     = { 0x06a0, 4, 4, 0, 1 },
1331                                 .utmi_ls        = { 0x049c, 14, 13, 0, 1 },
1332                                 .utmi_hstdet    = { 0x049c, 12, 12, 0, 1 }
1333                         }
1334                 },
1335         },
1336         { /* sentinel */ }
1337 };
1338
1339 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1340         {
1341                 .reg            = 0xe450,
1342                 .num_ports      = 2,
1343                 .clkout_ctl     = { 0xe450, 4, 4, 1, 0 },
1344                 .port_cfgs      = {
1345                         [USB2PHY_PORT_OTG] = {
1346                                 .phy_sus = { 0xe454, 15, 0, 0x1452, 0x15d1 },
1347                                 .bvalid_det_en  = { 0xe3c0, 3, 3, 0, 1 },
1348                                 .bvalid_det_st  = { 0xe3e0, 3, 3, 0, 1 },
1349                                 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
1350                                 .idfall_det_en  = { 0xe3c0, 5, 5, 0, 1 },
1351                                 .idfall_det_st  = { 0xe3e0, 5, 5, 0, 1 },
1352                                 .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 },
1353                                 .idrise_det_en  = { 0xe3c0, 4, 4, 0, 1 },
1354                                 .idrise_det_st  = { 0xe3e0, 4, 4, 0, 1 },
1355                                 .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 },
1356                                 .utmi_avalid    = { 0xe2ac, 7, 7, 0, 1 },
1357                                 .utmi_bvalid    = { 0xe2ac, 12, 12, 0, 1 },
1358                                 .utmi_iddig     = { 0xe2ac, 8, 8, 0, 1 },
1359                         },
1360                         [USB2PHY_PORT_HOST] = {
1361                                 .phy_sus        = { 0xe458, 1, 0, 0x2, 0x1 },
1362                                 .ls_det_en      = { 0xe3c0, 6, 6, 0, 1 },
1363                                 .ls_det_st      = { 0xe3e0, 6, 6, 0, 1 },
1364                                 .ls_det_clr     = { 0xe3d0, 6, 6, 0, 1 },
1365                                 .utmi_ls        = { 0xe2ac, 22, 21, 0, 1 },
1366                                 .utmi_hstdet    = { 0xe2ac, 23, 23, 0, 1 }
1367                         }
1368                 },
1369                 .chg_det = {
1370                         .opmode         = { 0xe454, 3, 0, 5, 1 },
1371                         .cp_det         = { 0xe2ac, 2, 2, 0, 1 },
1372                         .dcp_det        = { 0xe2ac, 1, 1, 0, 1 },
1373                         .dp_det         = { 0xe2ac, 0, 0, 0, 1 },
1374                         .idm_sink_en    = { 0xe450, 8, 8, 0, 1 },
1375                         .idp_sink_en    = { 0xe450, 7, 7, 0, 1 },
1376                         .idp_src_en     = { 0xe450, 9, 9, 0, 1 },
1377                         .rdm_pdwn_en    = { 0xe450, 10, 10, 0, 1 },
1378                         .vdm_src_en     = { 0xe450, 12, 12, 0, 1 },
1379                         .vdp_src_en     = { 0xe450, 11, 11, 0, 1 },
1380                 },
1381         },
1382         {
1383                 .reg            = 0xe460,
1384                 .num_ports      = 2,
1385                 .clkout_ctl     = { 0xe460, 4, 4, 1, 0 },
1386                 .port_cfgs      = {
1387                         [USB2PHY_PORT_OTG] = {
1388                                 .phy_sus = { 0xe464, 15, 0, 0x1452, 0x15d1 },
1389                                 .bvalid_det_en  = { 0xe3c0, 8, 8, 0, 1 },
1390                                 .bvalid_det_st  = { 0xe3e0, 8, 8, 0, 1 },
1391                                 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
1392                                 .idfall_det_en  = { 0xe3c0, 10, 10, 0, 1 },
1393                                 .idfall_det_st  = { 0xe3e0, 10, 10, 0, 1 },
1394                                 .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 },
1395                                 .idrise_det_en  = { 0xe3c0, 9, 9, 0, 1 },
1396                                 .idrise_det_st  = { 0xe3e0, 9, 9, 0, 1 },
1397                                 .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 },
1398                                 .utmi_avalid    = { 0xe2ac, 10, 10, 0, 1 },
1399                                 .utmi_bvalid    = { 0xe2ac, 16, 16, 0, 1 },
1400                                 .utmi_iddig     = { 0xe2ac, 11, 11, 0, 1 },
1401                         },
1402                         [USB2PHY_PORT_HOST] = {
1403                                 .phy_sus        = { 0xe468, 1, 0, 0x2, 0x1 },
1404                                 .ls_det_en      = { 0xe3c0, 11, 11, 0, 1 },
1405                                 .ls_det_st      = { 0xe3e0, 11, 11, 0, 1 },
1406                                 .ls_det_clr     = { 0xe3d0, 11, 11, 0, 1 },
1407                                 .utmi_ls        = { 0xe2ac, 26, 25, 0, 1 },
1408                                 .utmi_hstdet    = { 0xe2ac, 27, 27, 0, 1 }
1409                         }
1410                 },
1411         },
1412         { /* sentinel */ }
1413 };
1414
1415 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
1416         { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
1417         { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
1418         {}
1419 };
1420 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
1421
1422 static struct platform_driver rockchip_usb2phy_driver = {
1423         .probe          = rockchip_usb2phy_probe,
1424         .driver         = {
1425                 .name   = "rockchip-usb2phy",
1426                 .of_match_table = rockchip_usb2phy_dt_match,
1427         },
1428 };
1429 module_platform_driver(rockchip_usb2phy_driver);
1430
1431 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1432 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
1433 MODULE_LICENSE("GPL v2");