drivers/phy/phy-rockchip-emmc.c

   1 /*
   2  * Rockchip emmc PHY driver
   3  *
   4  * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
   5  * Copyright (C) 2016 ROCKCHIP, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/of_address.h>
  22 #include <linux/phy/phy.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/regmap.h>
  25
  26 /*
  27  * The higher 16-bit of this register is used for write protection
  28  * only if BIT(x + 16) set to 1 the BIT(x) can be written.
  29  */
  30 #define HIWORD_UPDATE(val, mask, shift) \
  31                 ((val) << (shift) | (mask) << ((shift) + 16))
  32
  33 /* Register definition */
  34 #define GRF_EMMCPHY_CON0                0x0
  35 #define GRF_EMMCPHY_CON1                0x4
  36 #define GRF_EMMCPHY_CON2                0x8
  37 #define GRF_EMMCPHY_CON3                0xc
  38 #define GRF_EMMCPHY_CON4                0x10
  39 #define GRF_EMMCPHY_CON5                0x14
  40 #define GRF_EMMCPHY_CON6                0x18
  41 #define GRF_EMMCPHY_STATUS              0x20
  42
  43 #define PHYCTRL_PDB_MASK                0x1
  44 #define PHYCTRL_PDB_SHIFT               0x0
  45 #define PHYCTRL_PDB_PWR_ON              0x1
  46 #define PHYCTRL_PDB_PWR_OFF             0x0
  47 #define PHYCTRL_ENDLL_MASK              0x1
  48 #define PHYCTRL_ENDLL_SHIFT             0x1
  49 #define PHYCTRL_ENDLL_ENABLE            0x1
  50 #define PHYCTRL_ENDLL_DISABLE           0x0
  51 #define PHYCTRL_CALDONE_MASK            0x1
  52 #define PHYCTRL_CALDONE_SHIFT           0x6
  53 #define PHYCTRL_CALDONE_DONE            0x1
  54 #define PHYCTRL_CALDONE_GOING           0x0
  55 #define PHYCTRL_DLLRDY_MASK             0x1
  56 #define PHYCTRL_DLLRDY_SHIFT            0x5
  57 #define PHYCTRL_DLLRDY_DONE             0x1
  58 #define PHYCTRL_DLLRDY_GOING            0x0
  59 #define PHYCTRL_FREQSEL_200M            0x0
  60 #define PHYCTRL_FREQSEL_50M             0x1
  61 #define PHYCTRL_FREQSEL_100M            0x2
  62 #define PHYCTRL_FREQSEL_150M            0x3
  63 #define PHYCTRL_FREQSEL_MASK            0x3
  64 #define PHYCTRL_FREQSEL_SHIFT           0xc
  65 #define PHYCTRL_DR_MASK                 0x7
  66 #define PHYCTRL_DR_SHIFT                0x4
  67 #define PHYCTRL_DR_50OHM                0x0
  68 #define PHYCTRL_DR_33OHM                0x1
  69 #define PHYCTRL_DR_66OHM                0x2
  70 #define PHYCTRL_DR_100OHM               0x3
  71 #define PHYCTRL_DR_40OHM                0x4
  72 #define PHYCTRL_OTAPDLYENA              0x1
  73 #define PHYCTRL_OTAPDLYENA_MASK         0x1
  74 #define PHYCTRL_OTAPDLYENA_SHIFT        11
  75 #define PHYCTRL_OTAPDLYSEL_MASK         0xf
  76 #define PHYCTRL_OTAPDLYSEL_SHIFT        7
  77
  78 struct rockchip_emmc_phy {
  79         unsigned int    reg_offset;
  80         struct regmap   *reg_base;
  81         u32     freq_sel;
  82         u32     dr_sel;
  83         u32     opdelay;
  84 };
  85
  86 static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy,
  87                                    bool on_off)
  88 {
  89         unsigned int caldone;
  90         unsigned int dllrdy;
  91
  92         /*
  93          * Keep phyctrl_pdb and phyctrl_endll low to allow
  94          * initialization of CALIO state M/C DFFs
  95          */
  96         regmap_write(rk_phy->reg_base,
  97                      rk_phy->reg_offset + GRF_EMMCPHY_CON6,
  98                      HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF,
  99                                    PHYCTRL_PDB_MASK,
 100                                    PHYCTRL_PDB_SHIFT));
 101         regmap_write(rk_phy->reg_base,
 102                      rk_phy->reg_offset + GRF_EMMCPHY_CON6,
 103                      HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE,
 104                                    PHYCTRL_ENDLL_MASK,
 105                                    PHYCTRL_ENDLL_SHIFT));
 106
 107         /* Already finish power_off above */
 108         if (on_off == PHYCTRL_PDB_PWR_OFF)
 109                 return 0;
 110
 111         /*
 112          * According to the user manual, calpad calibration
 113          * cycle takes more than 2us without the minimal recommended
 114          * value, so we may need a little margin here
 115          */
 116         udelay(3);
 117         regmap_write(rk_phy->reg_base,
 118                      rk_phy->reg_offset + GRF_EMMCPHY_CON6,
 119                      HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON,
 120                                    PHYCTRL_PDB_MASK,
 121                                    PHYCTRL_PDB_SHIFT));
 122
 123         /*
 124          * According to the user manual, it asks driver to
 125          * wait 5us for calpad busy trimming
 126          */
 127         udelay(5);
 128         regmap_read(rk_phy->reg_base,
 129                     rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
 130                     &caldone);
 131         caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK;
 132         if (caldone != PHYCTRL_CALDONE_DONE) {
 133                 pr_err("rockchip_emmc_phy_power: caldone timeout.\n");
 134                 return -ETIMEDOUT;
 135         }
 136
 137         regmap_write(rk_phy->reg_base,
 138                      rk_phy->reg_offset + GRF_EMMCPHY_CON6,
 139                      HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE,
 140                                    PHYCTRL_ENDLL_MASK,
 141                                    PHYCTRL_ENDLL_SHIFT));
 142         /*
 143          * After enable analog DLL circuits, we need extra 10.2us
 144          * for dll to be ready for work.
 145          */
 146         udelay(11);
 147         regmap_read(rk_phy->reg_base,
 148                     rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
 149                     &dllrdy);
 150         dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
 151         if (dllrdy != PHYCTRL_DLLRDY_DONE) {
 152                 pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n");
 153                 return -ETIMEDOUT;
 154         }
 155
 156         return 0;
 157 }
 158
 159 static int rockchip_emmc_phy_init(struct phy *phy)
 160 {
 161         struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
 162
 163         regmap_write(rk_phy->reg_base,
 164                      rk_phy->reg_offset + GRF_EMMCPHY_CON0,
 165                      HIWORD_UPDATE(rk_phy->freq_sel,
 166                                    PHYCTRL_FREQSEL_MASK,
 167                                    PHYCTRL_FREQSEL_SHIFT));
 168
 169         regmap_write(rk_phy->reg_base,
 170                      rk_phy->reg_offset + GRF_EMMCPHY_CON6,
 171                      HIWORD_UPDATE(rk_phy->dr_sel,
 172                                    PHYCTRL_DR_MASK,
 173                                    PHYCTRL_DR_SHIFT));
 174
 175         regmap_write(rk_phy->reg_base,
 176                      rk_phy->reg_offset + GRF_EMMCPHY_CON0,
 177                      HIWORD_UPDATE(PHYCTRL_OTAPDLYENA,
 178                                    PHYCTRL_OTAPDLYENA_MASK,
 179                                    PHYCTRL_OTAPDLYENA_SHIFT));
 180
 181         regmap_write(rk_phy->reg_base,
 182                      rk_phy->reg_offset + GRF_EMMCPHY_CON0,
 183                      HIWORD_UPDATE(rk_phy->opdelay,
 184                                    PHYCTRL_OTAPDLYSEL_MASK,
 185                                    PHYCTRL_OTAPDLYSEL_SHIFT));
 186
 187         return 0;
 188 }
 189
 190 static int rockchip_emmc_phy_power_off(struct phy *phy)
 191 {
 192         struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
 193         int ret = 0;
 194
 195         /* Power down emmc phy analog blocks */
 196         ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_OFF);
 197         if (ret)
 198                 return ret;
 199
 200         return 0;
 201 }
 202
 203 static int rockchip_emmc_phy_power_on(struct phy *phy)
 204 {
 205         struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
 206         int ret = 0;
 207
 208         /* Power up emmc phy analog blocks */
 209         ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_ON);
 210         if (ret)
 211                 return ret;
 212
 213         return 0;
 214 }
 215
 216 static const struct phy_ops ops = {
 217         .init           = rockchip_emmc_phy_init,
 218         .power_on       = rockchip_emmc_phy_power_on,
 219         .power_off      = rockchip_emmc_phy_power_off,
 220         .owner          = THIS_MODULE,
 221 };
 222
 223 static int rockchip_emmc_phy_probe(struct platform_device *pdev)
 224 {
 225         struct device *dev = &pdev->dev;
 226         struct rockchip_emmc_phy *rk_phy;
 227         struct phy *generic_phy;
 228         struct phy_provider *phy_provider;
 229         struct regmap *grf;
 230         unsigned int reg_offset;
 231         u32 freq_sel;
 232         u32 dr_sel;
 233         u32 opdelay;
 234
 235         grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
 236         if (IS_ERR(grf)) {
 237                 dev_err(dev, "Missing rockchip,grf property\n");
 238                 return PTR_ERR(grf);
 239         }
 240
 241         rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
 242         if (!rk_phy)
 243                 return -ENOMEM;
 244
 245         if (of_property_read_u32(dev->of_node, "reg-offset", &reg_offset)) {
 246                 dev_err(dev, "missing reg property in node %s\n",
 247                         dev->of_node->name);
 248                 return -EINVAL;
 249         }
 250
 251         rk_phy->freq_sel = 0x0;
 252         if (!of_property_read_u32(dev->of_node, "freq-sel", &freq_sel)) {
 253                 switch (freq_sel) {
 254                 case 50000000:
 255                         rk_phy->freq_sel = PHYCTRL_FREQSEL_50M;
 256                         break;
 257                 case 100000000:
 258                         rk_phy->freq_sel = PHYCTRL_FREQSEL_100M;
 259                         break;
 260                 case 150000000:
 261                         rk_phy->freq_sel = PHYCTRL_FREQSEL_150M;
 262                         break;
 263                 case 200000000:
 264                         rk_phy->freq_sel = PHYCTRL_FREQSEL_200M;
 265                         break;
 266                 default:
 267                         dev_info(dev, "Not support freq_sel, default 200M\n");
 268                         break;
 269                 }
 270         }
 271
 272         rk_phy->dr_sel = 0x0;
 273         if (!of_property_read_u32(dev->of_node, "dr-sel", &dr_sel)) {
 274                 switch (dr_sel) {
 275                 case 50:
 276                         rk_phy->dr_sel = PHYCTRL_DR_50OHM;
 277                         break;
 278                 case 33:
 279                         rk_phy->dr_sel = PHYCTRL_DR_33OHM;
 280                         break;
 281                 case 66:
 282                         rk_phy->dr_sel = PHYCTRL_DR_66OHM;
 283                         break;
 284                 case 100:
 285                         rk_phy->dr_sel = PHYCTRL_DR_100OHM;
 286                         break;
 287                 case 40:
 288                         rk_phy->dr_sel = PHYCTRL_DR_40OHM;
 289                         break;
 290                 default:
 291                         dev_info(dev, "Not support dr_sel, default 50OHM\n");
 292                         break;
 293                 }
 294         }
 295
 296         rk_phy->opdelay = 0x4;
 297         if (!of_property_read_u32(dev->of_node, "opdelay", &opdelay)) {
 298                 if (opdelay > 15)
 299                         dev_info(dev, "opdelay shouldn't larger than 15\n");
 300                 else
 301                         rk_phy->opdelay = opdelay;
 302         }
 303
 304         rk_phy->reg_offset = reg_offset;
 305         rk_phy->reg_base = grf;
 306
 307         generic_phy = devm_phy_create(dev, dev->of_node, &ops);
 308         if (IS_ERR(generic_phy)) {
 309                 dev_err(dev, "failed to create PHY\n");
 310                 return PTR_ERR(generic_phy);
 311         }
 312
 313         phy_set_drvdata(generic_phy, rk_phy);
 314         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 315
 316         return PTR_ERR_OR_ZERO(phy_provider);
 317 }
 318
 319 static const struct of_device_id rockchip_emmc_phy_dt_ids[] = {
 320         { .compatible = "rockchip,rk3399-emmc-phy" },
 321         {}
 322 };
 323
 324 MODULE_DEVICE_TABLE(of, rockchip_emmc_phy_dt_ids);
 325
 326 static struct platform_driver rockchip_emmc_driver = {
 327         .probe          = rockchip_emmc_phy_probe,
 328         .driver         = {
 329                 .name   = "rockchip-emmc-phy",
 330                 .of_match_table = rockchip_emmc_phy_dt_ids,
 331         },
 332 };
 333
 334 module_platform_driver(rockchip_emmc_driver);
 335
 336 MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
 337 MODULE_DESCRIPTION("Rockchip EMMC PHY driver");
 338 MODULE_LICENSE("GPL v2");