drivers/net/wireless/rtlwifi/rtl8192se/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../efuse.h"
  32 #include "../base.h"
  33 #include "../regd.h"
  34 #include "../cam.h"
  35 #include "../ps.h"
  36 #include "../pci.h"
  37 #include "reg.h"
  38 #include "def.h"
  39 #include "phy.h"
  40 #include "dm.h"
  41 #include "fw.h"
  42 #include "led.h"
  43 #include "hw.h"
  44
  45 void rtl92se_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  46 {
  47         struct rtl_priv *rtlpriv = rtl_priv(hw);
  48         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  49         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  50
  51         switch (variable) {
  52         case HW_VAR_RCR: {
  53                         *((u32 *) (val)) = rtlpci->receive_config;
  54                         break;
  55                 }
  56         case HW_VAR_RF_STATE: {
  57                         *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
  58                         break;
  59                 }
  60         case HW_VAR_FW_PSMODE_STATUS: {
  61                         *((bool *) (val)) = ppsc->fw_current_inpsmode;
  62                         break;
  63                 }
  64         case HW_VAR_CORRECT_TSF: {
  65                         u64 tsf;
  66                         u32 *ptsf_low = (u32 *)&tsf;
  67                         u32 *ptsf_high = ((u32 *)&tsf) + 1;
  68
  69                         *ptsf_high = rtl_read_dword(rtlpriv, (TSFR + 4));
  70                         *ptsf_low = rtl_read_dword(rtlpriv, TSFR);
  71
  72                         *((u64 *) (val)) = tsf;
  73
  74                         break;
  75                 }
  76         case HW_VAR_MRC: {
  77                         *((bool *)(val)) = rtlpriv->dm.current_mrc_switch;
  78                         break;
  79                 }
  80         default: {
  81                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  82                          "switch case not processed\n");
  83                         break;
  84                 }
  85         }
  86 }
  87
  88 void rtl92se_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  89 {
  90         struct rtl_priv *rtlpriv = rtl_priv(hw);
  91         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  92         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  93         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  94         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  95         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  96
  97         switch (variable) {
  98         case HW_VAR_ETHER_ADDR:{
  99                         rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]);
 100                         rtl_write_word(rtlpriv, IDR4, ((u16 *)(val + 4))[0]);
 101                         break;
 102                 }
 103         case HW_VAR_BASIC_RATE:{
 104                         u16 rate_cfg = ((u16 *) val)[0];
 105                         u8 rate_index = 0;
 106
 107                         if (rtlhal->version == VERSION_8192S_ACUT)
 108                                 rate_cfg = rate_cfg & 0x150;
 109                         else
 110                                 rate_cfg = rate_cfg & 0x15f;
 111
 112                         rate_cfg |= 0x01;
 113
 114                         rtl_write_byte(rtlpriv, RRSR, rate_cfg & 0xff);
 115                         rtl_write_byte(rtlpriv, RRSR + 1,
 116                                        (rate_cfg >> 8) & 0xff);
 117
 118                         while (rate_cfg > 0x1) {
 119                                 rate_cfg = (rate_cfg >> 1);
 120                                 rate_index++;
 121                         }
 122                         rtl_write_byte(rtlpriv, INIRTSMCS_SEL, rate_index);
 123
 124                         break;
 125                 }
 126         case HW_VAR_BSSID:{
 127                         rtl_write_dword(rtlpriv, BSSIDR, ((u32 *)(val))[0]);
 128                         rtl_write_word(rtlpriv, BSSIDR + 4,
 129                                        ((u16 *)(val + 4))[0]);
 130                         break;
 131                 }
 132         case HW_VAR_SIFS:{
 133                         rtl_write_byte(rtlpriv, SIFS_OFDM, val[0]);
 134                         rtl_write_byte(rtlpriv, SIFS_OFDM + 1, val[1]);
 135                         break;
 136                 }
 137         case HW_VAR_SLOT_TIME:{
 138                         u8 e_aci;
 139
 140                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 141                                  "HW_VAR_SLOT_TIME %x\n", val[0]);
 142
 143                         rtl_write_byte(rtlpriv, SLOT_TIME, val[0]);
 144
 145                         for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 146                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 147                                                 HW_VAR_AC_PARAM,
 148                                                 (&e_aci));
 149                         }
 150                         break;
 151                 }
 152         case HW_VAR_ACK_PREAMBLE:{
 153                         u8 reg_tmp;
 154                         u8 short_preamble = (bool) (*val);
 155                         reg_tmp = (mac->cur_40_prime_sc) << 5;
 156                         if (short_preamble)
 157                                 reg_tmp |= 0x80;
 158
 159                         rtl_write_byte(rtlpriv, RRSR + 2, reg_tmp);
 160                         break;
 161                 }
 162         case HW_VAR_AMPDU_MIN_SPACE:{
 163                         u8 min_spacing_to_set;
 164                         u8 sec_min_space;
 165
 166                         min_spacing_to_set = *val;
 167                         if (min_spacing_to_set <= 7) {
 168                                 if (rtlpriv->sec.pairwise_enc_algorithm ==
 169                                     NO_ENCRYPTION)
 170                                         sec_min_space = 0;
 171                                 else
 172                                         sec_min_space = 1;
 173
 174                                 if (min_spacing_to_set < sec_min_space)
 175                                         min_spacing_to_set = sec_min_space;
 176                                 if (min_spacing_to_set > 5)
 177                                         min_spacing_to_set = 5;
 178
 179                                 mac->min_space_cfg =
 180                                                 ((mac->min_space_cfg & 0xf8) |
 181                                                 min_spacing_to_set);
 182
 183                                 *val = min_spacing_to_set;
 184
 185                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 186                                          "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 187                                          mac->min_space_cfg);
 188
 189                                 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
 190                                                mac->min_space_cfg);
 191                         }
 192                         break;
 193                 }
 194         case HW_VAR_SHORTGI_DENSITY:{
 195                         u8 density_to_set;
 196
 197                         density_to_set = *val;
 198                         mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
 199                         mac->min_space_cfg |= (density_to_set << 3);
 200
 201                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 202                                  "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 203                                  mac->min_space_cfg);
 204
 205                         rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
 206                                        mac->min_space_cfg);
 207
 208                         break;
 209                 }
 210         case HW_VAR_AMPDU_FACTOR:{
 211                         u8 factor_toset;
 212                         u8 regtoset;
 213                         u8 factorlevel[18] = {
 214                                 2, 4, 4, 7, 7, 13, 13,
 215                                 13, 2, 7, 7, 13, 13,
 216                                 15, 15, 15, 15, 0};
 217                         u8 index = 0;
 218
 219                         factor_toset = *val;
 220                         if (factor_toset <= 3) {
 221                                 factor_toset = (1 << (factor_toset + 2));
 222                                 if (factor_toset > 0xf)
 223                                         factor_toset = 0xf;
 224
 225                                 for (index = 0; index < 17; index++) {
 226                                         if (factorlevel[index] > factor_toset)
 227                                                 factorlevel[index] =
 228                                                                  factor_toset;
 229                                 }
 230
 231                                 for (index = 0; index < 8; index++) {
 232                                         regtoset = ((factorlevel[index * 2]) |
 233                                                     (factorlevel[index *
 234                                                     2 + 1] << 4));
 235                                         rtl_write_byte(rtlpriv,
 236                                                        AGGLEN_LMT_L + index,
 237                                                        regtoset);
 238                                 }
 239
 240                                 regtoset = ((factorlevel[16]) |
 241                                             (factorlevel[17] << 4));
 242                                 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, regtoset);
 243
 244                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 245                                          "Set HW_VAR_AMPDU_FACTOR: %#x\n",
 246                                          factor_toset);
 247                         }
 248                         break;
 249                 }
 250         case HW_VAR_AC_PARAM:{
 251                         u8 e_aci = *val;
 252                         rtl92s_dm_init_edca_turbo(hw);
 253
 254                         if (rtlpci->acm_method != eAcmWay2_SW)
 255                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 256                                                  HW_VAR_ACM_CTRL,
 257                                                  &e_aci);
 258                         break;
 259                 }
 260         case HW_VAR_ACM_CTRL:{
 261                         u8 e_aci = *val;
 262                         union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)(&(
 263                                                         mac->ac[0].aifs));
 264                         u8 acm = p_aci_aifsn->f.acm;
 265                         u8 acm_ctrl = rtl_read_byte(rtlpriv, AcmHwCtrl);
 266
 267                         acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ?
 268                                    0x0 : 0x1);
 269
 270                         if (acm) {
 271                                 switch (e_aci) {
 272                                 case AC0_BE:
 273                                         acm_ctrl |= AcmHw_BeqEn;
 274                                         break;
 275                                 case AC2_VI:
 276                                         acm_ctrl |= AcmHw_ViqEn;
 277                                         break;
 278                                 case AC3_VO:
 279                                         acm_ctrl |= AcmHw_VoqEn;
 280                                         break;
 281                                 default:
 282                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 283                                                  "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 284                                                  acm);
 285                                         break;
 286                                 }
 287                         } else {
 288                                 switch (e_aci) {
 289                                 case AC0_BE:
 290                                         acm_ctrl &= (~AcmHw_BeqEn);
 291                                         break;
 292                                 case AC2_VI:
 293                                         acm_ctrl &= (~AcmHw_ViqEn);
 294                                         break;
 295                                 case AC3_VO:
 296                                         acm_ctrl &= (~AcmHw_BeqEn);
 297                                         break;
 298                                 default:
 299                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 300                                                  "switch case not processed\n");
 301                                         break;
 302                                 }
 303                         }
 304
 305                         RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 306                                  "HW_VAR_ACM_CTRL Write 0x%X\n", acm_ctrl);
 307                         rtl_write_byte(rtlpriv, AcmHwCtrl, acm_ctrl);
 308                         break;
 309                 }
 310         case HW_VAR_RCR:{
 311                         rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]);
 312                         rtlpci->receive_config = ((u32 *) (val))[0];
 313                         break;
 314                 }
 315         case HW_VAR_RETRY_LIMIT:{
 316                         u8 retry_limit = val[0];
 317
 318                         rtl_write_word(rtlpriv, RETRY_LIMIT,
 319                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 320                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
 321                         break;
 322                 }
 323         case HW_VAR_DUAL_TSF_RST: {
 324                         break;
 325                 }
 326         case HW_VAR_EFUSE_BYTES: {
 327                         rtlefuse->efuse_usedbytes = *((u16 *) val);
 328                         break;
 329                 }
 330         case HW_VAR_EFUSE_USAGE: {
 331                         rtlefuse->efuse_usedpercentage = *val;
 332                         break;
 333                 }
 334         case HW_VAR_IO_CMD: {
 335                         break;
 336                 }
 337         case HW_VAR_WPA_CONFIG: {
 338                         rtl_write_byte(rtlpriv, REG_SECR, *val);
 339                         break;
 340                 }
 341         case HW_VAR_SET_RPWM:{
 342                         break;
 343                 }
 344         case HW_VAR_H2C_FW_PWRMODE:{
 345                         break;
 346                 }
 347         case HW_VAR_FW_PSMODE_STATUS: {
 348                         ppsc->fw_current_inpsmode = *((bool *) val);
 349                         break;
 350                 }
 351         case HW_VAR_H2C_FW_JOINBSSRPT:{
 352                         break;
 353                 }
 354         case HW_VAR_AID:{
 355                         break;
 356                 }
 357         case HW_VAR_CORRECT_TSF:{
 358                         break;
 359                 }
 360         case HW_VAR_MRC: {
 361                         bool bmrc_toset = *((bool *)val);
 362                         u8 u1bdata = 0;
 363
 364                         if (bmrc_toset) {
 365                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 366                                               MASKBYTE0, 0x33);
 367                                 u1bdata = (u8)rtl_get_bbreg(hw,
 368                                                 ROFDM1_TRXPATHENABLE,
 369                                                 MASKBYTE0);
 370                                 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
 371                                               MASKBYTE0,
 372                                               ((u1bdata & 0xf0) | 0x03));
 373                                 u1bdata = (u8)rtl_get_bbreg(hw,
 374                                                 ROFDM0_TRXPATHENABLE,
 375                                                 MASKBYTE1);
 376                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 377                                               MASKBYTE1,
 378                                               (u1bdata | 0x04));
 379
 380                                 /* Update current settings. */
 381                                 rtlpriv->dm.current_mrc_switch = bmrc_toset;
 382                         } else {
 383                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 384                                               MASKBYTE0, 0x13);
 385                                 u1bdata = (u8)rtl_get_bbreg(hw,
 386                                                  ROFDM1_TRXPATHENABLE,
 387                                                  MASKBYTE0);
 388                                 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
 389                                               MASKBYTE0,
 390                                               ((u1bdata & 0xf0) | 0x01));
 391                                 u1bdata = (u8)rtl_get_bbreg(hw,
 392                                                 ROFDM0_TRXPATHENABLE,
 393                                                 MASKBYTE1);
 394                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 395                                               MASKBYTE1, (u1bdata & 0xfb));
 396
 397                                 /* Update current settings. */
 398                                 rtlpriv->dm.current_mrc_switch = bmrc_toset;
 399                         }
 400
 401                         break;
 402                 }
 403         case HW_VAR_FW_LPS_ACTION: {
 404                 bool enter_fwlps = *((bool *)val);
 405                 u8 rpwm_val, fw_pwrmode;
 406                 bool fw_current_inps;
 407
 408                 if (enter_fwlps) {
 409                         rpwm_val = 0x02;        /* RF off */
 410                         fw_current_inps = true;
 411                         rtlpriv->cfg->ops->set_hw_reg(hw,
 412                                         HW_VAR_FW_PSMODE_STATUS,
 413                                         (u8 *)(&fw_current_inps));
 414                         rtlpriv->cfg->ops->set_hw_reg(hw,
 415                                         HW_VAR_H2C_FW_PWRMODE,
 416                                         (u8 *)(&ppsc->fwctrl_psmode));
 417
 418                         rtlpriv->cfg->ops->set_hw_reg(hw,
 419                                         HW_VAR_SET_RPWM,
 420                                         (u8 *)(&rpwm_val));
 421                 } else {
 422                         rpwm_val = 0x0C;        /* RF on */
 423                         fw_pwrmode = FW_PS_ACTIVE_MODE;
 424                         fw_current_inps = false;
 425                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 426                                         (u8 *)(&rpwm_val));
 427                         rtlpriv->cfg->ops->set_hw_reg(hw,
 428                                         HW_VAR_H2C_FW_PWRMODE,
 429                                         (u8 *)(&fw_pwrmode));
 430
 431                         rtlpriv->cfg->ops->set_hw_reg(hw,
 432                                         HW_VAR_FW_PSMODE_STATUS,
 433                                         (u8 *)(&fw_current_inps));
 434                 }
 435                 break; }
 436         default:
 437                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 438                          "switch case not processed\n");
 439                 break;
 440         }
 441
 442 }
 443
 444 void rtl92se_enable_hw_security_config(struct ieee80211_hw *hw)
 445 {
 446         struct rtl_priv *rtlpriv = rtl_priv(hw);
 447         u8 sec_reg_value = 0x0;
 448
 449         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 450                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
 451                  rtlpriv->sec.pairwise_enc_algorithm,
 452                  rtlpriv->sec.group_enc_algorithm);
 453
 454         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 455                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
 456                          "not open hw encryption\n");
 457                 return;
 458         }
 459
 460         sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
 461
 462         if (rtlpriv->sec.use_defaultkey) {
 463                 sec_reg_value |= SCR_TXUSEDK;
 464                 sec_reg_value |= SCR_RXUSEDK;
 465         }
 466
 467         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",
 468                  sec_reg_value);
 469
 470         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
 471
 472 }
 473
 474 static u8 _rtl92se_halset_sysclk(struct ieee80211_hw *hw, u8 data)
 475 {
 476         struct rtl_priv *rtlpriv = rtl_priv(hw);
 477         u8 waitcount = 100;
 478         bool bresult = false;
 479         u8 tmpvalue;
 480
 481         rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
 482
 483         /* Wait the MAC synchronized. */
 484         udelay(400);
 485
 486         /* Check if it is set ready. */
 487         tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
 488         bresult = ((tmpvalue & BIT(7)) == (data & BIT(7)));
 489
 490         if ((data & (BIT(6) | BIT(7))) == false) {
 491                 waitcount = 100;
 492                 tmpvalue = 0;
 493
 494                 while (1) {
 495                         waitcount--;
 496
 497                         tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
 498                         if ((tmpvalue & BIT(6)))
 499                                 break;
 500
 501                         pr_err("wait for BIT(6) return value %x\n", tmpvalue);
 502                         if (waitcount == 0)
 503                                 break;
 504
 505                         udelay(10);
 506                 }
 507
 508                 if (waitcount == 0)
 509                         bresult = false;
 510                 else
 511                         bresult = true;
 512         }
 513
 514         return bresult;
 515 }
 516
 517 void rtl8192se_gpiobit3_cfg_inputmode(struct ieee80211_hw *hw)
 518 {
 519         struct rtl_priv *rtlpriv = rtl_priv(hw);
 520         u8 u1tmp;
 521
 522         /* The following config GPIO function */
 523         rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
 524         u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
 525
 526         /* config GPIO3 to input */
 527         u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
 528         rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
 529
 530 }
 531
 532 static u8 _rtl92se_rf_onoff_detect(struct ieee80211_hw *hw)
 533 {
 534         struct rtl_priv *rtlpriv = rtl_priv(hw);
 535         u8 u1tmp;
 536         u8 retval = ERFON;
 537
 538         /* The following config GPIO function */
 539         rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
 540         u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
 541
 542         /* config GPIO3 to input */
 543         u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
 544         rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
 545
 546         /* On some of the platform, driver cannot read correct
 547          * value without delay between Write_GPIO_SEL and Read_GPIO_IN */
 548         mdelay(10);
 549
 550         /* check GPIO3 */
 551         u1tmp = rtl_read_byte(rtlpriv, GPIO_IN_SE);
 552         retval = (u1tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? ERFON : ERFOFF;
 553
 554         return retval;
 555 }
 556
 557 static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw *hw)
 558 {
 559         struct rtl_priv *rtlpriv = rtl_priv(hw);
 560         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 561         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 562
 563         u8 i;
 564         u8 tmpu1b;
 565         u16 tmpu2b;
 566         u8 pollingcnt = 20;
 567
 568         if (rtlpci->first_init) {
 569                 /* Reset PCIE Digital */
 570                 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
 571                 tmpu1b &= 0xFE;
 572                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
 573                 udelay(1);
 574                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b | BIT(0));
 575         }
 576
 577         /* Switch to SW IO control */
 578         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
 579         if (tmpu1b & BIT(7)) {
 580                 tmpu1b &= ~(BIT(6) | BIT(7));
 581
 582                 /* Set failed, return to prevent hang. */
 583                 if (!_rtl92se_halset_sysclk(hw, tmpu1b))
 584                         return;
 585         }
 586
 587         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
 588         udelay(50);
 589         rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
 590         udelay(50);
 591
 592         /* Clear FW RPWM for FW control LPS.*/
 593         rtl_write_byte(rtlpriv, RPWM, 0x0);
 594
 595         /* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */
 596         tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
 597         tmpu1b &= 0x73;
 598         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
 599         /* wait for BIT 10/11/15 to pull high automatically!! */
 600         mdelay(1);
 601
 602         rtl_write_byte(rtlpriv, CMDR, 0);
 603         rtl_write_byte(rtlpriv, TCR, 0);
 604
 605         /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
 606         tmpu1b = rtl_read_byte(rtlpriv, 0x562);
 607         tmpu1b |= 0x08;
 608         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
 609         tmpu1b &= ~(BIT(3));
 610         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
 611
 612         /* Enable AFE clock source */
 613         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
 614         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
 615         /* Delay 1.5ms */
 616         mdelay(2);
 617         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
 618         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
 619
 620         /* Enable AFE Macro Block's Bandgap */
 621         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
 622         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
 623         mdelay(1);
 624
 625         /* Enable AFE Mbias */
 626         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
 627         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
 628         mdelay(1);
 629
 630         /* Enable LDOA15 block  */
 631         tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
 632         rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
 633
 634         /* Set Digital Vdd to Retention isolation Path. */
 635         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
 636         rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
 637
 638         /* For warm reboot NIC disappera bug. */
 639         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 640         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
 641
 642         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
 643
 644         /* Enable AFE PLL Macro Block */
 645         /* We need to delay 100u before enabling PLL. */
 646         udelay(200);
 647         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
 648         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
 649
 650         /* for divider reset  */
 651         udelay(100);
 652         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) |
 653                        BIT(4) | BIT(6)));
 654         udelay(10);
 655         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
 656         udelay(10);
 657
 658         /* Enable MAC 80MHZ clock  */
 659         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
 660         rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
 661         mdelay(1);
 662
 663         /* Release isolation AFE PLL & MD */
 664         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
 665
 666         /* Enable MAC clock */
 667         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
 668         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
 669
 670         /* Enable Core digital and enable IOREG R/W */
 671         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 672         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
 673
 674         tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
 675         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b & ~(BIT(7)));
 676
 677         /* enable REG_EN */
 678         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
 679
 680         /* Switch the control path. */
 681         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
 682         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
 683
 684         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
 685         tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
 686         if (!_rtl92se_halset_sysclk(hw, tmpu1b))
 687                 return; /* Set failed, return to prevent hang. */
 688
 689         rtl_write_word(rtlpriv, CMDR, 0x07FC);
 690
 691         /* MH We must enable the section of code to prevent load IMEM fail. */
 692         /* Load MAC register from WMAc temporarily We simulate macreg. */
 693         /* txt HW will provide MAC txt later  */
 694         rtl_write_byte(rtlpriv, 0x6, 0x30);
 695         rtl_write_byte(rtlpriv, 0x49, 0xf0);
 696
 697         rtl_write_byte(rtlpriv, 0x4b, 0x81);
 698
 699         rtl_write_byte(rtlpriv, 0xb5, 0x21);
 700
 701         rtl_write_byte(rtlpriv, 0xdc, 0xff);
 702         rtl_write_byte(rtlpriv, 0xdd, 0xff);
 703         rtl_write_byte(rtlpriv, 0xde, 0xff);
 704         rtl_write_byte(rtlpriv, 0xdf, 0xff);
 705
 706         rtl_write_byte(rtlpriv, 0x11a, 0x00);
 707         rtl_write_byte(rtlpriv, 0x11b, 0x00);
 708
 709         for (i = 0; i < 32; i++)
 710                 rtl_write_byte(rtlpriv, INIMCS_SEL + i, 0x1b);
 711
 712         rtl_write_byte(rtlpriv, 0x236, 0xff);
 713
 714         rtl_write_byte(rtlpriv, 0x503, 0x22);
 715
 716         if (ppsc->support_aspm && !ppsc->support_backdoor)
 717                 rtl_write_byte(rtlpriv, 0x560, 0x40);
 718         else
 719                 rtl_write_byte(rtlpriv, 0x560, 0x00);
 720
 721         rtl_write_byte(rtlpriv, DBG_PORT, 0x91);
 722
 723         /* Set RX Desc Address */
 724         rtl_write_dword(rtlpriv, RDQDA, rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
 725         rtl_write_dword(rtlpriv, RCDA, rtlpci->rx_ring[RX_CMD_QUEUE].dma);
 726
 727         /* Set TX Desc Address */
 728         rtl_write_dword(rtlpriv, TBKDA, rtlpci->tx_ring[BK_QUEUE].dma);
 729         rtl_write_dword(rtlpriv, TBEDA, rtlpci->tx_ring[BE_QUEUE].dma);
 730         rtl_write_dword(rtlpriv, TVIDA, rtlpci->tx_ring[VI_QUEUE].dma);
 731         rtl_write_dword(rtlpriv, TVODA, rtlpci->tx_ring[VO_QUEUE].dma);
 732         rtl_write_dword(rtlpriv, TBDA, rtlpci->tx_ring[BEACON_QUEUE].dma);
 733         rtl_write_dword(rtlpriv, TCDA, rtlpci->tx_ring[TXCMD_QUEUE].dma);
 734         rtl_write_dword(rtlpriv, TMDA, rtlpci->tx_ring[MGNT_QUEUE].dma);
 735         rtl_write_dword(rtlpriv, THPDA, rtlpci->tx_ring[HIGH_QUEUE].dma);
 736         rtl_write_dword(rtlpriv, HDA, rtlpci->tx_ring[HCCA_QUEUE].dma);
 737
 738         rtl_write_word(rtlpriv, CMDR, 0x37FC);
 739
 740         /* To make sure that TxDMA can ready to download FW. */
 741         /* We should reset TxDMA if IMEM RPT was not ready. */
 742         do {
 743                 tmpu1b = rtl_read_byte(rtlpriv, TCR);
 744                 if ((tmpu1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE)
 745                         break;
 746
 747                 udelay(5);
 748         } while (pollingcnt--);
 749
 750         if (pollingcnt <= 0) {
 751                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 752                          "Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n",
 753                          tmpu1b);
 754                 tmpu1b = rtl_read_byte(rtlpriv, CMDR);
 755                 rtl_write_byte(rtlpriv, CMDR, tmpu1b & (~TXDMA_EN));
 756                 udelay(2);
 757                 /* Reset TxDMA */
 758                 rtl_write_byte(rtlpriv, CMDR, tmpu1b | TXDMA_EN);
 759         }
 760
 761         /* After MACIO reset,we must refresh LED state. */
 762         if ((ppsc->rfoff_reason == RF_CHANGE_BY_IPS) ||
 763            (ppsc->rfoff_reason == 0)) {
 764                 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 765                 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 766                 enum rf_pwrstate rfpwr_state_toset;
 767                 rfpwr_state_toset = _rtl92se_rf_onoff_detect(hw);
 768
 769                 if (rfpwr_state_toset == ERFON)
 770                         rtl92se_sw_led_on(hw, pLed0);
 771         }
 772 }
 773
 774 static void _rtl92se_macconfig_after_fwdownload(struct ieee80211_hw *hw)
 775 {
 776         struct rtl_priv *rtlpriv = rtl_priv(hw);
 777         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 778         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 779         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 780         u8 i;
 781         u16 tmpu2b;
 782
 783         /* 1. System Configure Register (Offset: 0x0000 - 0x003F) */
 784
 785         /* 2. Command Control Register (Offset: 0x0040 - 0x004F) */
 786         /* Turn on 0x40 Command register */
 787         rtl_write_word(rtlpriv, CMDR, (BBRSTN | BB_GLB_RSTN |
 788                         SCHEDULE_EN | MACRXEN | MACTXEN | DDMA_EN | FW2HW_EN |
 789                         RXDMA_EN | TXDMA_EN | HCI_RXDMA_EN | HCI_TXDMA_EN));
 790
 791         /* Set TCR TX DMA pre 2 FULL enable bit */
 792         rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) |
 793                         TXDMAPRE2FULL);
 794
 795         /* Set RCR      */
 796         rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
 797
 798         /* 3. MACID Setting Register (Offset: 0x0050 - 0x007F) */
 799
 800         /* 4. Timing Control Register  (Offset: 0x0080 - 0x009F) */
 801         /* Set CCK/OFDM SIFS */
 802         /* CCK SIFS shall always be 10us. */
 803         rtl_write_word(rtlpriv, SIFS_CCK, 0x0a0a);
 804         rtl_write_word(rtlpriv, SIFS_OFDM, 0x1010);
 805
 806         /* Set AckTimeout */
 807         rtl_write_byte(rtlpriv, ACK_TIMEOUT, 0x40);
 808
 809         /* Beacon related */
 810         rtl_write_word(rtlpriv, BCN_INTERVAL, 100);
 811         rtl_write_word(rtlpriv, ATIMWND, 2);
 812
 813         /* 5. FIFO Control Register (Offset: 0x00A0 - 0x015F) */
 814         /* 5.1 Initialize Number of Reserved Pages in Firmware Queue */
 815         /* Firmware allocate now, associate with FW internal setting.!!! */
 816
 817         /* 5.2 Setting TX/RX page size 0/1/2/3/4=64/128/256/512/1024 */
 818         /* 5.3 Set driver info, we only accept PHY status now. */
 819         /* 5.4 Set RXDMA arbitration to control RXDMA/MAC/FW R/W for RXFIFO  */
 820         rtl_write_byte(rtlpriv, RXDMA, rtl_read_byte(rtlpriv, RXDMA) | BIT(6));
 821
 822         /* 6. Adaptive Control Register  (Offset: 0x0160 - 0x01CF) */
 823         /* Set RRSR to all legacy rate and HT rate
 824          * CCK rate is supported by default.
 825          * CCK rate will be filtered out only when associated
 826          * AP does not support it.
 827          * Only enable ACK rate to OFDM 24M
 828          * Disable RRSR for CCK rate in A-Cut   */
 829
 830         if (rtlhal->version == VERSION_8192S_ACUT)
 831                 rtl_write_byte(rtlpriv, RRSR, 0xf0);
 832         else if (rtlhal->version == VERSION_8192S_BCUT)
 833                 rtl_write_byte(rtlpriv, RRSR, 0xff);
 834         rtl_write_byte(rtlpriv, RRSR + 1, 0x01);
 835         rtl_write_byte(rtlpriv, RRSR + 2, 0x00);
 836
 837         /* A-Cut IC do not support CCK rate. We forbid ARFR to */
 838         /* fallback to CCK rate */
 839         for (i = 0; i < 8; i++) {
 840                 /*Disable RRSR for CCK rate in A-Cut */
 841                 if (rtlhal->version == VERSION_8192S_ACUT)
 842                         rtl_write_dword(rtlpriv, ARFR0 + i * 4, 0x1f0ff0f0);
 843         }
 844
 845         /* Different rate use different AMPDU size */
 846         /* MCS32/ MCS15_SG use max AMPDU size 15*2=30K */
 847         rtl_write_byte(rtlpriv, AGGLEN_LMT_H, 0x0f);
 848         /* MCS0/1/2/3 use max AMPDU size 4*2=8K */
 849         rtl_write_word(rtlpriv, AGGLEN_LMT_L, 0x7442);
 850         /* MCS4/5 use max AMPDU size 8*2=16K 6/7 use 10*2=20K */
 851         rtl_write_word(rtlpriv, AGGLEN_LMT_L + 2, 0xddd7);
 852         /* MCS8/9 use max AMPDU size 8*2=16K 10/11 use 10*2=20K */
 853         rtl_write_word(rtlpriv, AGGLEN_LMT_L + 4, 0xd772);
 854         /* MCS12/13/14/15 use max AMPDU size 15*2=30K */
 855         rtl_write_word(rtlpriv, AGGLEN_LMT_L + 6, 0xfffd);
 856
 857         /* Set Data / Response auto rate fallack retry count */
 858         rtl_write_dword(rtlpriv, DARFRC, 0x04010000);
 859         rtl_write_dword(rtlpriv, DARFRC + 4, 0x09070605);
 860         rtl_write_dword(rtlpriv, RARFRC, 0x04010000);
 861         rtl_write_dword(rtlpriv, RARFRC + 4, 0x09070605);
 862
 863         /* 7. EDCA Setting Register (Offset: 0x01D0 - 0x01FF) */
 864         /* Set all rate to support SG */
 865         rtl_write_word(rtlpriv, SG_RATE, 0xFFFF);
 866
 867         /* 8. WMAC, BA, and CCX related Register (Offset: 0x0200 - 0x023F) */
 868         /* Set NAV protection length */
 869         rtl_write_word(rtlpriv, NAV_PROT_LEN, 0x0080);
 870         /* CF-END Threshold */
 871         rtl_write_byte(rtlpriv, CFEND_TH, 0xFF);
 872         /* Set AMPDU minimum space */
 873         rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 0x07);
 874         /* Set TXOP stall control for several queue/HI/BCN/MGT/ */
 875         rtl_write_byte(rtlpriv, TXOP_STALL_CTRL, 0x00);
 876
 877         /* 9. Security Control Register (Offset: 0x0240 - 0x025F) */
 878         /* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */
 879         /* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */
 880         /* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */
 881         /* 13. Test Mode and Debug Control Register (Offset: 0x0310 - 0x034F) */
 882
 883         /* 14. Set driver info, we only accept PHY status now. */
 884         rtl_write_byte(rtlpriv, RXDRVINFO_SZ, 4);
 885
 886         /* 15. For EEPROM R/W Workaround */
 887         /* 16. For EFUSE to share REG_SYS_FUNC_EN with EEPROM!!! */
 888         tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
 889         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmpu2b | BIT(13));
 890         tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
 891         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, tmpu2b & (~BIT(8)));
 892
 893         /* 17. For EFUSE */
 894         /* We may R/W EFUSE in EEPROM mode */
 895         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
 896                 u8      tempval;
 897
 898                 tempval = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL + 1);
 899                 tempval &= 0xFE;
 900                 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, tempval);
 901
 902                 /* Change Program timing */
 903                 rtl_write_byte(rtlpriv, REG_EFUSE_CTRL + 3, 0x72);
 904                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "EFUSE CONFIG OK\n");
 905         }
 906
 907         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n");
 908
 909 }
 910
 911 static void _rtl92se_hw_configure(struct ieee80211_hw *hw)
 912 {
 913         struct rtl_priv *rtlpriv = rtl_priv(hw);
 914         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 915         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 916         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 917
 918         u8 reg_bw_opmode = 0;
 919         u32 reg_rrsr = 0;
 920         u8 regtmp = 0;
 921
 922         reg_bw_opmode = BW_OPMODE_20MHZ;
 923         reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 924
 925         regtmp = rtl_read_byte(rtlpriv, INIRTSMCS_SEL);
 926         reg_rrsr = ((reg_rrsr & 0x000fffff) << 8) | regtmp;
 927         rtl_write_dword(rtlpriv, INIRTSMCS_SEL, reg_rrsr);
 928         rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
 929
 930         /* Set Retry Limit here */
 931         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
 932                         (u8 *)(&rtlpci->shortretry_limit));
 933
 934         rtl_write_byte(rtlpriv, MLT, 0x8f);
 935
 936         /* For Min Spacing configuration. */
 937         switch (rtlphy->rf_type) {
 938         case RF_1T2R:
 939         case RF_1T1R:
 940                 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
 941                 break;
 942         case RF_2T2R:
 943         case RF_2T2R_GREEN:
 944                 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
 945                 break;
 946         }
 947         rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, rtlhal->minspace_cfg);
 948 }
 949
 950 int rtl92se_hw_init(struct ieee80211_hw *hw)
 951 {
 952         struct rtl_priv *rtlpriv = rtl_priv(hw);
 953         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 954         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 955         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 956         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 957         u8 tmp_byte = 0;
 958         unsigned long flags;
 959         bool rtstatus = true;
 960         u8 tmp_u1b;
 961         int err = false;
 962         u8 i;
 963         int wdcapra_add[] = {
 964                 EDCAPARA_BE, EDCAPARA_BK,
 965                 EDCAPARA_VI, EDCAPARA_VO};
 966         u8 secr_value = 0x0;
 967
 968         rtlpci->being_init_adapter = true;
 969
 970         /* As this function can take a very long time (up to 350 ms)
 971          * and can be called with irqs disabled, reenable the irqs
 972          * to let the other devices continue being serviced.
 973          *
 974          * It is safe doing so since our own interrupts will only be enabled
 975          * in a subsequent step.
 976          */
 977         local_save_flags(flags);
 978         local_irq_enable();
 979
 980         rtlpriv->intf_ops->disable_aspm(hw);
 981
 982         /* 1. MAC Initialize */
 983         /* Before FW download, we have to set some MAC register */
 984         _rtl92se_macconfig_before_fwdownload(hw);
 985
 986         rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv,
 987                         PMC_FSM) >> 16) & 0xF);
 988
 989         rtl8192se_gpiobit3_cfg_inputmode(hw);
 990
 991         /* 2. download firmware */
 992         rtstatus = rtl92s_download_fw(hw);
 993         if (!rtstatus) {
 994                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 995                          "Failed to download FW. Init HW without FW now... "
 996                          "Please copy FW into /lib/firmware/rtlwifi\n");
 997                 err = 1;
 998                 goto exit;
 999         }
1000
1001         /* After FW download, we have to reset MAC register */
1002         _rtl92se_macconfig_after_fwdownload(hw);
1003
1004         /*Retrieve default FW Cmd IO map. */
1005         rtlhal->fwcmd_iomap =   rtl_read_word(rtlpriv, LBUS_MON_ADDR);
1006         rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, LBUS_ADDR_MASK);
1007
1008         /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */
1009         if (!rtl92s_phy_mac_config(hw)) {
1010                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "MAC Config failed\n");
1011                 err = rtstatus;
1012                 goto exit;
1013         }
1014
1015         /* because last function modify RCR, so we update
1016          * rcr var here, or TP will unstable for receive_config
1017          * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1018          * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1019          */
1020         rtlpci->receive_config = rtl_read_dword(rtlpriv, RCR);
1021         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1022         rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
1023
1024         /* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */
1025         /* We must set flag avoid BB/RF config period later!! */
1026         rtl_write_dword(rtlpriv, CMDR, 0x37FC);
1027
1028         /* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */
1029         if (!rtl92s_phy_bb_config(hw)) {
1030                 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "BB Config failed\n");
1031                 err = rtstatus;
1032                 goto exit;
1033         }
1034
1035         /* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */
1036         /* Before initalizing RF. We can not use FW to do RF-R/W. */
1037
1038         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1039
1040         /* Before RF-R/W we must execute the IO from Scott's suggestion. */
1041         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, 0xDB);
1042         if (rtlhal->version == VERSION_8192S_ACUT)
1043                 rtl_write_byte(rtlpriv, SPS1_CTRL + 3, 0x07);
1044         else
1045                 rtl_write_byte(rtlpriv, RF_CTRL, 0x07);
1046
1047         if (!rtl92s_phy_rf_config(hw)) {
1048                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RF Config failed\n");
1049                 err = rtstatus;
1050                 goto exit;
1051         }
1052
1053         /* After read predefined TXT, we must set BB/MAC/RF
1054          * register as our requirement */
1055
1056         rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw,
1057                                                            (enum radio_path)0,
1058                                                            RF_CHNLBW,
1059                                                            RFREG_OFFSET_MASK);
1060         rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw,
1061                                                            (enum radio_path)1,
1062                                                            RF_CHNLBW,
1063                                                            RFREG_OFFSET_MASK);
1064
1065         /*---- Set CCK and OFDM Block "ON"----*/
1066         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1067         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1068
1069         /*3 Set Hardware(Do nothing now) */
1070         _rtl92se_hw_configure(hw);
1071
1072         /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1073         /* TX power index for different rate set. */
1074         /* Get original hw reg values */
1075         rtl92s_phy_get_hw_reg_originalvalue(hw);
1076         /* Write correct tx power index */
1077         rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1078
1079         /* We must set MAC address after firmware download. */
1080         for (i = 0; i < 6; i++)
1081                 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1082
1083         /* EEPROM R/W workaround */
1084         tmp_u1b = rtl_read_byte(rtlpriv, MAC_PINMUX_CFG);
1085         rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, tmp_u1b & (~BIT(3)));
1086
1087         rtl_write_byte(rtlpriv, 0x4d, 0x0);
1088
1089         if (hal_get_firmwareversion(rtlpriv) >= 0x49) {
1090                 tmp_byte = rtl_read_byte(rtlpriv, FW_RSVD_PG_CRTL) & (~BIT(4));
1091                 tmp_byte = tmp_byte | BIT(5);
1092                 rtl_write_byte(rtlpriv, FW_RSVD_PG_CRTL, tmp_byte);
1093                 rtl_write_dword(rtlpriv, TXDESC_MSK, 0xFFFFCFFF);
1094         }
1095
1096         /* We enable high power and RA related mechanism after NIC
1097          * initialized. */
1098         if (hal_get_firmwareversion(rtlpriv) >= 0x35) {
1099                 /* Fw v.53 and later. */
1100                 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT);
1101         } else if (hal_get_firmwareversion(rtlpriv) == 0x34) {
1102                 /* Fw v.52. */
1103                 rtl_write_dword(rtlpriv, WFM5, FW_RA_INIT);
1104                 rtl92s_phy_chk_fwcmd_iodone(hw);
1105         } else {
1106                 /* Compatible earlier FW version. */
1107                 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET);
1108                 rtl92s_phy_chk_fwcmd_iodone(hw);
1109                 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE);
1110                 rtl92s_phy_chk_fwcmd_iodone(hw);
1111                 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH);
1112                 rtl92s_phy_chk_fwcmd_iodone(hw);
1113         }
1114
1115         /* Add to prevent ASPM bug. */
1116         /* Always enable hst and NIC clock request. */
1117         rtl92s_phy_switch_ephy_parameter(hw);
1118
1119         /* Security related
1120          * 1. Clear all H/W keys.
1121          * 2. Enable H/W encryption/decryption. */
1122         rtl_cam_reset_all_entry(hw);
1123         secr_value |= SCR_TXENCENABLE;
1124         secr_value |= SCR_RXENCENABLE;
1125         secr_value |= SCR_NOSKMC;
1126         rtl_write_byte(rtlpriv, REG_SECR, secr_value);
1127
1128         for (i = 0; i < 4; i++)
1129                 rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322);
1130
1131         if (rtlphy->rf_type == RF_1T2R) {
1132                 bool mrc2set = true;
1133                 /* Turn on B-Path */
1134                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set);
1135         }
1136
1137         rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON);
1138         rtl92s_dm_init(hw);
1139 exit:
1140         local_irq_restore(flags);
1141         rtlpci->being_init_adapter = false;
1142         return err;
1143 }
1144
1145 void rtl92se_set_mac_addr(struct rtl_io *io, const u8 *addr)
1146 {
1147         /* This is a stub. */
1148 }
1149
1150 void rtl92se_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1151 {
1152         struct rtl_priv *rtlpriv = rtl_priv(hw);
1153         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1154         u32 reg_rcr = rtlpci->receive_config;
1155
1156         if (rtlpriv->psc.rfpwr_state != ERFON)
1157                 return;
1158
1159         if (check_bssid) {
1160                 reg_rcr |= (RCR_CBSSID);
1161                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1162         } else if (!check_bssid) {
1163                 reg_rcr &= (~RCR_CBSSID);
1164                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1165         }
1166
1167 }
1168
1169 static int _rtl92se_set_media_status(struct ieee80211_hw *hw,
1170                                      enum nl80211_iftype type)
1171 {
1172         struct rtl_priv *rtlpriv = rtl_priv(hw);
1173         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1174         u32 temp;
1175         bt_msr &= ~MSR_LINK_MASK;
1176
1177         switch (type) {
1178         case NL80211_IFTYPE_UNSPECIFIED:
1179                 bt_msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
1180                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1181                          "Set Network type to NO LINK!\n");
1182                 break;
1183         case NL80211_IFTYPE_ADHOC:
1184                 bt_msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
1185                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1186                          "Set Network type to Ad Hoc!\n");
1187                 break;
1188         case NL80211_IFTYPE_STATION:
1189                 bt_msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
1190                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1191                          "Set Network type to STA!\n");
1192                 break;
1193         case NL80211_IFTYPE_AP:
1194                 bt_msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
1195                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1196                          "Set Network type to AP!\n");
1197                 break;
1198         default:
1199                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1200                          "Network type %d not supported!\n", type);
1201                 return 1;
1202                 break;
1203
1204         }
1205
1206         rtl_write_byte(rtlpriv, (MSR), bt_msr);
1207
1208         temp = rtl_read_dword(rtlpriv, TCR);
1209         rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8)));
1210         rtl_write_dword(rtlpriv, TCR, temp | BIT(8));
1211
1212
1213         return 0;
1214 }
1215
1216 /* HW_VAR_MEDIA_STATUS & HW_VAR_CECHK_BSSID */
1217 int rtl92se_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1218 {
1219         struct rtl_priv *rtlpriv = rtl_priv(hw);
1220
1221         if (_rtl92se_set_media_status(hw, type))
1222                 return -EOPNOTSUPP;
1223
1224         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1225                 if (type != NL80211_IFTYPE_AP)
1226                         rtl92se_set_check_bssid(hw, true);
1227         } else {
1228                 rtl92se_set_check_bssid(hw, false);
1229         }
1230
1231         return 0;
1232 }
1233
1234 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1235 void rtl92se_set_qos(struct ieee80211_hw *hw, int aci)
1236 {
1237         struct rtl_priv *rtlpriv = rtl_priv(hw);
1238         rtl92s_dm_init_edca_turbo(hw);
1239
1240         switch (aci) {
1241         case AC1_BK:
1242                 rtl_write_dword(rtlpriv, EDCAPARA_BK, 0xa44f);
1243                 break;
1244         case AC0_BE:
1245                 /* rtl_write_dword(rtlpriv, EDCAPARA_BE, u4b_ac_param); */
1246                 break;
1247         case AC2_VI:
1248                 rtl_write_dword(rtlpriv, EDCAPARA_VI, 0x5e4322);
1249                 break;
1250         case AC3_VO:
1251                 rtl_write_dword(rtlpriv, EDCAPARA_VO, 0x2f3222);
1252                 break;
1253         default:
1254                 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1255                 break;
1256         }
1257 }
1258
1259 void rtl92se_enable_interrupt(struct ieee80211_hw *hw)
1260 {
1261         struct rtl_priv *rtlpriv = rtl_priv(hw);
1262         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1263
1264         rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]);
1265         /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */
1266         rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F);
1267 }
1268
1269 void rtl92se_disable_interrupt(struct ieee80211_hw *hw)
1270 {
1271         struct rtl_priv *rtlpriv;
1272         struct rtl_pci *rtlpci;
1273
1274         rtlpriv = rtl_priv(hw);
1275         /* if firmware not available, no interrupts */
1276         if (!rtlpriv || !rtlpriv->max_fw_size)
1277                 return;
1278         rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1279         rtl_write_dword(rtlpriv, INTA_MASK, 0);
1280         rtl_write_dword(rtlpriv, INTA_MASK + 4, 0);
1281
1282         synchronize_irq(rtlpci->pdev->irq);
1283 }
1284
1285 static u8 _rtl92s_set_sysclk(struct ieee80211_hw *hw, u8 data)
1286 {
1287         struct rtl_priv *rtlpriv = rtl_priv(hw);
1288         u8 waitcnt = 100;
1289         bool result = false;
1290         u8 tmp;
1291
1292         rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
1293
1294         /* Wait the MAC synchronized. */
1295         udelay(400);
1296
1297         /* Check if it is set ready. */
1298         tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1299         result = ((tmp & BIT(7)) == (data & BIT(7)));
1300
1301         if ((data & (BIT(6) | BIT(7))) == false) {
1302                 waitcnt = 100;
1303                 tmp = 0;
1304
1305                 while (1) {
1306                         waitcnt--;
1307                         tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1308
1309                         if ((tmp & BIT(6)))
1310                                 break;
1311
1312                         pr_err("wait for BIT(6) return value %x\n", tmp);
1313
1314                         if (waitcnt == 0)
1315                                 break;
1316                         udelay(10);
1317                 }
1318
1319                 if (waitcnt == 0)
1320                         result = false;
1321                 else
1322                         result = true;
1323         }
1324
1325         return result;
1326 }
1327
1328 static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw)
1329 {
1330         struct rtl_priv *rtlpriv = rtl_priv(hw);
1331         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1332         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1333         u8 u1btmp;
1334
1335         if (rtlhal->driver_going2unload)
1336                 rtl_write_byte(rtlpriv, 0x560, 0x0);
1337
1338         /* Power save for BB/RF */
1339         u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
1340         u1btmp |= BIT(0);
1341         rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
1342         rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
1343         rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
1344         rtl_write_word(rtlpriv, CMDR, 0x57FC);
1345         udelay(100);
1346         rtl_write_word(rtlpriv, CMDR, 0x77FC);
1347         rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
1348         udelay(10);
1349         rtl_write_word(rtlpriv, CMDR, 0x37FC);
1350         udelay(10);
1351         rtl_write_word(rtlpriv, CMDR, 0x77FC);
1352         udelay(10);
1353         rtl_write_word(rtlpriv, CMDR, 0x57FC);
1354         rtl_write_word(rtlpriv, CMDR, 0x0000);
1355
1356         if (rtlhal->driver_going2unload) {
1357                 u1btmp = rtl_read_byte(rtlpriv, (REG_SYS_FUNC_EN + 1));
1358                 u1btmp &= ~(BIT(0));
1359                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1btmp);
1360         }
1361
1362         u1btmp = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1363
1364         /* Add description. After switch control path. register
1365          * after page1 will be invisible. We can not do any IO
1366          * for register>0x40. After resume&MACIO reset, we need
1367          * to remember previous reg content. */
1368         if (u1btmp & BIT(7)) {
1369                 u1btmp &= ~(BIT(6) | BIT(7));
1370                 if (!_rtl92s_set_sysclk(hw, u1btmp)) {
1371                         pr_err("Switch ctrl path fail\n");
1372                         return;
1373                 }
1374         }
1375
1376         /* Power save for MAC */
1377         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS  &&
1378                 !rtlhal->driver_going2unload) {
1379                 /* enable LED function */
1380                 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1381         /* SW/HW radio off or halt adapter!! For example S3/S4 */
1382         } else {
1383                 /* LED function disable. Power range is about 8mA now. */
1384                 /* if write 0xF1 disconnet_pci power
1385                  *       ifconfig wlan0 down power are both high 35:70 */
1386                 /* if write oxF9 disconnet_pci power
1387                  * ifconfig wlan0 down power are both low  12:45*/
1388                 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1389         }
1390
1391         rtl_write_byte(rtlpriv, SYS_CLKR + 1, 0x70);
1392         rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, 0x68);
1393         rtl_write_byte(rtlpriv,  AFE_PLL_CTRL, 0x00);
1394         rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1395         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, 0x0E);
1396         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1397
1398 }
1399
1400 static void _rtl92se_gen_refreshledstate(struct ieee80211_hw *hw)
1401 {
1402         struct rtl_priv *rtlpriv = rtl_priv(hw);
1403         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1404         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1405         struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
1406
1407         if (rtlpci->up_first_time == 1)
1408                 return;
1409
1410         if (rtlpriv->psc.rfoff_reason == RF_CHANGE_BY_IPS)
1411                 rtl92se_sw_led_on(hw, pLed0);
1412         else
1413                 rtl92se_sw_led_off(hw, pLed0);
1414 }
1415
1416
1417 static void _rtl92se_power_domain_init(struct ieee80211_hw *hw)
1418 {
1419         struct rtl_priv *rtlpriv = rtl_priv(hw);
1420         u16 tmpu2b;
1421         u8 tmpu1b;
1422
1423         rtlpriv->psc.pwrdomain_protect = true;
1424
1425         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1426         if (tmpu1b & BIT(7)) {
1427                 tmpu1b &= ~(BIT(6) | BIT(7));
1428                 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1429                         rtlpriv->psc.pwrdomain_protect = false;
1430                         return;
1431                 }
1432         }
1433
1434         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
1435         rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1436
1437         /* Reset MAC-IO and CPU and Core Digital BIT10/11/15 */
1438         tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1439
1440         /* If IPS we need to turn LED on. So we not
1441          * not disable BIT 3/7 of reg3. */
1442         if (rtlpriv->psc.rfoff_reason & (RF_CHANGE_BY_IPS | RF_CHANGE_BY_HW))
1443                 tmpu1b &= 0xFB;
1444         else
1445                 tmpu1b &= 0x73;
1446
1447         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
1448         /* wait for BIT 10/11/15 to pull high automatically!! */
1449         mdelay(1);
1450
1451         rtl_write_byte(rtlpriv, CMDR, 0);
1452         rtl_write_byte(rtlpriv, TCR, 0);
1453
1454         /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
1455         tmpu1b = rtl_read_byte(rtlpriv, 0x562);
1456         tmpu1b |= 0x08;
1457         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1458         tmpu1b &= ~(BIT(3));
1459         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1460
1461         /* Enable AFE clock source */
1462         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
1463         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
1464         /* Delay 1.5ms */
1465         udelay(1500);
1466         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
1467         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
1468
1469         /* Enable AFE Macro Block's Bandgap */
1470         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1471         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
1472         mdelay(1);
1473
1474         /* Enable AFE Mbias */
1475         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1476         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
1477         mdelay(1);
1478
1479         /* Enable LDOA15 block */
1480         tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
1481         rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
1482
1483         /* Set Digital Vdd to Retention isolation Path. */
1484         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
1485         rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
1486
1487
1488         /* For warm reboot NIC disappera bug. */
1489         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1490         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
1491
1492         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
1493
1494         /* Enable AFE PLL Macro Block */
1495         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
1496         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
1497         /* Enable MAC 80MHZ clock */
1498         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
1499         rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
1500         mdelay(1);
1501
1502         /* Release isolation AFE PLL & MD */
1503         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
1504
1505         /* Enable MAC clock */
1506         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1507         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
1508
1509         /* Enable Core digital and enable IOREG R/W */
1510         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1511         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
1512         /* enable REG_EN */
1513         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
1514
1515         /* Switch the control path. */
1516         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1517         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
1518
1519         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1520         tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
1521         if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1522                 rtlpriv->psc.pwrdomain_protect = false;
1523                 return;
1524         }
1525
1526         rtl_write_word(rtlpriv, CMDR, 0x37FC);
1527
1528         /* After MACIO reset,we must refresh LED state. */
1529         _rtl92se_gen_refreshledstate(hw);
1530
1531         rtlpriv->psc.pwrdomain_protect = false;
1532 }
1533
1534 void rtl92se_card_disable(struct ieee80211_hw *hw)
1535 {
1536         struct rtl_priv *rtlpriv = rtl_priv(hw);
1537         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1538         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1539         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1540         enum nl80211_iftype opmode;
1541         u8 wait = 30;
1542
1543         rtlpriv->intf_ops->enable_aspm(hw);
1544
1545         if (rtlpci->driver_is_goingto_unload ||
1546                 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1547                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1548
1549         /* we should chnge GPIO to input mode
1550          * this will drop away current about 25mA*/
1551         rtl8192se_gpiobit3_cfg_inputmode(hw);
1552
1553         /* this is very important for ips power save */
1554         while (wait-- >= 10 && rtlpriv->psc.pwrdomain_protect) {
1555                 if (rtlpriv->psc.pwrdomain_protect)
1556                         mdelay(20);
1557                 else
1558                         break;
1559         }
1560
1561         mac->link_state = MAC80211_NOLINK;
1562         opmode = NL80211_IFTYPE_UNSPECIFIED;
1563         _rtl92se_set_media_status(hw, opmode);
1564
1565         _rtl92s_phy_set_rfhalt(hw);
1566         udelay(100);
1567 }
1568
1569 void rtl92se_interrupt_recognized(struct ieee80211_hw *hw, u32 *p_inta,
1570                              u32 *p_intb)
1571 {
1572         struct rtl_priv *rtlpriv = rtl_priv(hw);
1573         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1574
1575         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1576         rtl_write_dword(rtlpriv, ISR, *p_inta);
1577
1578         *p_intb = rtl_read_dword(rtlpriv, ISR + 4) & rtlpci->irq_mask[1];
1579         rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1580 }
1581
1582 void rtl92se_set_beacon_related_registers(struct ieee80211_hw *hw)
1583 {
1584         struct rtl_priv *rtlpriv = rtl_priv(hw);
1585         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1586         u16 bcntime_cfg = 0;
1587         u16 bcn_cw = 6, bcn_ifs = 0xf;
1588         u16 atim_window = 2;
1589
1590         /* ATIM Window (in unit of TU). */
1591         rtl_write_word(rtlpriv, ATIMWND, atim_window);
1592
1593         /* Beacon interval (in unit of TU). */
1594         rtl_write_word(rtlpriv, BCN_INTERVAL, mac->beacon_interval);
1595
1596         /* DrvErlyInt (in unit of TU). (Time to send
1597          * interrupt to notify driver to change
1598          * beacon content) */
1599         rtl_write_word(rtlpriv, BCN_DRV_EARLY_INT, 10 << 4);
1600
1601         /* BcnDMATIM(in unit of us). Indicates the
1602          * time before TBTT to perform beacon queue DMA  */
1603         rtl_write_word(rtlpriv, BCN_DMATIME, 256);
1604
1605         /* Force beacon frame transmission even
1606          * after receiving beacon frame from
1607          * other ad hoc STA */
1608         rtl_write_byte(rtlpriv, BCN_ERR_THRESH, 100);
1609
1610         /* Beacon Time Configuration */
1611         if (mac->opmode == NL80211_IFTYPE_ADHOC)
1612                 bcntime_cfg |= (bcn_cw << BCN_TCFG_CW_SHIFT);
1613
1614         /* TODO: bcn_ifs may required to be changed on ASIC */
1615         bcntime_cfg |= bcn_ifs << BCN_TCFG_IFS;
1616
1617         /*for beacon changed */
1618         rtl92s_phy_set_beacon_hwreg(hw, mac->beacon_interval);
1619 }
1620
1621 void rtl92se_set_beacon_interval(struct ieee80211_hw *hw)
1622 {
1623         struct rtl_priv *rtlpriv = rtl_priv(hw);
1624         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1625         u16 bcn_interval = mac->beacon_interval;
1626
1627         /* Beacon interval (in unit of TU). */
1628         rtl_write_word(rtlpriv, BCN_INTERVAL, bcn_interval);
1629         /* 2008.10.24 added by tynli for beacon changed. */
1630         rtl92s_phy_set_beacon_hwreg(hw, bcn_interval);
1631 }
1632
1633 void rtl92se_update_interrupt_mask(struct ieee80211_hw *hw,
1634                 u32 add_msr, u32 rm_msr)
1635 {
1636         struct rtl_priv *rtlpriv = rtl_priv(hw);
1637         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1638
1639         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1640                  add_msr, rm_msr);
1641
1642         if (add_msr)
1643                 rtlpci->irq_mask[0] |= add_msr;
1644
1645         if (rm_msr)
1646                 rtlpci->irq_mask[0] &= (~rm_msr);
1647
1648         rtl92se_disable_interrupt(hw);
1649         rtl92se_enable_interrupt(hw);
1650 }
1651
1652 static void _rtl8192se_get_IC_Inferiority(struct ieee80211_hw *hw)
1653 {
1654         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1655         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1656         u8 efuse_id;
1657
1658         rtlhal->ic_class = IC_INFERIORITY_A;
1659
1660         /* Only retrieving while using EFUSE. */
1661         if ((rtlefuse->epromtype == EEPROM_BOOT_EFUSE) &&
1662                 !rtlefuse->autoload_failflag) {
1663                 efuse_id = efuse_read_1byte(hw, EFUSE_IC_ID_OFFSET);
1664
1665                 if (efuse_id == 0xfe)
1666                         rtlhal->ic_class = IC_INFERIORITY_B;
1667         }
1668 }
1669
1670 static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1671 {
1672         struct rtl_priv *rtlpriv = rtl_priv(hw);
1673         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1674         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1675         u16 i, usvalue;
1676         u16     eeprom_id;
1677         u8 tempval;
1678         u8 hwinfo[HWSET_MAX_SIZE_92S];
1679         u8 rf_path, index;
1680
1681         if (rtlefuse->epromtype == EEPROM_93C46) {
1682                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1683                          "RTL819X Not boot from eeprom, check it !!\n");
1684         } else if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1685                 rtl_efuse_shadow_map_update(hw);
1686
1687                 memcpy((void *)hwinfo, (void *)
1688                         &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1689                         HWSET_MAX_SIZE_92S);
1690         }
1691
1692         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP",
1693                       hwinfo, HWSET_MAX_SIZE_92S);
1694
1695         eeprom_id = *((u16 *)&hwinfo[0]);
1696         if (eeprom_id != RTL8190_EEPROM_ID) {
1697                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1698                          "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1699                 rtlefuse->autoload_failflag = true;
1700         } else {
1701                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1702                 rtlefuse->autoload_failflag = false;
1703         }
1704
1705         if (rtlefuse->autoload_failflag)
1706                 return;
1707
1708         _rtl8192se_get_IC_Inferiority(hw);
1709
1710         /* Read IC Version && Channel Plan */
1711         /* VID, DID      SE     0xA-D */
1712         rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1713         rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1714         rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1715         rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1716         rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1717
1718         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1719                  "EEPROMId = 0x%4x\n", eeprom_id);
1720         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1721                  "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1722         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1723                  "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1724         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1725                  "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1726         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1727                  "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1728
1729         for (i = 0; i < 6; i += 2) {
1730                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1731                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1732         }
1733
1734         for (i = 0; i < 6; i++)
1735                 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1736
1737         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1738
1739         /* Get Tx Power Level by Channel */
1740         /* Read Tx power of Channel 1 ~ 14 from EEPROM. */
1741         /* 92S suupport RF A & B */
1742         for (rf_path = 0; rf_path < 2; rf_path++) {
1743                 for (i = 0; i < 3; i++) {
1744                         /* Read CCK RF A & B Tx power  */
1745                         rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1746                         hwinfo[EEPROM_TXPOWERBASE + rf_path * 3 + i];
1747
1748                         /* Read OFDM RF A & B Tx power for 1T */
1749                         rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1750                         hwinfo[EEPROM_TXPOWERBASE + 6 + rf_path * 3 + i];
1751
1752                         /* Read OFDM RF A & B Tx power for 2T */
1753                         rtlefuse->eprom_chnl_txpwr_ht40_2sdf[rf_path][i]
1754                                  = hwinfo[EEPROM_TXPOWERBASE + 12 +
1755                                    rf_path * 3 + i];
1756                 }
1757         }
1758
1759         for (rf_path = 0; rf_path < 2; rf_path++)
1760                 for (i = 0; i < 3; i++)
1761                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1762                                 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1763                                 rf_path, i,
1764                                 rtlefuse->eeprom_chnlarea_txpwr_cck
1765                                 [rf_path][i]);
1766         for (rf_path = 0; rf_path < 2; rf_path++)
1767                 for (i = 0; i < 3; i++)
1768                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1769                                 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1770                                 rf_path, i,
1771                                 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1772                                 [rf_path][i]);
1773         for (rf_path = 0; rf_path < 2; rf_path++)
1774                 for (i = 0; i < 3; i++)
1775                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1776                                 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1777                                 rf_path, i,
1778                                 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1779                                 [rf_path][i]);
1780
1781         for (rf_path = 0; rf_path < 2; rf_path++) {
1782
1783                 /* Assign dedicated channel tx power */
1784                 for (i = 0; i < 14; i++)        {
1785                         /* channel 1~3 use the same Tx Power Level. */
1786                         if (i < 3)
1787                                 index = 0;
1788                         /* Channel 4-8 */
1789                         else if (i < 8)
1790                                 index = 1;
1791                         /* Channel 9-14 */
1792                         else
1793                                 index = 2;
1794
1795                         /* Record A & B CCK /OFDM - 1T/2T Channel area
1796                          * tx power */
1797                         rtlefuse->txpwrlevel_cck[rf_path][i]  =
1798                                 rtlefuse->eeprom_chnlarea_txpwr_cck
1799                                                         [rf_path][index];
1800                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i]  =
1801                                 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1802                                                         [rf_path][index];
1803                         rtlefuse->txpwrlevel_ht40_2s[rf_path][i]  =
1804                                 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1805                                                         [rf_path][index];
1806                 }
1807
1808                 for (i = 0; i < 14; i++) {
1809                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1810                                 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1811                                 rf_path, i,
1812                                 rtlefuse->txpwrlevel_cck[rf_path][i],
1813                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1814                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1815                 }
1816         }
1817
1818         for (rf_path = 0; rf_path < 2; rf_path++) {
1819                 for (i = 0; i < 3; i++) {
1820                         /* Read Power diff limit. */
1821                         rtlefuse->eeprom_pwrgroup[rf_path][i] =
1822                                 hwinfo[EEPROM_TXPWRGROUP + rf_path * 3 + i];
1823                 }
1824         }
1825
1826         for (rf_path = 0; rf_path < 2; rf_path++) {
1827                 /* Fill Pwr group */
1828                 for (i = 0; i < 14; i++) {
1829                         /* Chanel 1-3 */
1830                         if (i < 3)
1831                                 index = 0;
1832                         /* Channel 4-8 */
1833                         else if (i < 8)
1834                                 index = 1;
1835                         /* Channel 9-13 */
1836                         else
1837                                 index = 2;
1838
1839                         rtlefuse->pwrgroup_ht20[rf_path][i] =
1840                                 (rtlefuse->eeprom_pwrgroup[rf_path][index] &
1841                                 0xf);
1842                         rtlefuse->pwrgroup_ht40[rf_path][i] =
1843                                 ((rtlefuse->eeprom_pwrgroup[rf_path][index] &
1844                                 0xf0) >> 4);
1845
1846                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1847                                 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1848                                 rf_path, i,
1849                                 rtlefuse->pwrgroup_ht20[rf_path][i]);
1850                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1851                                 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1852                                 rf_path, i,
1853                                 rtlefuse->pwrgroup_ht40[rf_path][i]);
1854                         }
1855         }
1856
1857         for (i = 0; i < 14; i++) {
1858                 /* Read tx power difference between HT OFDM 20/40 MHZ */
1859                 /* channel 1-3 */
1860                 if (i < 3)
1861                         index = 0;
1862                 /* Channel 4-8 */
1863                 else if (i < 8)
1864                         index = 1;
1865                 /* Channel 9-14 */
1866                 else
1867                         index = 2;
1868
1869                 tempval = hwinfo[EEPROM_TX_PWR_HT20_DIFF + index] & 0xff;
1870                 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1871                 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1872                                                  ((tempval >> 4) & 0xF);
1873
1874                 /* Read OFDM<->HT tx power diff */
1875                 /* Channel 1-3 */
1876                 if (i < 3)
1877                         index = 0;
1878                 /* Channel 4-8 */
1879                 else if (i < 8)
1880                         index = 0x11;
1881                 /* Channel 9-14 */
1882                 else
1883                         index = 1;
1884
1885                 tempval = hwinfo[EEPROM_TX_PWR_OFDM_DIFF + index] & 0xff;
1886                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] =
1887                                  (tempval & 0xF);
1888                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1889                                  ((tempval >> 4) & 0xF);
1890
1891                 tempval = hwinfo[TX_PWR_SAFETY_CHK];
1892                 rtlefuse->txpwr_safetyflag = (tempval & 0x01);
1893         }
1894
1895         rtlefuse->eeprom_regulatory = 0;
1896         if (rtlefuse->eeprom_version >= 2) {
1897                 /* BIT(0)~2 */
1898                 if (rtlefuse->eeprom_version >= 4)
1899                         rtlefuse->eeprom_regulatory =
1900                                  (hwinfo[EEPROM_REGULATORY] & 0x7);
1901                 else /* BIT(0) */
1902                         rtlefuse->eeprom_regulatory =
1903                                  (hwinfo[EEPROM_REGULATORY] & 0x1);
1904         }
1905         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1906                 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1907
1908         for (i = 0; i < 14; i++)
1909                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1910                         "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1911                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1912         for (i = 0; i < 14; i++)
1913                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1914                         "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1915                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1916         for (i = 0; i < 14; i++)
1917                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1918                         "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1919                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1920         for (i = 0; i < 14; i++)
1921                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1922                         "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1923                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1924
1925         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1926                 "TxPwrSafetyFlag = %d\n", rtlefuse->txpwr_safetyflag);
1927
1928         /* Read RF-indication and Tx Power gain
1929          * index diff of legacy to HT OFDM rate. */
1930         tempval = hwinfo[EEPROM_RFIND_POWERDIFF] & 0xff;
1931         rtlefuse->eeprom_txpowerdiff = tempval;
1932         rtlefuse->legacy_httxpowerdiff =
1933                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0];
1934
1935         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1936                 "TxPowerDiff = %#x\n", rtlefuse->eeprom_txpowerdiff);
1937
1938         /* Get TSSI value for each path. */
1939         usvalue = *(u16 *)&hwinfo[EEPROM_TSSI_A];
1940         rtlefuse->eeprom_tssi[RF90_PATH_A] = (u8)((usvalue & 0xff00) >> 8);
1941         usvalue = hwinfo[EEPROM_TSSI_B];
1942         rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff);
1943
1944         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1945                 rtlefuse->eeprom_tssi[RF90_PATH_A],
1946                 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1947
1948         /* Read antenna tx power offset of B/C/D to A  from EEPROM */
1949         /* and read ThermalMeter from EEPROM */
1950         tempval = hwinfo[EEPROM_THERMALMETER];
1951         rtlefuse->eeprom_thermalmeter = tempval;
1952         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1953                 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1954
1955         /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */
1956         rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f);
1957         rtlefuse->tssi_13dbm = rtlefuse->eeprom_thermalmeter * 100;
1958
1959         /* Read CrystalCap from EEPROM */
1960         tempval = hwinfo[EEPROM_CRYSTALCAP] >> 4;
1961         rtlefuse->eeprom_crystalcap = tempval;
1962         /* CrystalCap, BIT(12)~15 */
1963         rtlefuse->crystalcap = rtlefuse->eeprom_crystalcap;
1964
1965         /* Read IC Version && Channel Plan */
1966         /* Version ID, Channel plan */
1967         rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN];
1968         rtlefuse->txpwr_fromeprom = true;
1969         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1970                 "EEPROM ChannelPlan = 0x%4x\n", rtlefuse->eeprom_channelplan);
1971
1972         /* Read Customer ID or Board Type!!! */
1973         tempval = hwinfo[EEPROM_BOARDTYPE];
1974         /* Change RF type definition */
1975         if (tempval == 0)
1976                 rtlphy->rf_type = RF_2T2R;
1977         else if (tempval == 1)
1978                 rtlphy->rf_type = RF_1T2R;
1979         else if (tempval == 2)
1980                 rtlphy->rf_type = RF_1T2R;
1981         else if (tempval == 3)
1982                 rtlphy->rf_type = RF_1T1R;
1983
1984         /* 1T2R but 1SS (1x1 receive combining) */
1985         rtlefuse->b1x1_recvcombine = false;
1986         if (rtlphy->rf_type == RF_1T2R) {
1987                 tempval = rtl_read_byte(rtlpriv, 0x07);
1988                 if (!(tempval & BIT(0))) {
1989                         rtlefuse->b1x1_recvcombine = true;
1990                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1991                                  "RF_TYPE=1T2R but only 1SS\n");
1992                 }
1993         }
1994         rtlefuse->b1ss_support = rtlefuse->b1x1_recvcombine;
1995         rtlefuse->eeprom_oemid = *&hwinfo[EEPROM_CUSTOMID];
1996
1997         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x",
1998                  rtlefuse->eeprom_oemid);
1999
2000         /* set channel paln to world wide 13 */
2001         rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
2002 }
2003
2004 void rtl92se_read_eeprom_info(struct ieee80211_hw *hw)
2005 {
2006         struct rtl_priv *rtlpriv = rtl_priv(hw);
2007         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2008         u8 tmp_u1b = 0;
2009
2010         tmp_u1b = rtl_read_byte(rtlpriv, EPROM_CMD);
2011
2012         if (tmp_u1b & BIT(4)) {
2013                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2014                 rtlefuse->epromtype = EEPROM_93C46;
2015         } else {
2016                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2017                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2018         }
2019
2020         if (tmp_u1b & BIT(5)) {
2021                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2022                 rtlefuse->autoload_failflag = false;
2023                 _rtl92se_read_adapter_info(hw);
2024         } else {
2025                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
2026                 rtlefuse->autoload_failflag = true;
2027         }
2028 }
2029
2030 static void rtl92se_update_hal_rate_table(struct ieee80211_hw *hw,
2031                                           struct ieee80211_sta *sta)
2032 {
2033         struct rtl_priv *rtlpriv = rtl_priv(hw);
2034         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2035         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2036         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2037         u32 ratr_value;
2038         u8 ratr_index = 0;
2039         u8 nmode = mac->ht_enable;
2040         u8 mimo_ps = IEEE80211_SMPS_OFF;
2041         u16 shortgi_rate = 0;
2042         u32 tmp_ratr_value = 0;
2043         u8 curtxbw_40mhz = mac->bw_40;
2044         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2045                                 1 : 0;
2046         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2047                                 1 : 0;
2048         enum wireless_mode wirelessmode = mac->mode;
2049
2050         if (rtlhal->current_bandtype == BAND_ON_5G)
2051                 ratr_value = sta->supp_rates[1] << 4;
2052         else
2053                 ratr_value = sta->supp_rates[0];
2054         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2055                 ratr_value = 0xfff;
2056         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2057                         sta->ht_cap.mcs.rx_mask[0] << 12);
2058         switch (wirelessmode) {
2059         case WIRELESS_MODE_B:
2060                 ratr_value &= 0x0000000D;
2061                 break;
2062         case WIRELESS_MODE_G:
2063                 ratr_value &= 0x00000FF5;
2064                 break;
2065         case WIRELESS_MODE_N_24G:
2066         case WIRELESS_MODE_N_5G:
2067                 nmode = 1;
2068                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2069                         ratr_value &= 0x0007F005;
2070                 } else {
2071                         u32 ratr_mask;
2072
2073                         if (get_rf_type(rtlphy) == RF_1T2R ||
2074                             get_rf_type(rtlphy) == RF_1T1R) {
2075                                 if (curtxbw_40mhz)
2076                                         ratr_mask = 0x000ff015;
2077                                 else
2078                                         ratr_mask = 0x000ff005;
2079                         } else {
2080                                 if (curtxbw_40mhz)
2081                                         ratr_mask = 0x0f0ff015;
2082                                 else
2083                                         ratr_mask = 0x0f0ff005;
2084                         }
2085
2086                         ratr_value &= ratr_mask;
2087                 }
2088                 break;
2089         default:
2090                 if (rtlphy->rf_type == RF_1T2R)
2091                         ratr_value &= 0x000ff0ff;
2092                 else
2093                         ratr_value &= 0x0f0ff0ff;
2094
2095                 break;
2096         }
2097
2098         if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2099                 ratr_value &= 0x0FFFFFFF;
2100         else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2101                 ratr_value &= 0x0FFFFFF0;
2102
2103         if (nmode && ((curtxbw_40mhz &&
2104                          curshortgi_40mhz) || (!curtxbw_40mhz &&
2105                                                  curshortgi_20mhz))) {
2106
2107                 ratr_value |= 0x10000000;
2108                 tmp_ratr_value = (ratr_value >> 12);
2109
2110                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2111                         if ((1 << shortgi_rate) & tmp_ratr_value)
2112                                 break;
2113                 }
2114
2115                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2116                     (shortgi_rate << 4) | (shortgi_rate);
2117
2118                 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2119         }
2120
2121         rtl_write_dword(rtlpriv, ARFR0 + ratr_index * 4, ratr_value);
2122         if (ratr_value & 0xfffff000)
2123                 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_N);
2124         else
2125                 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_BG);
2126
2127         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
2128                  rtl_read_dword(rtlpriv, ARFR0));
2129 }
2130
2131 static void rtl92se_update_hal_rate_mask(struct ieee80211_hw *hw,
2132                                          struct ieee80211_sta *sta,
2133                                          u8 rssi_level)
2134 {
2135         struct rtl_priv *rtlpriv = rtl_priv(hw);
2136         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2137         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2138         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2139         struct rtl_sta_info *sta_entry = NULL;
2140         u32 ratr_bitmap;
2141         u8 ratr_index = 0;
2142         u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
2143         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2144                                 1 : 0;
2145         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2146                                 1 : 0;
2147         enum wireless_mode wirelessmode = 0;
2148         bool shortgi = false;
2149         u32 ratr_value = 0;
2150         u8 shortgi_rate = 0;
2151         u32 mask = 0;
2152         u32 band = 0;
2153         bool bmulticast = false;
2154         u8 macid = 0;
2155         u8 mimo_ps = IEEE80211_SMPS_OFF;
2156
2157         sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2158         wirelessmode = sta_entry->wireless_mode;
2159         if (mac->opmode == NL80211_IFTYPE_STATION)
2160                 curtxbw_40mhz = mac->bw_40;
2161         else if (mac->opmode == NL80211_IFTYPE_AP ||
2162                 mac->opmode == NL80211_IFTYPE_ADHOC)
2163                 macid = sta->aid + 1;
2164
2165         if (rtlhal->current_bandtype == BAND_ON_5G)
2166                 ratr_bitmap = sta->supp_rates[1] << 4;
2167         else
2168                 ratr_bitmap = sta->supp_rates[0];
2169         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2170                 ratr_bitmap = 0xfff;
2171         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2172                         sta->ht_cap.mcs.rx_mask[0] << 12);
2173         switch (wirelessmode) {
2174         case WIRELESS_MODE_B:
2175                 band |= WIRELESS_11B;
2176                 ratr_index = RATR_INX_WIRELESS_B;
2177                 if (ratr_bitmap & 0x0000000c)
2178                         ratr_bitmap &= 0x0000000d;
2179                 else
2180                         ratr_bitmap &= 0x0000000f;
2181                 break;
2182         case WIRELESS_MODE_G:
2183                 band |= (WIRELESS_11G | WIRELESS_11B);
2184                 ratr_index = RATR_INX_WIRELESS_GB;
2185
2186                 if (rssi_level == 1)
2187                         ratr_bitmap &= 0x00000f00;
2188                 else if (rssi_level == 2)
2189                         ratr_bitmap &= 0x00000ff0;
2190                 else
2191                         ratr_bitmap &= 0x00000ff5;
2192                 break;
2193         case WIRELESS_MODE_A:
2194                 band |= WIRELESS_11A;
2195                 ratr_index = RATR_INX_WIRELESS_A;
2196                 ratr_bitmap &= 0x00000ff0;
2197                 break;
2198         case WIRELESS_MODE_N_24G:
2199         case WIRELESS_MODE_N_5G:
2200                 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2201                 ratr_index = RATR_INX_WIRELESS_NGB;
2202
2203                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2204                         if (rssi_level == 1)
2205                                 ratr_bitmap &= 0x00070000;
2206                         else if (rssi_level == 2)
2207                                 ratr_bitmap &= 0x0007f000;
2208                         else
2209                                 ratr_bitmap &= 0x0007f005;
2210                 } else {
2211                         if (rtlphy->rf_type == RF_1T2R ||
2212                                 rtlphy->rf_type == RF_1T1R) {
2213                                 if (rssi_level == 1) {
2214                                                 ratr_bitmap &= 0x000f0000;
2215                                 } else if (rssi_level == 3) {
2216                                         ratr_bitmap &= 0x000fc000;
2217                                 } else if (rssi_level == 5) {
2218                                                 ratr_bitmap &= 0x000ff000;
2219                                 } else {
2220                                         if (curtxbw_40mhz)
2221                                                 ratr_bitmap &= 0x000ff015;
2222                                         else
2223                                                 ratr_bitmap &= 0x000ff005;
2224                                 }
2225                         } else {
2226                                 if (rssi_level == 1) {
2227                                         ratr_bitmap &= 0x0f8f0000;
2228                                 } else if (rssi_level == 3) {
2229                                         ratr_bitmap &= 0x0f8fc000;
2230                                 } else if (rssi_level == 5) {
2231                                         ratr_bitmap &= 0x0f8ff000;
2232                                 } else {
2233                                         if (curtxbw_40mhz)
2234                                                 ratr_bitmap &= 0x0f8ff015;
2235                                         else
2236                                                 ratr_bitmap &= 0x0f8ff005;
2237                                 }
2238                         }
2239                 }
2240
2241                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2242                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2243                         if (macid == 0)
2244                                 shortgi = true;
2245                         else if (macid == 1)
2246                                 shortgi = false;
2247                 }
2248                 break;
2249         default:
2250                 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2251                 ratr_index = RATR_INX_WIRELESS_NGB;
2252
2253                 if (rtlphy->rf_type == RF_1T2R)
2254                         ratr_bitmap &= 0x000ff0ff;
2255                 else
2256                         ratr_bitmap &= 0x0f8ff0ff;
2257                 break;
2258         }
2259         sta_entry->ratr_index = ratr_index;
2260
2261         if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2262                 ratr_bitmap &= 0x0FFFFFFF;
2263         else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2264                 ratr_bitmap &= 0x0FFFFFF0;
2265
2266         if (shortgi) {
2267                 ratr_bitmap |= 0x10000000;
2268                 /* Get MAX MCS available. */
2269                 ratr_value = (ratr_bitmap >> 12);
2270                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2271                         if ((1 << shortgi_rate) & ratr_value)
2272                                 break;
2273                 }
2274
2275                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2276                         (shortgi_rate << 4) | (shortgi_rate);
2277                 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2278         }
2279
2280         mask |= (bmulticast ? 1 : 0) << 9 | (macid & 0x1f) << 4 | (band & 0xf);
2281
2282         RT_TRACE(rtlpriv, COMP_RATR, DBG_TRACE, "mask = %x, bitmap = %x\n",
2283                  mask, ratr_bitmap);
2284         rtl_write_dword(rtlpriv, 0x2c4, ratr_bitmap);
2285         rtl_write_dword(rtlpriv, WFM5, (FW_RA_UPDATE_MASK | (mask << 8)));
2286
2287         if (macid != 0)
2288                 sta_entry->ratr_index = ratr_index;
2289 }
2290
2291 void rtl92se_update_hal_rate_tbl(struct ieee80211_hw *hw,
2292                 struct ieee80211_sta *sta, u8 rssi_level)
2293 {
2294         struct rtl_priv *rtlpriv = rtl_priv(hw);
2295
2296         if (rtlpriv->dm.useramask)
2297                 rtl92se_update_hal_rate_mask(hw, sta, rssi_level);
2298         else
2299                 rtl92se_update_hal_rate_table(hw, sta);
2300 }
2301
2302 void rtl92se_update_channel_access_setting(struct ieee80211_hw *hw)
2303 {
2304         struct rtl_priv *rtlpriv = rtl_priv(hw);
2305         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2306         u16 sifs_timer;
2307
2308         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2309                                       &mac->slot_time);
2310         sifs_timer = 0x0e0e;
2311         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2312
2313 }
2314
2315 /* this ifunction is for RFKILL, it's different with windows,
2316  * because UI will disable wireless when GPIO Radio Off.
2317  * And here we not check or Disable/Enable ASPM like windows*/
2318 bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2319 {
2320         struct rtl_priv *rtlpriv = rtl_priv(hw);
2321         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2322         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2323         enum rf_pwrstate rfpwr_toset /*, cur_rfstate */;
2324         unsigned long flag = 0;
2325         bool actuallyset = false;
2326         bool turnonbypowerdomain = false;
2327
2328         /* just 8191se can check gpio before firstup, 92c/92d have fixed it */
2329         if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter))
2330                 return false;
2331
2332         if (ppsc->swrf_processing)
2333                 return false;
2334
2335         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2336         if (ppsc->rfchange_inprogress) {
2337                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2338                 return false;
2339         } else {
2340                 ppsc->rfchange_inprogress = true;
2341                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2342         }
2343
2344         /* cur_rfstate = ppsc->rfpwr_state;*/
2345
2346         /* because after _rtl92s_phy_set_rfhalt, all power
2347          * closed, so we must open some power for GPIO check,
2348          * or we will always check GPIO RFOFF here,
2349          * And we should close power after GPIO check */
2350         if (RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
2351                 _rtl92se_power_domain_init(hw);
2352                 turnonbypowerdomain = true;
2353         }
2354
2355         rfpwr_toset = _rtl92se_rf_onoff_detect(hw);
2356
2357         if ((ppsc->hwradiooff) && (rfpwr_toset == ERFON)) {
2358                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2359                          "RFKILL-HW Radio ON, RF ON\n");
2360
2361                 rfpwr_toset = ERFON;
2362                 ppsc->hwradiooff = false;
2363                 actuallyset = true;
2364         } else if ((!ppsc->hwradiooff) && (rfpwr_toset == ERFOFF)) {
2365                 RT_TRACE(rtlpriv, COMP_RF,
2366                          DBG_DMESG, "RFKILL-HW Radio OFF, RF OFF\n");
2367
2368                 rfpwr_toset = ERFOFF;
2369                 ppsc->hwradiooff = true;
2370                 actuallyset = true;
2371         }
2372
2373         if (actuallyset) {
2374                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2375                 ppsc->rfchange_inprogress = false;
2376                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2377
2378         /* this not include ifconfig wlan0 down case */
2379         /* } else if (rfpwr_toset == ERFOFF || cur_rfstate == ERFOFF) { */
2380         } else {
2381                 /* because power_domain_init may be happen when
2382                  * _rtl92s_phy_set_rfhalt, this will open some powers
2383                  * and cause current increasing about 40 mA for ips,
2384                  * rfoff and ifconfig down, so we set
2385                  * _rtl92s_phy_set_rfhalt again here */
2386                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC &&
2387                         turnonbypowerdomain) {
2388                         _rtl92s_phy_set_rfhalt(hw);
2389                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2390                 }
2391
2392                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2393                 ppsc->rfchange_inprogress = false;
2394                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2395         }
2396
2397         *valid = 1;
2398         return !ppsc->hwradiooff;
2399
2400 }
2401
2402 /* Is_wepkey just used for WEP used as group & pairwise key
2403  * if pairwise is AES ang group is WEP Is_wepkey == false.*/
2404 void rtl92se_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr,
2405         bool is_group, u8 enc_algo, bool is_wepkey, bool clear_all)
2406 {
2407         struct rtl_priv *rtlpriv = rtl_priv(hw);
2408         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2409         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2410         u8 *macaddr = p_macaddr;
2411
2412         u32 entry_id = 0;
2413         bool is_pairwise = false;
2414
2415         static u8 cam_const_addr[4][6] = {
2416                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2417                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2418                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2419                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2420         };
2421         static u8 cam_const_broad[] = {
2422                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2423         };
2424
2425         if (clear_all) {
2426                 u8 idx = 0;
2427                 u8 cam_offset = 0;
2428                 u8 clear_number = 5;
2429
2430                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2431
2432                 for (idx = 0; idx < clear_number; idx++) {
2433                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2434                         rtl_cam_empty_entry(hw, cam_offset + idx);
2435
2436                         if (idx < 5) {
2437                                 memset(rtlpriv->sec.key_buf[idx], 0,
2438                                        MAX_KEY_LEN);
2439                                 rtlpriv->sec.key_len[idx] = 0;
2440                         }
2441                 }
2442
2443         } else {
2444                 switch (enc_algo) {
2445                 case WEP40_ENCRYPTION:
2446                         enc_algo = CAM_WEP40;
2447                         break;
2448                 case WEP104_ENCRYPTION:
2449                         enc_algo = CAM_WEP104;
2450                         break;
2451                 case TKIP_ENCRYPTION:
2452                         enc_algo = CAM_TKIP;
2453                         break;
2454                 case AESCCMP_ENCRYPTION:
2455                         enc_algo = CAM_AES;
2456                         break;
2457                 default:
2458                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2459                                  "switch case not processed\n");
2460                         enc_algo = CAM_TKIP;
2461                         break;
2462                 }
2463
2464                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2465                         macaddr = cam_const_addr[key_index];
2466                         entry_id = key_index;
2467                 } else {
2468                         if (is_group) {
2469                                 macaddr = cam_const_broad;
2470                                 entry_id = key_index;
2471                         } else {
2472                                 if (mac->opmode == NL80211_IFTYPE_AP) {
2473                                         entry_id = rtl_cam_get_free_entry(hw,
2474                                                                  p_macaddr);
2475                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2476                                                 RT_TRACE(rtlpriv,
2477                                                          COMP_SEC, DBG_EMERG,
2478                                                          "Can not find free hw security cam entry\n");
2479                                                 return;
2480                                         }
2481                                 } else {
2482                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2483                                 }
2484
2485                                 key_index = PAIRWISE_KEYIDX;
2486                                 is_pairwise = true;
2487                         }
2488                 }
2489
2490                 if (rtlpriv->sec.key_len[key_index] == 0) {
2491                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2492                                  "delete one entry, entry_id is %d\n",
2493                                  entry_id);
2494                         if (mac->opmode == NL80211_IFTYPE_AP)
2495                                 rtl_cam_del_entry(hw, p_macaddr);
2496                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2497                 } else {
2498                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2499                                  "add one entry\n");
2500                         if (is_pairwise) {
2501                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2502                                          "set Pairwise key\n");
2503
2504                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2505                                         entry_id, enc_algo,
2506                                         CAM_CONFIG_NO_USEDK,
2507                                         rtlpriv->sec.key_buf[key_index]);
2508                         } else {
2509                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2510                                          "set group key\n");
2511
2512                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2513                                         rtl_cam_add_one_entry(hw,
2514                                                 rtlefuse->dev_addr,
2515                                                 PAIRWISE_KEYIDX,
2516                                                 CAM_PAIRWISE_KEY_POSITION,
2517                                                 enc_algo, CAM_CONFIG_NO_USEDK,
2518                                                 rtlpriv->sec.key_buf[entry_id]);
2519                                 }
2520
2521                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2522                                               entry_id, enc_algo,
2523                                               CAM_CONFIG_NO_USEDK,
2524                                               rtlpriv->sec.key_buf[entry_id]);
2525                         }
2526
2527                 }
2528         }
2529 }
2530
2531 void rtl92se_suspend(struct ieee80211_hw *hw)
2532 {
2533         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2534
2535         rtlpci->up_first_time = true;
2536 }
2537
2538 void rtl92se_resume(struct ieee80211_hw *hw)
2539 {
2540         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2541         u32 val;
2542
2543         pci_read_config_dword(rtlpci->pdev, 0x40, &val);
2544         if ((val & 0x0000ff00) != 0)
2545                 pci_write_config_dword(rtlpci->pdev, 0x40,
2546                         val & 0xffff00ff);
2547 }
2548
2549 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
2550 void rtl92se_allow_all_destaddr(struct ieee80211_hw *hw,
2551                                 bool allow_all_da, bool write_into_reg)
2552 {
2553         struct rtl_priv *rtlpriv = rtl_priv(hw);
2554         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2555
2556         if (allow_all_da) /* Set BIT0 */
2557                 rtlpci->receive_config |= RCR_AAP;
2558         else /* Clear BIT0 */
2559                 rtlpci->receive_config &= ~RCR_AAP;
2560
2561         if (write_into_reg)
2562                 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
2563
2564         RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
2565                  "receive_config=0x%08X, write_into_reg=%d\n",
2566                  rtlpci->receive_config, write_into_reg);
2567 }