drivers/net/wireless/rockchip_wlan/rtl8723cs/include/rtw_mp_phy_regdef.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 /*****************************************************************************
  21  *
  22  * Module:      __RTW_MP_PHY_REGDEF_H_
  23  *
  24  *
  25  * Note:        1. Define PMAC/BB register map
  26  *                      2. Define RF register map
  27  *                      3. PMAC/BB register bit mask.
  28  *                      4. RF reg bit mask.
  29  *                      5. Other BB/RF relative definition.
  30  *
  31  *
  32  * Export:      Constants, macro, functions(API), global variables(None).
  33  *
  34  * Abbrev:
  35  *
  36  * History:
  37  *      Data                    Who             Remark
  38  *      08/07/2007      MHC             1. Porting from 9x series PHYCFG.h.
  39  *                                              2. Reorganize code architecture.
  40  *      09/25/2008      MH              1. Add RL6052 register definition
  41  *
  42  *****************************************************************************/
  43 #ifndef __RTW_MP_PHY_REGDEF_H_
  44 #define __RTW_MP_PHY_REGDEF_H_
  45
  46
  47 /*--------------------------Define Parameters-------------------------------*/
  48
  49 /* ************************************************************
  50  * 8192S Regsiter offset definition
  51  * ************************************************************ */
  52
  53 /*
  54  * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
  55  * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
  56  * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
  57  * 3. RF register 0x00-2E
  58  * 4. Bit Mask for BB/RF register
  59  * 5. Other defintion for BB/RF R/W
  60  *   */
  61
  62
  63 /*
  64  * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
  65  * 1. Page1(0x100)
  66  *   */
  67 #define         rPMAC_Reset                                     0x100
  68 #define         rPMAC_TxStart                                   0x104
  69 #define         rPMAC_TxLegacySIG                               0x108
  70 #define         rPMAC_TxHTSIG1                          0x10c
  71 #define         rPMAC_TxHTSIG2                          0x110
  72 #define         rPMAC_PHYDebug                          0x114
  73 #define         rPMAC_TxPacketNum                               0x118
  74 #define         rPMAC_TxIdle                                    0x11c
  75 #define         rPMAC_TxMACHeader0                      0x120
  76 #define         rPMAC_TxMACHeader1                      0x124
  77 #define         rPMAC_TxMACHeader2                      0x128
  78 #define         rPMAC_TxMACHeader3                      0x12c
  79 #define         rPMAC_TxMACHeader4                      0x130
  80 #define         rPMAC_TxMACHeader5                      0x134
  81 #define         rPMAC_TxDataType                                0x138
  82 #define         rPMAC_TxRandomSeed                      0x13c
  83 #define         rPMAC_CCKPLCPPreamble                   0x140
  84 #define         rPMAC_CCKPLCPHeader                     0x144
  85 #define         rPMAC_CCKCRC16                          0x148
  86 #define         rPMAC_OFDMRxCRC32OK                     0x170
  87 #define         rPMAC_OFDMRxCRC32Er                     0x174
  88 #define         rPMAC_OFDMRxParityEr                    0x178
  89 #define         rPMAC_OFDMRxCRC8Er                      0x17c
  90 #define         rPMAC_CCKCRxRC16Er                      0x180
  91 #define         rPMAC_CCKCRxRC32Er                      0x184
  92 #define         rPMAC_CCKCRxRC32OK                      0x188
  93 #define         rPMAC_TxStatus                                  0x18c
  94
  95 /*
  96  * 2. Page2(0x200)
  97  *
  98  * The following two definition are only used for USB interface.
  99  * #define              RF_BB_CMD_ADDR                          0x02c0 */       /* RF/BB read/write command address.
 100  * #define              RF_BB_CMD_DATA                          0x02c4 */       /* RF/BB read/write command data. */
 101
 102 /*
 103  * 3. Page8(0x800)
 104  *   */
 105 #define         rFPGA0_RFMOD                            0x800   /* RF mode & CCK TxSC */ /* RF BW Setting?? */
 106
 107 #define         rFPGA0_TxInfo                           0x804   /* Status report?? */
 108 #define         rFPGA0_PSDFunction                      0x808
 109
 110 #define         rFPGA0_TxGainStage                      0x80c   /* Set TX PWR init gain? */
 111
 112 #define         rFPGA0_RFTiming1                        0x810   /* Useless now */
 113 #define         rFPGA0_RFTiming2                        0x814
 114 /* #define rFPGA0_XC_RFTiming           0x818 */
 115 /* #define rFPGA0_XD_RFTiming           0x81c */
 116
 117 #define         rFPGA0_XA_HSSIParameter1                0x820   /* RF 3 wire register */
 118 #define         rFPGA0_XA_HSSIParameter2                0x824
 119 #define         rFPGA0_XB_HSSIParameter1                0x828
 120 #define         rFPGA0_XB_HSSIParameter2                0x82c
 121 #define         rFPGA0_XC_HSSIParameter1                0x830
 122 #define         rFPGA0_XC_HSSIParameter2                0x834
 123 #define         rFPGA0_XD_HSSIParameter1                0x838
 124 #define         rFPGA0_XD_HSSIParameter2                0x83c
 125 #define         rFPGA0_XA_LSSIParameter         0x840
 126 #define         rFPGA0_XB_LSSIParameter         0x844
 127 #define         rFPGA0_XC_LSSIParameter         0x848
 128 #define         rFPGA0_XD_LSSIParameter         0x84c
 129
 130 #define         rFPGA0_RFWakeUpParameter                0x850   /* Useless now */
 131 #define         rFPGA0_RFSleepUpParameter               0x854
 132
 133 #define         rFPGA0_XAB_SwitchControl                0x858   /* RF Channel switch */
 134 #define         rFPGA0_XCD_SwitchControl                0x85c
 135
 136 #define         rFPGA0_XA_RFInterfaceOE         0x860   /* RF Channel switch */
 137 #define         rFPGA0_XB_RFInterfaceOE         0x864
 138 #define         rFPGA0_XC_RFInterfaceOE         0x868
 139 #define         rFPGA0_XD_RFInterfaceOE         0x86c
 140
 141 #define         rFPGA0_XAB_RFInterfaceSW                0x870   /* RF Interface Software Control */
 142 #define         rFPGA0_XCD_RFInterfaceSW                0x874
 143
 144 #define         rFPGA0_XAB_RFParameter          0x878   /* RF Parameter */
 145 #define         rFPGA0_XCD_RFParameter          0x87c
 146
 147 #define         rFPGA0_AnalogParameter1         0x880   /* Crystal cap setting RF-R/W protection for parameter4?? */
 148 #define         rFPGA0_AnalogParameter2         0x884
 149 #define         rFPGA0_AnalogParameter3         0x888   /* Useless now */
 150 #define         rFPGA0_AnalogParameter4         0x88c
 151
 152 #define         rFPGA0_XA_LSSIReadBack          0x8a0   /* Tranceiver LSSI Readback */
 153 #define         rFPGA0_XB_LSSIReadBack          0x8a4
 154 #define         rFPGA0_XC_LSSIReadBack          0x8a8
 155 #define         rFPGA0_XD_LSSIReadBack          0x8ac
 156
 157 #define         rFPGA0_PSDReport                                0x8b4   /* Useless now */
 158 #define         rFPGA0_XAB_RFInterfaceRB                0x8e0   /* Useless now */ /* RF Interface Readback Value */
 159 #define         rFPGA0_XCD_RFInterfaceRB                0x8e4   /* Useless now */
 160
 161 /*
 162  * 4. Page9(0x900)
 163  *   */
 164 #define         rFPGA1_RFMOD                            0x900   /* RF mode & OFDM TxSC */ /* RF BW Setting?? */
 165
 166 #define         rFPGA1_TxBlock                          0x904   /* Useless now */
 167 #define         rFPGA1_DebugSelect                      0x908   /* Useless now */
 168 #define         rFPGA1_TxInfo                           0x90c   /* Useless now */ /* Status report?? */
 169 #define rS0S1_PathSwitch                        0x948
 170
 171 /*
 172  * 5. PageA(0xA00)
 173  *
 174  * Set Control channel to upper or lower. These settings are required only for 40MHz */
 175 #define         rCCK0_System                            0xa00
 176
 177 #define         rCCK0_AFESetting                        0xa04   /* Disable init gain now */ /* Select RX path by RSSI */
 178 #define         rCCK0_CCA                                       0xa08   /* Disable init gain now */ /* Init gain */
 179
 180 #define         rCCK0_RxAGC1                            0xa0c   /* AGC default value, saturation level  */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
 181 #define         rCCK0_RxAGC2                            0xa10   /* AGC & DAGC */
 182
 183 #define         rCCK0_RxHP                                      0xa14
 184
 185 #define         rCCK0_DSPParameter1             0xa18   /* Timing recovery & Channel estimation threshold */
 186 #define         rCCK0_DSPParameter2             0xa1c   /* SQ threshold */
 187
 188 #define         rCCK0_TxFilter1                         0xa20
 189 #define         rCCK0_TxFilter2                         0xa24
 190 #define         rCCK0_DebugPort                 0xa28   /* debug port and Tx filter3 */
 191 #define         rCCK0_FalseAlarmReport          0xa2c   /* 0xa2d        useless now 0xa30-a4f channel report */
 192 #define         rCCK0_TRSSIReport               0xa50
 193 #define         rCCK0_RxReport                          0xa54  /* 0xa57 */
 194 #define         rCCK0_FACounterLower            0xa5c  /* 0xa5b */
 195 #define         rCCK0_FACounterUpper            0xa58  /* 0xa5c */
 196
 197 /*
 198  * 6. PageC(0xC00)
 199  *   */
 200 #define         rOFDM0_LSTF                             0xc00
 201
 202 #define         rOFDM0_TRxPathEnable            0xc04
 203 #define         rOFDM0_TRMuxPar                 0xc08
 204 #define         rOFDM0_TRSWIsolation            0xc0c
 205
 206 #define         rOFDM0_XARxAFE                  0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
 207 #define         rOFDM0_XARxIQImbalance          0xc14  /* RxIQ imblance matrix */
 208 #define         rOFDM0_XBRxAFE          0xc18
 209 #define         rOFDM0_XBRxIQImbalance  0xc1c
 210 #define         rOFDM0_XCRxAFE          0xc20
 211 #define         rOFDM0_XCRxIQImbalance  0xc24
 212 #define         rOFDM0_XDRxAFE          0xc28
 213 #define         rOFDM0_XDRxIQImbalance  0xc2c
 214
 215 #define         rOFDM0_RxDetector1                      0xc30  /* PD, BW & SBD   */ /* DM tune init gain */
 216 #define         rOFDM0_RxDetector2                      0xc34  /* SBD & Fame Sync. */
 217 #define         rOFDM0_RxDetector3                      0xc38  /* Frame Sync. */
 218 #define         rOFDM0_RxDetector4                      0xc3c  /* PD, SBD, Frame Sync & Short-GI */
 219
 220 #define         rOFDM0_RxDSP                            0xc40  /* Rx Sync Path */
 221 #define         rOFDM0_CFOandDAGC               0xc44  /* CFO & DAGC */
 222 #define         rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */
 223 #define         rOFDM0_ECCAThreshold            0xc4c /* energy CCA */
 224
 225 #define         rOFDM0_XAAGCCore1                       0xc50   /* DIG  */
 226 #define         rOFDM0_XAAGCCore2                       0xc54
 227 #define         rOFDM0_XBAGCCore1                       0xc58
 228 #define         rOFDM0_XBAGCCore2                       0xc5c
 229 #define         rOFDM0_XCAGCCore1                       0xc60
 230 #define         rOFDM0_XCAGCCore2                       0xc64
 231 #define         rOFDM0_XDAGCCore1                       0xc68
 232 #define         rOFDM0_XDAGCCore2                       0xc6c
 233
 234 #define         rOFDM0_AGCParameter1                    0xc70
 235 #define         rOFDM0_AGCParameter2                    0xc74
 236 #define         rOFDM0_AGCRSSITable                     0xc78
 237 #define         rOFDM0_HTSTFAGC                         0xc7c
 238
 239 #define         rOFDM0_XATxIQImbalance          0xc80   /* TX PWR TRACK and DIG */
 240 #define         rOFDM0_XATxAFE                          0xc84
 241 #define         rOFDM0_XBTxIQImbalance          0xc88
 242 #define         rOFDM0_XBTxAFE                          0xc8c
 243 #define         rOFDM0_XCTxIQImbalance          0xc90
 244 #define         rOFDM0_XCTxAFE                  0xc94
 245 #define         rOFDM0_XDTxIQImbalance          0xc98
 246 #define         rOFDM0_XDTxAFE                          0xc9c
 247 #define         rOFDM0_RxIQExtAnta                      0xca0
 248
 249 #define         rOFDM0_RxHPParameter                    0xce0
 250 #define         rOFDM0_TxPseudoNoiseWgt         0xce4
 251 #define         rOFDM0_FrameSync                                0xcf0
 252 #define         rOFDM0_DFSReport                                0xcf4
 253 #define         rOFDM0_TxCoeff1                         0xca4
 254 #define         rOFDM0_TxCoeff2                         0xca8
 255 #define         rOFDM0_TxCoeff3                         0xcac
 256 #define         rOFDM0_TxCoeff4                         0xcb0
 257 #define         rOFDM0_TxCoeff5                         0xcb4
 258 #define         rOFDM0_TxCoeff6                         0xcb8
 259
 260
 261 /*
 262  * 7. PageD(0xD00)
 263  *   */
 264 #define         rOFDM1_LSTF                                     0xd00
 265 #define         rOFDM1_TRxPathEnable                    0xd04
 266
 267 #define         rOFDM1_CFO                                              0xd08   /* No setting now */
 268 #define         rOFDM1_CSI1                                     0xd10
 269 #define         rOFDM1_SBD                                              0xd14
 270 #define         rOFDM1_CSI2                                     0xd18
 271 #define         rOFDM1_CFOTracking                      0xd2c
 272 #define         rOFDM1_TRxMesaure1                      0xd34
 273 #define         rOFDM1_IntfDet                                  0xd3c
 274 #define         rOFDM1_PseudoNoiseStateAB               0xd50
 275 #define         rOFDM1_PseudoNoiseStateCD               0xd54
 276 #define         rOFDM1_RxPseudoNoiseWgt         0xd58
 277
 278 #define         rOFDM_PHYCounter1                               0xda0  /* cca, parity fail */
 279 #define         rOFDM_PHYCounter2                               0xda4  /* rate illegal, crc8 fail */
 280 #define         rOFDM_PHYCounter3                               0xda8  /* MCS not support */
 281
 282 #define         rOFDM_ShortCFOAB                                0xdac   /* No setting now */
 283 #define         rOFDM_ShortCFOCD                                0xdb0
 284 #define         rOFDM_LongCFOAB                         0xdb4
 285 #define         rOFDM_LongCFOCD                         0xdb8
 286 #define         rOFDM_TailCFOAB                         0xdbc
 287 #define         rOFDM_TailCFOCD                         0xdc0
 288 #define         rOFDM_PWMeasure1                0xdc4
 289 #define         rOFDM_PWMeasure2                0xdc8
 290 #define         rOFDM_BWReport                          0xdcc
 291 #define         rOFDM_AGCReport                         0xdd0
 292 #define         rOFDM_RxSNR                                     0xdd4
 293 #define         rOFDM_RxEVMCSI                          0xdd8
 294 #define         rOFDM_SIGReport                         0xddc
 295
 296
 297 /*
 298  * 8. PageE(0xE00)
 299  *   */
 300 #define         rTxAGC_Rate18_06                                0xe00
 301 #define         rTxAGC_Rate54_24                                0xe04
 302 #define         rTxAGC_CCK_Mcs32                                0xe08
 303 #define         rTxAGC_Mcs03_Mcs00                      0xe10
 304 #define         rTxAGC_Mcs07_Mcs04                      0xe14
 305 #define         rTxAGC_Mcs11_Mcs08                      0xe18
 306 #define         rTxAGC_Mcs15_Mcs12                      0xe1c
 307
 308 /* Analog- control in RX_WAIT_CCA : REG: EE0 [Analog- Power & Control Register] */
 309 #define         rRx_Wait_CCCA                                   0xe70
 310 #define         rAnapar_Ctrl_BB                                 0xee0
 311
 312 /*
 313  * 7. RF Register 0x00-0x2E (RF 8256)
 314  * RF-0222D 0x00-3F
 315  *
 316  * Zebra1 */
 317 #define RTL92SE_FPGA_VERIFY 0
 318 #define         rZebra1_HSSIEnable                              0x0     /* Useless now */
 319 #define         rZebra1_TRxEnable1                              0x1
 320 #define         rZebra1_TRxEnable2                              0x2
 321 #define         rZebra1_AGC                                     0x4
 322 #define         rZebra1_ChargePump                      0x5
 323 /* #if (RTL92SE_FPGA_VERIFY == 1) */
 324 #define         rZebra1_Channel                         0x7     /* RF channel switch
 325  * #else */
 326
 327 /* #endif */
 328 #define         rZebra1_TxGain                                  0x8     /* Useless now */
 329 #define         rZebra1_TxLPF                                   0x9
 330 #define         rZebra1_RxLPF                                   0xb
 331 #define         rZebra1_RxHPFCorner                     0xc
 332
 333 /* Zebra4 */
 334 #define         rGlobalCtrl                                             0       /* Useless now */
 335 #define         rRTL8256_TxLPF                                  19
 336 #define         rRTL8256_RxLPF                                  11
 337
 338 /* RTL8258 */
 339 #define         rRTL8258_TxLPF                                  0x11    /* Useless now */
 340 #define         rRTL8258_RxLPF                                  0x13
 341 #define         rRTL8258_RSSILPF                                0xa
 342
 343 /*
 344  * RL6052 Register definition
 345  *   */
 346 #define         RF_AC                                           0x00    /*  */
 347
 348 #define         RF_IQADJ_G1                             0x01    /*  */
 349 #define         RF_IQADJ_G2                             0x02    /*  */
 350 #define         RF_POW_TRSW                             0x05    /*  */
 351
 352 #define         RF_GAIN_RX                                      0x06    /*  */
 353 #define         RF_GAIN_TX                                      0x07    /*  */
 354
 355 #define         RF_TXM_IDAC                             0x08    /*  */
 356 #define         RF_BS_IQGEN                             0x0F    /*  */
 357
 358 #define         RF_MODE1                                        0x10    /*  */
 359 #define         RF_MODE2                                        0x11    /*  */
 360
 361 #define         RF_RX_AGC_HP                            0x12    /*  */
 362 #define         RF_TX_AGC                                       0x13    /*  */
 363 #define         RF_BIAS                                         0x14    /*  */
 364 #define         RF_IPA                                          0x15    /*  */
 365 #define         RF_TXBIAS                                       0x16
 366 #define         RF_POW_ABILITY                  0x17    /*  */
 367 #define         RF_MODE_AG                              0x18    /*  */
 368 #define         rRfChannel                                      0x18    /* RF channel and BW switch */
 369 #define         RF_CHNLBW                                       0x18    /* RF channel and BW switch */
 370 #define         RF_TOP                                          0x19    /*  */
 371
 372 #define         RF_RX_G1                                        0x1A    /*  */
 373 #define         RF_RX_G2                                        0x1B    /*  */
 374
 375 #define         RF_RX_BB2                                       0x1C    /*  */
 376 #define         RF_RX_BB1                                       0x1D    /*  */
 377
 378 #define         RF_RCK1                                 0x1E    /*  */
 379 #define         RF_RCK2                                 0x1F    /*  */
 380
 381 #define         RF_TX_G1                                        0x20    /*  */
 382 #define         RF_TX_G2                                        0x21    /*  */
 383 #define         RF_TX_G3                                        0x22    /*  */
 384
 385 #define         RF_TX_BB1                                       0x23    /*  */
 386
 387 #define         RF_T_METER                                      0x24    /*  */
 388
 389 #define         RF_SYN_G1                                       0x25    /* RF TX Power control */
 390 #define         RF_SYN_G2                                       0x26    /* RF TX Power control */
 391 #define         RF_SYN_G3                                       0x27    /* RF TX Power control */
 392 #define         RF_SYN_G4                                       0x28    /* RF TX Power control */
 393 #define         RF_SYN_G5                                       0x29    /* RF TX Power control */
 394 #define         RF_SYN_G6                                       0x2A    /* RF TX Power control */
 395 #define         RF_SYN_G7                                       0x2B    /* RF TX Power control */
 396 #define         RF_SYN_G8                                       0x2C    /* RF TX Power control */
 397
 398 #define         RF_RCK_OS                                       0x30    /* RF TX PA control */
 399
 400 #define         RF_TXPA_G1                                      0x31    /* RF TX PA control */
 401 #define         RF_TXPA_G2                                      0x32    /* RF TX PA control */
 402 #define         RF_TXPA_G3                                      0x33    /* RF TX PA control */
 403
 404 /*
 405  * Bit Mask
 406  *
 407  * 1. Page1(0x100) */
 408 #define         bBBResetB                                               0x100   /* Useless now? */
 409 #define         bGlobalResetB                                   0x200
 410 #define         bOFDMTxStart                                    0x4
 411 #define         bCCKTxStart                                             0x8
 412 #define         bCRC32Debug                                     0x100
 413 #define         bPMACLoopback                                   0x10
 414 #define         bTxLSIG                                                 0xffffff
 415 #define         bOFDMTxRate                                     0xf
 416 #define         bOFDMTxReserved                         0x10
 417 #define         bOFDMTxLength                                   0x1ffe0
 418 #define         bOFDMTxParity                                   0x20000
 419 #define         bTxHTSIG1                                               0xffffff
 420 #define         bTxHTMCSRate                                    0x7f
 421 #define         bTxHTBW                                         0x80
 422 #define         bTxHTLength                                     0xffff00
 423 #define         bTxHTSIG2                                               0xffffff
 424 #define         bTxHTSmoothing                                  0x1
 425 #define         bTxHTSounding                                   0x2
 426 #define         bTxHTReserved                                   0x4
 427 #define         bTxHTAggreation                         0x8
 428 #define         bTxHTSTBC                                               0x30
 429 #define         bTxHTAdvanceCoding                      0x40
 430 #define         bTxHTShortGI                                    0x80
 431 #define         bTxHTNumberHT_LTF                       0x300
 432 #define         bTxHTCRC8                                               0x3fc00
 433 #define         bCounterReset                                   0x10000
 434 #define         bNumOfOFDMTx                                    0xffff
 435 #define         bNumOfCCKTx                                     0xffff0000
 436 #define         bTxIdleInterval                                 0xffff
 437 #define         bOFDMService                                    0xffff0000
 438 #define         bTxMACHeader                                    0xffffffff
 439 #define         bTxDataInit                                             0xff
 440 #define         bTxHTMode                                               0x100
 441 #define         bTxDataType                                     0x30000
 442 #define         bTxRandomSeed                                   0xffffffff
 443 #define         bCCKTxPreamble                                  0x1
 444 #define         bCCKTxSFD                                               0xffff0000
 445 #define         bCCKTxSIG                                               0xff
 446 #define         bCCKTxService                                   0xff00
 447 #define         bCCKLengthExt                                   0x8000
 448 #define         bCCKTxLength                                    0xffff0000
 449 #define         bCCKTxCRC16                                     0xffff
 450 #define         bCCKTxStatus                                    0x1
 451 #define         bOFDMTxStatus                                   0x2
 452
 453 #define         IS_BB_REG_OFFSET_92S(_Offset)           ((_Offset >= 0x800) && (_Offset <= 0xfff))
 454
 455 /* 2. Page8(0x800) */
 456 #define         bRFMOD                                                  0x1     /* Reg 0x800 rFPGA0_RFMOD */
 457 #define         bJapanMode                                              0x2
 458 #define         bCCKTxSC                                                0x30
 459 #define         bCCKEn                                                  0x1000000
 460 #define         bOFDMEn                                         0x2000000
 461
 462 #define         bOFDMRxADCPhase                         0x10000 /* Useless now */
 463 #define         bOFDMTxDACPhase         0x40000
 464 #define         bXATxAGC                        0x3f
 465
 466 #define         bXBTxAGC                                        0xf00   /* Reg 80c rFPGA0_TxGainStage */
 467 #define         bXCTxAGC                        0xf000
 468 #define         bXDTxAGC                        0xf0000
 469
 470 #define         bPAStart                                        0xf0000000      /* Useless now */
 471 #define         bTRStart                        0x00f00000
 472 #define         bRFStart                        0x0000f000
 473 #define         bBBStart                        0x000000f0
 474 #define         bBBCCKStart             0x0000000f
 475 #define         bPAEnd                                          0xf          /* Reg0x814 */
 476 #define         bTREnd                  0x0f000000
 477 #define         bRFEnd                  0x000f0000
 478 #define         bCCAMask                                        0x000000f0   /* T2R */
 479 #define         bR2RCCAMask             0x00000f00
 480 #define         bHSSI_R2TDelay          0xf8000000
 481 #define         bHSSI_T2RDelay          0xf80000
 482 #define         bContTxHSSI                             0x400     /* chane gain at continue Tx */
 483 #define         bIGFromCCK              0x200
 484 #define         bAGCAddress             0x3f
 485 #define         bRxHPTx                 0x7000
 486 #define         bRxHPT2R                        0x38000
 487 #define         bRxHPCCKIni             0xc0000
 488 #define         bAGCTxCode              0xc00000
 489 #define         bAGCRxCode              0x300000
 490
 491 #define         b3WireDataLength                        0x800   /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
 492 #define         b3WireAddressLength             0x400
 493
 494 #define         b3WireRFPowerDown                       0x1     /* Useless now
 495  * #define bHWSISelect          0x8 */
 496 #define         b5GPAPEPolarity         0x40000000
 497 #define         b2GPAPEPolarity         0x80000000
 498 #define         bRFSW_TxDefaultAnt              0x3
 499 #define         bRFSW_TxOptionAnt               0x30
 500 #define         bRFSW_RxDefaultAnt              0x300
 501 #define         bRFSW_RxOptionAnt               0x3000
 502 #define         bRFSI_3WireData         0x1
 503 #define         bRFSI_3WireClock                0x2
 504 #define         bRFSI_3WireLoad         0x4
 505 #define         bRFSI_3WireRW           0x8
 506 #define         bRFSI_3Wire                     0xf
 507
 508 #define         bRFSI_RFENV                             0x10    /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
 509
 510 #define         bRFSI_TRSW                              0x20    /* Useless now */
 511 #define         bRFSI_TRSWB             0x40
 512 #define         bRFSI_ANTSW             0x100
 513 #define         bRFSI_ANTSWB            0x200
 514 #define         bRFSI_PAPE                      0x400
 515 #define         bRFSI_PAPE5G            0x800
 516 #define         bBandSelect                     0x1
 517 #define         bHTSIG2_GI                      0x80
 518 #define         bHTSIG2_Smoothing               0x01
 519 #define         bHTSIG2_Sounding                0x02
 520 #define         bHTSIG2_Aggreaton               0x08
 521 #define         bHTSIG2_STBC            0x30
 522 #define         bHTSIG2_AdvCoding               0x40
 523 #define         bHTSIG2_NumOfHTLTF      0x300
 524 #define         bHTSIG2_CRC8            0x3fc
 525 #define         bHTSIG1_MCS             0x7f
 526 #define         bHTSIG1_BandWidth               0x80
 527 #define         bHTSIG1_HTLength                0xffff
 528 #define         bLSIG_Rate                      0xf
 529 #define         bLSIG_Reserved          0x10
 530 #define         bLSIG_Length            0x1fffe
 531 #define         bLSIG_Parity                    0x20
 532 #define         bCCKRxPhase             0x4
 533 #if (RTL92SE_FPGA_VERIFY == 1)
 534         #define         bLSSIReadAddress                        0x3f000000   /* LSSI "Read" Address      */ /* Reg 0x824 rFPGA0_XA_HSSIParameter2 */
 535 #else
 536         #define         bLSSIReadAddress                        0x7f800000   /* T65 RF */
 537 #endif
 538 #define         bLSSIReadEdge                           0x80000000   /* LSSI "Read" edge signal */
 539 #if (RTL92SE_FPGA_VERIFY == 1)
 540         #define         bLSSIReadBackData                       0xfff           /* Reg 0x8a0 rFPGA0_XA_LSSIReadBack */
 541 #else
 542         #define         bLSSIReadBackData                       0xfffff         /* T65 RF */
 543 #endif
 544 #define         bLSSIReadOKFlag                         0x1000  /* Useless now */
 545 #define         bCCKSampleRate                          0x8       /* 0: 44MHz, 1:88MHz                   */
 546 #define         bRegulator0Standby              0x1
 547 #define         bRegulatorPLLStandby            0x2
 548 #define         bRegulator1Standby              0x4
 549 #define         bPLLPowerUp             0x8
 550 #define         bDPLLPowerUp            0x10
 551 #define         bDA10PowerUp            0x20
 552 #define         bAD7PowerUp             0x200
 553 #define         bDA6PowerUp             0x2000
 554 #define         bXtalPowerUp            0x4000
 555 #define         b40MDClkPowerUP         0x8000
 556 #define         bDA6DebugMode           0x20000
 557 #define         bDA6Swing                       0x380000
 558
 559 #define         bADClkPhase                             0x4000000       /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
 560
 561 #define         b80MClkDelay                            0x18000000      /* Useless */
 562 #define         bAFEWatchDogEnable              0x20000000
 563
 564 #define         bXtalCap01                                      0xc0000000      /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
 565 #define         bXtalCap23                      0x3
 566 #define         bXtalCap92x                                     0x0f000000
 567 #define         bXtalCap                        0x0f000000
 568
 569 #define         bIntDifClkEnable                        0x400   /* Useless */
 570 #define         bExtSigClkEnable                0x800
 571 #define         bBandgapMbiasPowerUp    0x10000
 572 #define         bAD11SHGain             0xc0000
 573 #define         bAD11InputRange         0x700000
 574 #define         bAD11OPCurrent          0x3800000
 575 #define         bIPathLoopback          0x4000000
 576 #define         bQPathLoopback          0x8000000
 577 #define         bAFELoopback            0x10000000
 578 #define         bDA10Swing              0x7e0
 579 #define         bDA10Reverse            0x800
 580 #define         bDAClkSource            0x1000
 581 #define         bAD7InputRange          0x6000
 582 #define         bAD7Gain                        0x38000
 583 #define         bAD7OutputCMMode                0x40000
 584 #define         bAD7InputCMMode         0x380000
 585 #define         bAD7Current                     0xc00000
 586 #define         bRegulatorAdjust                0x7000000
 587 #define         bAD11PowerUpAtTx                0x1
 588 #define         bDA10PSAtTx             0x10
 589 #define         bAD11PowerUpAtRx                0x100
 590 #define         bDA10PSAtRx             0x1000
 591 #define         bCCKRxAGCFormat         0x200
 592 #define         bPSDFFTSamplepPoint             0xc000
 593 #define         bPSDAverageNum          0x3000
 594 #define         bIQPathControl          0xc00
 595 #define         bPSDFreq                        0x3ff
 596 #define         bPSDAntennaPath         0x30
 597 #define         bPSDIQSwitch            0x40
 598 #define         bPSDRxTrigger           0x400000
 599 #define         bPSDTxTrigger           0x80000000
 600 #define         bPSDSineToneScale               0x7f000000
 601 #define         bPSDReport                      0xffff
 602
 603 /* 3. Page9(0x900) */
 604 #define         bOFDMTxSC                               0x30000000      /* Useless */
 605 #define         bCCKTxOn                        0x1
 606 #define         bOFDMTxOn               0x2
 607 #define         bDebugPage                              0xfff  /* reset debug page and also HWord, LWord */
 608 #define         bDebugItem                              0xff   /* reset debug page and LWord */
 609 #define         bAntL                   0x10
 610 #define         bAntNonHT                               0x100
 611 #define         bAntHT1                 0x1000
 612 #define         bAntHT2                 0x10000
 613 #define         bAntHT1S1                       0x100000
 614 #define         bAntNonHTS1             0x1000000
 615
 616 /* 4. PageA(0xA00) */
 617 #define         bCCKBBMode                              0x3     /* Useless */
 618 #define         bCCKTxPowerSaving               0x80
 619 #define         bCCKRxPowerSaving               0x40
 620
 621 #define         bCCKSideBand                            0x10    /* Reg 0xa00 rCCK0_System 20/40 switch */
 622
 623 #define         bCCKScramble                            0x8     /* Useless */
 624 #define         bCCKAntDiversity                        0x8000
 625 #define         bCCKCarrierRecovery             0x4000
 626 #define         bCCKTxRate                      0x3000
 627 #define         bCCKDCCancel            0x0800
 628 #define         bCCKISICancel           0x0400
 629 #define         bCCKMatchFilter         0x0200
 630 #define         bCCKEqualizer           0x0100
 631 #define         bCCKPreambleDetect              0x800000
 632 #define         bCCKFastFalseCCA                0x400000
 633 #define         bCCKChEstStart          0x300000
 634 #define         bCCKCCACount            0x080000
 635 #define         bCCKcs_lim                      0x070000
 636 #define         bCCKBistMode            0x80000000
 637 #define         bCCKCCAMask             0x40000000
 638 #define         bCCKTxDACPhase          0x4
 639 #define         bCCKRxADCPhase                  0x20000000   /* r_rx_clk */
 640 #define         bCCKr_cp_mode0          0x0100
 641 #define         bCCKTxDCOffset          0xf0
 642 #define         bCCKRxDCOffset          0xf
 643 #define         bCCKCCAMode             0xc000
 644 #define         bCCKFalseCS_lim         0x3f00
 645 #define         bCCKCS_ratio            0xc00000
 646 #define         bCCKCorgBit_sel         0x300000
 647 #define         bCCKPD_lim                      0x0f0000
 648 #define         bCCKNewCCA              0x80000000
 649 #define         bCCKRxHPofIG            0x8000
 650 #define         bCCKRxIG                        0x7f00
 651 #define         bCCKLNAPolarity         0x800000
 652 #define         bCCKRx1stGain           0x7f0000
 653 #define         bCCKRFExtend                            0x20000000 /* CCK Rx Iinital gain polarity */
 654 #define         bCCKRxAGCSatLevel               0x1f000000
 655 #define         bCCKRxAGCSatCount               0xe0
 656 #define         bCCKRxRFSettle                          0x1f       /* AGCsamp_dly */
 657 #define         bCCKFixedRxAGC          0x8000
 658 /* #define bCCKRxAGCFormat              0x4000 */   /* remove to HSSI register 0x824 */
 659 #define         bCCKAntennaPolarity             0x2000
 660 #define         bCCKTxFilterType                0x0c00
 661 #define         bCCKRxAGCReportType             0x0300
 662 #define         bCCKRxDAGCEn            0x80000000
 663 #define         bCCKRxDAGCPeriod                0x20000000
 664 #define         bCCKRxDAGCSatLevel              0x1f000000
 665 #define         bCCKTimingRecovery              0x800000
 666 #define         bCCKTxC0                        0x3f0000
 667 #define         bCCKTxC1                        0x3f000000
 668 #define         bCCKTxC2                        0x3f
 669 #define         bCCKTxC3                        0x3f00
 670 #define         bCCKTxC4                        0x3f0000
 671 #define         bCCKTxC5                        0x3f000000
 672 #define         bCCKTxC6                        0x3f
 673 #define         bCCKTxC7                        0x3f00
 674 #define         bCCKDebugPort           0xff0000
 675 #define         bCCKDACDebug            0x0f000000
 676 #define         bCCKFalseAlarmEnable            0x8000
 677 #define         bCCKFalseAlarmRead              0x4000
 678 #define         bCCKTRSSI                       0x7f
 679 #define         bCCKRxAGCReport         0xfe
 680 #define         bCCKRxReport_AntSel             0x80000000
 681 #define         bCCKRxReport_MFOff              0x40000000
 682 #define         bCCKRxRxReport_SQLoss   0x20000000
 683 #define         bCCKRxReport_Pktloss            0x10000000
 684 #define         bCCKRxReport_Lockedbit  0x08000000
 685 #define         bCCKRxReport_RateError  0x04000000
 686 #define         bCCKRxReport_RxRate             0x03000000
 687 #define         bCCKRxFACounterLower    0xff
 688 #define         bCCKRxFACounterUpper    0xff000000
 689 #define         bCCKRxHPAGCStart                0xe000
 690 #define         bCCKRxHPAGCFinal                0x1c00
 691 #define         bCCKRxFalseAlarmEnable  0x8000
 692 #define         bCCKFACounterFreeze             0x4000
 693 #define         bCCKTxPathSel           0x10000000
 694 #define         bCCKDefaultRxPath               0xc000000
 695 #define         bCCKOptionRxPath                0x3000000
 696
 697 /* 5. PageC(0xC00) */
 698 #define         bNumOfSTF                                       0x3     /* Useless */
 699 #define         bShift_L                        0xc0
 700 #define         bGI_TH                  0xc
 701 #define         bRxPathA                        0x1
 702 #define         bRxPathB                        0x2
 703 #define         bRxPathC                        0x4
 704 #define         bRxPathD                        0x8
 705 #define         bTxPathA                        0x1
 706 #define         bTxPathB                        0x2
 707 #define         bTxPathC                        0x4
 708 #define         bTxPathD                        0x8
 709 #define         bTRSSIFreq                      0x200
 710 #define         bADCBackoff                     0x3000
 711 #define         bDFIRBackoff                    0xc000
 712 #define         bTRSSILatchPhase                0x10000
 713 #define         bRxIDCOffset                    0xff
 714 #define         bRxQDCOffset                    0xff00
 715 #define         bRxDFIRMode             0x1800000
 716 #define         bRxDCNFType             0xe000000
 717 #define         bRXIQImb_A                      0x3ff
 718 #define         bRXIQImb_B                      0xfc00
 719 #define         bRXIQImb_C                      0x3f0000
 720 #define         bRXIQImb_D                      0xffc00000
 721 #define         bDC_dc_Notch            0x60000
 722 #define         bRxNBINotch                     0x1f000000
 723 #define         bPD_TH                  0xf
 724 #define         bPD_TH_Opt2             0xc000
 725 #define         bPWED_TH                        0x700
 726 #define         bIfMF_Win_L                     0x800
 727 #define         bPD_Option                      0x1000
 728 #define         bMF_Win_L                       0xe000
 729 #define         bBW_Search_L            0x30000
 730 #define         bwin_enh_L                      0xc0000
 731 #define         bBW_TH                  0x700000
 732 #define         bED_TH2                 0x3800000
 733 #define         bBW_option                      0x4000000
 734 #define         bRatio_TH                       0x18000000
 735 #define         bWindow_L                       0xe0000000
 736 #define         bSBD_Option                     0x1
 737 #define         bFrame_TH                       0x1c
 738 #define         bFS_Option                      0x60
 739 #define         bDC_Slope_check         0x80
 740 #define         bFGuard_Counter_DC_L            0xe00
 741 #define         bFrame_Weight_Short             0x7000
 742 #define         bSub_Tune                       0xe00000
 743 #define         bFrame_DC_Length                0xe000000
 744 #define         bSBD_start_offset               0x30000000
 745 #define         bFrame_TH_2             0x7
 746 #define         bFrame_GI2_TH           0x38
 747 #define         bGI2_Sync_en            0x40
 748 #define         bSarch_Short_Early              0x300
 749 #define         bSarch_Short_Late               0xc00
 750 #define         bSarch_GI2_Late         0x70000
 751 #define         bCFOAntSum              0x1
 752 #define         bCFOAcc                 0x2
 753 #define         bCFOStartOffset         0xc
 754 #define         bCFOLookBack            0x70
 755 #define         bCFOSumWeight           0x80
 756 #define         bDAGCEnable                     0x10000
 757 #define         bTXIQImb_A                      0x3ff
 758 #define         bTXIQImb_B                      0xfc00
 759 #define         bTXIQImb_C                      0x3f0000
 760 #define         bTXIQImb_D                      0xffc00000
 761 #define         bTxIDCOffset                    0xff
 762 #define         bTxQDCOffset                    0xff00
 763 #define         bTxDFIRMode             0x10000
 764 #define         bTxPesudoNoiseOn                0x4000000
 765 #define         bTxPesudoNoise_A                0xff
 766 #define         bTxPesudoNoise_B                0xff00
 767 #define         bTxPesudoNoise_C                0xff0000
 768 #define         bTxPesudoNoise_D                0xff000000
 769 #define         bCCADropOption          0x20000
 770 #define         bCCADropThres           0xfff00000
 771 #define         bEDCCA_H                        0xf
 772 #define         bEDCCA_L                        0xf0
 773 #define         bLambda_ED               0x300
 774 #define         bRxInitialGain           0x7f
 775 #define         bRxAntDivEn              0x80
 776 #define         bRxAGCAddressForLNA      0x7f00
 777 #define         bRxHighPowerFlow         0x8000
 778 #define         bRxAGCFreezeThres        0xc0000
 779 #define         bRxFreezeStep_AGC1       0x300000
 780 #define         bRxFreezeStep_AGC2       0xc00000
 781 #define         bRxFreezeStep_AGC3       0x3000000
 782 #define         bRxFreezeStep_AGC0       0xc000000
 783 #define         bRxRssi_Cmp_En           0x10000000
 784 #define         bRxQuickAGCEn            0x20000000
 785 #define         bRxAGCFreezeThresMode    0x40000000
 786 #define         bRxOverFlowCheckType     0x80000000
 787 #define         bRxAGCShift              0x7f
 788 #define         bTRSW_Tri_Only           0x80
 789 #define         bPowerThres              0x300
 790 #define         bRxAGCEn                 0x1
 791 #define         bRxAGCTogetherEn         0x2
 792 #define         bRxAGCMin                0x4
 793 #define         bRxHP_Ini                0x7
 794 #define         bRxHP_TRLNA              0x70
 795 #define         bRxHP_RSSI               0x700
 796 #define         bRxHP_BBP1               0x7000
 797 #define         bRxHP_BBP2               0x70000
 798 #define         bRxHP_BBP3               0x700000
 799 #define         bRSSI_H                  0x7f0000     /* the threshold for high power */
 800 #define         bRSSI_Gen                0x7f000000   /* the threshold for ant diversity */
 801 #define         bRxSettle_TRSW           0x7
 802 #define         bRxSettle_LNA            0x38
 803 #define         bRxSettle_RSSI           0x1c0
 804 #define         bRxSettle_BBP            0xe00
 805 #define         bRxSettle_RxHP           0x7000
 806 #define         bRxSettle_AntSW_RSSI     0x38000
 807 #define         bRxSettle_AntSW          0xc0000
 808 #define         bRxProcessTime_DAGC      0x300000
 809 #define         bRxSettle_HSSI           0x400000
 810 #define         bRxProcessTime_BBPPW     0x800000
 811 #define         bRxAntennaPowerShift     0x3000000
 812 #define         bRSSITableSelect         0xc000000
 813 #define         bRxHP_Final              0x7000000
 814 #define         bRxHTSettle_BBP          0x7
 815 #define         bRxHTSettle_HSSI         0x8
 816 #define         bRxHTSettle_RxHP         0x70
 817 #define         bRxHTSettle_BBPPW        0x80
 818 #define         bRxHTSettle_Idle         0x300
 819 #define         bRxHTSettle_Reserved     0x1c00
 820 #define         bRxHTRxHPEn              0x8000
 821 #define         bRxHTAGCFreezeThres      0x30000
 822 #define         bRxHTAGCTogetherEn       0x40000
 823 #define         bRxHTAGCMin              0x80000
 824 #define         bRxHTAGCEn               0x100000
 825 #define         bRxHTDAGCEn              0x200000
 826 #define         bRxHTRxHP_BBP            0x1c00000
 827 #define         bRxHTRxHP_Final          0xe0000000
 828 #define         bRxPWRatioTH             0x3
 829 #define         bRxPWRatioEn             0x4
 830 #define         bRxMFHold                0x3800
 831 #define         bRxPD_Delay_TH1          0x38
 832 #define         bRxPD_Delay_TH2          0x1c0
 833 #define         bRxPD_DC_COUNT_MAX       0x600
 834 /* #define bRxMF_Hold               0x3800 */
 835 #define         bRxPD_Delay_TH           0x8000
 836 #define         bRxProcess_Delay         0xf0000
 837 #define         bRxSearchrange_GI2_Early 0x700000
 838 #define         bRxFrame_Guard_Counter_L 0x3800000
 839 #define         bRxSGI_Guard_L           0xc000000
 840 #define         bRxSGI_Search_L          0x30000000
 841 #define         bRxSGI_TH                0xc0000000
 842 #define         bDFSCnt0                 0xff
 843 #define         bDFSCnt1                 0xff00
 844 #define         bDFSFlag                 0xf0000
 845 #define         bMFWeightSum             0x300000
 846 #define         bMinIdxTH                0x7f000000
 847 #define         bDAFormat                0x40000
 848 #define         bTxChEmuEnable           0x01000000
 849 #define         bTRSWIsolation_A         0x7f
 850 #define         bTRSWIsolation_B         0x7f00
 851 #define         bTRSWIsolation_C         0x7f0000
 852 #define         bTRSWIsolation_D         0x7f000000
 853 #define         bExtLNAGain              0x7c00
 854
 855 /* 6. PageE(0xE00) */
 856 #define         bSTBCEn                  0x4    /* Useless */
 857 #define         bAntennaMapping          0x10
 858 #define         bNss                     0x20
 859 #define         bCFOAntSumD              0x200
 860 #define         bPHYCounterReset         0x8000000
 861 #define         bCFOReportGet            0x4000000
 862 #define         bOFDMContinueTx          0x10000000
 863 #define         bOFDMSingleCarrier       0x20000000
 864 #define         bOFDMSingleTone          0x40000000
 865 /* #define bRxPath1                 0x01 */
 866 /* #define bRxPath2                 0x02 */
 867 /* #define bRxPath3                 0x04 */
 868 /* #define bRxPath4                 0x08 */
 869 /* #define bTxPath1                 0x10 */
 870 /* #define bTxPath2                 0x20 */
 871 #define         bHTDetect                0x100
 872 #define         bCFOEn                   0x10000
 873 #define         bCFOValue                0xfff00000
 874 #define         bSigTone_Re              0x3f
 875 #define         bSigTone_Im              0x7f00
 876 #define         bCounter_CCA             0xffff
 877 #define         bCounter_ParityFail      0xffff0000
 878 #define         bCounter_RateIllegal     0xffff
 879 #define         bCounter_CRC8Fail        0xffff0000
 880 #define         bCounter_MCSNoSupport    0xffff
 881 #define         bCounter_FastSync        0xffff
 882 #define         bShortCFO                0xfff
 883 #define         bShortCFOTLength         12   /* total */
 884 #define         bShortCFOFLength         11   /* fraction */
 885 #define         bLongCFO                 0x7ff
 886 #define         bLongCFOTLength          11
 887 #define         bLongCFOFLength          11
 888 #define         bTailCFO                 0x1fff
 889 #define         bTailCFOTLength          13
 890 #define         bTailCFOFLength          12
 891 #define         bmax_en_pwdB             0xffff
 892 #define         bCC_power_dB             0xffff0000
 893 #define         bnoise_pwdB              0xffff
 894 #define         bPowerMeasTLength        10
 895 #define         bPowerMeasFLength        3
 896 #define         bRx_HT_BW                0x1
 897 #define         bRxSC                    0x6
 898 #define         bRx_HT                   0x8
 899 #define         bNB_intf_det_on          0x1
 900 #define         bIntf_win_len_cfg        0x30
 901 #define         bNB_Intf_TH_cfg          0x1c0
 902 #define         bRFGain                  0x3f
 903 #define         bTableSel                0x40
 904 #define         bTRSW                    0x80
 905 #define         bRxSNR_A                 0xff
 906 #define         bRxSNR_B                 0xff00
 907 #define         bRxSNR_C                 0xff0000
 908 #define         bRxSNR_D                 0xff000000
 909 #define         bSNREVMTLength           8
 910 #define         bSNREVMFLength           1
 911 #define         bCSI1st                  0xff
 912 #define         bCSI2nd                  0xff00
 913 #define         bRxEVM1st                0xff0000
 914 #define         bRxEVM2nd                0xff000000
 915 #define         bSIGEVM                  0xff
 916 #define         bPWDB                    0xff00
 917 #define         bSGIEN                   0x10000
 918
 919 #define         bSFactorQAM1             0xf    /* Useless */
 920 #define         bSFactorQAM2             0xf0
 921 #define         bSFactorQAM3             0xf00
 922 #define         bSFactorQAM4             0xf000
 923 #define         bSFactorQAM5             0xf0000
 924 #define         bSFactorQAM6             0xf0000
 925 #define         bSFactorQAM7             0xf00000
 926 #define         bSFactorQAM8             0xf000000
 927 #define         bSFactorQAM9             0xf0000000
 928 #define         bCSIScheme               0x100000
 929
 930 #define         bNoiseLvlTopSet          0x3    /* Useless */
 931 #define         bChSmooth                0x4
 932 #define         bChSmoothCfg1            0x38
 933 #define         bChSmoothCfg2            0x1c0
 934 #define         bChSmoothCfg3            0xe00
 935 #define         bChSmoothCfg4            0x7000
 936 #define         bMRCMode                 0x800000
 937 #define         bTHEVMCfg                0x7000000
 938
 939 #define         bLoopFitType             0x1    /* Useless */
 940 #define         bUpdCFO                  0x40
 941 #define         bUpdCFOOffData           0x80
 942 #define         bAdvUpdCFO               0x100
 943 #define         bAdvTimeCtrl             0x800
 944 #define         bUpdClko                 0x1000
 945 #define         bFC                      0x6000
 946 #define         bTrackingMode            0x8000
 947 #define         bPhCmpEnable             0x10000
 948 #define         bUpdClkoLTF              0x20000
 949 #define         bComChCFO                0x40000
 950 #define         bCSIEstiMode             0x80000
 951 #define         bAdvUpdEqz               0x100000
 952 #define         bUChCfg                  0x7000000
 953 #define         bUpdEqz                  0x8000000
 954
 955 #define         bTxAGCRate18_06                 0x7f7f7f7f      /* Useless */
 956 #define         bTxAGCRate54_24                 0x7f7f7f7f
 957 #define         bTxAGCRateMCS32                 0x7f
 958 #define         bTxAGCRateCCK                   0x7f00
 959 #define         bTxAGCRateMCS3_MCS0             0x7f7f7f7f
 960 #define         bTxAGCRateMCS7_MCS4             0x7f7f7f7f
 961 #define         bTxAGCRateMCS11_MCS8    0x7f7f7f7f
 962 #define         bTxAGCRateMCS15_MCS12   0x7f7f7f7f
 963
 964 /* Rx Pseduo noise */
 965 #define         bRxPesudoNoiseOn         0x20000000     /* Useless */
 966 #define         bRxPesudoNoise_A         0xff
 967 #define         bRxPesudoNoise_B         0xff00
 968 #define         bRxPesudoNoise_C         0xff0000
 969 #define         bRxPesudoNoise_D         0xff000000
 970 #define         bPesudoNoiseState_A      0xffff
 971 #define         bPesudoNoiseState_B      0xffff0000
 972 #define         bPesudoNoiseState_C      0xffff
 973 #define         bPesudoNoiseState_D      0xffff0000
 974
 975 /* 7. RF Register
 976  * Zebra1 */
 977 #define         bZebra1_HSSIEnable        0x8           /* Useless */
 978 #define         bZebra1_TRxControl        0xc00
 979 #define         bZebra1_TRxGainSetting    0x07f
 980 #define         bZebra1_RxCorner          0xc00
 981 #define         bZebra1_TxChargePump      0x38
 982 #define         bZebra1_RxChargePump      0x7
 983 #define         bZebra1_ChannelNum        0xf80
 984 #define         bZebra1_TxLPFBW           0x400
 985 #define         bZebra1_RxLPFBW           0x600
 986
 987 /* Zebra4 */
 988 #define         bRTL8256RegModeCtrl1      0x100 /* Useless */
 989 #define         bRTL8256RegModeCtrl0      0x40
 990 #define         bRTL8256_TxLPFBW          0x18
 991 #define         bRTL8256_RxLPFBW          0x600
 992
 993 /* RTL8258 */
 994 #define         bRTL8258_TxLPFBW          0xc   /* Useless */
 995 #define         bRTL8258_RxLPFBW          0xc00
 996 #define         bRTL8258_RSSILPFBW        0xc0
 997
 998
 999 /*
1000  * Other Definition
1001  *   */
1002
1003 /* byte endable for sb_write */
1004 #define         bByte0                    0x1   /* Useless */
1005 #define         bByte1                    0x2
1006 #define         bByte2                    0x4
1007 #define         bByte3                    0x8
1008 #define         bWord0                    0x3
1009 #define         bWord1                    0xc
1010 #define         bDWord                    0xf
1011
1012 /* for PutRegsetting & GetRegSetting BitMask */
1013 #define         bMaskByte0              0xff    /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
1014 #define         bMaskByte1              0xff00
1015 #define         bMaskByte2              0xff0000
1016 #define         bMaskByte3              0xff000000
1017 #define         bMaskHWord      0xffff0000
1018 #define         bMaskLWord              0x0000ffff
1019 #define         bMaskDWord      0xffffffff
1020 #define         bMaskH4Bits             0xf0000000
1021 #define         bMaskH3Bytes    0xffffff00
1022 #define         bMaskOFDM_D     0xffc00000
1023 #define         bMaskCCK                0x3f3f3f3f
1024 #define         bMask12Bits             0xfff
1025
1026 /* for PutRFRegsetting & GetRFRegSetting BitMask */
1027 #if (RTL92SE_FPGA_VERIFY == 1)
1028 /* #define              bMask12Bits               0xfff */      /* RF Reg mask bits */
1029 /* #define              bMask20Bits               0xfff */      /* RF Reg mask bits T65 RF */
1030 #define         bRFRegOffsetMask        0xfff
1031 #else
1032 /* #define              bMask12Bits               0xfffff */    /* RF Reg mask bits */
1033 /* #define              bMask20Bits               0xfffff */    /* RF Reg mask bits T65 RF */
1034 #define         bRFRegOffsetMask        0xfffff
1035 #endif
1036 #define         bEnable                   0x1   /* Useless */
1037 #define         bDisable                  0x0
1038
1039 #define         LeftAntenna               0x0   /* Useless */
1040 #define         RightAntenna              0x1
1041
1042 #define         tCheckTxStatus            500   /* 500ms */ /* Useless */
1043 #define         tUpdateRxCounter          100   /* 100ms */
1044
1045 #define         rateCCK     0   /* Useless */
1046 #define         rateOFDM    1
1047 #define         rateHT      2
1048
1049 /* define Register-End */
1050 #define         bPMAC_End                 0x1ff /* Useless */
1051 #define         bFPGAPHY0_End             0x8ff
1052 #define         bFPGAPHY1_End             0x9ff
1053 #define         bCCKPHY0_End              0xaff
1054 #define         bOFDMPHY0_End             0xcff
1055 #define         bOFDMPHY1_End             0xdff
1056
1057 /* define max debug item in each debug page
1058  * #define bMaxItem_FPGA_PHY0        0x9
1059  * #define bMaxItem_FPGA_PHY1        0x3
1060  * #define bMaxItem_PHY_11B          0x16
1061  * #define bMaxItem_OFDM_PHY0        0x29
1062  * #define bMaxItem_OFDM_PHY1        0x0 */
1063
1064 #define         bPMACControl    0x0             /* Useless */
1065 #define         bWMACControl    0x1
1066 #define         bWNICControl    0x2
1067
1068 #if 0
1069 #define         ANTENNA_A       0x1     /* Useless */
1070 #define         ANTENNA_B       0x2
1071 #define         ANTENNA_AB      0x3     /* ANTENNA_A | ANTENNA_B */
1072
1073 #define         ANTENNA_C       0x4
1074 #define         ANTENNA_D       0x8
1075 #endif
1076
1077 #define RCR_AAP                 BIT(0)                          /* accept all physical address */
1078 #define RCR_APM                 BIT(1)                          /* accept physical match */
1079 #define RCR_AM                  BIT(2)                          /* accept multicast */
1080 #define RCR_AB                  BIT(3)                          /* accept broadcast */
1081 #define RCR_ACRC32              BIT(5)                          /* accept error packet */
1082 #define RCR_9356SEL             BIT(6)
1083 #define RCR_AICV                BIT(9)                          /* Accept ICV error packet */
1084 #define RCR_RXFTH0              (BIT(13) | BIT(14) | BIT(15))   /* Rx FIFO threshold */
1085 #define RCR_ADF                 BIT(18)                         /* Accept Data(frame type) frame */
1086 #define RCR_ACF                 BIT(19)                         /* Accept control frame */
1087 #define RCR_AMF                 BIT(20)                         /* Accept management frame */
1088 #define RCR_ADD3                BIT(21)
1089 #define RCR_APWRMGT             BIT(22)                         /* Accept power management packet */
1090 #define RCR_CBSSID              BIT(23)                         /* Accept BSSID match packet */
1091 #define RCR_ENMARP              BIT(28)                         /* enable mac auto reset phy */
1092 #define RCR_EnCS1               BIT(29)                         /* enable carrier sense method 1 */
1093 #define RCR_EnCS2               BIT(30)                         /* enable carrier sense method 2 */
1094 #define RCR_OnlyErlPkt          BIT(31)                         /* Rx Early mode is performed for packet size greater than 1536 */
1095
1096 /*--------------------------Define Parameters-------------------------------*/
1097
1098
1099 #endif /* __INC_HAL8192SPHYREG_H */