drivers/net/wireless/rockchip_wlan/rtl8723cs/include/rtl8812a_spec.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *******************************************************************************/
  19 #ifndef __RTL8812A_SPEC_H__
  20 #define __RTL8812A_SPEC_H__
  21
  22 #include <drv_conf.h>
  23
  24
  25 /* ************************************************************
  26 * 8812 Regsiter offset definition
  27 * ************************************************************ */
  28
  29 /* ************************************************************
  30 *
  31 * ************************************************************ */
  32
  33 /* -----------------------------------------------------
  34 *
  35 *       0x0000h ~ 0x00FFh       System Configuration
  36 *
  37 * ----------------------------------------------------- */
  38 #define REG_SYS_CLKR_8812A                              0x0008
  39 #define REG_AFE_PLL_CTRL_8812A          0x0028
  40 #define REG_HSIMR_8812                                  0x0058
  41 #define REG_HSISR_8812                                  0x005c
  42 #define REG_GPIO_EXT_CTRL                               0x0060
  43 #define REG_GPIO_STATUS_8812                    0x006C
  44 #define REG_SDIO_CTRL_8812                              0x0070
  45 #define REG_OPT_CTRL_8812                               0x0074
  46 #define REG_RF_B_CTRL_8812                              0x0076
  47 #define REG_FW_DRV_MSG_8812                     0x0088
  48 #define REG_HMEBOX_E2_E3_8812                   0x008C
  49 #define REG_HIMR0_8812                                  0x00B0
  50 #define REG_HISR0_8812                                  0x00B4
  51 #define REG_HIMR1_8812                                  0x00B8
  52 #define REG_HISR1_8812                                  0x00BC
  53 #define REG_EFUSE_BURN_GNT_8812         0x00CF
  54 #define REG_SYS_CFG1_8812                               0x00FC
  55
  56 /* -----------------------------------------------------
  57 *
  58 *       0x0100h ~ 0x01FFh       MACTOP General Configuration
  59 *
  60 * ----------------------------------------------------- */
  61 #define REG_CR_8812A                                    0x100
  62 #define REG_PKTBUF_DBG_ADDR                     (REG_PKTBUF_DBG_CTRL)
  63 #define REG_RXPKTBUF_DBG                                (REG_PKTBUF_DBG_CTRL+2)
  64 #define REG_TXPKTBUF_DBG                                (REG_PKTBUF_DBG_CTRL+3)
  65 #define REG_WOWLAN_WAKE_REASON                  REG_MCUTST_WOWLAN
  66
  67 #define REG_RSVD3_8812                                  0x0168
  68 #define REG_C2HEVT_CMD_SEQ_88XX         0x01A1
  69 #define REG_C2hEVT_CMD_CONTENT_88XX     0x01A2
  70 #define REG_C2HEVT_CMD_LEN_88XX         0x01AE
  71
  72 #define REG_HMEBOX_EXT0_8812                    0x01F0
  73 #define REG_HMEBOX_EXT1_8812                    0x01F4
  74 #define REG_HMEBOX_EXT2_8812                    0x01F8
  75 #define REG_HMEBOX_EXT3_8812                    0x01FC
  76
  77 /* -----------------------------------------------------
  78 *
  79 *       0x0200h ~ 0x027Fh       TXDMA Configuration
  80 *
  81 * ----------------------------------------------------- */
  82 #define REG_DWBCN0_CTRL_8812                            REG_TDECTRL
  83 #define REG_DWBCN1_CTRL_8812                            0x0228
  84
  85 /* -----------------------------------------------------
  86 *
  87 *       0x0280h ~ 0x02FFh       RXDMA Configuration
  88 *
  89 * ----------------------------------------------------- */
  90 #define REG_TDECTRL_8812A                               0x0208
  91 #define REG_RXDMA_CONTROL_8812A         0x0286          /*Control the RX DMA.*/
  92 #define REG_RXDMA_PRO_8812                      0x0290
  93 #define REG_EARLY_MODE_CONTROL_8812     0x02BC
  94 #define REG_RSVD5_8812                                  0x02F0
  95 #define REG_RSVD6_8812                                  0x02F4
  96 #define REG_RSVD7_8812                                  0x02F8
  97 #define REG_RSVD8_8812                                  0x02FC
  98
  99
 100 /* -----------------------------------------------------
 101 *
 102 *       0x0300h ~ 0x03FFh       PCIe
 103 *
 104 * ----------------------------------------------------- */
 105 #define REG_PCIE_CTRL_REG_8812A         0x0300
 106 #define REG_DBI_WDATA_8812                      0x0348  /* DBI Write Data */
 107 #define REG_DBI_RDATA_8812                      0x034C  /* DBI Read Data */
 108 #define REG_DBI_ADDR_8812                               0x0350  /* DBI Address */
 109 #define REG_DBI_FLAG_8812                               0x0352  /* DBI Read/Write Flag */
 110 #define REG_MDIO_WDATA_8812                     0x0354  /* MDIO for Write PCIE PHY */
 111 #define REG_MDIO_RDATA_8812                     0x0356  /* MDIO for Reads PCIE PHY */
 112 #define REG_MDIO_CTL_8812                               0x0358  /* MDIO for Control */
 113 #define REG_PCIE_MULTIFET_CTRL_8812     0x036A  /* PCIE Multi-Fethc Control */
 114
 115 /* -----------------------------------------------------
 116 *
 117 *       0x0400h ~ 0x047Fh       Protocol Configuration
 118 *
 119 * ----------------------------------------------------- */
 120 #define REG_TXPKT_EMPTY_8812A                   0x041A
 121 #define REG_FWHW_TXQ_CTRL_8812A         0x0420
 122 #define REG_TXBF_CTRL_8812A                     0x042C
 123 #define REG_ARFR0_8812                                  0x0444
 124 #define REG_ARFR1_8812                                  0x044C
 125 #define REG_CCK_CHECK_8812                              0x0454
 126 #define REG_AMPDU_MAX_TIME_8812         0x0456
 127 #define REG_TXPKTBUF_BCNQ_BDNY1_8812    0x0457
 128
 129 #define REG_AMPDU_MAX_LENGTH_8812       0x0458
 130 #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8812        0x045D
 131 #define REG_NDPA_OPT_CTRL_8812A         0x045F
 132 #define REG_DATA_SC_8812                                0x0483
 133 #ifdef CONFIG_WOWLAN
 134 #define REG_TXPKTBUF_IV_LOW             0x0484
 135 #define REG_TXPKTBUF_IV_HIGH            0x0488
 136 #endif
 137 #define REG_ARFR2_8812                                  0x048C
 138 #define REG_ARFR3_8812                                  0x0494
 139 #define REG_TXRPT_START_OFFSET          0x04AC
 140 #define REG_AMPDU_BURST_MODE_8812       0x04BC
 141 #define REG_HT_SINGLE_AMPDU_8812                0x04C7
 142 #define REG_MACID_PKT_DROP0_8812                0x04D0
 143
 144 /* -----------------------------------------------------
 145 *
 146 *       0x0500h ~ 0x05FFh       EDCA Configuration
 147 *
 148 * ----------------------------------------------------- */
 149 #define REG_TXPAUSE_8812A                               0x0522
 150 #define REG_CTWND_8812                                  0x0572
 151 #define REG_SECONDARY_CCA_CTRL_8812     0x0577
 152 #define REG_SCH_TXCMD_8812A                     0x05F8
 153
 154 /* -----------------------------------------------------
 155 *
 156 *       0x0600h ~ 0x07FFh       WMAC Configuration
 157 *
 158 * ----------------------------------------------------- */
 159 #define REG_MAC_CR_8812                         0x0600
 160
 161 #define REG_MAC_TX_SM_STATE_8812                0x06B4
 162
 163 /* Power */
 164 #define REG_BFMER0_INFO_8812A                   0x06E4
 165 #define REG_BFMER1_INFO_8812A                   0x06EC
 166 #define REG_CSI_RPT_PARAM_BW20_8812A    0x06F4
 167 #define REG_CSI_RPT_PARAM_BW40_8812A    0x06F8
 168 #define REG_CSI_RPT_PARAM_BW80_8812A    0x06FC
 169
 170 /* Hardware Port 2 */
 171 #define REG_BFMEE_SEL_8812A                     0x0714
 172 #define REG_SND_PTCL_CTRL_8812A         0x0718
 173
 174
 175 /* -----------------------------------------------------
 176 *
 177 *       Redifine register definition for compatibility
 178 *
 179 * ----------------------------------------------------- */
 180
 181 /* TODO: use these definition when using REG_xxx naming rule.
 182 * NOTE: DO NOT Remove these definition. Use later. */
 183 #define ISR_8812                                                        REG_HISR0_8812
 184
 185 /* ----------------------------------------------------------------------------
 186 * 8195 IMR/ISR bits                                             (offset 0xB0,  8bits)
 187 * ---------------------------------------------------------------------------- */
 188 #define IMR_DISABLED_8812                                       0
 189 /* IMR DW0(0x00B0-00B3) Bit 0-31 */
 190 #define IMR_TIMER2_8812                                 BIT31           /* Timeout interrupt 2 */
 191 #define IMR_TIMER1_8812                                 BIT30           /* Timeout interrupt 1   */
 192 #define IMR_PSTIMEOUT_8812                              BIT29           /* Power Save Time Out Interrupt */
 193 #define IMR_GTINT4_8812                                 BIT28           /* When GTIMER4 expires, this bit is set to 1    */
 194 #define IMR_GTINT3_8812                                 BIT27           /* When GTIMER3 expires, this bit is set to 1    */
 195 #define IMR_TXBCN0ERR_8812                              BIT26           /* Transmit Beacon0 Error                        */
 196 #define IMR_TXBCN0OK_8812                                       BIT25           /* Transmit Beacon0 OK                   */
 197 #define IMR_TSF_BIT32_TOGGLE_8812               BIT24           /* TSF Timer BIT32 toggle indication interrupt                   */
 198 #define IMR_BCNDMAINT0_8812                             BIT20           /* Beacon DMA Interrupt 0                        */
 199 #define IMR_BCNDERR0_8812                                       BIT16           /* Beacon Queue DMA OK0                  */
 200 #define IMR_HSISR_IND_ON_INT_8812               BIT15           /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
 201 #define IMR_BCNDMAINT_E_8812                            BIT14           /* Beacon DMA Interrupt Extension for Win7                       */
 202 #define IMR_ATIMEND_8812                                        BIT12           /* CTWidnow End or ATIM Window End */
 203 #define IMR_C2HCMD_8812                                 BIT10           /* CPU to Host Command INT Status, Write 1 clear         */
 204 #define IMR_CPWM2_8812                                  BIT9                    /* CPU power Mode exchange INT Status, Write 1 clear     */
 205 #define IMR_CPWM_8812                                           BIT8                    /* CPU power Mode exchange INT Status, Write 1 clear     */
 206 #define IMR_HIGHDOK_8812                                        BIT7                    /* High Queue DMA OK     */
 207 #define IMR_MGNTDOK_8812                                        BIT6                    /* Management Queue DMA OK       */
 208 #define IMR_BKDOK_8812                                  BIT5                    /* AC_BK DMA OK          */
 209 #define IMR_BEDOK_8812                                  BIT4                    /* AC_BE DMA OK  */
 210 #define IMR_VIDOK_8812                                  BIT3                    /* AC_VI DMA OK          */
 211 #define IMR_VODOK_8812                                  BIT2                    /* AC_VO DMA OK  */
 212 #define IMR_RDU_8812                                            BIT1                    /* Rx Descriptor Unavailable     */
 213 #define IMR_ROK_8812                                            BIT0                    /* Receive DMA OK */
 214
 215 /* IMR DW1(0x00B4-00B7) Bit 0-31 */
 216 #define IMR_BCNDMAINT7_8812                             BIT27           /* Beacon DMA Interrupt 7 */
 217 #define IMR_BCNDMAINT6_8812                             BIT26           /* Beacon DMA Interrupt 6 */
 218 #define IMR_BCNDMAINT5_8812                             BIT25           /* Beacon DMA Interrupt 5 */
 219 #define IMR_BCNDMAINT4_8812                             BIT24           /* Beacon DMA Interrupt 4 */
 220 #define IMR_BCNDMAINT3_8812                             BIT23           /* Beacon DMA Interrupt 3 */
 221 #define IMR_BCNDMAINT2_8812                             BIT22           /* Beacon DMA Interrupt 2 */
 222 #define IMR_BCNDMAINT1_8812                             BIT21           /* Beacon DMA Interrupt 1 */
 223 #define IMR_BCNDOK7_8812                                        BIT20           /* Beacon Queue DMA OK Interrup 7 */
 224 #define IMR_BCNDOK6_8812                                        BIT19           /* Beacon Queue DMA OK Interrup 6 */
 225 #define IMR_BCNDOK5_8812                                        BIT18           /* Beacon Queue DMA OK Interrup 5 */
 226 #define IMR_BCNDOK4_8812                                        BIT17           /* Beacon Queue DMA OK Interrup 4 */
 227 #define IMR_BCNDOK3_8812                                        BIT16           /* Beacon Queue DMA OK Interrup 3 */
 228 #define IMR_BCNDOK2_8812                                        BIT15           /* Beacon Queue DMA OK Interrup 2 */
 229 #define IMR_BCNDOK1_8812                                        BIT14           /* Beacon Queue DMA OK Interrup 1 */
 230 #define IMR_ATIMEND_E_8812                              BIT13           /* ATIM Window End Extension for Win7 */
 231 #define IMR_TXERR_8812                                  BIT11           /* Tx Error Flag Interrupt Status, write 1 clear. */
 232 #define IMR_RXERR_8812                                  BIT10           /* Rx Error Flag INT Status, Write 1 clear */
 233 #define IMR_TXFOVW_8812                                 BIT9                    /* Transmit FIFO Overflow */
 234 #define IMR_RXFOVW_8812                                 BIT8                    /* Receive FIFO Overflow */
 235
 236
 237 #ifdef CONFIG_PCI_HCI
 238 /* #define IMR_RX_MASK          (IMR_ROK_8812|IMR_RDU_8812|IMR_RXFOVW_8812) */
 239 #define IMR_TX_MASK                     (IMR_VODOK_8812 | IMR_VIDOK_8812 | IMR_BEDOK_8812 | IMR_BKDOK_8812 | IMR_MGNTDOK_8812 | IMR_HIGHDOK_8812)
 240
 241 #define RT_BCN_INT_MASKS        (IMR_BCNDMAINT0_8812 | IMR_TXBCN0OK_8812 | IMR_TXBCN0ERR_8812 | IMR_BCNDERR0_8812)
 242
 243 #define RT_AC_INT_MASKS (IMR_VIDOK_8812 | IMR_VODOK_8812 | IMR_BEDOK_8812 | IMR_BKDOK_8812)
 244 #endif
 245
 246
 247 /* ****************************************************************************
 248 * Regsiter Bit and Content definition
 249 * **************************************************************************** */
 250
 251 /* 2 ACMHWCTRL 0x05C0 */
 252 #define AcmHw_HwEn_8812                         BIT(0)
 253 #define AcmHw_VoqEn_8812                                BIT(1)
 254 #define AcmHw_ViqEn_8812                                BIT(2)
 255 #define AcmHw_BeqEn_8812                                BIT(3)
 256 #define AcmHw_VoqStatus_8812                    BIT(5)
 257 #define AcmHw_ViqStatus_8812                    BIT(6)
 258 #define AcmHw_BeqStatus_8812                    BIT(7)
 259
 260 #endif /* __RTL8812A_SPEC_H__ */
 261
 262 #ifdef CONFIG_RTL8821A
 263 #include "rtl8821a_spec.h"
 264 #endif /* CONFIG_RTL8821A */