drivers/net/wireless/rockchip_wlan/rtl8723cs/include/hal_data.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #ifndef __HAL_DATA_H__
  21 #define __HAL_DATA_H__
  22
  23 #if 1/* def  CONFIG_SINGLE_IMG */
  24
  25 #include "../hal/phydm/phydm_precomp.h"
  26 #ifdef CONFIG_BT_COEXIST
  27         #include <hal_btcoex.h>
  28 #endif
  29
  30 #ifdef CONFIG_SDIO_HCI
  31         #include <hal_sdio.h>
  32 #endif
  33 #ifdef CONFIG_GSPI_HCI
  34         #include <hal_gspi.h>
  35 #endif
  36 /*
  37  * <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06.
  38  *   */
  39 typedef enum _RT_MULTI_FUNC {
  40         RT_MULTI_FUNC_NONE      = 0x00,
  41         RT_MULTI_FUNC_WIFI      = 0x01,
  42         RT_MULTI_FUNC_BT                = 0x02,
  43         RT_MULTI_FUNC_GPS       = 0x04,
  44 } RT_MULTI_FUNC, *PRT_MULTI_FUNC;
  45 /*
  46  * <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08.
  47  *   */
  48 typedef enum _RT_POLARITY_CTL {
  49         RT_POLARITY_LOW_ACT     = 0,
  50         RT_POLARITY_HIGH_ACT    = 1,
  51 } RT_POLARITY_CTL, *PRT_POLARITY_CTL;
  52
  53 /* For RTL8723 regulator mode. by tynli. 2011.01.14. */
  54 typedef enum _RT_REGULATOR_MODE {
  55         RT_SWITCHING_REGULATOR  = 0,
  56         RT_LDO_REGULATOR                        = 1,
  57 } RT_REGULATOR_MODE, *PRT_REGULATOR_MODE;
  58
  59 /*
  60  * Interface type.
  61  *   */
  62 typedef enum _INTERFACE_SELECT_PCIE {
  63         INTF_SEL0_SOLO_MINICARD                 = 0,            /* WiFi solo-mCard */
  64         INTF_SEL1_BT_COMBO_MINICARD             = 1,            /* WiFi+BT combo-mCard */
  65         INTF_SEL2_PCIe                                          = 2,            /* PCIe Card */
  66 } INTERFACE_SELECT_PCIE, *PINTERFACE_SELECT_PCIE;
  67
  68
  69 typedef enum _INTERFACE_SELECT_USB {
  70         INTF_SEL0_USB                           = 0,            /* USB */
  71         INTF_SEL1_USB_High_Power        = 1,            /* USB with high power PA */
  72         INTF_SEL2_MINICARD                      = 2,            /* Minicard */
  73         INTF_SEL3_USB_Solo              = 3,            /* USB solo-Slim module */
  74         INTF_SEL4_USB_Combo             = 4,            /* USB Combo-Slim module */
  75         INTF_SEL5_USB_Combo_MF  = 5,            /* USB WiFi+BT Multi-Function Combo, i.e., Proprietary layout(AS-VAU) which is the same as SDIO card */
  76 } INTERFACE_SELECT_USB, *PINTERFACE_SELECT_USB;
  77
  78 typedef enum _RT_AMPDU_BRUST_MODE {
  79         RT_AMPDU_BRUST_NONE             = 0,
  80         RT_AMPDU_BRUST_92D              = 1,
  81         RT_AMPDU_BRUST_88E              = 2,
  82         RT_AMPDU_BRUST_8812_4   = 3,
  83         RT_AMPDU_BRUST_8812_8   = 4,
  84         RT_AMPDU_BRUST_8812_12  = 5,
  85         RT_AMPDU_BRUST_8812_15  = 6,
  86         RT_AMPDU_BRUST_8723B            = 7,
  87 } RT_AMPDU_BRUST, *PRT_AMPDU_BRUST_MODE;
  88
  89 /* Tx Power Limit Table Size */
  90 #define MAX_REGULATION_NUM                                              4
  91 #define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE    4
  92 #define MAX_2_4G_BANDWIDTH_NUM                                  2
  93 #define MAX_RATE_SECTION_NUM                                            10
  94 #define MAX_5G_BANDWIDTH_NUM                                            4
  95
  96 #define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G                 10 /* CCK:1, OFDM:1, HT:4, VHT:4 */
  97 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G                   9 /* OFDM:1, HT:4, VHT:4 */
  98
  99
 100 /* ###### duplicate code,will move to ODM ######### */
 101 /* #define IQK_MAC_REG_NUM              4 */
 102 /* #define IQK_ADDA_REG_NUM             16 */
 103
 104 /* #define IQK_BB_REG_NUM                       10 */
 105 #define IQK_BB_REG_NUM_92C      9
 106 #define IQK_BB_REG_NUM_92D      10
 107 #define IQK_BB_REG_NUM_test     6
 108
 109 #define IQK_Matrix_Settings_NUM_92D     (1+24+21)
 110
 111 /* #define HP_THERMAL_NUM               8 */
 112 /* ###### duplicate code,will move to ODM ######### */
 113
 114 #ifdef RTW_RX_AGGREGATION
 115 typedef enum _RX_AGG_MODE {
 116         RX_AGG_DISABLE,
 117         RX_AGG_DMA,
 118         RX_AGG_USB,
 119         RX_AGG_MIX
 120 } RX_AGG_MODE;
 121
 122 /* #define MAX_RX_DMA_BUFFER_SIZE       10240 */                /* 10K for 8192C RX DMA buffer */
 123
 124 #endif /* RTW_RX_AGGREGATION */
 125
 126 /* E-Fuse */
 127 #ifdef CONFIG_RTL8188E
 128         #define EFUSE_MAP_SIZE  512
 129 #endif
 130 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)
 131         #define EFUSE_MAP_SIZE  512
 132 #endif
 133 #ifdef CONFIG_RTL8192E
 134         #define EFUSE_MAP_SIZE  512
 135 #endif
 136 #ifdef CONFIG_RTL8723B
 137         #define EFUSE_MAP_SIZE  512
 138 #endif
 139 #ifdef CONFIG_RTL8814A
 140         #define EFUSE_MAP_SIZE  512
 141 #endif
 142 #ifdef CONFIG_RTL8703B
 143         #define EFUSE_MAP_SIZE  512
 144 #endif
 145 #ifdef CONFIG_RTL8723D
 146         #define EFUSE_MAP_SIZE  512
 147 #endif
 148 #ifdef CONFIG_RTL8188F
 149         #define EFUSE_MAP_SIZE  512
 150 #endif
 151
 152 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
 153         #define EFUSE_MAX_SIZE  1024
 154 #elif defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8703B)
 155         #define EFUSE_MAX_SIZE  256
 156 #else
 157         #define EFUSE_MAX_SIZE  512
 158 #endif
 159 /* end of E-Fuse */
 160
 161 #define Mac_OFDM_OK                     0x00000000
 162 #define Mac_OFDM_Fail           0x10000000
 163 #define Mac_OFDM_FasleAlarm     0x20000000
 164 #define Mac_CCK_OK                      0x30000000
 165 #define Mac_CCK_Fail            0x40000000
 166 #define Mac_CCK_FasleAlarm      0x50000000
 167 #define Mac_HT_OK                       0x60000000
 168 #define Mac_HT_Fail                     0x70000000
 169 #define Mac_HT_FasleAlarm       0x90000000
 170 #define Mac_DropPacket          0xA0000000
 171
 172 #ifdef CONFIG_RF_POWER_TRIM
 173 #if defined(CONFIG_RTL8723B)
 174         #define REG_RF_BB_GAIN_OFFSET   0x7f
 175         #define RF_GAIN_OFFSET_MASK             0xfffff
 176 #elif defined(CONFIG_RTL8188E)
 177         #define REG_RF_BB_GAIN_OFFSET   0x55
 178         #define RF_GAIN_OFFSET_MASK             0xfffff
 179 #else
 180         #define REG_RF_BB_GAIN_OFFSET   0x55
 181         #define RF_GAIN_OFFSET_MASK             0xfffff
 182 #endif /* CONFIG_RTL8723B */
 183 #endif /*CONFIG_RF_POWER_TRIM*/
 184
 185 /* For store initial value of BB register */
 186 typedef struct _BB_INIT_REGISTER {
 187         u16     offset;
 188         u32     value;
 189
 190 } BB_INIT_REGISTER, *PBB_INIT_REGISTER;
 191
 192 #define PAGE_SIZE_128   128
 193 #define PAGE_SIZE_256   256
 194 #define PAGE_SIZE_512   512
 195
 196 #define HCI_SUS_ENTER           0
 197 #define HCI_SUS_LEAVING         1
 198 #define HCI_SUS_LEAVE           2
 199 #define HCI_SUS_ENTERING        3
 200 #define HCI_SUS_ERR                     4
 201
 202 #ifdef CONFIG_AUTO_CHNL_SEL_NHM
 203 typedef enum _ACS_OP {
 204         ACS_INIT,               /*ACS - Variable init*/
 205         ACS_RESET,              /*ACS - NHM Counter reset*/
 206         ACS_SELECT,             /*ACS - NHM Counter Statistics */
 207 } ACS_OP;
 208
 209 typedef enum _ACS_STATE {
 210         ACS_DISABLE,
 211         ACS_ENABLE,
 212 } ACS_STATE;
 213
 214 struct auto_chan_sel {
 215         ATOMIC_T state;
 216         u8      ch; /* previous channel*/
 217 };
 218 #endif /*CONFIG_AUTO_CHNL_SEL_NHM*/
 219
 220 #define EFUSE_FILE_UNUSED 0
 221 #define EFUSE_FILE_FAILED 1
 222 #define EFUSE_FILE_LOADED 2
 223
 224 #define MACADDR_FILE_UNUSED 0
 225 #define MACADDR_FILE_FAILED 1
 226 #define MACADDR_FILE_LOADED 2
 227
 228 #define KFREE_FLAG_ON                           BIT(0)
 229 #define KFREE_FLAG_THERMAL_K_ON         BIT(1)
 230
 231 #define MAX_IQK_INFO_BACKUP_CHNL_NUM    5
 232 #define MAX_IQK_INFO_BACKUP_REG_NUM             10
 233
 234 struct kfree_data_t {
 235         u8 flag;
 236         s8 bb_gain[BB_GAIN_NUM][RF_PATH_MAX];
 237
 238 #ifdef CONFIG_IEEE80211_BAND_5GHZ
 239         s8 pa_bias_5g[RF_PATH_MAX];
 240         s8 pad_bias_5g[RF_PATH_MAX];
 241 #endif
 242         s8 thermal;
 243 };
 244
 245 bool kfree_data_is_bb_gain_empty(struct kfree_data_t *data);
 246
 247 struct hal_spec_t {
 248         char *ic_name;
 249         u8 macid_num;
 250
 251         u8 sec_cam_ent_num;
 252         u8 sec_cap;
 253
 254         u8 rfpath_num_2g:4;     /* used for tx power index path */
 255         u8 rfpath_num_5g:4;     /* used for tx power index path */
 256
 257         u8 max_tx_cnt;
 258         u8 tx_nss_num:4;
 259         u8 rx_nss_num:4;
 260         u8 band_cap;    /* value of BAND_CAP_XXX */
 261         u8 bw_cap;              /* value of BW_CAP_XXX */
 262         u8 port_num;
 263         u8 proto_cap;   /* value of PROTO_CAP_XXX */
 264         u8 wl_func;             /* value of WL_FUNC_XXX */
 265         u8 hci_type;    /* value of HCI Type */
 266 };
 267
 268 #define HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) ((_spec)->rfpath_num_2g > (_path))
 269 #define HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) ((_spec)->rfpath_num_5g > (_path))
 270 #define HAL_SPEC_CHK_RF_PATH(_spec, _band, _path) ( \
 271         _band == BAND_ON_2_4G ? HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) : \
 272         _band == BAND_ON_5G ? HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) : 0)
 273
 274 #define HAL_SPEC_CHK_TX_CNT(_spec, _cnt_idx) ((_spec)->max_tx_cnt > (_cnt_idx))
 275
 276 #ifdef CONFIG_PHY_CAPABILITY_QUERY
 277 struct phy_spec_t {
 278         u32 trx_cap;
 279         u32 stbc_cap;
 280         u32 ldpc_cap;
 281         u32 txbf_param;
 282         u32 txbf_cap;
 283 };
 284 #endif
 285 struct hal_iqk_reg_backup {
 286         u8 central_chnl;
 287         u8 bw_mode;
 288         u32 reg_backup[MAX_RF_PATH][MAX_IQK_INFO_BACKUP_REG_NUM];
 289 };
 290
 291 typedef struct hal_com_data {
 292         HAL_VERSION                     version_id;
 293         RT_MULTI_FUNC           MultiFunc; /* For multi-function consideration. */
 294         RT_POLARITY_CTL         PolarityCtl; /* For Wifi PDn Polarity control. */
 295         RT_REGULATOR_MODE       RegulatorMode; /* switching regulator or LDO */
 296         u8      hw_init_completed;
 297         /****** FW related ******/
 298         u16 firmware_version;
 299         u16     FirmwareVersionRev;
 300         u16 firmware_sub_version;
 301         u16     FirmwareSignature;
 302         u8      RegFWOffload;
 303         u8      fw_ractrl;
 304         u8      FwRsvdPageStartOffset; /* 2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.*/
 305         u8      LastHMEBoxNum;  /* H2C - for host message to fw */
 306
 307         /****** current WIFI_PHY values ******/
 308         WIRELESS_MODE   CurrentWirelessMode;
 309         CHANNEL_WIDTH   current_channel_bw;
 310         BAND_TYPE               current_band_type;      /* 0:2.4G, 1:5G */
 311         BAND_TYPE               BandSet;
 312         u8                              current_channel;
 313         u8                              cch_20;
 314         u8                              cch_40;
 315         u8                              cch_80;
 316         u8                              CurrentCenterFrequencyIndex1;
 317         u8                              nCur40MhzPrimeSC;       /* Control channel sub-carrier */
 318         u8                              nCur80MhzPrimeSC;   /* used for primary 40MHz of 80MHz mode */
 319         BOOLEAN         bSwChnlAndSetBWInProgress;
 320         u8                              bDisableSWChannelPlan; /* flag of disable software change channel plan   */
 321         u16                             BasicRateSet;
 322         u32                             ReceiveConfig;
 323         u8                              rx_tsf_addr_filter_config; /* for 8822B/8821C USE */
 324         BOOLEAN                 bSwChnl;
 325         BOOLEAN                 bSetChnlBW;
 326         BOOLEAN                 bSWToBW40M;
 327         BOOLEAN                 bSWToBW80M;
 328         BOOLEAN                 bChnlBWInitialized;
 329         u32                             BackUp_BB_REG_4_2nd_CCA[3];
 330 #ifdef CONFIG_AUTO_CHNL_SEL_NHM
 331         struct auto_chan_sel acs;
 332 #endif
 333         /****** rf_ctrl *****/
 334         u8      rf_chip;
 335         u8      rf_type;
 336         u8      PackageType;
 337         u8      NumTotalRFPath;
 338         u8      antenna_test;
 339
 340         /****** Debug ******/
 341         u16     ForcedDataRate; /* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */
 342         u8      u1ForcedIgiLb;  /* forced IGI lower bound */
 343         u8      bDumpRxPkt;
 344         u8      bDumpTxPkt;
 345         u8      bDisableTXPowerTraining;
 346
 347
 348         /****** EEPROM setting.******/
 349         u8      bautoload_fail_flag;
 350         u8      efuse_file_status;
 351         u8      macaddr_file_status;
 352         u8      EepromOrEfuse;
 353         u8      efuse_eeprom_data[EEPROM_MAX_SIZE]; /*92C:256bytes, 88E:512bytes, we use union set (512bytes)*/
 354         u8      InterfaceSel; /* board type kept in eFuse */
 355         u16     CustomerID;
 356
 357         u16     EEPROMVID;
 358         u16     EEPROMSVID;
 359 #ifdef CONFIG_USB_HCI
 360         u8      EEPROMUsbSwitch;
 361         u16     EEPROMPID;
 362         u16     EEPROMSDID;
 363 #endif
 364 #ifdef CONFIG_PCI_HCI
 365         u16     EEPROMDID;
 366         u16     EEPROMSMID;
 367 #endif
 368
 369         u8      EEPROMCustomerID;
 370         u8      EEPROMSubCustomerID;
 371         u8      EEPROMVersion;
 372         u8      EEPROMRegulatory;
 373         u8      eeprom_thermal_meter;
 374         u8      EEPROMBluetoothCoexist;
 375         u8      EEPROMBluetoothType;
 376         u8      EEPROMBluetoothAntNum;
 377         u8      EEPROMBluetoothAntIsolation;
 378         u8      EEPROMBluetoothRadioShared;
 379         u8      EEPROMMACAddr[ETH_ALEN];
 380         u8      tx_bbswing_24G;
 381         u8      tx_bbswing_5G;
 382
 383 #ifdef CONFIG_RF_POWER_TRIM
 384         u8      EEPROMRFGainOffset;
 385         u8      EEPROMRFGainVal;
 386         struct kfree_data_t kfree_data;
 387 #endif /*CONFIG_RF_POWER_TRIM*/
 388
 389 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || \
 390         defined(CONFIG_RTL8723D)
 391         u8      adjuseVoltageVal;
 392         u8      need_restore;
 393 #endif
 394         u8      EfuseUsedPercentage;
 395         u16     EfuseUsedBytes;
 396         /*u8            EfuseMap[2][HWSET_MAX_SIZE_JAGUAR];*/
 397         EFUSE_HAL       EfuseHal;
 398
 399         /*---------------------------------------------------------------------------------*/
 400         /* 2.4G TX power info for target TX power*/
 401         u8      Index24G_CCK_Base[MAX_RF_PATH][CENTER_CH_2G_NUM];
 402         u8      Index24G_BW40_Base[MAX_RF_PATH][CENTER_CH_2G_NUM];
 403         s8      CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 404         s8      OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 405         s8      BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 406         s8      BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 407
 408         /* 5G TX power info for target TX power*/
 409 #ifdef CONFIG_IEEE80211_BAND_5GHZ
 410         u8      Index5G_BW40_Base[MAX_RF_PATH][CENTER_CH_5G_ALL_NUM];
 411         u8      Index5G_BW80_Base[MAX_RF_PATH][CENTER_CH_5G_80M_NUM];
 412         s8      OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 413         s8      BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 414         s8      BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 415         s8      BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 416 #endif
 417
 418         u8      Regulation2_4G;
 419         u8      Regulation5G;
 420
 421         /********************************
 422         *       TX power by rate table at most 4RF path.
 423         *       The register is
 424         *
 425         *       VHT TX power by rate off setArray =
 426         *       Band:-2G&5G = 0 / 1
 427         *       RF: at most 4*4 = ABCD=0/1/2/3
 428         *       CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11
 429         **********************************/
 430
 431         u8 txpwr_by_rate_undefined_band_path[TX_PWR_BY_RATE_NUM_BAND]
 432                 [TX_PWR_BY_RATE_NUM_RF];
 433
 434         s8      TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND]
 435                 [TX_PWR_BY_RATE_NUM_RF]
 436                 [TX_PWR_BY_RATE_NUM_RF]
 437                 [TX_PWR_BY_RATE_NUM_RATE];
 438
 439 #ifdef CONFIG_PHYDM_POWERTRACK_BY_TSSI
 440         s8      TxPwrByRate[TX_PWR_BY_RATE_NUM_BAND]
 441                 [TX_PWR_BY_RATE_NUM_RF]
 442                 [TX_PWR_BY_RATE_NUM_RF]
 443                 [TX_PWR_BY_RATE_NUM_RATE];
 444 #endif
 445         /* --------------------------------------------------------------------------------- */
 446
 447         u8 tx_pwr_lmt_5g_20_40_ref;
 448
 449         /* Power Limit Table for 2.4G */
 450         s8      TxPwrLimit_2_4G[MAX_REGULATION_NUM]
 451                 [MAX_2_4G_BANDWIDTH_NUM]
 452                 [MAX_RATE_SECTION_NUM]
 453                 [CENTER_CH_2G_NUM]
 454                 [MAX_RF_PATH];
 455
 456         /* Power Limit Table for 5G */
 457         s8      TxPwrLimit_5G[MAX_REGULATION_NUM]
 458                 [MAX_5G_BANDWIDTH_NUM]
 459                 [MAX_RATE_SECTION_NUM]
 460                 [CENTER_CH_5G_ALL_NUM]
 461                 [MAX_RF_PATH];
 462
 463
 464 #ifdef CONFIG_PHYDM_POWERTRACK_BY_TSSI
 465         s8      TxPwrLimit_2_4G_Original[MAX_REGULATION_NUM]
 466                 [MAX_2_4G_BANDWIDTH_NUM]
 467                 [MAX_RATE_SECTION_NUM]
 468                 [CENTER_CH_2G_NUM]
 469                 [MAX_RF_PATH];
 470
 471
 472         s8      TxPwrLimit_5G_Original[MAX_REGULATION_NUM]
 473                 [MAX_5G_BANDWIDTH_NUM]
 474                 [MAX_RATE_SECTION_NUM]
 475                 [CENTER_CH_5G_ALL_NUM]
 476                 [MAX_RF_PATH];
 477
 478 #endif
 479
 480         /* Store the original power by rate value of the base of each rate section of rf path A & B */
 481         u8      TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF]
 482                 [TX_PWR_BY_RATE_NUM_RF]
 483                 [MAX_BASE_NUM_IN_PHY_REG_PG_2_4G];
 484         u8      TxPwrByRateBase5G[TX_PWR_BY_RATE_NUM_RF]
 485                 [TX_PWR_BY_RATE_NUM_RF]
 486                 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
 487
 488         u8      txpwr_by_rate_loaded:1;
 489         u8      txpwr_by_rate_from_file:1;
 490         u8      txpwr_limit_loaded:1;
 491         u8      txpwr_limit_from_file:1;
 492         u8      rf_power_tracking_type;
 493
 494         /* Read/write are allow for following hardware information variables     */
 495         u8      crystal_cap;
 496
 497         u8      PAType_2G;
 498         u8      PAType_5G;
 499         u8      LNAType_2G;
 500         u8      LNAType_5G;
 501         u8      ExternalPA_2G;
 502         u8      ExternalLNA_2G;
 503         u8      external_pa_5g;
 504         u8      external_lna_5g;
 505         u16     TypeGLNA;
 506         u16     TypeGPA;
 507         u16     TypeALNA;
 508         u16     TypeAPA;
 509         u16     rfe_type;
 510
 511         u8      bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */
 512         u32     ac_param_be; /* Original parameter for BE, use for EDCA turbo.  */
 513
 514         BB_REGISTER_DEFINITION_T        PHYRegDef[MAX_RF_PATH]; /* Radio A/B/C/D */
 515
 516         u32     RfRegChnlVal[MAX_RF_PATH];
 517
 518         /* RDG enable */
 519         BOOLEAN  bRDGEnable;
 520
 521         u8      RegTxPause;
 522         /* Beacon function related global variable. */
 523         u8      RegBcnCtrlVal;
 524         u8      RegFwHwTxQCtrl;
 525         u8      RegReg542;
 526         u8      RegCR_1;
 527         u8      Reg837;
 528         u16     RegRRSR;
 529
 530         /****** antenna diversity ******/
 531         u8      AntDivCfg;
 532         u8      with_extenal_ant_switch;
 533         u8      b_fix_tx_ant;
 534         u8      AntDetection;
 535         u8      TRxAntDivType;
 536         u8      ant_path; /* for 8723B s0/s1 selection   */
 537         u32     antenna_tx_path;                                        /* Antenna path Tx */
 538         u32     AntennaRxPath;                                  /* Antenna path Rx */
 539         u8 sw_antdiv_bl_state;
 540
 541         /******** PHY DM & DM Section **********/
 542         u8                      DM_Type;
 543         _lock           IQKSpinLock;
 544         u8                      INIDATA_RATE[MACID_NUM_SW_LIMIT];
 545         /* Upper and Lower Signal threshold for Rate Adaptive*/
 546         int                     entry_min_undecorated_smoothed_pwdb;
 547         int                     entry_max_undecorated_smoothed_pwdb;
 548         int                     min_undecorated_pwdb_for_dm;
 549         struct PHY_DM_STRUCT     odmpriv;
 550         u8                      bIQKInitialized;
 551         u8                      bNeedIQK;
 552         u8              IQK_MP_Switch;
 553         /******** PHY DM & DM Section **********/
 554
 555
 556
 557         /* 2010/08/09 MH Add CU power down mode. */
 558         BOOLEAN         pwrdown;
 559
 560         /* Add for dual MAC  0--Mac0 1--Mac1 */
 561         u32     interfaceIndex;
 562
 563 #ifdef CONFIG_P2P
 564         u8      p2p_ps_offload;
 565 #endif
 566         /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */
 567         u8      bMacPwrCtrlOn;
 568         u8 hci_sus_state;
 569
 570         u8      RegIQKFWOffload;
 571         struct submit_ctx       iqk_sctx;
 572
 573         RT_AMPDU_BRUST          AMPDUBurstMode; /* 92C maybe not use, but for compile successfully */
 574
 575         u8      OutEpQueueSel;
 576         u8      OutEpNumber;
 577
 578 #ifdef RTW_RX_AGGREGATION
 579         RX_AGG_MODE rxagg_mode;
 580
 581         /* For RX Aggregation DMA Mode */
 582         u8 rxagg_dma_size;
 583         u8 rxagg_dma_timeout;
 584 #endif /* RTW_RX_AGGREGATION */
 585
 586 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
 587         /*  */
 588         /* For SDIO Interface HAL related */
 589         /*  */
 590
 591         /*  */
 592         /* SDIO ISR Related */
 593         /*
 594         *       u32                     IntrMask[1];
 595         *       u32                     IntrMaskToSet[1];
 596         *       LOG_INTERRUPT           InterruptLog; */
 597         u32                     sdio_himr;
 598         u32                     sdio_hisr;
 599 #ifndef RTW_HALMAC
 600         /*  */
 601         /* SDIO Tx FIFO related. */
 602         /*  */
 603         /* HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg */
 604         u8                      SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];
 605         _lock           SdioTxFIFOFreePageLock;
 606         u8                      SdioTxOQTMaxFreeSpace;
 607         u8                      SdioTxOQTFreeSpace;
 608 #else /* RTW_HALMAC */
 609         u16                     SdioTxOQTFreeSpace;
 610 #endif /* RTW_HALMAC */
 611
 612         /*  */
 613         /* SDIO Rx FIFO related. */
 614         /*  */
 615         u8                      SdioRxFIFOCnt;
 616         u16                     SdioRxFIFOSize;
 617
 618 #ifndef RTW_HALMAC
 619         u32                     sdio_tx_max_len[SDIO_MAX_TX_QUEUE];/* H, N, L, used for sdio tx aggregation max length per queue */
 620 #else
 621 #ifdef CONFIG_RTL8821C
 622         u16                     tx_high_page;
 623         u16                     tx_low_page;
 624         u16                     tx_normal_page;
 625         u16                     tx_extra_page;
 626         u16                     tx_pub_page;
 627         u16                     max_oqt_page;
 628         u32                     max_xmit_size_vovi;
 629         u32                     max_xmit_size_bebk;
 630 #endif
 631 #endif /* !RTW_HALMAC */
 632 #endif /* CONFIG_SDIO_HCI */
 633
 634 #ifdef CONFIG_USB_HCI
 635
 636         /* 2010/12/10 MH Add for USB aggreation mode dynamic shceme. */
 637         BOOLEAN         UsbRxHighSpeedMode;
 638         BOOLEAN         UsbTxVeryHighSpeedMode;
 639         u32                     UsbBulkOutSize;
 640         BOOLEAN         bSupportUSB3;
 641         u8                      usb_intf_start;
 642
 643         /* Interrupt relatd register information. */
 644         u32                     IntArray[3];/* HISR0,HISR1,HSISR */
 645         u32                     IntrMask[3];
 646 #ifdef CONFIG_USB_TX_AGGREGATION
 647         u8                      UsbTxAggMode;
 648         u8                      UsbTxAggDescNum;
 649 #endif /* CONFIG_USB_TX_AGGREGATION */
 650
 651 #ifdef CONFIG_USB_RX_AGGREGATION
 652         u16                     HwRxPageSize;                           /* Hardware setting */
 653
 654         /* For RX Aggregation USB Mode */
 655         u8                      rxagg_usb_size;
 656         u8                      rxagg_usb_timeout;
 657 #endif/* CONFIG_USB_RX_AGGREGATION */
 658 #endif /* CONFIG_USB_HCI */
 659
 660
 661 #ifdef CONFIG_PCI_HCI
 662         /*  */
 663         /* EEPROM setting. */
 664         /*  */
 665         u32                     TransmitConfig;
 666         u32                     IntrMaskToSet[2];
 667         u32                     IntArray[4];
 668         u32                     IntrMask[4];
 669         u32                     SysIntArray[1];
 670         u32                     SysIntrMask[1];
 671         u32                     IntrMaskReg[2];
 672         u32                     IntrMaskDefault[4];
 673
 674         BOOLEAN         bL1OffSupport;
 675         BOOLEAN bSupportBackDoor;
 676
 677         u8                      bDefaultAntenna;
 678
 679         u8                      bInterruptMigration;
 680         u8                      bDisableTxInt;
 681
 682         u16                     RxTag;
 683 #endif /* CONFIG_PCI_HCI */
 684
 685
 686 #ifdef DBG_CONFIG_ERROR_DETECT
 687         struct sreset_priv srestpriv;
 688 #endif /* #ifdef DBG_CONFIG_ERROR_DETECT */
 689
 690 #ifdef CONFIG_BT_COEXIST
 691         /* For bluetooth co-existance */
 692         BT_COEXIST              bt_coexist;
 693 #endif /* CONFIG_BT_COEXIST */
 694
 695 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) \
 696         || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8723D)
 697 #ifndef CONFIG_PCI_HCI  /* mutual exclusive with PCI -- so they're SDIO and GSPI */
 698         /* Interrupt relatd register information. */
 699         u32                     SysIntrStatus;
 700         u32                     SysIntrMask;
 701 #endif
 702 #endif /*endif CONFIG_RTL8723B  */
 703
 704 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
 705         char    para_file_buf[MAX_PARA_FILE_BUF_LEN];
 706         char *mac_reg;
 707         u32     mac_reg_len;
 708         char *bb_phy_reg;
 709         u32     bb_phy_reg_len;
 710         char *bb_agc_tab;
 711         u32     bb_agc_tab_len;
 712         char *bb_phy_reg_pg;
 713         u32     bb_phy_reg_pg_len;
 714         char *bb_phy_reg_mp;
 715         u32     bb_phy_reg_mp_len;
 716         char *rf_radio_a;
 717         u32     rf_radio_a_len;
 718         char *rf_radio_b;
 719         u32     rf_radio_b_len;
 720         char *rf_tx_pwr_track;
 721         u32     rf_tx_pwr_track_len;
 722         char *rf_tx_pwr_lmt;
 723         u32     rf_tx_pwr_lmt_len;
 724 #endif
 725
 726 #ifdef CONFIG_BACKGROUND_NOISE_MONITOR
 727         s16 noise[ODM_MAX_CHANNEL_NUM];
 728 #endif
 729
 730         struct hal_spec_t hal_spec;
 731 #ifdef CONFIG_PHY_CAPABILITY_QUERY
 732         struct phy_spec_t phy_spec;
 733 #endif
 734         u8      RfKFreeEnable;
 735         u8      RfKFree_ch_group;
 736         BOOLEAN                         bCCKinCH14;
 737         BB_INIT_REGISTER        RegForRecover[5];
 738
 739 #if defined(CONFIG_PCI_HCI) && defined(RTL8814AE_SW_BCN)
 740         BOOLEAN bCorrectBCN;
 741 #endif
 742         u32 RxGainOffset[4]; /*{2G, 5G_Low, 5G_Middle, G_High}*/
 743         u8 BackUp_IG_REG_4_Chnl_Section[4]; /*{A,B,C,D}*/
 744
 745         struct hal_iqk_reg_backup iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM];
 746
 747 #ifdef RTW_HALMAC
 748         u8 drv_rsvd_page_number;
 749 #endif
 750
 751 #ifdef CONFIG_BEAMFORMING
 752         u8 backup_snd_ptcl_ctrl;
 753 #ifdef RTW_BEAMFORMING_VERSION_2
 754         struct beamforming_info beamforming_info;
 755 #endif /* RTW_BEAMFORMING_VERSION_2 */
 756 #endif /* CONFIG_BEAMFORMING */
 757
 758         u8 not_xmitframe_fw_dl; /*not use xmitframe to download fw*/
 759 } HAL_DATA_COMMON, *PHAL_DATA_COMMON;
 760
 761
 762
 763 typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE;
 764 #define GET_HAL_DATA(__pAdapter)                        ((HAL_DATA_TYPE *)((__pAdapter)->HalData))
 765 #define GET_HAL_SPEC(__pAdapter)                        (&(GET_HAL_DATA((__pAdapter))->hal_spec))
 766 #define GET_ODM(__pAdapter)                     (&(GET_HAL_DATA((__pAdapter))->odmpriv))
 767
 768 #define GET_HAL_RFPATH_NUM(__pAdapter)          (((HAL_DATA_TYPE *)((__pAdapter)->HalData))->NumTotalRFPath)
 769 #define RT_GetInterfaceSelection(_Adapter)              (GET_HAL_DATA(_Adapter)->InterfaceSel)
 770 #define GET_RF_TYPE(__pAdapter)                         (GET_HAL_DATA(__pAdapter)->rf_type)
 771 #define GET_KFREE_DATA(_adapter) (&(GET_HAL_DATA((_adapter))->kfree_data))
 772
 773 #define SUPPORT_HW_RADIO_DETECT(Adapter)        (RT_GetInterfaceSelection(Adapter) == INTF_SEL2_MINICARD || \
 774                 RT_GetInterfaceSelection(Adapter) == INTF_SEL3_USB_Solo || \
 775                 RT_GetInterfaceSelection(Adapter) == INTF_SEL4_USB_Combo)
 776
 777 #define get_hal_mac_addr(adapter)                               (GET_HAL_DATA(adapter)->EEPROMMACAddr)
 778 #define is_boot_from_eeprom(adapter)                    (GET_HAL_DATA(adapter)->EepromOrEfuse)
 779 #define rtw_get_hw_init_completed(adapter)              (GET_HAL_DATA(adapter)->hw_init_completed)
 780 #define rtw_is_hw_init_completed(adapter)               (GET_HAL_DATA(adapter)->hw_init_completed == _TRUE)
 781 #endif
 782
 783 #ifdef CONFIG_AUTO_CHNL_SEL_NHM
 784 #define GET_ACS_STATE(padapter)                                 (ATOMIC_READ(&GET_HAL_DATA(padapter)->acs.state))
 785 #define SET_ACS_STATE(padapter, set_state)                      (ATOMIC_SET(&GET_HAL_DATA(padapter)->acs.state, set_state))
 786 #define rtw_get_acs_channel(padapter)                           (GET_HAL_DATA(padapter)->acs.ch)
 787 #define rtw_set_acs_channel(padapter, survey_ch)        (GET_HAL_DATA(padapter)->acs.ch = survey_ch)
 788 #endif /*CONFIG_AUTO_CHNL_SEL_NHM*/
 789
 790 #ifdef RTW_HALMAC
 791 int rtw_halmac_deinit_adapter(struct dvobj_priv *);
 792 #endif /* RTW_HALMAC */
 793
 794 /* alias for phydm coding style */
 795 #define REG_OFDM_0_XA_TX_IQ_IMBALANCE   rOFDM0_XATxIQImbalance
 796 #define REG_OFDM_0_ECCA_THRESHOLD               rOFDM0_ECCAThreshold
 797 #define REG_FPGA0_XB_LSSI_READ_BACK             rFPGA0_XB_LSSIReadBack
 798 #define REG_FPGA0_TX_GAIN_STAGE                 rFPGA0_TxGainStage
 799 #define REG_OFDM_0_XA_AGC_CORE1                 rOFDM0_XAAGCCore1
 800 #define REG_OFDM_0_XB_AGC_CORE1                 rOFDM0_XBAGCCore1
 801 #define REG_A_TX_SCALE_JAGUAR                   rA_TxScale_Jaguar
 802 #define REG_B_TX_SCALE_JAGUAR                   rB_TxScale_Jaguar
 803
 804 #define REG_FPGA0_XAB_RF_INTERFACE_SW   rFPGA0_XAB_RFInterfaceSW
 805 #define REG_FPGA0_XAB_RF_PARAMETER      rFPGA0_XAB_RFParameter
 806 #define REG_FPGA0_XA_HSSI_PARAMETER1    rFPGA0_XA_HSSIParameter1
 807 #define REG_FPGA0_XA_LSSI_PARAMETER     rFPGA0_XA_LSSIParameter
 808 #define REG_FPGA0_XA_RF_INTERFACE_OE    rFPGA0_XA_RFInterfaceOE
 809 #define REG_FPGA0_XB_HSSI_PARAMETER1    rFPGA0_XB_HSSIParameter1
 810 #define REG_FPGA0_XB_LSSI_PARAMETER     rFPGA0_XB_LSSIParameter
 811 #define REG_FPGA0_XB_LSSI_READ_BACK     rFPGA0_XB_LSSIReadBack
 812 #define REG_FPGA0_XB_RF_INTERFACE_OE    rFPGA0_XB_RFInterfaceOE
 813 #define REG_FPGA0_XCD_RF_INTERFACE_SW   rFPGA0_XCD_RFInterfaceSW
 814 #define REG_FPGA0_XCD_SWITCH_CONTROL    rFPGA0_XCD_SwitchControl
 815 #define REG_FPGA1_TX_BLOCK      rFPGA1_TxBlock
 816 #define REG_FPGA1_TX_INFO       rFPGA1_TxInfo
 817 #define REG_IQK_AGC_CONT        rIQK_AGC_Cont
 818 #define REG_IQK_AGC_PTS rIQK_AGC_Pts
 819 #define REG_IQK_AGC_RSP rIQK_AGC_Rsp
 820 #define REG_OFDM_0_AGC_RSSI_TABLE       rOFDM0_AGCRSSITable
 821 #define REG_OFDM_0_ECCA_THRESHOLD       rOFDM0_ECCAThreshold
 822 #define REG_OFDM_0_RX_IQ_EXT_ANTA       rOFDM0_RxIQExtAnta
 823 #define REG_OFDM_0_TR_MUX_PAR   rOFDM0_TRMuxPar
 824 #define REG_OFDM_0_TRX_PATH_ENABLE      rOFDM0_TRxPathEnable
 825 #define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1
 826 #define REG_OFDM_0_XA_RX_IQ_IMBALANCE   rOFDM0_XARxIQImbalance
 827 #define REG_OFDM_0_XA_TX_IQ_IMBALANCE   rOFDM0_XATxIQImbalance
 828 #define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1
 829 #define REG_OFDM_0_XB_RX_IQ_IMBALANCE   rOFDM0_XBRxIQImbalance
 830 #define REG_OFDM_0_XB_TX_IQ_IMBALANCE   rOFDM0_XBTxIQImbalance
 831 #define REG_OFDM_0_XC_TX_AFE    rOFDM0_XCTxAFE
 832 #define REG_OFDM_0_XD_TX_AFE    rOFDM0_XDTxAFE
 833
 834 /*#define REG_A_CFO_LONG_DUMP_92E       rA_CfoLongDump_92E*/
 835 #define REG_A_CFO_LONG_DUMP_JAGUAR      rA_CfoLongDump_Jaguar
 836 /*#define REG_A_CFO_SHORT_DUMP_92E      rA_CfoShortDump_92E*/
 837 #define REG_A_CFO_SHORT_DUMP_JAGUAR     rA_CfoShortDump_Jaguar
 838 #define REG_A_RFE_PINMUX_JAGUAR rA_RFE_Pinmux_Jaguar
 839 /*#define REG_A_RSSI_DUMP_92E   rA_RSSIDump_92E*/
 840 #define REG_A_RSSI_DUMP_JAGUAR  rA_RSSIDump_Jaguar
 841 /*#define REG_A_RX_SNR_DUMP_92E rA_RXsnrDump_92E*/
 842 #define REG_A_RX_SNR_DUMP_JAGUAR        rA_RXsnrDump_Jaguar
 843 /*#define REG_A_TX_AGC  rA_TXAGC*/
 844 #define REG_A_TX_SCALE_JAGUAR   rA_TxScale_Jaguar
 845 #define REG_BW_INDICATION_JAGUAR        rBWIndication_Jaguar
 846 /*#define REG_B_BBSWING rB_BBSWING*/
 847 /*#define REG_B_CFO_LONG_DUMP_92E       rB_CfoLongDump_92E*/
 848 #define REG_B_CFO_LONG_DUMP_JAGUAR      rB_CfoLongDump_Jaguar
 849 /*#define REG_B_CFO_SHORT_DUMP_92E      rB_CfoShortDump_92E*/
 850 #define REG_B_CFO_SHORT_DUMP_JAGUAR     rB_CfoShortDump_Jaguar
 851 /*#define REG_B_RSSI_DUMP_92E   rB_RSSIDump_92E*/
 852 #define REG_B_RSSI_DUMP_JAGUAR  rB_RSSIDump_Jaguar
 853 /*#define REG_B_RX_SNR_DUMP_92E rB_RXsnrDump_92E*/
 854 #define REG_B_RX_SNR_DUMP_JAGUAR        rB_RXsnrDump_Jaguar
 855 /*#define REG_B_TX_AGC  rB_TXAGC*/
 856 #define REG_B_TX_SCALE_JAGUAR   rB_TxScale_Jaguar
 857 #define REG_BLUE_TOOTH  rBlue_Tooth
 858 #define REG_CCK_0_AFE_SETTING   rCCK0_AFESetting
 859 /*#define REG_C_BBSWING rC_BBSWING*/
 860 /*#define REG_C_TX_AGC  rC_TXAGC*/
 861 #define REG_C_TX_SCALE_JAGUAR2  rC_TxScale_Jaguar2
 862 #define REG_CONFIG_ANT_A        rConfig_AntA
 863 #define REG_CONFIG_ANT_B        rConfig_AntB
 864 #define REG_CONFIG_PMPD_ANT_A   rConfig_Pmpd_AntA
 865 #define REG_CONFIG_PMPD_ANT_B   rConfig_Pmpd_AntB
 866 #define REG_DPDT_CONTROL        rDPDT_control
 867 /*#define REG_D_BBSWING rD_BBSWING*/
 868 /*#define REG_D_TX_AGC  rD_TXAGC*/
 869 #define REG_D_TX_SCALE_JAGUAR2  rD_TxScale_Jaguar2
 870 #define REG_FPGA0_ANALOG_PARAMETER4     rFPGA0_AnalogParameter4
 871 #define REG_FPGA0_IQK   rFPGA0_IQK
 872 #define REG_FPGA0_PSD_FUNCTION  rFPGA0_PSDFunction
 873 #define REG_FPGA0_PSD_REPORT    rFPGA0_PSDReport
 874 #define REG_FPGA0_RFMOD rFPGA0_RFMOD
 875 #define REG_FPGA0_TX_GAIN_STAGE rFPGA0_TxGainStage
 876 #define REG_FPGA0_XAB_RF_INTERFACE_SW   rFPGA0_XAB_RFInterfaceSW
 877 #define REG_FPGA0_XAB_RF_PARAMETER      rFPGA0_XAB_RFParameter
 878 #define REG_FPGA0_XA_HSSI_PARAMETER1    rFPGA0_XA_HSSIParameter1
 879 #define REG_FPGA0_XA_LSSI_PARAMETER     rFPGA0_XA_LSSIParameter
 880 #define REG_FPGA0_XA_RF_INTERFACE_OE    rFPGA0_XA_RFInterfaceOE
 881 #define REG_FPGA0_XB_HSSI_PARAMETER1    rFPGA0_XB_HSSIParameter1
 882 #define REG_FPGA0_XB_LSSI_PARAMETER     rFPGA0_XB_LSSIParameter
 883 #define REG_FPGA0_XB_LSSI_READ_BACK     rFPGA0_XB_LSSIReadBack
 884 #define REG_FPGA0_XB_RF_INTERFACE_OE    rFPGA0_XB_RFInterfaceOE
 885 #define REG_FPGA0_XCD_RF_INTERFACE_SW   rFPGA0_XCD_RFInterfaceSW
 886 #define REG_FPGA0_XCD_SWITCH_CONTROL    rFPGA0_XCD_SwitchControl
 887 #define REG_FPGA1_TX_BLOCK      rFPGA1_TxBlock
 888 #define REG_FPGA1_TX_INFO       rFPGA1_TxInfo
 889 #define REG_IQK_AGC_CONT        rIQK_AGC_Cont
 890 #define REG_IQK_AGC_PTS rIQK_AGC_Pts
 891 #define REG_IQK_AGC_RSP rIQK_AGC_Rsp
 892 #define REG_OFDM_0_AGC_RSSI_TABLE       rOFDM0_AGCRSSITable
 893 #define REG_OFDM_0_ECCA_THRESHOLD       rOFDM0_ECCAThreshold
 894 #define REG_OFDM_0_RX_IQ_EXT_ANTA       rOFDM0_RxIQExtAnta
 895 #define REG_OFDM_0_TR_MUX_PAR   rOFDM0_TRMuxPar
 896 #define REG_OFDM_0_TRX_PATH_ENABLE      rOFDM0_TRxPathEnable
 897 #define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1
 898 #define REG_OFDM_0_XA_RX_IQ_IMBALANCE   rOFDM0_XARxIQImbalance
 899 #define REG_OFDM_0_XA_TX_IQ_IMBALANCE   rOFDM0_XATxIQImbalance
 900 #define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1
 901 #define REG_OFDM_0_XB_RX_IQ_IMBALANCE   rOFDM0_XBRxIQImbalance
 902 #define REG_OFDM_0_XB_TX_IQ_IMBALANCE   rOFDM0_XBTxIQImbalance
 903 #define REG_OFDM_0_XC_TX_AFE    rOFDM0_XCTxAFE
 904 #define REG_OFDM_0_XD_TX_AFE    rOFDM0_XDTxAFE
 905 #define REG_PMPD_ANAEN  rPMPD_ANAEN
 906 #define REG_PDP_ANT_A   rPdp_AntA
 907 #define REG_PDP_ANT_A_4 rPdp_AntA_4
 908 #define REG_PDP_ANT_B   rPdp_AntB
 909 #define REG_PDP_ANT_B_4 rPdp_AntB_4
 910 #define REG_PWED_TH_JAGUAR      rPwed_TH_Jaguar
 911 #define REG_RX_CCK      rRx_CCK
 912 #define REG_RX_IQK      rRx_IQK
 913 #define REG_RX_IQK_PI_A rRx_IQK_PI_A
 914 #define REG_RX_IQK_PI_B rRx_IQK_PI_B
 915 #define REG_RX_IQK_TONE_A       rRx_IQK_Tone_A
 916 #define REG_RX_IQK_TONE_B       rRx_IQK_Tone_B
 917 #define REG_RX_OFDM     rRx_OFDM
 918 #define REG_RX_POWER_AFTER_IQK_A_2      rRx_Power_After_IQK_A_2
 919 #define REG_RX_POWER_AFTER_IQK_B_2      rRx_Power_After_IQK_B_2
 920 #define REG_RX_POWER_BEFORE_IQK_A_2     rRx_Power_Before_IQK_A_2
 921 #define REG_RX_POWER_BEFORE_IQK_B_2     rRx_Power_Before_IQK_B_2
 922 #define REG_RX_TO_RX    rRx_TO_Rx
 923 #define REG_RX_WAIT_CCA rRx_Wait_CCA
 924 #define REG_RX_WAIT_RIFS        rRx_Wait_RIFS
 925 #define REG_S0_S1_PATH_SWITCH   rS0S1_PathSwitch
 926 /*#define REG_S1_RXEVM_DUMP_92E rS1_RXevmDump_92E*/
 927 #define REG_S1_RXEVM_DUMP_JAGUAR        rS1_RXevmDump_Jaguar
 928 /*#define REG_S2_RXEVM_DUMP_92E rS2_RXevmDump_92E*/
 929 #define REG_S2_RXEVM_DUMP_JAGUAR        rS2_RXevmDump_Jaguar
 930 #define REG_SYM_WLBT_PAPE_SEL   rSYM_WLBT_PAPE_SEL
 931 #define REG_SINGLE_TONE_CONT_TX_JAGUAR  rSingleTone_ContTx_Jaguar
 932 #define REG_SLEEP       rSleep
 933 #define REG_STANDBY     rStandby
 934 #define REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR        rTxAGC_A_CCK11_CCK1_JAguar
 935 #define REG_TX_AGC_A_CCK_1_MCS32        rTxAGC_A_CCK1_Mcs32
 936 #define REG_TX_AGC_A_MCS11_MCS8_JAGUAR  rTxAGC_A_MCS11_MCS8_JAguar
 937 #define REG_TX_AGC_A_MCS15_MCS12_JAGUAR rTxAGC_A_MCS15_MCS12_JAguar
 938 #define REG_TX_AGC_A_MCS19_MCS16_JAGUAR rTxAGC_A_MCS19_MCS16_JAguar
 939 #define REG_TX_AGC_A_MCS23_MCS20_JAGUAR rTxAGC_A_MCS23_MCS20_JAguar
 940 #define REG_TX_AGC_A_MCS3_MCS0_JAGUAR   rTxAGC_A_MCS3_MCS0_JAguar
 941 #define REG_TX_AGC_A_MCS7_MCS4_JAGUAR   rTxAGC_A_MCS7_MCS4_JAguar
 942 #define REG_TX_AGC_A_MCS03_MCS00        rTxAGC_A_Mcs03_Mcs00
 943 #define REG_TX_AGC_A_MCS07_MCS04        rTxAGC_A_Mcs07_Mcs04
 944 #define REG_TX_AGC_A_MCS11_MCS08        rTxAGC_A_Mcs11_Mcs08
 945 #define REG_TX_AGC_A_MCS15_MCS12        rTxAGC_A_Mcs15_Mcs12
 946 #define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR     rTxAGC_A_Nss1Index3_Nss1Index0_JAguar
 947 #define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR     rTxAGC_A_Nss1Index7_Nss1Index4_JAguar
 948 #define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR     rTxAGC_A_Nss2Index1_Nss1Index8_JAguar
 949 #define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR     rTxAGC_A_Nss2Index5_Nss2Index2_JAguar
 950 #define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR     rTxAGC_A_Nss2Index9_Nss2Index6_JAguar
 951 #define REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR     rTxAGC_A_Nss3Index3_Nss3Index0_JAguar
 952 #define REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR     rTxAGC_A_Nss3Index7_Nss3Index4_JAguar
 953 #define REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR     rTxAGC_A_Nss3Index9_Nss3Index8_JAguar
 954 #define REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR        rTxAGC_A_Ofdm18_Ofdm6_JAguar
 955 #define REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR       rTxAGC_A_Ofdm54_Ofdm24_JAguar
 956 #define REG_TX_AGC_A_RATE18_06  rTxAGC_A_Rate18_06
 957 #define REG_TX_AGC_A_RATE54_24  rTxAGC_A_Rate54_24
 958 #define REG_TX_AGC_B_CCK_11_A_CCK_2_11  rTxAGC_B_CCK11_A_CCK2_11
 959 #define REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR        rTxAGC_B_CCK11_CCK1_JAguar
 960 #define REG_TX_AGC_B_CCK_1_55_MCS32     rTxAGC_B_CCK1_55_Mcs32
 961 #define REG_TX_AGC_B_MCS11_MCS8_JAGUAR  rTxAGC_B_MCS11_MCS8_JAguar
 962 #define REG_TX_AGC_B_MCS15_MCS12_JAGUAR rTxAGC_B_MCS15_MCS12_JAguar
 963 #define REG_TX_AGC_B_MCS19_MCS16_JAGUAR rTxAGC_B_MCS19_MCS16_JAguar
 964 #define REG_TX_AGC_B_MCS23_MCS20_JAGUAR rTxAGC_B_MCS23_MCS20_JAguar
 965 #define REG_TX_AGC_B_MCS3_MCS0_JAGUAR   rTxAGC_B_MCS3_MCS0_JAguar
 966 #define REG_TX_AGC_B_MCS7_MCS4_JAGUAR   rTxAGC_B_MCS7_MCS4_JAguar
 967 #define REG_TX_AGC_B_MCS03_MCS00        rTxAGC_B_Mcs03_Mcs00
 968 #define REG_TX_AGC_B_MCS07_MCS04        rTxAGC_B_Mcs07_Mcs04
 969 #define REG_TX_AGC_B_MCS11_MCS08        rTxAGC_B_Mcs11_Mcs08
 970 #define REG_TX_AGC_B_MCS15_MCS12        rTxAGC_B_Mcs15_Mcs12
 971 #define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR     rTxAGC_B_Nss1Index3_Nss1Index0_JAguar
 972 #define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR     rTxAGC_B_Nss1Index7_Nss1Index4_JAguar
 973 #define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR     rTxAGC_B_Nss2Index1_Nss1Index8_JAguar
 974 #define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR     rTxAGC_B_Nss2Index5_Nss2Index2_JAguar
 975 #define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR     rTxAGC_B_Nss2Index9_Nss2Index6_JAguar
 976 #define REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR     rTxAGC_B_Nss3Index3_Nss3Index0_JAguar
 977 #define REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR     rTxAGC_B_Nss3Index7_Nss3Index4_JAguar
 978 #define REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR     rTxAGC_B_Nss3Index9_Nss3Index8_JAguar
 979 #define REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR        rTxAGC_B_Ofdm18_Ofdm6_JAguar
 980 #define REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR       rTxAGC_B_Ofdm54_Ofdm24_JAguar
 981 #define REG_TX_AGC_B_RATE18_06  rTxAGC_B_Rate18_06
 982 #define REG_TX_AGC_B_RATE54_24  rTxAGC_B_Rate54_24
 983 #define REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR        rTxAGC_C_CCK11_CCK1_JAguar
 984 #define REG_TX_AGC_C_MCS11_MCS8_JAGUAR  rTxAGC_C_MCS11_MCS8_JAguar
 985 #define REG_TX_AGC_C_MCS15_MCS12_JAGUAR rTxAGC_C_MCS15_MCS12_JAguar
 986 #define REG_TX_AGC_C_MCS19_MCS16_JAGUAR rTxAGC_C_MCS19_MCS16_JAguar
 987 #define REG_TX_AGC_C_MCS23_MCS20_JAGUAR rTxAGC_C_MCS23_MCS20_JAguar
 988 #define REG_TX_AGC_C_MCS3_MCS0_JAGUAR   rTxAGC_C_MCS3_MCS0_JAguar
 989 #define REG_TX_AGC_C_MCS7_MCS4_JAGUAR   rTxAGC_C_MCS7_MCS4_JAguar
 990 #define REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR     rTxAGC_C_Nss1Index3_Nss1Index0_JAguar
 991 #define REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR     rTxAGC_C_Nss1Index7_Nss1Index4_JAguar
 992 #define REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR     rTxAGC_C_Nss2Index1_Nss1Index8_JAguar
 993 #define REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR     rTxAGC_C_Nss2Index5_Nss2Index2_JAguar
 994 #define REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR     rTxAGC_C_Nss2Index9_Nss2Index6_JAguar
 995 #define REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR     rTxAGC_C_Nss3Index3_Nss3Index0_JAguar
 996 #define REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR     rTxAGC_C_Nss3Index7_Nss3Index4_JAguar
 997 #define REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR     rTxAGC_C_Nss3Index9_Nss3Index8_JAguar
 998 #define REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR        rTxAGC_C_Ofdm18_Ofdm6_JAguar
 999 #define REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR       rTxAGC_C_Ofdm54_Ofdm24_JAguar
1000 #define REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR        rTxAGC_D_CCK11_CCK1_JAguar
1001 #define REG_TX_AGC_D_MCS11_MCS8_JAGUAR  rTxAGC_D_MCS11_MCS8_JAguar
1002 #define REG_TX_AGC_D_MCS15_MCS12_JAGUAR rTxAGC_D_MCS15_MCS12_JAguar
1003 #define REG_TX_AGC_D_MCS19_MCS16_JAGUAR rTxAGC_D_MCS19_MCS16_JAguar
1004 #define REG_TX_AGC_D_MCS23_MCS20_JAGUAR rTxAGC_D_MCS23_MCS20_JAguar
1005 #define REG_TX_AGC_D_MCS3_MCS0_JAGUAR   rTxAGC_D_MCS3_MCS0_JAguar
1006 #define REG_TX_AGC_D_MCS7_MCS4_JAGUAR   rTxAGC_D_MCS7_MCS4_JAguar
1007 #define REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR     rTxAGC_D_Nss1Index3_Nss1Index0_JAguar
1008 #define REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR     rTxAGC_D_Nss1Index7_Nss1Index4_JAguar
1009 #define REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR     rTxAGC_D_Nss2Index1_Nss1Index8_JAguar
1010 #define REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR     rTxAGC_D_Nss2Index5_Nss2Index2_JAguar
1011 #define REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR     rTxAGC_D_Nss2Index9_Nss2Index6_JAguar
1012 #define REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR     rTxAGC_D_Nss3Index3_Nss3Index0_JAguar
1013 #define REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR     rTxAGC_D_Nss3Index7_Nss3Index4_JAguar
1014 #define REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR     rTxAGC_D_Nss3Index9_Nss3Index8_JAguar
1015 #define REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR        rTxAGC_D_Ofdm18_Ofdm6_JAguar
1016 #define REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR       rTxAGC_D_Ofdm54_Ofdm24_JAguar
1017 #define REG_TX_PATH_JAGUAR      rTxPath_Jaguar
1018 #define REG_TX_CCK_BBON rTx_CCK_BBON
1019 #define REG_TX_CCK_RFON rTx_CCK_RFON
1020 #define REG_TX_IQK      rTx_IQK
1021 #define REG_TX_IQK_PI_A rTx_IQK_PI_A
1022 #define REG_TX_IQK_PI_B rTx_IQK_PI_B
1023 #define REG_TX_IQK_TONE_A       rTx_IQK_Tone_A
1024 #define REG_TX_IQK_TONE_B       rTx_IQK_Tone_B
1025 #define REG_TX_OFDM_BBON        rTx_OFDM_BBON
1026 #define REG_TX_OFDM_RFON        rTx_OFDM_RFON
1027 #define REG_TX_POWER_AFTER_IQK_A        rTx_Power_After_IQK_A
1028 #define REG_TX_POWER_AFTER_IQK_B        rTx_Power_After_IQK_B
1029 #define REG_TX_POWER_BEFORE_IQK_A       rTx_Power_Before_IQK_A
1030 #define REG_TX_POWER_BEFORE_IQK_B       rTx_Power_Before_IQK_B
1031 #define REG_TX_TO_RX    rTx_To_Rx
1032 #define REG_TX_TO_TX    rTx_To_Tx
1033 #define REG_APK rAPK
1034 #define REG_ANTSEL_SW_JAGUAR    r_ANTSEL_SW_Jaguar
1035
1036
1037
1038 #define rf_welut_jaguar RF_WeLut_Jaguar
1039 #define rf_mode_table_addr      RF_ModeTableAddr
1040 #define rf_mode_table_data0     RF_ModeTableData0
1041 #define rf_mode_table_data1     RF_ModeTableData1
1042
1043
1044
1045
1046
1047
1048 #define RX_SMOOTH_FACTOR        Rx_Smooth_Factor
1049
1050 #endif /* __HAL_DATA_H__ */