1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
20 #ifndef __ODM_TYPES_H__
21 #define __ODM_TYPES_H__
24 /*Define Different SW team support*/
25 #define ODM_AP 0x01 /*BIT0*/
26 #define ODM_CE 0x04 /*BIT2*/
27 #define ODM_WIN 0x08 /*BIT3*/
28 #define ODM_ADSL 0x10 /*BIT4*/
29 #define ODM_IOT 0x20 /*BIT5*/
31 /*Deifne HW endian support*/
32 #define ODM_ENDIAN_BIG 0
33 #define ODM_ENDIAN_LITTLE 1
35 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
36 #define GET_PDM_ODM(__padapter) ((struct PHY_DM_STRUCT*)(&((GET_HAL_DATA(__padapter))->DM_OutSrc)))
37 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
38 #define GET_PDM_ODM(__padapter) ((struct PHY_DM_STRUCT*)(&((GET_HAL_DATA(__padapter))->odmpriv)))
41 #if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
42 #define RT_PCI_INTERFACE 1
43 #define RT_USB_INTERFACE 2
44 #define RT_SDIO_INTERFACE 3
52 RT_STATUS_INVALID_CONTEXT,
53 RT_STATUS_INVALID_PARAMETER,
54 RT_STATUS_NOT_SUPPORT,
55 RT_STATUS_OS_API_FAILED,*/
58 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
61 #if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
63 #define VISTA_USB_RX_REVISE 0
66 * Declare for ODM spin lock defintion temporarily fro compile pass.
68 enum rt_spinlock_type {
76 RT_CHNLOP_SPINLOCK = 9,
77 RT_RF_OPERATE_SPINLOCK = 10,
78 RT_INITIAL_SPINLOCK = 11,
79 RT_RF_STATE_SPINLOCK = 12, /* For RF state. Added by Bruce, 2007-10-30. */
80 #if VISTA_USB_RX_REVISE
81 RT_USBRX_CONTEXT_SPINLOCK = 13,
82 RT_USBRX_POSTPROC_SPINLOCK = 14, /* protect data of adapter->IndicateW/ IndicateR */
84 /* Shall we define Ndis 6.2 SpinLock Here ? */
85 RT_PORT_SPINLOCK = 16,
86 RT_VNIC_SPINLOCK = 17,
88 RT_H2C_SPINLOCK = 20, /* For H2C cmd. Added by tynli. 2009.11.09. */
90 rt_bt_data_spinlock = 25,
92 RT_WAPI_OPTION_SPINLOCK = 26,
93 RT_WAPI_RX_SPINLOCK = 27,
95 /* add for 92D CCK control issue */
96 RT_CCK_PAGEA_SPINLOCK = 28,
97 RT_BUFFER_SPINLOCK = 29,
98 RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30,
99 RT_GEN_TEMP_BUF_SPINLOCK = 31,
100 RT_AWB_SPINLOCK = 32,
101 RT_FW_PS_SPINLOCK = 33,
102 RT_HW_TIMER_SPIN_LOCK = 34,
103 RT_MPT_WI_SPINLOCK = 35,
104 RT_P2P_SPIN_LOCK = 36, /* Protect P2P context */
105 RT_DBG_SPIN_LOCK = 37,
106 RT_IQK_SPINLOCK = 38,
107 RT_PENDED_OID_SPINLOCK = 39,
108 RT_CHNLLIST_SPINLOCK = 40,
109 RT_INDIC_SPINLOCK = 41, /* protect indication */
110 RT_RFD_SPINLOCK = 42,
111 RT_SYNC_IO_CNT_SPINLOCK = 43,
118 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
119 #define sta_info _RT_WLAN_STA
120 #define __func__ __FUNCTION__
121 #define PHYDM_TESTCHIP_SUPPORT TESTCHIP_SUPPORT
122 #define MASKH3BYTES 0xffffff00
138 #define timer_list _RT_TIMER
141 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
143 /* To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07. */
144 #define ADSL_AP_BUILD_WORKAROUND
145 #define AP_BUILD_WORKAROUND
147 #ifdef AP_BUILD_WORKAROUND
148 #include "../typedef.h"
150 typedef void void, *void *;
151 typedef unsigned char boolean, *boolean *;
152 typedef unsigned char u8, *u8 *;
153 typedef unsigned short u16, *u16 *;
154 typedef unsigned int u32, *u32 *;
155 typedef unsigned long long u64, *u64 *;
157 /* In ARM platform, system would use the type -- "char" as "unsigned char"
158 * And we only use s8/s8* as INT8 now, so changes the type of s8.*/
159 typedef signed char s8, *s8 *;
161 typedef char s8, *s8 *;
163 typedef short s16, *s16 *;
164 typedef long s32, *s32 *;
165 typedef long long s64, *s64 *;
169 #ifdef CONFIG_PCI_HCI
170 #define DEV_BUS_TYPE RT_PCI_INTERFACE
176 #if (defined(TESTCHIP_SUPPORT))
177 #define PHYDM_TESTCHIP_SUPPORT 1
179 #define PHYDM_TESTCHIP_SUPPORT 0
182 #define sta_info stat_info
185 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
186 #include <drv_types.h>
188 typedef u8 u8, *u8 *;
189 typedef u16 u16, *u16 *;
190 typedef u32 u32, *u32 *;
191 typedef u64 u64, *u64 *;
192 typedef s8 s8, *s8 *;
193 typedef s16 s16, *s16 *;
194 typedef s32 s32, *s32 *;
195 typedef s64 s64, *s64 *;
222 #ifdef CONFIG_USB_HCI
223 #define DEV_BUS_TYPE RT_USB_INTERFACE
224 #elif defined(CONFIG_PCI_HCI)
225 #define DEV_BUS_TYPE RT_PCI_INTERFACE
226 #elif defined(CONFIG_SDIO_HCI)
227 #define DEV_BUS_TYPE RT_SDIO_INTERFACE
228 #elif defined(CONFIG_GSPI_HCI)
229 #define DEV_BUS_TYPE RT_SDIO_INTERFACE
233 #if defined(CONFIG_LITTLE_ENDIAN)
234 #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
235 #elif defined (CONFIG_BIG_ENDIAN)
236 #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
245 #define SET_TX_DESC_ANTSEL_A_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc+8, 24, 1, __value)
246 #define SET_TX_DESC_ANTSEL_B_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc+8, 25, 1, __value)
247 #define SET_TX_DESC_ANTSEL_C_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc+28, 29, 1, __value)
249 /* define useless flag to avoid compile warning */
250 #define USE_WORKITEM 0
251 #define FOR_BRAZIL_PRETEST 0
252 #define FPGA_TWO_MAC_VERIFICATION 0
253 #define RTL8881A_SUPPORT 0
255 #if (defined(TESTCHIP_SUPPORT))
256 #define PHYDM_TESTCHIP_SUPPORT 1
258 #define PHYDM_TESTCHIP_SUPPORT 0
262 #define READ_NEXT_PAIR(v1, v2, i) do { if (i+2 >= array_len) break; i += 2; v1 = array[i]; v2 = array[i+1]; } while (0)
266 #define MASKBYTE0 0xff
267 #define MASKBYTE1 0xff00
268 #define MASKBYTE2 0xff0000
269 #define MASKBYTE3 0xff000000
270 #define MASKHWORD 0xffff0000
271 #define MASKLWORD 0x0000ffff
272 #define MASKDWORD 0xffffffff
273 #define MASK7BITS 0x7f
274 #define MASK12BITS 0xfff
275 #define MASKH4BITS 0xf0000000
276 #define MASK20BITS 0xfffff
277 #define MASKOFDM_D 0xffc00000
278 #define MASKCCK 0x3f3f3f3f
279 #define RFREGOFFSETMASK 0xfffff
280 #define MASKH3BYTES 0xffffff00
281 #define MASKL3BYTES 0x00ffffff
282 #define MASKBYTE2HIGHNIBBLE 0x00f00000
283 #define MASKBYTE3LOWNIBBLE 0x0f000000
284 #define MASKL3BYTES 0x00ffffff
285 #define RFREGOFFSETMASK 0xfffff
288 #include "phydm_features.h"
290 #endif /* __ODM_TYPES_H__ */