drivers/net/wireless/rockchip_wlan/rtl8723cs/hal/phydm/phydm_noisemonitor.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20
  21 /* ************************************************************
  22  * include files
  23  * ************************************************************ */
  24 #include "mp_precomp.h"
  25 #include "phydm_precomp.h"
  26 #include "phydm_noisemonitor.h"
  27
  28 /* *************************************************
  29  * This function is for inband noise test utility only
  30  * To obtain the inband noise level(dbm), do the following.
  31  * 1. disable DIG and Power Saving
  32  * 2. Set initial gain = 0x1a
  33  * 3. Stop updating idle time pwer report (for driver read)
  34  *      - 0x80c[25]
  35  *
  36  * ************************************************* */
  37
  38 #define VALID_MIN                               -35
  39 #define VALID_MAX                       10
  40 #define VALID_CNT                               5
  41
  42 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
  43
  44 s16 odm_inband_noise_monitor_n_series(struct PHY_DM_STRUCT      *p_dm_odm, u8 is_pause_dig, u8 igi_value, u32 max_time)
  45 {
  46         u32                             tmp4b;
  47         u8                              max_rf_path = 0, rf_path;
  48         u8                              reg_c50, reg_c58, valid_done = 0;
  49         struct noise_level              noise_data;
  50         u64     start  = 0, func_start = 0,     func_end = 0;
  51
  52         func_start = odm_get_current_time(p_dm_odm);
  53         p_dm_odm->noise_level.noise_all = 0;
  54
  55         if ((p_dm_odm->rf_type == ODM_1T2R) || (p_dm_odm->rf_type == ODM_2T2R))
  56                 max_rf_path = 2;
  57         else
  58                 max_rf_path = 1;
  59
  60         ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_DebugControlInbandNoise_Nseries() ==>\n"));
  61
  62         odm_memory_set(p_dm_odm, &noise_data, 0, sizeof(struct noise_level));
  63
  64         /*  */
  65         /* step 1. Disable DIG && Set initial gain. */
  66         /*  */
  67
  68         if (is_pause_dig)
  69                 odm_pause_dig(p_dm_odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value);
  70         /*  */
  71         /* step 2. Disable all power save for read registers */
  72         /*  */
  73         /* dcmd_DebugControlPowerSave(p_adapter, PSDisable); */
  74
  75         /*  */
  76         /* step 3. Get noise power level */
  77         /*  */
  78         start = odm_get_current_time(p_dm_odm);
  79         while (1) {
  80
  81                 /* Stop updating idle time pwer report (for driver read) */
  82                 odm_set_bb_reg(p_dm_odm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 1);
  83
  84                 /* Read Noise Floor Report */
  85                 tmp4b = odm_get_bb_reg(p_dm_odm, 0x8f8, MASKDWORD);
  86                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Noise Floor Report (0x8f8) = 0x%08x\n", tmp4b));
  87
  88                 /* odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKBYTE0, TestInitialGain); */
  89                 /* if(max_rf_path == 2) */
  90                 /*      odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XB_AGC_CORE1, MASKBYTE0, TestInitialGain); */
  91
  92                 /* update idle time pwer report per 5us */
  93                 odm_set_bb_reg(p_dm_odm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 0);
  94
  95                 noise_data.value[ODM_RF_PATH_A] = (u8)(tmp4b & 0xff);
  96                 noise_data.value[ODM_RF_PATH_B]  = (u8)((tmp4b & 0xff00) >> 8);
  97
  98                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("value_a = 0x%x(%d), value_b = 0x%x(%d)\n",
  99                         noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_B], noise_data.value[ODM_RF_PATH_B]));
 100
 101                 for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) {
 102                         noise_data.sval[rf_path] = (s8)noise_data.value[rf_path];
 103                         noise_data.sval[rf_path] /= 2;
 104                 }
 105
 106
 107                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("sval_a = %d, sval_b = %d\n",
 108                         noise_data.sval[ODM_RF_PATH_A], noise_data.sval[ODM_RF_PATH_B]));
 109                 /* ODM_delay_ms(10); */
 110                 /* ODM_sleep_ms(10); */
 111
 112                 for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) {
 113                         if ((noise_data.valid_cnt[rf_path] < VALID_CNT) && (noise_data.sval[rf_path] < VALID_MAX && noise_data.sval[rf_path] >= VALID_MIN)) {
 114                                 noise_data.valid_cnt[rf_path]++;
 115                                 noise_data.sum[rf_path] += noise_data.sval[rf_path];
 116                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("rf_path:%d Valid sval = %d\n", rf_path, noise_data.sval[rf_path]));
 117                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Sum of sval = %d,\n", noise_data.sum[rf_path]));
 118                                 if (noise_data.valid_cnt[rf_path] == VALID_CNT) {
 119                                         valid_done++;
 120                                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("After divided, rf_path:%d,sum = %d\n", rf_path, noise_data.sum[rf_path]));
 121                                 }
 122
 123                         }
 124
 125                 }
 126
 127                 /* printk("####### valid_done:%d #############\n",valid_done); */
 128                 if ((valid_done == max_rf_path) || (odm_get_progressing_time(p_dm_odm, start) > max_time)) {
 129                         for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) {
 130                                 /* printk("%s PATH_%d - sum = %d, VALID_CNT = %d\n",__FUNCTION__,rf_path,noise_data.sum[rf_path], noise_data.valid_cnt[rf_path]); */
 131                                 if (noise_data.valid_cnt[rf_path])
 132                                         noise_data.sum[rf_path] /= noise_data.valid_cnt[rf_path];
 133                                 else
 134                                         noise_data.sum[rf_path]  = 0;
 135                         }
 136                         break;
 137                 }
 138         }
 139         reg_c50 = (u8)odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKBYTE0);
 140         reg_c50 &= ~BIT(7);
 141         ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("0x%x = 0x%02x(%d)\n", REG_OFDM_0_XA_AGC_CORE1, reg_c50, reg_c50));
 142         p_dm_odm->noise_level.noise[ODM_RF_PATH_A] = (u8)(-110 + reg_c50 + noise_data.sum[ODM_RF_PATH_A]);
 143         p_dm_odm->noise_level.noise_all += p_dm_odm->noise_level.noise[ODM_RF_PATH_A];
 144
 145         if (max_rf_path == 2) {
 146                 reg_c58 = (u8)odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XB_AGC_CORE1, MASKBYTE0);
 147                 reg_c58 &= ~BIT(7);
 148                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("0x%x = 0x%02x(%d)\n", REG_OFDM_0_XB_AGC_CORE1, reg_c58, reg_c58));
 149                 p_dm_odm->noise_level.noise[ODM_RF_PATH_B] = (u8)(-110 + reg_c58 + noise_data.sum[ODM_RF_PATH_B]);
 150                 p_dm_odm->noise_level.noise_all += p_dm_odm->noise_level.noise[ODM_RF_PATH_B];
 151         }
 152         p_dm_odm->noise_level.noise_all /= max_rf_path;
 153
 154         ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("noise_a = %d, noise_b = %d\n",
 155                         p_dm_odm->noise_level.noise[ODM_RF_PATH_A],
 156                         p_dm_odm->noise_level.noise[ODM_RF_PATH_B]));
 157
 158         /*  */
 159         /* step 4. Recover the Dig */
 160         /*  */
 161         if (is_pause_dig)
 162                 odm_pause_dig(p_dm_odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value);
 163         func_end = odm_get_progressing_time(p_dm_odm, func_start) ;
 164
 165         ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_DebugControlInbandNoise_Nseries() <==\n"));
 166         return p_dm_odm->noise_level.noise_all;
 167
 168 }
 169
 170 s16
 171 odm_inband_noise_monitor_ac_series(struct PHY_DM_STRUCT *p_dm_odm, u8 is_pause_dig, u8 igi_value, u32 max_time
 172                                   )
 173 {
 174         s32          rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/
 175         s32             value32, pwdb_A = 0, sval, noise, sum;
 176         boolean         pd_flag;
 177         u8                      i, valid_cnt;
 178         u64     start = 0, func_start = 0, func_end = 0;
 179
 180
 181         if (!(p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A)))
 182                 return 0;
 183
 184         func_start = odm_get_current_time(p_dm_odm);
 185         p_dm_odm->noise_level.noise_all = 0;
 186
 187         ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_inband_noise_monitor_ac_series() ==>\n"));
 188
 189         /* step 1. Disable DIG && Set initial gain. */
 190         if (is_pause_dig)
 191                 odm_pause_dig(p_dm_odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value);
 192
 193         /* step 2. Disable all power save for read registers */
 194         /*dcmd_DebugControlPowerSave(p_adapter, PSDisable); */
 195
 196         /* step 3. Get noise power level */
 197         start = odm_get_current_time(p_dm_odm);
 198
 199         /* reset counters */
 200         sum = 0;
 201         valid_cnt = 0;
 202
 203         /* step 3. Get noise power level */
 204         while (1) {
 205                 /*Set IGI=0x1C */
 206                 odm_write_dig(p_dm_odm, 0x1C);
 207                 /*stop CK320&CK88 */
 208                 odm_set_bb_reg(p_dm_odm, 0x8B4, BIT(6), 1);
 209                 /*Read path-A */
 210                 odm_set_bb_reg(p_dm_odm, 0x8FC, MASKDWORD, 0x200); /*set debug port*/
 211                 value32 = odm_get_bb_reg(p_dm_odm, 0xFA0, MASKDWORD); /*read debug port*/
 212
 213                 rxi_buf_anta = (value32 & 0xFFC00) >> 10; /*rxi_buf_anta=RegFA0[19:10]*/
 214                 rxq_buf_anta = value32 & 0x3FF; /*rxq_buf_anta=RegFA0[19:10]*/
 215
 216                 pd_flag = (boolean)((value32 & BIT(31)) >> 31);
 217
 218                 /*Not in packet detection period or Tx state */
 219                 if ((!pd_flag) || (rxi_buf_anta != 0x200)) {
 220                         /*sign conversion*/
 221                         rxi_buf_anta = odm_sign_conversion(rxi_buf_anta, 10);
 222                         rxq_buf_anta = odm_sign_conversion(rxq_buf_anta, 10);
 223
 224                         pwdb_A = odm_pwdb_conversion(rxi_buf_anta * rxi_buf_anta + rxq_buf_anta * rxq_buf_anta, 20, 18); /*S(10,9)*S(10,9)=S(20,18)*/
 225
 226                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n", pwdb_A, rxi_buf_anta & 0x3FF, rxq_buf_anta & 0x3FF));
 227                 }
 228                 /*Start CK320&CK88*/
 229                 odm_set_bb_reg(p_dm_odm, 0x8B4, BIT(6), 0);
 230                 /*BB Reset*/
 231                 odm_write_1byte(p_dm_odm, 0x02, odm_read_1byte(p_dm_odm, 0x02) & (~BIT(0)));
 232                 odm_write_1byte(p_dm_odm, 0x02, odm_read_1byte(p_dm_odm, 0x02) | BIT(0));
 233                 /*PMAC Reset*/
 234                 odm_write_1byte(p_dm_odm, 0xB03, odm_read_1byte(p_dm_odm, 0xB03) & (~BIT(0)));
 235                 odm_write_1byte(p_dm_odm, 0xB03, odm_read_1byte(p_dm_odm, 0xB03) | BIT(0));
 236                 /*CCK Reset*/
 237                 if (odm_read_1byte(p_dm_odm, 0x80B) & BIT(4)) {
 238                         odm_write_1byte(p_dm_odm, 0x80B, odm_read_1byte(p_dm_odm, 0x80B) & (~BIT(4)));
 239                         odm_write_1byte(p_dm_odm, 0x80B, odm_read_1byte(p_dm_odm, 0x80B) | BIT(4));
 240                 }
 241
 242                 sval = pwdb_A;
 243
 244                 if (sval < 0 && sval >= -27) {
 245                         if (valid_cnt < VALID_CNT) {
 246                                 valid_cnt++;
 247                                 sum += sval;
 248                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Valid sval = %d\n", sval));
 249                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Sum of sval = %d,\n", sum));
 250                                 if ((valid_cnt >= VALID_CNT) || (odm_get_progressing_time(p_dm_odm, start) > max_time)) {
 251                                         sum /= VALID_CNT;
 252                                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("After divided, sum = %d\n", sum));
 253                                         break;
 254                                 }
 255                         }
 256                 }
 257         }
 258
 259         /*ADC backoff is 12dB,*/
 260         /*Ptarget=0x1C-110=-82dBm*/
 261         noise = sum + 12 + 0x1C - 110;
 262
 263         /*Offset*/
 264         noise = noise - 3;
 265         ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("noise = %d\n", noise));
 266         p_dm_odm->noise_level.noise_all = (s16)noise;
 267
 268         /* step 4. Recover the Dig*/
 269         if (is_pause_dig)
 270                 odm_pause_dig(p_dm_odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value);
 271
 272         func_end = odm_get_progressing_time(p_dm_odm, func_start);
 273
 274         ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_inband_noise_monitor_ac_series() <==\n"));
 275
 276         return p_dm_odm->noise_level.noise_all;
 277 }
 278
 279
 280
 281 s16
 282 odm_inband_noise_monitor(void *p_dm_void, u8 is_pause_dig, u8 igi_value, u32 max_time)
 283 {
 284
 285         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 286         if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES)
 287                 return odm_inband_noise_monitor_ac_series(p_dm_odm, is_pause_dig, igi_value, max_time);
 288         else
 289                 return odm_inband_noise_monitor_n_series(p_dm_odm, is_pause_dig, igi_value, max_time);
 290 }
 291
 292 #endif