drivers/net/wireless/rockchip_wlan/rtl8723cs/hal/phydm/phydm_adaptivity.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20
  21 /* ************************************************************
  22  * include files
  23  * ************************************************************ */
  24 #include "mp_precomp.h"
  25 #include "phydm_precomp.h"
  26
  27 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
  28         #if WPP_SOFTWARE_TRACE
  29                 #include "PhyDM_Adaptivity.tmh"
  30         #endif
  31 #endif
  32
  33
  34 void
  35 phydm_check_adaptivity(
  36         void                    *p_dm_void
  37 )
  38 {
  39         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  40         struct _ADAPTIVITY_STATISTICS   *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY);
  41
  42         if (p_dm_odm->support_ability & ODM_BB_ADAPTIVITY) {
  43 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
  44                 if (p_dm_odm->ap_total_num > adaptivity->ap_num_th) {
  45                         p_dm_odm->adaptivity_enable = false;
  46                         p_dm_odm->adaptivity_flag = false;
  47                         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("AP total num > %d!!, disable adaptivity\n", adaptivity->ap_num_th));
  48                 } else
  49 #endif
  50                 {
  51                         if (adaptivity->dynamic_link_adaptivity || adaptivity->acs_for_adaptivity) {
  52                                 if (p_dm_odm->is_linked && adaptivity->is_check == false) {
  53                                         phydm_nhm_counter_statistics(p_dm_odm);
  54                                         phydm_check_environment(p_dm_odm);
  55                                 } else if (!p_dm_odm->is_linked)
  56                                         adaptivity->is_check = false;
  57                         } else {
  58                                 p_dm_odm->adaptivity_enable = true;
  59
  60                                 if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))
  61                                         p_dm_odm->adaptivity_flag = false;
  62                                 else
  63                                         p_dm_odm->adaptivity_flag = true;
  64                         }
  65                 }
  66         } else {
  67                 p_dm_odm->adaptivity_enable = false;
  68                 p_dm_odm->adaptivity_flag = false;
  69         }
  70
  71
  72
  73 }
  74
  75 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
  76 boolean
  77 phydm_check_channel_plan(
  78         void                    *p_dm_void
  79 )
  80 {
  81         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  82         struct _ADAPTER         *p_adapter      = p_dm_odm->adapter;
  83         PMGNT_INFO              p_mgnt_info = &(p_adapter->MgntInfo);
  84
  85         if (p_mgnt_info->RegEnableAdaptivity == 2) {
  86                 if (p_dm_odm->carrier_sense_enable == false) {          /*check domain Code for adaptivity or CarrierSense*/
  87                         if ((*p_dm_odm->p_band_type == ODM_BAND_5G) &&
  88                             !(p_dm_odm->odm_regulation_5g == REGULATION_ETSI || p_dm_odm->odm_regulation_5g == REGULATION_WW)) {
  89                                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity skip 5G domain code : %d\n", p_dm_odm->odm_regulation_5g));
  90                                 p_dm_odm->adaptivity_enable = false;
  91                                 p_dm_odm->adaptivity_flag = false;
  92                                 return true;
  93                         } else if ((*p_dm_odm->p_band_type == ODM_BAND_2_4G) &&
  94                                 !(p_dm_odm->odm_regulation_2_4g == REGULATION_ETSI || p_dm_odm->odm_regulation_2_4g == REGULATION_WW)) {
  95                                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity skip 2.4G domain code : %d\n", p_dm_odm->odm_regulation_2_4g));
  96                                 p_dm_odm->adaptivity_enable = false;
  97                                 p_dm_odm->adaptivity_flag = false;
  98                                 return true;
  99
 100                         } else if ((*p_dm_odm->p_band_type != ODM_BAND_2_4G) && (*p_dm_odm->p_band_type != ODM_BAND_5G)) {
 101                                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity neither 2G nor 5G band, return\n"));
 102                                 p_dm_odm->adaptivity_enable = false;
 103                                 p_dm_odm->adaptivity_flag = false;
 104                                 return true;
 105                         }
 106                 } else {
 107                         if ((*p_dm_odm->p_band_type == ODM_BAND_5G) &&
 108                             !(p_dm_odm->odm_regulation_5g == REGULATION_MKK || p_dm_odm->odm_regulation_5g == REGULATION_WW)) {
 109                                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 5G domain code : %d\n", p_dm_odm->odm_regulation_5g));
 110                                 p_dm_odm->adaptivity_enable = false;
 111                                 p_dm_odm->adaptivity_flag = false;
 112                                 return true;
 113                         }
 114
 115                         else if ((*p_dm_odm->p_band_type == ODM_BAND_2_4G) &&
 116                                 !(p_dm_odm->odm_regulation_2_4g == REGULATION_MKK  || p_dm_odm->odm_regulation_2_4g == REGULATION_WW)) {
 117                                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 2.4G domain code : %d\n", p_dm_odm->odm_regulation_2_4g));
 118                                 p_dm_odm->adaptivity_enable = false;
 119                                 p_dm_odm->adaptivity_flag = false;
 120                                 return true;
 121
 122                         } else if ((*p_dm_odm->p_band_type != ODM_BAND_2_4G) && (*p_dm_odm->p_band_type != ODM_BAND_5G)) {
 123                                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense neither 2G nor 5G band, return\n"));
 124                                 p_dm_odm->adaptivity_enable = false;
 125                                 p_dm_odm->adaptivity_flag = false;
 126                                 return true;
 127                         }
 128                 }
 129         }
 130
 131         return false;
 132
 133 }
 134 #endif
 135
 136 void
 137 phydm_nhm_counter_statistics_init(
 138         void                    *p_dm_void
 139 )
 140 {
 141         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 142
 143         if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
 144                 /*PHY parameters initialize for n series*/
 145                 odm_write_2byte(p_dm_odm, ODM_REG_CCX_PERIOD_11N + 2, 0xC350);                  /*0x894[31:16]=0x0xC350 Time duration for NHM unit: us, 0xc350=200ms*/
 146                 odm_write_2byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N + 2, 0xffff);                /*0x890[31:16]=0xffff           th_9, th_10*/
 147                 odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50);              /*0x898=0xffffff52                      th_3, th_2, th_1, th_0*/
 148                 odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff);              /*0x89c=0xffffffff                      th_7, th_6, th_5, th_4*/
 149                 odm_set_bb_reg(p_dm_odm, ODM_REG_FPGA0_IQK_11N, MASKBYTE0, 0xff);               /*0xe28[7:0]=0xff                       th_8*/
 150                 odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10) | BIT9 | BIT8, 0x1); /*0x890[10:8]=1                 ignoreCCA ignore PHYTXON enable CCX*/
 151                 odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(7), 0x1);                        /*0xc0c[7]=1                            max power among all RX ants*/
 152         }
 153 #if (RTL8195A_SUPPORT == 0)
 154         else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
 155                 /*PHY parameters initialize for ac series*/
 156                 odm_write_2byte(p_dm_odm, ODM_REG_CCX_PERIOD_11AC + 2, 0xC350);                 /*0x990[31:16]=0xC350   Time duration for NHM unit: us, 0xc350=200ms*/
 157                 odm_write_2byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC + 2, 0xffff);               /*0x994[31:16]=0xffff           th_9, th_10*/
 158                 odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50);     /*0x998=0xffffff52                      th_3, th_2, th_1, th_0*/
 159                 odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff);     /*0x99c=0xffffffff                      th_7, th_6, th_5, th_4*/
 160                 odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11AC, MASKBYTE0, 0xff);                /*0x9a0[7:0]=0xff                       th_8*/
 161                 odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8) | BIT9 | BIT10, 0x1); /*0x994[10:8]=1                        ignoreCCA ignore PHYTXON        enable CCX*/
 162                 odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_9E8_11AC, BIT(0), 0x1);                            /*0x9e8[7]=1                            max power among all RX ants*/
 163
 164         }
 165 #endif
 166 }
 167
 168 void
 169 phydm_nhm_counter_statistics(
 170         void                    *p_dm_void
 171 )
 172 {
 173         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 174
 175         if (!(p_dm_odm->support_ability & ODM_BB_NHM_CNT))
 176                 return;
 177
 178         /*Get NHM report*/
 179         phydm_get_nhm_counter_statistics(p_dm_odm);
 180
 181         /*Reset NHM counter*/
 182         phydm_nhm_counter_statistics_reset(p_dm_odm);
 183 }
 184
 185 void
 186 phydm_get_nhm_counter_statistics(
 187         void                    *p_dm_void
 188 )
 189 {
 190         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 191         u32             value32 = 0;
 192 #if (RTL8195A_SUPPORT == 0)
 193         if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES)
 194                 value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_CNT_11AC, MASKDWORD);
 195         else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES)
 196 #endif
 197                 value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_CNT_11N, MASKDWORD);
 198
 199         p_dm_odm->nhm_cnt_0 = (u8)(value32 & MASKBYTE0);
 200         p_dm_odm->nhm_cnt_1 = (u8)((value32 & MASKBYTE1) >> 8);
 201
 202 }
 203
 204 void
 205 phydm_nhm_counter_statistics_reset(
 206         void                    *p_dm_void
 207 )
 208 {
 209         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 210
 211         if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
 212                 odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 0);
 213                 odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 1);
 214         }
 215 #if (RTL8195A_SUPPORT == 0)
 216         else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
 217                 odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 0);
 218                 odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 1);
 219         }
 220
 221 #endif
 222
 223 }
 224
 225 void
 226 phydm_set_edcca_threshold(
 227         void    *p_dm_void,
 228         s8      H2L,
 229         s8      L2H
 230 )
 231 {
 232         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 233
 234         if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES)
 235                 odm_set_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKBYTE2 | MASKBYTE0, (u32)((u8)L2H | (u8)H2L << 16));
 236 #if (RTL8195A_SUPPORT == 0)
 237         else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES)
 238                 odm_set_bb_reg(p_dm_odm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD, (u16)((u8)L2H | (u8)H2L << 8));
 239 #endif
 240
 241 }
 242
 243 void
 244 phydm_set_lna(
 245         void                            *p_dm_void,
 246         enum phydm_set_lna      type
 247 )
 248 {
 249         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 250
 251         if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E)) {
 252                 if (type == phydm_disable_lna) {
 253                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
 254                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000);        /*select Rx mode*/
 255                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f);
 256                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x37f82);        /*disable LNA*/
 257                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
 258                         if (p_dm_odm->rf_type > ODM_1T1R) {
 259                                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);
 260                                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000);
 261                                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f);
 262                                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x37f82);
 263                                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);
 264                         }
 265                 } else if (type == phydm_enable_lna) {
 266                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
 267                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000);        /*select Rx mode*/
 268                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f);
 269                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x77f82);        /*back to normal*/
 270                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
 271                         if (p_dm_odm->rf_type > ODM_1T1R) {
 272                                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);
 273                                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000);
 274                                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f);
 275                                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x77f82);
 276                                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);
 277                         }
 278                 }
 279         } else if (p_dm_odm->support_ic_type & ODM_RTL8723B) {
 280                 if (type == phydm_disable_lna) {
 281                         /*S0*/
 282                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
 283                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000);        /*select Rx mode*/
 284                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f);
 285                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6137);        /*disable LNA*/
 286                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
 287                         /*S1*/
 288                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1);
 289                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x3008d);        /*select Rx mode and disable LNA*/
 290                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0);
 291                 } else if (type == phydm_enable_lna) {
 292                         /*S0*/
 293                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
 294                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000);        /*select Rx mode*/
 295                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f);
 296                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6177);        /*disable LNA*/
 297                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
 298                         /*S1*/
 299                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1);
 300                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x300bd);        /*select Rx mode and disable LNA*/
 301                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0);
 302                 }
 303
 304         } else if (p_dm_odm->support_ic_type & ODM_RTL8812) {
 305                 if (type == phydm_disable_lna) {
 306                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
 307                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000);        /*select Rx mode*/
 308                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff);
 309                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc22bf);        /*disable LNA*/
 310                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
 311                         if (p_dm_odm->rf_type > ODM_1T1R) {
 312                                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);
 313                                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000);        /*select Rx mode*/
 314                                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff);
 315                                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc22bf);        /*disable LNA*/
 316                                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);
 317                         }
 318                 } else if (type == phydm_enable_lna) {
 319                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
 320                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000);        /*select Rx mode*/
 321                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff);
 322                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc26bf);        /*disable LNA*/
 323                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
 324                         if (p_dm_odm->rf_type > ODM_1T1R) {
 325                                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);
 326                                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000);        /*select Rx mode*/
 327                                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff);
 328                                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc26bf);        /*disable LNA*/
 329                                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);
 330                         }
 331                 }
 332         } else if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) {
 333                 if (type == phydm_disable_lna) {
 334                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
 335                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000);        /*select Rx mode*/
 336                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f);
 337                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb09b);        /*disable LNA*/
 338                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
 339                 } else if (type == phydm_enable_lna) {
 340                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
 341                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000);        /*select Rx mode*/
 342                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f);
 343                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb0bb);        /*disable LNA*/
 344                         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
 345                 }
 346         }
 347 }
 348
 349
 350
 351 void
 352 phydm_set_trx_mux(
 353         void                            *p_dm_void,
 354         enum phydm_trx_mux_type tx_mode,
 355         enum phydm_trx_mux_type rx_mode
 356 )
 357 {
 358         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 359
 360         if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
 361                 odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT(3) | BIT2 | BIT1, tx_mode);                    /*set TXmod to standby mode to remove outside noise affect*/
 362                 odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT(22) | BIT21 | BIT20, rx_mode);         /*set RXmod to standby mode to remove outside noise affect*/
 363                 if (p_dm_odm->rf_type > ODM_1T1R) {
 364                         odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT(3) | BIT2 | BIT1, tx_mode);          /*set TXmod to standby mode to remove outside noise affect*/
 365                         odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT(22) | BIT21 | BIT20, rx_mode);       /*set RXmod to standby mode to remove outside noise affect*/
 366                 }
 367         }
 368 #if (RTL8195A_SUPPORT == 0)
 369         else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
 370                 odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC, BIT(11) | BIT10 | BIT9 | BIT8, tx_mode);                           /*set TXmod to standby mode to remove outside noise affect*/
 371                 odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC, BIT(7) | BIT6 | BIT5 | BIT4, rx_mode);                             /*set RXmod to standby mode to remove outside noise affect*/
 372                 if (p_dm_odm->rf_type > ODM_1T1R) {
 373                         odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC_B, BIT(11) | BIT10 | BIT9 | BIT8, tx_mode);         /*set TXmod to standby mode to remove outside noise affect*/
 374                         odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC_B, BIT(7) | BIT6 | BIT5 | BIT4, rx_mode);                   /*set RXmod to standby mode to remove outside noise affect*/
 375                 }
 376         }
 377 #endif
 378
 379 }
 380
 381 void
 382 phydm_mac_edcca_state(
 383         void                                    *p_dm_void,
 384         enum phydm_mac_edcca_type               state
 385 )
 386 {
 387         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 388         if (state == phydm_ignore_edcca) {
 389                 odm_set_mac_reg(p_dm_odm, REG_TX_PTCL_CTRL, BIT(15), 1);        /*ignore EDCCA  reg520[15]=1*/
 390                 /*              odm_set_mac_reg(p_dm_odm, REG_RD_CTRL, BIT(11), 0);                     */ /*reg524[11]=0*/
 391         } else {        /*don't set MAC ignore EDCCA signal*/
 392                 odm_set_mac_reg(p_dm_odm, REG_TX_PTCL_CTRL, BIT(15), 0);        /*don't ignore EDCCA     reg520[15]=0\14*/
 393                 /*              odm_set_mac_reg(p_dm_odm, REG_RD_CTRL, BIT(11), 1);                     */ /*reg524[11]=1       */
 394         }
 395         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("EDCCA enable state = %d\n", state));
 396
 397 }
 398
 399 boolean
 400 phydm_cal_nhm_cnt(
 401         void            *p_dm_void
 402 )
 403 {
 404         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 405         u16                     base = 0;
 406
 407         base = p_dm_odm->nhm_cnt_0 + p_dm_odm->nhm_cnt_1;
 408
 409         if (base != 0) {
 410                 p_dm_odm->nhm_cnt_0 = ((p_dm_odm->nhm_cnt_0) << 8) / base;
 411                 p_dm_odm->nhm_cnt_1 = ((p_dm_odm->nhm_cnt_1) << 8) / base;
 412         }
 413         if ((p_dm_odm->nhm_cnt_0 - p_dm_odm->nhm_cnt_1) >= 100)
 414                 return true;                    /*clean environment*/
 415         else
 416                 return false;           /*noisy environment*/
 417
 418 }
 419
 420
 421 void
 422 phydm_check_environment(
 423         void    *p_dm_void
 424 )
 425 {
 426         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 427         struct _ADAPTIVITY_STATISTICS   *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY);
 428         boolean is_clean_environment = false;
 429 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
 430         struct rtl8192cd_priv   *priv = p_dm_odm->priv;
 431 #endif
 432
 433         if (adaptivity->is_first_link == true) {
 434                 if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))
 435                         p_dm_odm->adaptivity_flag = false;
 436                 else
 437                         p_dm_odm->adaptivity_flag = true;
 438
 439                 adaptivity->is_first_link = false;
 440                 return;
 441         } else {
 442                 if (adaptivity->nhm_wait < 3) {         /*Start enter NHM after 4 nhm_wait*/
 443                         adaptivity->nhm_wait++;
 444                         phydm_nhm_counter_statistics(p_dm_odm);
 445                         return;
 446                 } else {
 447                         phydm_nhm_counter_statistics(p_dm_odm);
 448                         is_clean_environment = phydm_cal_nhm_cnt(p_dm_odm);
 449                         if (is_clean_environment == true) {
 450                                 p_dm_odm->th_l2h_ini = adaptivity->th_l2h_ini_backup;                   /*adaptivity mode*/
 451                                 p_dm_odm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup;
 452
 453                                 p_dm_odm->adaptivity_enable = true;
 454
 455                                 if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))
 456                                         p_dm_odm->adaptivity_flag = false;
 457                                 else
 458                                         p_dm_odm->adaptivity_flag = true;
 459 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
 460                                 priv->pshare->rf_ft_var.is_clean_environment = true;
 461 #endif
 462                         } else {
 463                                 if (!adaptivity->acs_for_adaptivity) {
 464                                         p_dm_odm->th_l2h_ini = p_dm_odm->th_l2h_ini_mode2;                      /*mode2*/
 465                                         p_dm_odm->th_edcca_hl_diff = p_dm_odm->th_edcca_hl_diff_mode2;
 466
 467                                         p_dm_odm->adaptivity_flag = false;
 468                                         p_dm_odm->adaptivity_enable = false;
 469                                 }
 470 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
 471                                 priv->pshare->rf_ft_var.is_clean_environment = false;
 472 #endif
 473                         }
 474                         adaptivity->nhm_wait = 0;
 475                         adaptivity->is_first_link = true;
 476                         adaptivity->is_check = true;
 477                 }
 478
 479         }
 480
 481
 482 }
 483
 484 void
 485 phydm_search_pwdb_lower_bound(
 486         void            *p_dm_void
 487 )
 488 {
 489         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 490         struct _ADAPTIVITY_STATISTICS   *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY);
 491         u32                     value32 = 0, reg_value32 = 0;
 492         u8                      cnt, try_count = 0;
 493         u8                      tx_edcca1 = 0, tx_edcca0 = 0;
 494         boolean                 is_adjust = true;
 495         s8                      th_l2h_dmc, th_h2l_dmc, igi_target = 0x32;
 496         s8                      diff;
 497         u8                      IGI = adaptivity->igi_base + 30 + (u8)p_dm_odm->th_l2h_ini - (u8)p_dm_odm->th_edcca_hl_diff;
 498
 499         if (p_dm_odm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A))
 500                 phydm_set_lna(p_dm_odm, phydm_disable_lna);
 501         else {
 502                 phydm_set_trx_mux(p_dm_odm, phydm_standby_mode, phydm_standby_mode);
 503                 odm_pause_dig(p_dm_odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, 0x7e);
 504         }
 505
 506         diff = igi_target - (s8)IGI;
 507         th_l2h_dmc = p_dm_odm->th_l2h_ini + diff;
 508         if (th_l2h_dmc > 10)
 509                 th_l2h_dmc = 10;
 510         th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff;
 511
 512         phydm_set_edcca_threshold(p_dm_odm, th_h2l_dmc, th_l2h_dmc);
 513         ODM_delay_ms(30);
 514
 515         while (is_adjust) {
 516                 if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
 517                         odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11N, MASKDWORD, 0x0);
 518                         reg_value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11N, MASKDWORD);
 519                 }
 520 #if (RTL8195A_SUPPORT == 0)
 521                 else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
 522                         odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x0);
 523                         reg_value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD);
 524                 }
 525 #endif
 526                 while (reg_value32 & BIT(3) && try_count < 3) {
 527                         ODM_delay_ms(3);
 528                         try_count = try_count + 1;
 529                         if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES)
 530                                 reg_value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11N, MASKDWORD);
 531 #if (RTL8195A_SUPPORT == 0)
 532                         else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES)
 533                                 reg_value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD);
 534 #endif
 535                 }
 536                 try_count = 0;
 537
 538                 for (cnt = 0; cnt < 20; cnt++) {
 539                         if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
 540                                 odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11N, MASKDWORD, 0x208);
 541                                 value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11N, MASKDWORD);
 542                         }
 543 #if (RTL8195A_SUPPORT == 0)
 544                         else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
 545                                 odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x209);
 546                                 value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD);
 547                         }
 548 #endif
 549                         if (value32 & BIT(30) && (p_dm_odm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E)))
 550                                 tx_edcca1 = tx_edcca1 + 1;
 551                         else if (value32 & BIT(29))
 552                                 tx_edcca1 = tx_edcca1 + 1;
 553                         else
 554                                 tx_edcca0 = tx_edcca0 + 1;
 555                 }
 556
 557                 if (tx_edcca1 > 1) {
 558                         IGI = IGI - 1;
 559                         th_l2h_dmc = th_l2h_dmc + 1;
 560                         if (th_l2h_dmc > 10)
 561                                 th_l2h_dmc = 10;
 562                         th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff;
 563
 564                         phydm_set_edcca_threshold(p_dm_odm, th_h2l_dmc, th_l2h_dmc);
 565                         if (th_l2h_dmc == 10) {
 566                                 is_adjust = false;
 567                                 adaptivity->h2l_lb = th_h2l_dmc;
 568                                 adaptivity->l2h_lb = th_l2h_dmc;
 569                                 p_dm_odm->adaptivity_igi_upper = IGI;
 570                         }
 571
 572                         tx_edcca1 = 0;
 573                         tx_edcca0 = 0;
 574
 575                 } else {
 576                         is_adjust = false;
 577                         adaptivity->h2l_lb = th_h2l_dmc;
 578                         adaptivity->l2h_lb = th_l2h_dmc;
 579                         p_dm_odm->adaptivity_igi_upper = IGI;
 580                         tx_edcca1 = 0;
 581                         tx_edcca0 = 0;
 582                 }
 583         }
 584
 585         p_dm_odm->adaptivity_igi_upper = p_dm_odm->adaptivity_igi_upper - p_dm_odm->dc_backoff;
 586         adaptivity->h2l_lb = adaptivity->h2l_lb + p_dm_odm->dc_backoff;
 587         adaptivity->l2h_lb = adaptivity->l2h_lb + p_dm_odm->dc_backoff;
 588
 589         if (p_dm_odm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A))
 590                 phydm_set_lna(p_dm_odm, phydm_enable_lna);
 591         else {
 592                 phydm_set_trx_mux(p_dm_odm, phydm_tx_mode, phydm_rx_mode);
 593                 odm_pause_dig(p_dm_odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, NONE);
 594         }
 595
 596         phydm_set_edcca_threshold(p_dm_odm, 0x7f, 0x7f);                                /*resume to no link state*/
 597 }
 598
 599 boolean
 600 phydm_re_search_condition(
 601         void                            *p_dm_void
 602 )
 603 {
 604         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 605         /*struct _ADAPTIVITY_STATISTICS*        adaptivity = (struct _ADAPTIVITY_STATISTICS*)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY);*/
 606         u8                      adaptivity_igi_upper;
 607         u8                      count = 0;
 608         /*s8            TH_L2H_dmc, IGI_target = 0x32;*/
 609         /*s8            diff;*/
 610
 611         adaptivity_igi_upper = p_dm_odm->adaptivity_igi_upper + p_dm_odm->dc_backoff;
 612
 613         /*TH_L2H_dmc = 10;*/
 614
 615         /*diff = TH_L2H_dmc - p_dm_odm->TH_L2H_ini;*/
 616         /*lowest_IGI_upper = IGI_target - diff;*/
 617
 618         /*if ((adaptivity_igi_upper - lowest_IGI_upper) <= 5)*/
 619         if (adaptivity_igi_upper <= 0x26 && count < 3) {
 620                 count = count + 1;
 621                 return true;
 622         }
 623         else
 624                 return false;
 625
 626 }
 627
 628 void
 629 phydm_adaptivity_info_init(
 630         void                            *p_dm_void,
 631         enum phydm_adapinfo_e   cmn_info,
 632         u32                             value
 633 )
 634 {
 635         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 636         struct _ADAPTIVITY_STATISTICS   *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY);
 637
 638         switch (cmn_info)       {
 639         case PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE:
 640                 p_dm_odm->carrier_sense_enable = (boolean)value;
 641                 break;
 642
 643         case PHYDM_ADAPINFO_DCBACKOFF:
 644                 p_dm_odm->dc_backoff = (u8)value;
 645                 break;
 646
 647         case PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY:
 648                 adaptivity->dynamic_link_adaptivity = (boolean)value;
 649                 break;
 650
 651         case PHYDM_ADAPINFO_TH_L2H_INI:
 652                 p_dm_odm->th_l2h_ini = (s8)value;
 653                 break;
 654
 655         case PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF:
 656                 p_dm_odm->th_edcca_hl_diff = (s8)value;
 657                 break;
 658
 659         case PHYDM_ADAPINFO_AP_NUM_TH:
 660                 adaptivity->ap_num_th = (u8)value;
 661                 break;
 662
 663         default:
 664                 break;
 665
 666         }
 667
 668 }
 669
 670
 671
 672 void
 673 phydm_adaptivity_init(
 674         void            *p_dm_void
 675 )
 676 {
 677         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 678         struct _ADAPTIVITY_STATISTICS   *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY);
 679         s8      igi_target = 0x32;
 680         /*struct _dynamic_initial_gain_threshold_* p_dm_dig_table = &p_dm_odm->dm_dig_table;*/
 681
 682 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
 683
 684         if (p_dm_odm->carrier_sense_enable == false) {
 685                 if (p_dm_odm->th_l2h_ini == 0)
 686                         p_dm_odm->th_l2h_ini = 0xf5;
 687         } else
 688                 p_dm_odm->th_l2h_ini = 0xa;
 689
 690         if (p_dm_odm->th_edcca_hl_diff == 0)
 691                 p_dm_odm->th_edcca_hl_diff = 7;
 692 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
 693         if (p_dm_odm->wifi_test == true || p_dm_odm->mp_mode == true)
 694 #else
 695         if ((p_dm_odm->wifi_test & RT_WIFI_LOGO) == true)
 696 #endif
 697                 p_dm_odm->edcca_enable = false;         /*even no adaptivity, we still enable EDCCA, AP side use mib control*/
 698         else
 699                 p_dm_odm->edcca_enable = true;
 700
 701 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
 702         struct rtl8192cd_priv   *priv = p_dm_odm->priv;
 703
 704         if (p_dm_odm->carrier_sense_enable) {
 705                 p_dm_odm->th_l2h_ini = 0xa;
 706                 p_dm_odm->th_edcca_hl_diff = 7;
 707         } else {
 708                 p_dm_odm->th_l2h_ini = p_dm_odm->TH_L2H_default;        /*set by mib*/
 709                 p_dm_odm->th_edcca_hl_diff = p_dm_odm->th_edcca_hl_diff_default;
 710         }
 711
 712         if (priv->pshare->rf_ft_var.adaptivity_enable == 3)
 713                 adaptivity->acs_for_adaptivity = true;
 714         else
 715                 adaptivity->acs_for_adaptivity = false;
 716
 717         if (priv->pshare->rf_ft_var.adaptivity_enable == 2)
 718                 adaptivity->dynamic_link_adaptivity = true;
 719         else
 720                 adaptivity->dynamic_link_adaptivity = false;
 721
 722         priv->pshare->rf_ft_var.is_clean_environment = false;
 723
 724 #endif
 725
 726         p_dm_odm->adaptivity_igi_upper = 0;
 727         p_dm_odm->adaptivity_enable = false;    /*use this flag to decide enable or disable*/
 728
 729         p_dm_odm->th_l2h_ini_mode2 = 20;
 730         p_dm_odm->th_edcca_hl_diff_mode2 = 8;
 731         adaptivity->th_l2h_ini_backup = p_dm_odm->th_l2h_ini;
 732         adaptivity->th_edcca_hl_diff_backup = p_dm_odm->th_edcca_hl_diff;
 733
 734         adaptivity->igi_base = 0x32;
 735         adaptivity->igi_target = 0x1c;
 736         adaptivity->h2l_lb = 0;
 737         adaptivity->l2h_lb = 0;
 738         adaptivity->nhm_wait = 0;
 739         adaptivity->is_check = false;
 740         adaptivity->is_first_link = true;
 741         adaptivity->adajust_igi_level = 0;
 742         adaptivity->is_stop_edcca = false;
 743         adaptivity->backup_h2l = 0;
 744         adaptivity->backup_l2h = 0;
 745
 746         phydm_mac_edcca_state(p_dm_odm, phydm_dont_ignore_edcca);
 747
 748         /*Search pwdB lower bound*/
 749         if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES)
 750                 odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11N, MASKDWORD, 0x208);
 751 #if (RTL8195A_SUPPORT == 0)
 752         else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES)
 753                 odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x209);
 754 #endif
 755
 756         if (p_dm_odm->support_ic_type & ODM_IC_11N_GAIN_IDX_EDCCA) {
 757                 /*odm_set_bb_reg(p_dm_odm, ODM_REG_EDCCA_DOWN_OPT_11N, BIT(12) | BIT11 | BIT10, 0x7);*/         /*interfernce need > 2^x us, and then EDCCA will be 1*/
 758                 if (p_dm_odm->support_ic_type & ODM_RTL8197F) {
 759                         odm_set_bb_reg(p_dm_odm, ODM_REG_PAGE_B1_97F, BIT(30), 0x1);                                                            /*set to page B1*/
 760                         odm_set_bb_reg(p_dm_odm, ODM_REG_EDCCA_DCNF_97F, BIT(27) | BIT26, 0x1);         /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
 761                         odm_set_bb_reg(p_dm_odm, ODM_REG_PAGE_B1_97F, BIT(30), 0x0);
 762 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
 763                         if (priv->pshare->rf_ft_var.adaptivity_enable == 1)
 764                                 odm_set_bb_reg(p_dm_odm, 0xce8, BIT(13), 0x1);                                          /*0: mean, 1:max pwdB*/
 765 #endif
 766                 } else
 767                         odm_set_bb_reg(p_dm_odm, ODM_REG_EDCCA_DCNF_11N, BIT(21) | BIT20, 0x1);         /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
 768         }
 769 #if (RTL8195A_SUPPORT == 0)
 770         if (p_dm_odm->support_ic_type & ODM_IC_11AC_GAIN_IDX_EDCCA) {           /*8814a no need to find pwdB lower bound, maybe*/
 771                 /*odm_set_bb_reg(p_dm_odm, ODM_REG_EDCCA_DOWN_OPT, BIT(30) | BIT29 | BIT28, 0x7);*/             /*interfernce need > 2^x us, and then EDCCA will be 1*/
 772                 odm_set_bb_reg(p_dm_odm, ODM_REG_ACBB_EDCCA_ENHANCE, BIT(29) | BIT28, 0x1);             /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
 773         }
 774
 775         if (!(p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))) {
 776                 phydm_search_pwdb_lower_bound(p_dm_odm);
 777                 if (phydm_re_search_condition(p_dm_odm))
 778                         phydm_search_pwdb_lower_bound(p_dm_odm);
 779         }
 780 #endif
 781
 782         /*we need to consider PwdB upper bound for 8814 later IC*/
 783         adaptivity->adajust_igi_level = (u8)((p_dm_odm->th_l2h_ini + igi_target) - pwdb_upper_bound + dfir_loss);       /*IGI = L2H - PwdB - dfir_loss*/
 784
 785         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("th_l2h_ini = 0x%x, th_edcca_hl_diff = 0x%x, adaptivity->adajust_igi_level = 0x%x\n", p_dm_odm->th_l2h_ini, p_dm_odm->th_edcca_hl_diff, adaptivity->adajust_igi_level));
 786
 787         /*Check this later on Windows*/
 788         /*phydm_set_edcca_threshold_api(p_dm_odm, p_dm_dig_table->cur_ig_value);*/
 789
 790 }
 791
 792
 793 void
 794 phydm_adaptivity(
 795         void                    *p_dm_void
 796 )
 797 {
 798         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 799         struct _dynamic_initial_gain_threshold_                 *p_dm_dig_table = &p_dm_odm->dm_dig_table;
 800         u8                      IGI = p_dm_dig_table->cur_ig_value;
 801         s8                      th_l2h_dmc, th_h2l_dmc;
 802         s8                      diff = 0, igi_target;
 803         struct _ADAPTIVITY_STATISTICS   *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY);
 804 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 805         struct _ADAPTER         *p_adapter      = p_dm_odm->adapter;
 806         boolean                 is_fw_current_in_ps_mode = false;
 807
 808         p_adapter->HalFunc.GetHwRegHandler(p_adapter, HW_VAR_FW_PSMODE_STATUS, (u8 *)(&is_fw_current_in_ps_mode));
 809
 810         /*Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.*/
 811         if (is_fw_current_in_ps_mode)
 812                 return;
 813 #endif
 814
 815         if ((p_dm_odm->edcca_enable == false) || (adaptivity->is_stop_edcca == true)) {
 816                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Disable EDCCA!!!\n"));
 817                 return;
 818         }
 819
 820         if (!(p_dm_odm->support_ability & ODM_BB_ADAPTIVITY)) {
 821                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity disable, enable EDCCA mode!!!\n"));
 822                 p_dm_odm->th_l2h_ini = p_dm_odm->th_l2h_ini_mode2;
 823                 p_dm_odm->th_edcca_hl_diff = p_dm_odm->th_edcca_hl_diff_mode2;
 824         }
 825 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 826         else {
 827                 if (phydm_check_channel_plan(p_dm_odm) || (p_dm_odm->ap_total_num > adaptivity->ap_num_th)) {
 828                         p_dm_odm->th_l2h_ini = p_dm_odm->th_l2h_ini_mode2;
 829                         p_dm_odm->th_edcca_hl_diff = p_dm_odm->th_edcca_hl_diff_mode2;
 830                 } else {
 831                         p_dm_odm->th_l2h_ini = adaptivity->th_l2h_ini_backup;
 832                         p_dm_odm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup;
 833                 }
 834         }
 835 #endif
 836
 837         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("odm_Adaptivity() =====>\n"));
 838         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("igi_base=0x%x, th_l2h_ini = %d, th_edcca_hl_diff = %d\n",
 839                 adaptivity->igi_base, p_dm_odm->th_l2h_ini, p_dm_odm->th_edcca_hl_diff));
 840 #if (RTL8195A_SUPPORT == 0)
 841         if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
 842                 /*fix AC series when enable EDCCA hang issue*/
 843                 odm_set_bb_reg(p_dm_odm, 0x800, BIT(10), 1);    /*ADC_mask disable*/
 844                 odm_set_bb_reg(p_dm_odm, 0x800, BIT(10), 0);    /*ADC_mask enable*/
 845         }
 846 #endif
 847         if (*p_dm_odm->p_band_width == ODM_BW20M)               /*CHANNEL_WIDTH_20*/
 848                 igi_target = adaptivity->igi_base;
 849         else if (*p_dm_odm->p_band_width == ODM_BW40M)
 850                 igi_target = adaptivity->igi_base + 2;
 851 #if (RTL8195A_SUPPORT == 0)
 852         else if (*p_dm_odm->p_band_width == ODM_BW80M)
 853                 igi_target = adaptivity->igi_base + 2;
 854 #endif
 855         else
 856                 igi_target = adaptivity->igi_base;
 857         adaptivity->igi_target = (u8) igi_target;
 858
 859         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("band_width=%s, igi_target=0x%x, dynamic_link_adaptivity = %d, acs_for_adaptivity = %d\n",
 860                 (*p_dm_odm->p_band_width == ODM_BW80M) ? "80M" : ((*p_dm_odm->p_band_width == ODM_BW40M) ? "40M" : "20M"), igi_target, adaptivity->dynamic_link_adaptivity, adaptivity->acs_for_adaptivity));
 861         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("RSSI_min = %d, adaptivity->adajust_igi_level= 0x%x, adaptivity_flag = %d, adaptivity_enable = %d\n",
 862                 p_dm_odm->rssi_min, adaptivity->adajust_igi_level, p_dm_odm->adaptivity_flag, p_dm_odm->adaptivity_enable));
 863
 864         if ((adaptivity->dynamic_link_adaptivity == true) && (!p_dm_odm->is_linked) && (p_dm_odm->adaptivity_enable == false)) {
 865                 phydm_set_edcca_threshold(p_dm_odm, 0x7f, 0x7f);
 866                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("In DynamicLink mode(noisy) and No link, Turn off EDCCA!!\n"));
 867                 return;
 868         }
 869
 870         if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
 871                 if ((adaptivity->adajust_igi_level > IGI) && (p_dm_odm->adaptivity_enable == true))
 872                         diff = adaptivity->adajust_igi_level - IGI;
 873
 874                 th_l2h_dmc = p_dm_odm->th_l2h_ini - diff + igi_target;
 875                 th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff;
 876         }
 877 #if (RTL8195A_SUPPORT == 0)
 878         else    {
 879                 diff = igi_target - (s8)IGI;
 880                 th_l2h_dmc = p_dm_odm->th_l2h_ini + diff;
 881                 if (th_l2h_dmc > 10 && (p_dm_odm->adaptivity_enable == true))
 882                         th_l2h_dmc = 10;
 883
 884                 th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff;
 885
 886                 /*replace lower bound to prevent EDCCA always equal 1*/
 887                 if (th_h2l_dmc < adaptivity->h2l_lb)
 888                         th_h2l_dmc = adaptivity->h2l_lb;
 889                 if (th_l2h_dmc < adaptivity->l2h_lb)
 890                         th_l2h_dmc = adaptivity->l2h_lb;
 891         }
 892 #endif
 893         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n", IGI, th_l2h_dmc, th_h2l_dmc));
 894         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity_igi_upper=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n", p_dm_odm->adaptivity_igi_upper, adaptivity->h2l_lb, adaptivity->l2h_lb));
 895
 896         phydm_set_edcca_threshold(p_dm_odm, th_h2l_dmc, th_l2h_dmc);
 897
 898         if (p_dm_odm->adaptivity_enable == true)
 899                 odm_set_mac_reg(p_dm_odm, REG_RD_CTRL, BIT(11), 1);
 900
 901         return;
 902 }
 903
 904
 905 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 906
 907 void
 908 phydm_adaptivity_bsod(
 909         void            *p_dm_void
 910 )
 911 {
 912         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 913         struct _ADAPTER         *p_adapter = p_dm_odm->adapter;
 914         PMGNT_INFO              p_mgnt_info = &(p_adapter->MgntInfo);
 915         u8                      count = 0;
 916         u32                     u4_value;
 917
 918         /*
 919         1. turn off RF (TRX Mux in standby mode)
 920         2. H2C mac id drop
 921         3. ignore EDCCA
 922         4. wait for clear FIFO
 923         5. don't ignore EDCCA
 924         6. turn on RF (TRX Mux in TRx mdoe)
 925         7. H2C mac id resume
 926         */
 927
 928         RT_TRACE(COMP_MLME, DBG_WARNING, ("MAC id drop packet!!!!!\n"));
 929
 930         p_adapter->dropPktByMacIdCnt++;
 931         p_mgnt_info->bDropPktInProgress = true;
 932
 933         p_adapter->HalFunc.GetHwRegHandler(p_adapter, HW_VAR_MAX_Q_PAGE_NUM, (u8 *)(&u4_value));
 934         RT_TRACE(COMP_INIT, DBG_LOUD, ("Queue Reserved Page number = 0x%08x\n", u4_value));
 935         p_adapter->HalFunc.GetHwRegHandler(p_adapter, HW_VAR_AVBL_Q_PAGE_NUM, (u8 *)(&u4_value));
 936         RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page number = 0x%08x\n", u4_value));
 937
 938         /*Standby mode*/
 939         phydm_set_trx_mux(p_dm_odm, phydm_standby_mode, phydm_standby_mode);
 940         odm_write_dig(p_dm_odm, 0x20);
 941
 942         /*H2C mac id drop*/
 943         MacIdIndicateDisconnect(p_adapter);
 944
 945         /*Ignore EDCCA*/
 946         phydm_mac_edcca_state(p_dm_odm, phydm_ignore_edcca);
 947
 948         delay_ms(50);
 949         count = 5;
 950
 951         /*Resume EDCCA*/
 952         phydm_mac_edcca_state(p_dm_odm, phydm_dont_ignore_edcca);
 953
 954         /*Turn on TRx mode*/
 955         phydm_set_trx_mux(p_dm_odm, phydm_tx_mode, phydm_rx_mode);
 956         odm_write_dig(p_dm_odm, 0x20);
 957
 958         /*Resume H2C macid*/
 959         MacIdRecoverMediaStatus(p_adapter);
 960
 961         p_adapter->HalFunc.GetHwRegHandler(p_adapter, HW_VAR_AVBL_Q_PAGE_NUM, (u8 *)(&u4_value));
 962         RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page number = 0x%08x\n", u4_value));
 963
 964         p_mgnt_info->bDropPktInProgress = false;
 965         RT_TRACE(COMP_MLME, DBG_WARNING, ("End of MAC id drop packet, spent %dms\n", count * 10));
 966
 967 }
 968
 969 #endif
 970
 971 /*This API is for solving USB can't Tx problem due to USB3.0 interference in 2.4G*/
 972 void
 973 phydm_pause_edcca(
 974         void    *p_dm_void,
 975         boolean is_pasue_edcca
 976 )
 977 {
 978         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 979         struct _ADAPTIVITY_STATISTICS   *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY);
 980         struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table;
 981         u8      IGI = p_dm_dig_table->cur_ig_value;
 982         s8      diff = 0;
 983
 984         if (is_pasue_edcca) {
 985                 adaptivity->is_stop_edcca = true;
 986
 987                 if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
 988                         if (adaptivity->adajust_igi_level > IGI)
 989                                 diff = adaptivity->adajust_igi_level - IGI;
 990
 991                         adaptivity->backup_l2h = p_dm_odm->th_l2h_ini - diff + adaptivity->igi_target;
 992                         adaptivity->backup_h2l = adaptivity->backup_l2h - p_dm_odm->th_edcca_hl_diff;
 993                 }
 994 #if (RTL8195A_SUPPORT == 0)
 995                 else {
 996                         diff = adaptivity->igi_target - (s8)IGI;
 997                         adaptivity->backup_l2h = p_dm_odm->th_l2h_ini + diff;
 998                         if (adaptivity->backup_l2h > 10)
 999                                 adaptivity->backup_l2h = 10;
1000
1001                         adaptivity->backup_h2l = adaptivity->backup_l2h - p_dm_odm->th_edcca_hl_diff;
1002
1003                         /*replace lower bound to prevent EDCCA always equal 1*/
1004                         if (adaptivity->backup_h2l < adaptivity->h2l_lb)
1005                                 adaptivity->backup_h2l = adaptivity->h2l_lb;
1006                         if (adaptivity->backup_l2h < adaptivity->l2h_lb)
1007                                 adaptivity->backup_l2h = adaptivity->l2h_lb;
1008                 }
1009 #endif
1010                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("pauseEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", adaptivity->backup_l2h, adaptivity->backup_h2l, IGI));
1011
1012                 /*Disable EDCCA*/
1013 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1014                 if (odm_is_work_item_scheduled(&(adaptivity->phydm_pause_edcca_work_item)) == false)
1015                         odm_schedule_work_item(&(adaptivity->phydm_pause_edcca_work_item));
1016 #else
1017                 phydm_pause_edcca_work_item_callback(p_dm_odm);
1018 #endif
1019
1020         } else {
1021
1022                 adaptivity->is_stop_edcca = false;
1023                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("resumeEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", adaptivity->backup_l2h, adaptivity->backup_h2l, IGI));
1024                 /*Resume EDCCA*/
1025 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1026                 if (odm_is_work_item_scheduled(&(adaptivity->phydm_resume_edcca_work_item)) == false)
1027                         odm_schedule_work_item(&(adaptivity->phydm_resume_edcca_work_item));
1028 #else
1029                 phydm_resume_edcca_work_item_callback(p_dm_odm);
1030 #endif
1031
1032         }
1033
1034 }
1035
1036
1037 void
1038 phydm_pause_edcca_work_item_callback(
1039 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1040         struct _ADAPTER         *adapter
1041 #else
1042         void                    *p_dm_void
1043 #endif
1044 )
1045 {
1046 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1047         PHAL_DATA_TYPE  p_hal_data = GET_HAL_DATA(adapter);
1048         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->DM_OutSrc;
1049 #else
1050         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
1051 #endif
1052
1053         if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES)
1054                 odm_set_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKBYTE2 | MASKBYTE0, (u32)(0x7f | 0x7f << 16));
1055 #if (RTL8195A_SUPPORT == 0)
1056         else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES)
1057                 odm_set_bb_reg(p_dm_odm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD, (u16)(0x7f | 0x7f << 8));
1058 #endif
1059
1060 }
1061
1062 void
1063 phydm_resume_edcca_work_item_callback(
1064 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1065         struct _ADAPTER         *adapter
1066 #else
1067         void                    *p_dm_void
1068 #endif
1069 )
1070 {
1071 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1072         PHAL_DATA_TYPE  p_hal_data = GET_HAL_DATA(adapter);
1073         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->DM_OutSrc;
1074 #else
1075         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
1076 #endif
1077         struct _ADAPTIVITY_STATISTICS   *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY);
1078
1079         if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES)
1080                 odm_set_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKBYTE2 | MASKBYTE0, (u32)((u8)adaptivity->backup_l2h | (u8)adaptivity->backup_h2l << 16));
1081 #if (RTL8195A_SUPPORT == 0)
1082         else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES)
1083                 odm_set_bb_reg(p_dm_odm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD, (u16)((u8)adaptivity->backup_l2h | (u8)adaptivity->backup_h2l << 8));
1084 #endif
1085
1086 }
1087
1088
1089 void
1090 phydm_set_edcca_threshold_api(
1091         void    *p_dm_void,
1092         u8      IGI
1093 )
1094 {
1095         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
1096         struct _ADAPTIVITY_STATISTICS   *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY);
1097         s8                      th_l2h_dmc, th_h2l_dmc;
1098         s8                      diff = 0, igi_target = 0x32;
1099
1100         if (p_dm_odm->support_ability & ODM_BB_ADAPTIVITY) {
1101                 if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
1102                         if (adaptivity->adajust_igi_level > IGI)
1103                                 diff = adaptivity->adajust_igi_level - IGI;
1104
1105                         th_l2h_dmc = p_dm_odm->th_l2h_ini - diff + igi_target;
1106                         th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff;
1107                 }
1108 #if (RTL8195A_SUPPORT == 0)
1109                 else    {
1110                         diff = igi_target - (s8)IGI;
1111                         th_l2h_dmc = p_dm_odm->th_l2h_ini + diff;
1112                         if (th_l2h_dmc > 10)
1113                                 th_l2h_dmc = 10;
1114
1115                         th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff;
1116
1117                         /*replace lower bound to prevent EDCCA always equal 1*/
1118                         if (th_h2l_dmc < adaptivity->h2l_lb)
1119                                 th_h2l_dmc = adaptivity->h2l_lb;
1120                         if (th_l2h_dmc < adaptivity->l2h_lb)
1121                                 th_l2h_dmc = adaptivity->l2h_lb;
1122                 }
1123 #endif
1124                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("API :IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n", IGI, th_l2h_dmc, th_h2l_dmc));
1125                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("API :adaptivity_igi_upper=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n", p_dm_odm->adaptivity_igi_upper, adaptivity->h2l_lb, adaptivity->l2h_lb));
1126
1127                 phydm_set_edcca_threshold(p_dm_odm, th_h2l_dmc, th_l2h_dmc);
1128         }
1129
1130 }