drivers/net/wireless/rockchip_wlan/rtl8723cs/hal/phydm/phydm.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20
  21
  22 #ifndef __HALDMOUTSRC_H__
  23 #define __HALDMOUTSRC_H__
  24
  25 /*============================================================*/
  26 /*include files*/
  27 /*============================================================*/
  28 #include "phydm_pre_define.h"
  29 #include "phydm_dig.h"
  30 #if PHYDM_SUPPORT_EDCA
  31 #include "phydm_edcaturbocheck.h"
  32 #endif
  33 #include "phydm_pathdiv.h"
  34 #include "phydm_antdiv.h"
  35 #include "phydm_antdect.h"
  36 #include "phydm_dynamicbbpowersaving.h"
  37 #include "phydm_rainfo.h"
  38 #include "phydm_dynamictxpower.h"
  39 #include "phydm_cfotracking.h"
  40 #include "phydm_acs.h"
  41 #include "phydm_adaptivity.h"
  42 #include "phydm_iqk.h"
  43 #include "phydm_dfs.h"
  44 #include "phydm_ccx.h"
  45 #include "txbf/phydm_hal_txbf_api.h"
  46
  47 #include "phydm_adc_sampling.h"
  48 #include "phydm_dynamic_rx_path.h"
  49 #include "phydm_psd.h"
  50
  51
  52 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
  53         #include "phydm_beamforming.h"
  54 #endif
  55
  56 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
  57         #include "halphyrf_ap.h"
  58 #endif
  59
  60 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
  61         #include "phydm_noisemonitor.h"
  62         #include "halphyrf_ce.h"
  63 #endif
  64
  65 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
  66         #include "halphyrf_win.h"
  67         #include "phydm_noisemonitor.h"
  68 #endif
  69
  70 /*============================================================*/
  71 /*Definition */
  72 /*============================================================*/
  73
  74 /* Traffic load decision */
  75 #define TRAFFIC_ULTRA_LOW       1
  76 #define TRAFFIC_LOW                     2
  77 #define TRAFFIC_MID                     3
  78 #define TRAFFIC_HIGH                    4
  79
  80 #define NONE                    0
  81
  82 /*NBI API------------------------------------*/
  83 #define NBI_ENABLE 1
  84 #define NBI_DISABLE 2
  85
  86 #define NBI_TABLE_SIZE_128      27
  87 #define NBI_TABLE_SIZE_256      59
  88
  89 #define NUM_START_CH_80M        7
  90 #define NUM_START_CH_40M        14
  91
  92 #define CH_OFFSET_40M           2
  93 #define CH_OFFSET_80M           6
  94
  95 /*CSI MASK API------------------------------------*/
  96 #define CSI_MASK_ENABLE 1
  97 #define CSI_MASK_DISABLE 2
  98
  99 /*------------------------------------------------*/
 100
 101 #define FFT_128_TYPE    1
 102 #define FFT_256_TYPE    2
 103
 104 #define SET_SUCCESS     1
 105 #define SET_ERROR               2
 106 #define SET_NO_NEED     3
 107
 108 #define FREQ_POSITIVE   1
 109 #define FREQ_NEGATIVE   2
 110
 111
 112 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
 113         #define PHYDM_WATCH_DOG_PERIOD  1
 114 #else
 115         #define PHYDM_WATCH_DOG_PERIOD  2
 116 #endif
 117
 118 /*============================================================*/
 119 /*structure and define*/
 120 /*============================================================*/
 121
 122 /*2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement.*/
 123 /*We need to remove to other position???*/
 124
 125 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
 126 struct rtl8192cd_priv {
 127                 u8              temp;
 128
 129         };
 130 #endif
 131
 132
 133 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
 134 struct _ADAPTER {
 135         u8              temp;
 136 #ifdef AP_BUILD_WORKAROUND
 137         HAL_DATA_TYPE           *temp2;
 138         struct rtl8192cd_priv           *priv;
 139 #endif
 140 };
 141 #endif
 142
 143 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
 144
 145 struct _WLAN_STA {
 146         u8              temp;
 147 };
 148
 149 #endif
 150
 151 struct _dynamic_primary_cca {
 152         u8      pri_cca_flag;
 153         u8      intf_flag;
 154         u8      intf_type;
 155         u8      dup_rts_flag;
 156         u8      monitor_flag;
 157         u8      CH_offset;
 158         u8      MF_state;
 159 };
 160
 161
 162 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
 163         #ifdef ADSL_AP_BUILD_WORKAROUND
 164                 #define MAX_TOLERANCE                   5
 165                 #define IQK_DELAY_TIME                  1               /*ms*/
 166         #endif
 167 #endif  /*#if(DM_ODM_SUPPORT_TYPE & (ODM_AP))*/
 168
 169 #define         dm_type_by_fw                   0
 170 #define         dm_type_by_driver               1
 171
 172 /*Declare for common info*/
 173
 174 #define IQK_THRESHOLD                   8
 175 #define DPK_THRESHOLD                   4
 176
 177
 178 #if (DM_ODM_SUPPORT_TYPE &  (ODM_AP))
 179 __PACK struct _odm_phy_status_info_ {
 180         u8              rx_pwdb_all;
 181         u8              signal_quality;                                 /* in 0-100 index. */
 182         u8              rx_mimo_signal_strength[4];             /* in 0~100 index */
 183         s8              rx_mimo_signal_quality[4];              /* EVM */
 184         s8              rx_snr[4];                                      /* per-path's SNR */
 185 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
 186         u8              rx_count:2;                                     /* RX path counter---*/
 187         u8              band_width:2;
 188         u8              rxsc:4;                                         /* sub-channel---*/
 189 #else
 190         u8              band_width;
 191 #endif
 192 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
 193         u8              channel;                                                /* channel number---*/
 194         boolean         is_mu_packet;                                   /* is MU packet or not---*/
 195         boolean         is_beamformed;                          /* BF packet---*/
 196 #endif
 197 };
 198
 199 struct _odm_phy_status_info_append_ {
 200         u8              MAC_CRC32;
 201
 202 };
 203
 204 #else
 205
 206 struct _odm_phy_status_info_ {
 207         /*  */
 208         /* Be care, if you want to add any element please insert between */
 209         /* rx_pwdb_all & signal_strength. */
 210         /*  */
 211 #if (DM_ODM_SUPPORT_TYPE &  (ODM_WIN))
 212         u32             rx_pwdb_all; /*in new Phy-status IC, represent the max PWDB among all path*/
 213 #else
 214         u8              rx_pwdb_all;
 215 #endif
 216         u8              signal_quality;                         /* in 0-100 index. */
 217         s8              rx_mimo_signal_quality[4];              /* per-path's EVM translate to 0~100% */
 218         u8              rx_mimo_evm_dbm[4];                     /* per-path's original EVM (dbm) */
 219         u8              rx_mimo_signal_strength[4];     /* in 0~100 index */
 220         s16             cfo_short[4];                           /* per-path's cfo_short */
 221         s16             cfo_tail[4];                                    /* per-path's cfo_tail */
 222         s8              rx_power;                                       /* in dBm Translate from PWdB */
 223         s8              recv_signal_power;                      /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */
 224         u8              bt_rx_rssi_percentage;
 225         u8              signal_strength;                                /* in 0-100 index. */
 226         s8              rx_pwr[4];                                      /* per-path's pwdb */
 227         s8              rx_snr[4];                                      /* per-path's SNR       */
 228         /* s8      BB_Backup[13];                   backup reg. */
 229 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
 230         u8              rx_count:2;                                     /* RX path counter---*/
 231         u8              band_width:2;
 232         u8              rxsc:4;                                         /* sub-channel---*/
 233 #else
 234         u8              band_width;
 235 #endif
 236 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
 237         u8              bt_coex_pwr_adjust;
 238 #endif
 239 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
 240         u8              channel;                                                /* channel number---*/
 241         boolean         is_mu_packet;                                   /* is MU packet or not---*/
 242         boolean         is_beamformed;                          /* BF packet---*/
 243 #endif
 244 };
 245 #endif
 246
 247 struct _odm_per_pkt_info_ {
 248         u8              data_rate;
 249         u8              station_id;
 250         boolean         is_packet_match_bssid;
 251         boolean         is_packet_to_self;
 252         boolean         is_packet_beacon;
 253         boolean         is_to_self;
 254         u8              ppdu_cnt;
 255 };
 256
 257
 258 struct _odm_phy_dbg_info_ {
 259         /*ODM Write,debug info*/
 260         s8              rx_snr_db[4];
 261         u32             num_qry_phy_status;
 262         u32             num_qry_phy_status_cck;
 263         u32             num_qry_phy_status_ofdm;
 264 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
 265         u32             num_qry_mu_pkt;
 266         u32             num_qry_bf_pkt;
 267         u32             num_qry_mu_vht_pkt[40];
 268         u32             num_qry_vht_pkt[40];
 269         boolean         is_ldpc_pkt;
 270         boolean         is_stbc_pkt;
 271         u8              num_of_ppdu[4];
 272         u8              gid_num[4];
 273 #endif
 274         u8              num_qry_beacon_pkt;
 275         /* Others */
 276         s32             rx_evm[4];
 277
 278 };
 279
 280
 281 /*2011/20/20 MH For MP driver RT_WLAN_STA =  struct sta_info*/
 282 /*Please declare below ODM relative info in your STA info structure.*/
 283
 284 #if 1
 285 struct _ODM_STA_INFO {
 286         /*Driver Write*/
 287         boolean         is_used;                        /*record the sta status link or not?*/
 288         u8              iot_peer;               /*Enum value.   HT_IOT_PEER_E*/
 289
 290         /*ODM Write*/
 291         /*PHY_STATUS_INFO*/
 292         u8              rssi_path[4];
 293         u8              rssi_ave;
 294         u8              RXEVM[4];
 295         u8              RXSNR[4];
 296
 297 };
 298 #endif
 299
 300 enum odm_cmninfo_e {
 301         /*Fixed value*/
 302         /*-----------HOOK BEFORE REG INIT-----------*/
 303         ODM_CMNINFO_PLATFORM = 0,
 304         ODM_CMNINFO_ABILITY,
 305         ODM_CMNINFO_INTERFACE,
 306         ODM_CMNINFO_MP_TEST_CHIP,
 307         ODM_CMNINFO_IC_TYPE,
 308         ODM_CMNINFO_CUT_VER,
 309         ODM_CMNINFO_FAB_VER,
 310         ODM_CMNINFO_RF_TYPE,
 311         ODM_CMNINFO_RFE_TYPE,
 312         ODM_CMNINFO_DPK_EN,
 313         ODM_CMNINFO_BOARD_TYPE,
 314         ODM_CMNINFO_PACKAGE_TYPE,
 315         ODM_CMNINFO_EXT_LNA,
 316         ODM_CMNINFO_5G_EXT_LNA,
 317         ODM_CMNINFO_EXT_PA,
 318         ODM_CMNINFO_5G_EXT_PA,
 319         ODM_CMNINFO_GPA,
 320         ODM_CMNINFO_APA,
 321         ODM_CMNINFO_GLNA,
 322         ODM_CMNINFO_ALNA,
 323         ODM_CMNINFO_EXT_TRSW,
 324         ODM_CMNINFO_EXT_LNA_GAIN,
 325         ODM_CMNINFO_PATCH_ID,
 326         ODM_CMNINFO_BINHCT_TEST,
 327         ODM_CMNINFO_BWIFI_TEST,
 328         ODM_CMNINFO_SMART_CONCURRENT,
 329         ODM_CMNINFO_CONFIG_BB_RF,
 330         ODM_CMNINFO_DOMAIN_CODE_2G,
 331         ODM_CMNINFO_DOMAIN_CODE_5G,
 332         ODM_CMNINFO_IQKFWOFFLOAD,
 333         ODM_CMNINFO_IQKPAOFF,
 334         ODM_CMNINFO_HUBUSBMODE,
 335         ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS,
 336         ODM_CMNINFO_TX_TP,
 337         ODM_CMNINFO_RX_TP,
 338         ODM_CMNINFO_SOUNDING_SEQ,
 339         ODM_CMNINFO_REGRFKFREEENABLE,
 340         ODM_CMNINFO_RFKFREEENABLE,
 341         ODM_CMNINFO_NORMAL_RX_PATH_CHANGE,
 342         ODM_CMNINFO_EFUSE0X3D8,
 343         ODM_CMNINFO_EFUSE0X3D7,
 344         /*-----------HOOK BEFORE REG INIT-----------*/
 345
 346         /*Dynamic value:*/
 347
 348         /*--------- POINTER REFERENCE-----------*/
 349         ODM_CMNINFO_MAC_PHY_MODE,
 350         ODM_CMNINFO_TX_UNI,
 351         ODM_CMNINFO_RX_UNI,
 352         ODM_CMNINFO_WM_MODE,
 353         ODM_CMNINFO_BAND,
 354         ODM_CMNINFO_SEC_CHNL_OFFSET,
 355         ODM_CMNINFO_SEC_MODE,
 356         ODM_CMNINFO_BW,
 357         ODM_CMNINFO_CHNL,
 358         ODM_CMNINFO_FORCED_RATE,
 359         ODM_CMNINFO_ANT_DIV,
 360         ODM_CMNINFO_ADAPTIVITY,
 361         ODM_CMNINFO_DMSP_GET_VALUE,
 362         ODM_CMNINFO_BUDDY_ADAPTOR,
 363         ODM_CMNINFO_DMSP_IS_MASTER,
 364         ODM_CMNINFO_SCAN,
 365         ODM_CMNINFO_POWER_SAVING,
 366         ODM_CMNINFO_ONE_PATH_CCA,
 367         ODM_CMNINFO_DRV_STOP,
 368         ODM_CMNINFO_PNP_IN,
 369         ODM_CMNINFO_INIT_ON,
 370         ODM_CMNINFO_ANT_TEST,
 371         ODM_CMNINFO_NET_CLOSED,
 372         ODM_CMNINFO_FORCED_IGI_LB,
 373         ODM_CMNINFO_P2P_LINK,
 374         ODM_CMNINFO_FCS_MODE,
 375         ODM_CMNINFO_IS1ANTENNA,
 376         ODM_CMNINFO_RFDEFAULTPATH,
 377         ODM_CMNINFO_DFS_MASTER_ENABLE,
 378         ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC,
 379         ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA,
 380         /*--------- POINTER REFERENCE-----------*/
 381
 382         /*------------CALL BY VALUE-------------*/
 383         ODM_CMNINFO_WIFI_DIRECT,
 384         ODM_CMNINFO_WIFI_DISPLAY,
 385         ODM_CMNINFO_LINK_IN_PROGRESS,
 386         ODM_CMNINFO_LINK,
 387         ODM_CMNINFO_CMW500LINK,
 388         ODM_CMNINFO_LPSPG,
 389         ODM_CMNINFO_STATION_STATE,
 390         ODM_CMNINFO_RSSI_MIN,
 391         ODM_CMNINFO_DBG_COMP,
 392         ODM_CMNINFO_DBG_LEVEL,
 393         ODM_CMNINFO_RA_THRESHOLD_HIGH,
 394         ODM_CMNINFO_RA_THRESHOLD_LOW,
 395         ODM_CMNINFO_RF_ANTENNA_TYPE,
 396         ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH,
 397         ODM_CMNINFO_BE_FIX_TX_ANT,
 398         ODM_CMNINFO_BT_ENABLED,
 399         ODM_CMNINFO_BT_HS_CONNECT_PROCESS,
 400         ODM_CMNINFO_BT_HS_RSSI,
 401         ODM_CMNINFO_BT_OPERATION,
 402         ODM_CMNINFO_BT_LIMITED_DIG,
 403         ODM_CMNINFO_BT_DIG,
 404         ODM_CMNINFO_BT_BUSY,
 405         ODM_CMNINFO_BT_DISABLE_EDCA,
 406 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)              /*for repeater mode add by YuChen 2014.06.23*/
 407 #ifdef UNIVERSAL_REPEATER
 408         ODM_CMNINFO_VXD_LINK,
 409 #endif
 410 #endif
 411         ODM_CMNINFO_AP_TOTAL_NUM,
 412         ODM_CMNINFO_POWER_TRAINING,
 413         ODM_CMNINFO_DFS_REGION_DOMAIN,
 414         /*------------CALL BY VALUE-------------*/
 415
 416         /*Dynamic ptr array hook itms.*/
 417         ODM_CMNINFO_STA_STATUS,
 418         ODM_CMNINFO_MAX,
 419
 420 };
 421
 422
 423 enum phydm_info_query_e {
 424         PHYDM_INFO_FA_OFDM,
 425         PHYDM_INFO_FA_CCK,
 426         PHYDM_INFO_FA_TOTAL,
 427         PHYDM_INFO_CCA_OFDM,
 428         PHYDM_INFO_CCA_CCK,
 429         PHYDM_INFO_CCA_ALL,
 430         PHYDM_INFO_CRC32_OK_VHT,
 431         PHYDM_INFO_CRC32_OK_HT,
 432         PHYDM_INFO_CRC32_OK_LEGACY,
 433         PHYDM_INFO_CRC32_OK_CCK,
 434         PHYDM_INFO_CRC32_ERROR_VHT,
 435         PHYDM_INFO_CRC32_ERROR_HT,
 436         PHYDM_INFO_CRC32_ERROR_LEGACY,
 437         PHYDM_INFO_CRC32_ERROR_CCK,
 438         PHYDM_INFO_EDCCA_FLAG,
 439         PHYDM_INFO_OFDM_ENABLE,
 440         PHYDM_INFO_CCK_ENABLE,
 441         PHYDM_INFO_DBG_PORT_0
 442 };
 443
 444 enum phydm_api_e {
 445
 446         PHYDM_API_NBI                   = 1,
 447         PHYDM_API_CSI_MASK,
 448
 449 };
 450
 451
 452 /*2011/10/20 MH Define ODM support ability.  ODM_CMNINFO_ABILITY*/
 453 enum odm_ability_e {
 454
 455         /*BB ODM section BIT 0-19*/
 456         ODM_BB_DIG                                      = BIT(0),
 457         ODM_BB_RA_MASK                          = BIT(1),
 458         ODM_BB_DYNAMIC_TXPWR            = BIT(2),
 459         ODM_BB_FA_CNT                                   = BIT(3),
 460         ODM_BB_RSSI_MONITOR                     = BIT(4),
 461         ODM_BB_CCK_PD                                   = BIT(5),
 462         ODM_BB_ANT_DIV                          = BIT(6),
 463         ODM_BB_PWR_TRAIN                                = BIT(8),
 464         ODM_BB_RATE_ADAPTIVE                    = BIT(9),
 465         ODM_BB_PATH_DIV                         = BIT(10),
 466         ODM_BB_ADAPTIVITY                               = BIT(13),
 467         ODM_BB_CFO_TRACKING                     = BIT(14),
 468         ODM_BB_NHM_CNT                          = BIT(15),
 469         ODM_BB_PRIMARY_CCA                      = BIT(16),
 470         ODM_BB_TXBF                                     = BIT(17),
 471         ODM_BB_DYNAMIC_ARFR                     = BIT(18),
 472
 473         ODM_MAC_EDCA_TURBO                      = BIT(20),
 474         ODM_BB_DYNAMIC_RX_PATH          = BIT(21),
 475
 476         /*RF ODM section BIT 24-31*/
 477         ODM_RF_TX_PWR_TRACK                     = BIT(24),
 478         ODM_RF_RX_GAIN_TRACK                    = BIT(25),
 479         ODM_RF_CALIBRATION                      = BIT(26),
 480
 481 };
 482
 483
 484 /*ODM_CMNINFO_ONE_PATH_CCA*/
 485 enum odm_cca_path_e {
 486         ODM_CCA_2R              = 0,
 487         ODM_CCA_1R_A            = 1,
 488         ODM_CCA_1R_B            = 2,
 489 };
 490
 491 enum cca_pathdiv_en_e {
 492         CCA_PATHDIV_DISABLE             = 0,
 493         CCA_PATHDIV_ENABLE              = 1,
 494
 495 };
 496
 497
 498 enum phy_reg_pg_type {
 499         PHY_REG_PG_RELATIVE_VALUE = 0,
 500         PHY_REG_PG_EXACT_VALUE = 1
 501 };
 502
 503 /*2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration.*/
 504
 505 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 506         #if (RT_PLATFORM != PLATFORM_LINUX)
 507                 typedef
 508         #endif
 509
 510         struct PHY_DM_STRUCT
 511 #else/*for AP,ADSL,CE Team*/
 512         struct PHY_DM_STRUCT
 513 #endif
 514 {
 515         /*Add for different team use temporarily*/
 516         struct _ADAPTER         *adapter;               /*For CE/NIC team*/
 517         struct rtl8192cd_priv   *priv;                  /*For AP/ADSL team*/
 518         /*WHen you use adapter or priv pointer, you must make sure the pointer is ready.*/
 519         boolean                 odm_ready;
 520
 521 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
 522         struct rtl8192cd_priv           fake_priv;
 523 #endif
 524 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
 525         /* ADSL_AP_BUILD_WORKAROUND */
 526         struct _ADAPTER                 fake_adapter;
 527 #endif
 528
 529         enum phy_reg_pg_type            phy_reg_pg_value_type;
 530         u8                              phy_reg_pg_version;
 531
 532         u32                     debug_components;
 533         u32                     fw_debug_components;
 534         u32                     debug_level;
 535
 536         u32                     num_qry_phy_status_all;         /*CCK + OFDM*/
 537         u32                     last_num_qry_phy_status_all;
 538         u32                     rx_pwdb_ave;
 539         boolean                 MPDIG_2G;                               /*off MPDIG*/
 540         u8                      times_2g;
 541         boolean                 is_init_hw_info_by_rfe;
 542
 543         /*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
 544         boolean                 is_cck_high_power;
 545         u8                      rf_path_rx_enable;
 546         u8                      control_channel;
 547         /*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
 548
 549
 550         /* 1  COMMON INFORMATION */
 551
 552         /*Init value*/
 553         /*-----------HOOK BEFORE REG INIT-----------*/
 554         /*ODM Platform info AP/ADSL/CE/MP = 1/2/3/4*/
 555         u8                      support_platform;
 556         /* ODM Platform info WIN/AP/CE = 1/2/3 */
 557         u8                      normal_rx_path;
 558         /*ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K*/
 559         u32                     support_ability;
 560         /*ODM PCIE/USB/SDIO = 1/2/3*/
 561         u8                      support_interface;
 562         /*ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/...*/
 563         u32                     support_ic_type;
 564         /*cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/
 565         u8                      cut_version;
 566         /*Fab version TSMC/UMC = 0/1*/
 567         u8                      fab_version;
 568         /*RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/
 569         u8                      rf_type;
 570         u8                      rfe_type;
 571         /*Board type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/...*/
 572         /*Enable Function DPK OFF/ON = 0/1*/
 573         u8                      dpk_en;
 574         u8                      board_type;
 575         u8                      package_type;
 576         u16                     type_glna;
 577         u16                     type_gpa;
 578         u16                     type_alna;
 579         u16                     type_apa;
 580         /*with external LNA  NO/Yes = 0/1*/
 581         u8                      ext_lna;                /*2G*/
 582         u8                      ext_lna_5g;     /*5G*/
 583         /*with external PA  NO/Yes = 0/1*/
 584         u8                      ext_pa;         /*2G*/
 585         u8                      ext_pa_5g;      /*5G*/
 586         /*with Efuse number*/
 587         u8                      efuse0x3d7;
 588         u8                      efuse0x3d8;
 589         /*with external TRSW  NO/Yes = 0/1*/
 590         u8                      ext_trsw;
 591         u8                      ext_lna_gain;   /*2G*/
 592         u8                      patch_id;       /*Customer ID*/
 593         boolean                 is_in_hct_test;
 594         u8                      wifi_test;
 595
 596         boolean                 is_dual_mac_smart_concurrent;
 597         u32                     bk_support_ability;
 598         u8                      ant_div_type;
 599         u8                      with_extenal_ant_switch;
 600         boolean                 config_bbrf;
 601         u8                      odm_regulation_2_4g;
 602         u8                      odm_regulation_5g;
 603         u8                      iqk_fw_offload;
 604         boolean                 cck_new_agc;
 605         u8                      phydm_period;
 606         u32                     phydm_sys_up_time;
 607         u8                      num_rf_path;
 608         /*-----------HOOK BEFORE REG INIT-----------*/
 609
 610         /*Dynamic value*/
 611
 612         /*--------- POINTER REFERENCE-----------*/
 613
 614         u8                      u1_byte_temp;
 615         boolean                 BOOLEAN_temp;
 616         struct _ADAPTER         *PADAPTER_temp;
 617
 618         /*MAC PHY mode SMSP/DMSP/DMDP = 0/1/2*/
 619         u8                      *p_mac_phy_mode;
 620         /*TX Unicast byte count*/
 621         u64                     *p_num_tx_bytes_unicast;
 622         /*RX Unicast byte count*/
 623         u64                     *p_num_rx_bytes_unicast;
 624         /*Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3*/
 625         u8                      *p_wireless_mode;
 626         /*Frequence band 2.4G/5G = 0/1*/
 627         u8                      *p_band_type;
 628         /*Secondary channel offset don't_care/below/above = 0/1/2*/
 629         u8                      *p_sec_ch_offset;
 630         /*security mode Open/WEP/AES/TKIP = 0/1/2/3*/
 631         u8                      *p_security;
 632         /*BW info 20M/40M/80M = 0/1/2*/
 633         u8                      *p_band_width;
 634         /*Central channel location Ch1/Ch2/....*/
 635         u8                      *p_channel;                     /*central channel number*/
 636         boolean                 dpk_done;
 637         /*Common info for 92D DMSP*/
 638
 639         boolean                 *p_is_get_value_from_other_mac;
 640         struct _ADAPTER **p_buddy_adapter;
 641         boolean                 *p_is_master_of_dmsp; /* MAC0: master, MAC1: slave */
 642         /*Common info for status*/
 643         boolean                 *p_is_scan_in_process;
 644         boolean                 *p_is_power_saving;
 645         /*CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path_e.*/
 646         u8                      *p_one_path_cca;
 647         u8                      *p_antenna_test;
 648         boolean                 *p_is_net_closed;
 649         u8                      *pu1_forced_igi_lb;
 650         boolean                 *p_is_fcs_mode_enable;
 651         /*--------- For 8723B IQK-----------*/
 652         boolean                 *p_is_1_antenna;
 653         u8                      *p_rf_default_path;
 654         /* 0:S1, 1:S0 */
 655
 656         /*--------- POINTER REFERENCE-----------*/
 657         u16                     *p_forced_data_rate;
 658         u8                      *p_enable_antdiv;
 659         u8                      *p_enable_adaptivity;
 660         u8                      *hub_usb_mode;
 661         boolean                 *p_is_fw_dw_rsvd_page_in_progress;
 662         u32                     *p_current_tx_tp;
 663         u32                     *p_current_rx_tp;
 664         u8                      *p_sounding_seq;
 665         /*------------CALL BY VALUE-------------*/
 666         boolean                 is_link_in_process;
 667         boolean                 is_wifi_direct;
 668         boolean                 is_wifi_display;
 669         boolean                 is_linked;
 670         boolean                 bLinkedcmw500;
 671         boolean                 is_in_lps_pg;
 672         boolean                 bsta_state;
 673 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)              /*for repeater mode add by YuChen 2014.06.23*/
 674 #ifdef UNIVERSAL_REPEATER
 675         boolean                 vxd_linked;
 676 #endif
 677 #endif
 678         u8                      rssi_min;
 679         u8                      interface_index;                /*Add for 92D  dual MAC: 0--Mac0 1--Mac1*/
 680         boolean                 is_mp_chip;
 681         boolean                 is_one_entry_only;
 682         boolean                 mp_mode;
 683         u32                     one_entry_macid;
 684         u8                      pre_number_linked_client;
 685         u8                      number_linked_client;
 686         u8                      pre_number_active_client;
 687         u8                      number_active_client;
 688         /*Common info for BTDM*/
 689         boolean                 is_bt_enabled;                  /*BT is enabled*/
 690         boolean                 is_bt_connect_process;  /*BT HS is under connection progress.*/
 691         u8                      bt_hs_rssi;                     /*BT HS mode wifi rssi value.*/
 692         boolean                 is_bt_hs_operation;             /*BT HS mode is under progress*/
 693         u8                      bt_hs_dig_val;                  /*use BT rssi to decide the DIG value*/
 694         boolean                 is_bt_disable_edca_turbo;       /*Under some condition, don't enable the EDCA Turbo*/
 695         boolean                 is_bt_busy;                     /*BT is busy.*/
 696         boolean                 is_bt_limited_dig;              /*BT is busy.*/
 697         boolean                 is_disable_phy_api;
 698         /*------------CALL BY VALUE-------------*/
 699         u8                      RSSI_A;
 700         u8                      RSSI_B;
 701         u8                      RSSI_C;
 702         u8                      RSSI_D;
 703         u64                     RSSI_TRSW;
 704         u64                     RSSI_TRSW_H;
 705         u64                     RSSI_TRSW_L;
 706         u64                     RSSI_TRSW_iso;
 707         u8                      tx_ant_status;
 708         u8                      rx_ant_status;
 709         u8                      cck_lna_idx;
 710         u8                      cck_vga_idx;
 711         u8                      curr_station_id;
 712         u8                      ofdm_agc_idx[4];
 713
 714         u8                      rx_rate;
 715         boolean                 is_noisy_state;
 716         u8                      tx_rate;
 717         u8                      linked_interval;
 718         u8                      pre_channel;
 719         u32                     txagc_offset_value_a;
 720         boolean                 is_txagc_offset_positive_a;
 721         u32                     txagc_offset_value_b;
 722         boolean                 is_txagc_offset_positive_b;
 723         u32                     tx_tp;
 724         u32                     rx_tp;
 725         u32                     total_tp;
 726         u64                     cur_tx_ok_cnt;
 727         u64                     cur_rx_ok_cnt;
 728         u64                     last_tx_ok_cnt;
 729         u64                     last_rx_ok_cnt;
 730         u32                     bb_swing_offset_a;
 731         boolean                 is_bb_swing_offset_positive_a;
 732         u32                     bb_swing_offset_b;
 733         boolean                 is_bb_swing_offset_positive_b;
 734         u8                      igi_lower_bound;
 735         u8                      igi_upper_bound;
 736         u8                      antdiv_rssi;
 737         u8                      fat_comb_a;
 738         u8                      fat_comb_b;
 739         u8                      antdiv_intvl;
 740         u8                      ant_type;
 741         u8                      pre_ant_type;
 742         u8                      antdiv_period;
 743         u8                      evm_antdiv_period;
 744         u8                      antdiv_select;
 745         u8                      path_select;
 746         u8                      antdiv_evm_en;
 747         u8                      bdc_holdstate;
 748         u8                      ndpa_period;
 749         boolean                 h2c_rarpt_connect;
 750         boolean                 cck_agc_report_type;
 751
 752         u8                      dm_dig_max_TH;
 753         u8                      dm_dig_min_TH;
 754         u8                      print_agc;
 755         u8                      traffic_load;
 756         u8                      pre_traffic_load;
 757         /*8821C Antenna BTG/WLG/WLA Select*/
 758         u8                      current_rf_set_8821c;
 759         u8                      default_rf_set_8821c;
 760         /*For Adaptivtiy*/
 761         u16                     nhm_cnt_0;
 762         u16                     nhm_cnt_1;
 763         s8                      TH_L2H_default;
 764         s8                      th_edcca_hl_diff_default;
 765         s8                      th_l2h_ini;
 766         s8                      th_edcca_hl_diff;
 767         s8                      th_l2h_ini_mode2;
 768         s8                      th_edcca_hl_diff_mode2;
 769         boolean         carrier_sense_enable;
 770         u8                      adaptivity_igi_upper;
 771         boolean         adaptivity_flag;
 772         u8                      dc_backoff;
 773         boolean         adaptivity_enable;
 774         u8                      ap_total_num;
 775         boolean         edcca_enable;
 776         u8                      pre_dbg_priority;
 777         struct _ADAPTIVITY_STATISTICS   adaptivity;
 778         /*For Adaptivtiy*/
 779         u8                      last_usb_hub;
 780         u8                      tx_bf_data_rate;
 781
 782         u8                      nbi_set_result;
 783
 784         u8                      c2h_cmd_start;
 785         u8                      fw_debug_trace[60];
 786         u8                      pre_c2h_seq;
 787         boolean                 fw_buff_is_enpty;
 788         u32                     data_frame_num;
 789
 790         /*for noise detection*/
 791         boolean                 noisy_decision; /*b_noisy*/
 792         boolean                 pre_b_noisy;
 793         u32                     noisy_decision_smooth;
 794         boolean                 is_disable_dym_ecs;
 795
 796 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
 797         struct _ODM_NOISE_MONITOR_ noise_level;
 798 #endif
 799         /*Define STA info.*/
 800         /*_ODM_STA_INFO*/
 801         /*2012/01/12 MH For MP, we need to reduce one array pointer for default port.??*/
 802         struct sta_info         *p_odm_sta_info[ODM_ASSOCIATE_ENTRY_NUM];
 803         u16                     platform2phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];
 804         /* platform_macid_table[platform_macid] = phydm_macid */
 805 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
 806         s32                     accumulate_pwdb[ODM_ASSOCIATE_ENTRY_NUM];
 807 #endif
 808
 809 #if (RATE_ADAPTIVE_SUPPORT == 1)
 810         u16                     currmin_rpt_time;
 811         struct _odm_ra_info_   ra_info[ODM_ASSOCIATE_ENTRY_NUM];
 812         /*Use mac_id as array index. STA mac_id=0, VWiFi Client mac_id={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119*/
 813 #endif
 814
 815         /*2012/02/14 MH Add to share 88E ra with other SW team.*/
 816         /*We need to colelct all support abilit to a proper area.*/
 817
 818         boolean                         ra_support88e;
 819
 820         struct _odm_phy_dbg_info_        phy_dbg_info;
 821
 822         /*ODM Structure*/
 823 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
 824 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
 825         struct _BF_DIV_COEX_                                    dm_bdc_table;
 826 #endif
 827
 828 #if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2))
 829         struct _SMART_ANTENNA_TRAINNING_        dm_sat_table;
 830 #endif
 831
 832 #endif
 833         struct _FAST_ANTENNA_TRAINNING_         dm_fat_table;
 834         struct _dynamic_initial_gain_threshold_ dm_dig_table;
 835 #if (defined(CONFIG_BB_POWER_SAVING))
 836         struct _dynamic_power_saving                    dm_ps_table;
 837 #endif
 838         struct _dynamic_primary_cca                     dm_pri_cca;
 839         struct _rate_adaptive_table_                    dm_ra_table;
 840         struct _FALSE_ALARM_STATISTICS          false_alm_cnt;
 841         struct _FALSE_ALARM_STATISTICS          flase_alm_cnt_buddy_adapter;
 842         struct _sw_antenna_switch_                              dm_swat_table;
 843         struct _CFO_TRACKING_                           dm_cfo_track;
 844         struct _ACS_                                                    dm_acs;
 845         struct _CCX_INFO                                                dm_ccx_info;
 846 #if (CONFIG_PSD_TOOL == 1)
 847         struct  _PHYDM_PSD_                             dm_psd_table;
 848 #endif
 849
 850 #if (PHYDM_LA_MODE_SUPPORT == 1)
 851         struct _RT_ADCSMP                                       adcsmp;
 852 #endif
 853 #if (CONFIG_DYNAMIC_RX_PATH == 1)
 854         struct _DYNAMIC_RX_PATH_                        dm_drp_table;
 855 #endif
 856
 857 #if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
 858         struct _IQK_INFORMATION IQK_info;
 859 #endif
 860
 861 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 862         /*path Div Struct*/
 863         struct _path_div_parameter_define_      path_iqk;
 864 #endif
 865 #if (defined(CONFIG_PATH_DIVERSITY))
 866         struct _ODM_PATH_DIVERSITY_     dm_path_div;
 867 #endif
 868
 869 #if PHYDM_SUPPORT_EDCA
 870         struct _EDCA_TURBO_             dm_edca_table;
 871         u32             WMMEDCA_BE;
 872 #endif
 873
 874         boolean                 *p_is_driver_stopped;
 875         boolean                 *p_is_driver_is_going_to_pnp_set_power_sleep;
 876         boolean                 *pinit_adpt_in_progress;
 877
 878         /*PSD*/
 879         boolean                 is_user_assign_level;
 880         u8                      RSSI_BT;                                /*come from BT*/
 881         boolean                 is_psd_in_process;
 882         boolean                 is_psd_active;
 883         boolean                 is_dm_initial_gain_enable;
 884
 885         /*MPT DIG*/
 886         struct timer_list               mpt_dig_timer;
 887
 888         /*for rate adaptive, in fact,  88c/92c fw will handle this*/
 889         u8                      is_use_ra_mask;
 890
 891         /* for dynamic SoML control */
 892         boolean                 bsomlenabled;
 893
 894         struct _ODM_RATE_ADAPTIVE       rate_adaptive;
 895 #if (defined(CONFIG_ANT_DETECTION))
 896         struct _ANT_DETECTED_INFO       ant_detected_info;      /* Antenna detected information for RSSI tool*/
 897 #endif
 898         struct odm_rf_calibration_structure     rf_calibrate_info;
 899         u32                     n_iqk_cnt;
 900         u32                     n_iqk_ok_cnt;
 901         u32                     n_iqk_fail_cnt;
 902
 903 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
 904         /*Power Training*/
 905         u8                      force_power_training_state;
 906         boolean                 is_change_state;
 907         u32                     PT_score;
 908         u64                     ofdm_rx_cnt;
 909         u64                     cck_rx_cnt;
 910 #endif
 911         boolean                 is_disable_power_training;
 912         u8                      dynamic_tx_high_power_lvl;
 913         u8                      last_dtp_lvl;
 914         u32                     tx_agc_ofdm_18_6;
 915         u8                      rx_pkt_type;
 916
 917         /*ODM relative time.*/
 918         struct timer_list       path_div_switch_timer;
 919         /*2011.09.27 add for path Diversity*/
 920         struct timer_list       cck_path_diversity_timer;
 921         struct timer_list       fast_ant_training_timer;
 922 #ifdef ODM_EVM_ENHANCE_ANTDIV
 923         struct timer_list                       evm_fast_ant_training_timer;
 924 #endif
 925         struct timer_list               sbdcnt_timer;
 926
 927         /*ODM relative workitem.*/
 928 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 929 #if USE_WORKITEM
 930         RT_WORK_ITEM                    path_div_switch_workitem;
 931         RT_WORK_ITEM                    cck_path_diversity_workitem;
 932         RT_WORK_ITEM                    fast_ant_training_workitem;
 933         RT_WORK_ITEM                    mpt_dig_workitem;
 934         RT_WORK_ITEM                    ra_rpt_workitem;
 935         RT_WORK_ITEM                    sbdcnt_workitem;
 936 #endif
 937 #endif
 938
 939 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
 940 #if (BEAMFORMING_SUPPORT == 1)
 941         struct _RT_BEAMFORMING_INFO beamforming_info;
 942 #endif
 943 #endif
 944
 945 #ifdef CONFIG_PHYDM_DFS_MASTER
 946         u8 dfs_region_domain;
 947         u8 *dfs_master_enabled;
 948
 949         /*====== phydm_radar_detect_with_dbg_parm start ======*/
 950         u8 radar_detect_dbg_parm_en;
 951         u32 radar_detect_reg_918;
 952         u32 radar_detect_reg_91c;
 953         u32 radar_detect_reg_920;
 954         u32 radar_detect_reg_924;
 955         /*====== phydm_radar_detect_with_dbg_parm end ======*/
 956 #endif
 957
 958 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 959
 960 #if (RT_PLATFORM != PLATFORM_LINUX)
 961 }PHY_DM_STRUCT;         /*DM_Dynamic_Mechanism_Structure*/
 962 #else
 963 };
 964 #endif
 965
 966 #else   /*for AP,ADSL,CE Team*/
 967 };
 968 #endif
 969
 970
 971 enum phydm_structure_type {
 972         PHYDM_FALSEALMCNT,
 973         PHYDM_CFOTRACK,
 974         PHYDM_ADAPTIVITY,
 975         PHYDM_ROMINFO,
 976
 977 };
 978
 979
 980
 981 enum odm_rf_content {
 982         odm_radioa_txt = 0x1000,
 983         odm_radiob_txt = 0x1001,
 984         odm_radioc_txt = 0x1002,
 985         odm_radiod_txt = 0x1003
 986 };
 987
 988 enum odm_bb_config_type {
 989         CONFIG_BB_PHY_REG,
 990         CONFIG_BB_AGC_TAB,
 991         CONFIG_BB_AGC_TAB_2G,
 992         CONFIG_BB_AGC_TAB_5G,
 993         CONFIG_BB_PHY_REG_PG,
 994         CONFIG_BB_PHY_REG_MP,
 995         CONFIG_BB_AGC_TAB_DIFF,
 996 };
 997
 998 enum odm_rf_config_type {
 999         CONFIG_RF_RADIO,
1000         CONFIG_RF_TXPWR_LMT,
1001 };
1002
1003 enum odm_fw_config_type {
1004         CONFIG_FW_NIC,
1005         CONFIG_FW_NIC_2,
1006         CONFIG_FW_AP,
1007         CONFIG_FW_AP_2,
1008         CONFIG_FW_MP,
1009         CONFIG_FW_WOWLAN,
1010         CONFIG_FW_WOWLAN_2,
1011         CONFIG_FW_AP_WOWLAN,
1012         CONFIG_FW_BT,
1013 };
1014
1015 /*status code*/
1016 #if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
1017 enum rt_status {
1018         RT_STATUS_SUCCESS,
1019         RT_STATUS_FAILURE,
1020         RT_STATUS_PENDING,
1021         RT_STATUS_RESOURCE,
1022         RT_STATUS_INVALID_CONTEXT,
1023         RT_STATUS_INVALID_PARAMETER,
1024         RT_STATUS_NOT_SUPPORT,
1025         RT_STATUS_OS_API_FAILED,
1026 };
1027 #endif  /*end of enum rt_status definition*/
1028
1029 #ifdef REMOVE_PACK
1030         #pragma pack()
1031 #endif
1032
1033 /*===========================================================*/
1034 /*AGC RX High Power mode*/
1035 /*===========================================================*/
1036 #define          lna_low_gain_1                      0x64
1037 #define          lna_low_gain_2                      0x5A
1038 #define          lna_low_gain_3                      0x58
1039
1040 #define          FA_RXHP_TH1                           5000
1041 #define          FA_RXHP_TH2                           1500
1042 #define          FA_RXHP_TH3                             800
1043 #define          FA_RXHP_TH4                             600
1044 #define          FA_RXHP_TH5                             500
1045
1046 enum dm_1r_cca_e {
1047         CCA_1R = 0,
1048         CCA_2R = 1,
1049         CCA_MAX = 2,
1050 };
1051
1052 enum dm_rf_e {
1053         rf_save = 0,
1054         rf_normal = 1,
1055         RF_MAX = 2,
1056 };
1057
1058 /*check Sta pointer valid or not*/
1059
1060 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1061         #define IS_STA_VALID(p_sta)             (p_sta && p_sta->expire_to)
1062 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1063         #define IS_STA_VALID(p_sta)             (p_sta && p_sta->bUsed)
1064 #else
1065         #define IS_STA_VALID(p_sta)             (p_sta)
1066 #endif
1067
1068 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP))
1069
1070 boolean
1071 odm_check_power_status(
1072         struct _ADAPTER         *adapter
1073 );
1074
1075 #endif
1076
1077 u32 odm_convert_to_db(u32 value);
1078
1079 u32 odm_convert_to_linear(u32 value);
1080
1081 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1082 void
1083 odm_dm_watchdog_lps(
1084         struct PHY_DM_STRUCT            *p_dm_odm
1085 );
1086 #endif
1087
1088
1089 s32
1090 odm_pwdb_conversion(
1091         s32 X,
1092         u32 total_bit,
1093         u32 decimal_bit
1094 );
1095
1096 s32
1097 odm_sign_conversion(
1098         s32 value,
1099         u32 total_bit
1100 );
1101
1102 void
1103 odm_init_mp_driver_status(
1104         struct PHY_DM_STRUCT            *p_dm_odm
1105 );
1106
1107 void
1108 phydm_txcurrentcalibration(
1109         struct PHY_DM_STRUCT    *p_dm_odm
1110 );
1111
1112
1113 void
1114 phydm_seq_sorting(
1115         void    *p_dm_void,
1116         u32     *p_value,
1117         u32     *rank_idx,
1118         u32     *p_idx_out,
1119         u8      seq_length
1120 );
1121
1122 void
1123 odm_dm_init(
1124         struct PHY_DM_STRUCT    *p_dm_odm
1125 );
1126
1127 void
1128 odm_dm_reset(
1129         struct PHY_DM_STRUCT    *p_dm_odm
1130 );
1131
1132 void
1133 phydm_support_ability_debug(
1134         void            *p_dm_void,
1135         u32             *const dm_value,
1136         u32                     *_used,
1137         char                            *output,
1138         u32                     *_out_len
1139 );
1140
1141 void
1142 phydm_config_ofdm_rx_path(
1143         struct PHY_DM_STRUCT            *p_dm_odm,
1144         u32                     path
1145 );
1146
1147 void
1148 phydm_config_trx_path(
1149         void            *p_dm_void,
1150         u32             *const dm_value,
1151         u32                     *_used,
1152         char                    *output,
1153         u32                     *_out_len
1154 );
1155
1156 void
1157 odm_dm_watchdog(
1158         struct PHY_DM_STRUCT                    *p_dm_odm
1159 );
1160
1161 void
1162 phydm_watchdog_mp(
1163         struct PHY_DM_STRUCT            *p_dm_odm
1164 );
1165
1166 void
1167 odm_cmn_info_init(
1168         struct PHY_DM_STRUCT            *p_dm_odm,
1169         enum odm_cmninfo_e      cmn_info,
1170         u32                     value
1171 );
1172
1173 void
1174 odm_cmn_info_hook(
1175         struct PHY_DM_STRUCT            *p_dm_odm,
1176         enum odm_cmninfo_e      cmn_info,
1177         void                    *p_value
1178 );
1179
1180 void
1181 odm_cmn_info_ptr_array_hook(
1182         struct PHY_DM_STRUCT            *p_dm_odm,
1183         enum odm_cmninfo_e      cmn_info,
1184         u16                     index,
1185         void                    *p_value
1186 );
1187
1188 void
1189 odm_cmn_info_update(
1190         struct PHY_DM_STRUCT            *p_dm_odm,
1191         u32                     cmn_info,
1192         u64                     value
1193 );
1194
1195 u32
1196 phydm_cmn_info_query(
1197         struct PHY_DM_STRUCT                                    *p_dm_odm,
1198         enum phydm_info_query_e                 info_type
1199 );
1200
1201 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
1202 void
1203 odm_init_all_threads(
1204         struct PHY_DM_STRUCT    *p_dm_odm
1205 );
1206
1207 void
1208 odm_stop_all_threads(
1209         struct PHY_DM_STRUCT    *p_dm_odm
1210 );
1211 #endif
1212
1213 void
1214 odm_init_all_timers(
1215         struct PHY_DM_STRUCT    *p_dm_odm
1216 );
1217
1218 void
1219 odm_cancel_all_timers(
1220         struct PHY_DM_STRUCT    *p_dm_odm
1221 );
1222
1223 void
1224 odm_release_all_timers(
1225         struct PHY_DM_STRUCT    *p_dm_odm
1226 );
1227
1228
1229 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1230 void odm_init_all_work_items(struct PHY_DM_STRUCT       *p_dm_odm);
1231 void odm_free_all_work_items(struct PHY_DM_STRUCT       *p_dm_odm);
1232
1233 u64
1234 platform_division64(
1235         u64     x,
1236         u64     y
1237 );
1238
1239 #define dm_change_dynamic_init_gain_thresh              odm_change_dynamic_init_gain_thresh
1240
1241 enum dm_dig_connect_e {
1242         DIG_STA_DISCONNECT = 0,
1243         DIG_STA_CONNECT = 1,
1244         DIG_STA_BEFORE_CONNECT = 2,
1245         DIG_MULTI_STA_DISCONNECT = 3,
1246         DIG_MULTI_STA_CONNECT = 4,
1247         DIG_CONNECT_MAX
1248 };
1249
1250 /*2012/01/12 MH Check afapter status. Temp fix BSOD.*/
1251
1252 #define HAL_ADAPTER_STS_CHK(p_dm_odm) do {\
1253                 if (p_dm_odm->adapter == NULL) { \
1254                         \
1255                         return;\
1256                 } \
1257         } while (0)
1258
1259 #endif  /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
1260
1261 void
1262 odm_asoc_entry_init(
1263         struct PHY_DM_STRUCT            *p_dm_odm
1264 );
1265
1266
1267 void *
1268 phydm_get_structure(
1269         struct PHY_DM_STRUCT            *p_dm_odm,
1270         u8                      structure_type
1271 );
1272
1273 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) || (DM_ODM_SUPPORT_TYPE == ODM_CE)
1274         /*===========================================================*/
1275         /* The following is for compile only*/
1276         /*===========================================================*/
1277
1278         #define IS_HARDWARE_TYPE_8723A(_adapter)                        false
1279         #define IS_HARDWARE_TYPE_8723AE(_adapter)                       false
1280         #define IS_HARDWARE_TYPE_8192C(_adapter)                        false
1281         #define IS_HARDWARE_TYPE_8192D(_adapter)                        false
1282         #define RF_T_METER_92D  0x42
1283
1284
1285         #define GET_RX_STATUS_DESC_RX_MCS(__prx_status_desc)    LE_BITS_TO_1BYTE(__prx_status_desc+12, 0, 6)
1286
1287         #define REG_CONFIG_RAM64X16                             0xb2c
1288
1289         #define TARGET_CHNL_NUM_2G_5G   59
1290
1291         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1292                 u8 get_right_chnl_place_for_iqk(u8 chnl);
1293         #endif
1294
1295         /* *********************************************************** */
1296 #endif
1297
1298 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1299         void odm_dtc(struct PHY_DM_STRUCT *p_dm_odm);
1300 #endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
1301
1302
1303 void phydm_noisy_detection(struct PHY_DM_STRUCT *p_dm_odm);
1304
1305
1306 #endif
1307
1308 void
1309 phydm_set_ext_switch(
1310         void            *p_dm_void,
1311         u32             *const dm_value,
1312         u32             *_used,
1313         char                    *output,
1314         u32             *_out_len
1315 );
1316
1317 void
1318 phydm_api_debug(
1319         void            *p_dm_void,
1320         u32             function_map,
1321         u32             *const dm_value,
1322         u32             *_used,
1323         char                    *output,
1324         u32             *_out_len
1325 );
1326
1327 u8
1328 phydm_nbi_setting(
1329         void            *p_dm_void,
1330         u32             enable,
1331         u32             channel,
1332         u32             bw,
1333         u32             f_interference,
1334         u32             second_ch
1335 );