drivers/net/wireless/rockchip_wlan/rtl8723cs/hal/phydm/phydm.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20
  21 /* ************************************************************
  22  * include files
  23  * ************************************************************ */
  24
  25 #include "mp_precomp.h"
  26 #include "phydm_precomp.h"
  27
  28 const u16 db_invert_table[12][8] = {
  29         {       1,              1,              1,              2,              2,              2,              2,              3},
  30         {       3,              3,              4,              4,              4,              5,              6,              6},
  31         {       7,              8,              9,              10,             11,             13,             14,             16},
  32         {       18,             20,             22,             25,             28,             32,             35,             40},
  33         {       45,             50,             56,             63,             71,             79,             89,             100},
  34         {       112,            126,            141,            158,            178,            200,            224,            251},
  35         {       282,            316,            355,            398,            447,            501,            562,            631},
  36         {       708,            794,            891,            1000,   1122,   1259,   1413,   1585},
  37         {       1778,   1995,   2239,   2512,   2818,   3162,   3548,   3981},
  38         {       4467,   5012,   5623,   6310,   7079,   7943,   8913,   10000},
  39         {       11220,  12589,  14125,  15849,  17783,  19953,  22387,  25119},
  40         {       28184,  31623,  35481,  39811,  44668,  50119,  56234,  65535}
  41 };
  42
  43
  44 /* ************************************************************
  45  * Local Function predefine.
  46  * ************************************************************ */
  47
  48 /* START------------COMMON INFO RELATED--------------- */
  49
  50 void
  51 odm_global_adapter_check(
  52         void
  53 );
  54
  55 /* move to odm_PowerTacking.h by YuChen */
  56
  57
  58
  59 void
  60 odm_update_power_training_state(
  61         struct PHY_DM_STRUCT    *p_dm_odm
  62 );
  63
  64 /* ************************************************************
  65  * 3 Export Interface
  66  * ************************************************************ */
  67
  68 /*Y = 10*log(X)*/
  69 s32
  70 odm_pwdb_conversion(
  71         s32 X,
  72         u32 total_bit,
  73         u32 decimal_bit
  74 )
  75 {
  76         s32 Y, integer = 0, decimal = 0;
  77         u32 i;
  78
  79         if (X == 0)
  80                 X = 1; /* log2(x), x can't be 0 */
  81
  82         for (i = (total_bit - 1); i > 0; i--) {
  83                 if (X & BIT(i)) {
  84                         integer = i;
  85                         if (i > 0)
  86                                 decimal = (X & BIT(i - 1)) ? 2 : 0; /* decimal is 0.5dB*3=1.5dB~=2dB */
  87                         break;
  88                 }
  89         }
  90
  91         Y = 3 * (integer - decimal_bit) + decimal; /* 10*log(x)=3*log2(x), */
  92
  93         return Y;
  94 }
  95
  96 s32
  97 odm_sign_conversion(
  98         s32 value,
  99         u32 total_bit
 100 )
 101 {
 102         if (value & BIT(total_bit - 1))
 103                 value -= BIT(total_bit);
 104         return value;
 105 }
 106
 107 void
 108 phydm_seq_sorting(
 109         void    *p_dm_void,
 110         u32     *p_value,
 111         u32     *rank_idx,
 112         u32     *p_idx_out,
 113         u8      seq_length
 114 )
 115 {
 116         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 117         u8              i = 0, j = 0;
 118         u32             tmp_a, tmp_b;
 119         u32             tmp_idx_a, tmp_idx_b;
 120
 121         for (i = 0; i < seq_length; i++) {
 122                 rank_idx[i] = i;
 123                 /**/
 124         }
 125
 126         for (i = 0; i < (seq_length - 1); i++) {
 127
 128                 for (j = 0; j < (seq_length - 1 - i); j++) {
 129
 130                         tmp_a = p_value[j];
 131                         tmp_b = p_value[j + 1];
 132
 133                         tmp_idx_a = rank_idx[j];
 134                         tmp_idx_b = rank_idx[j + 1];
 135
 136                         if (tmp_a < tmp_b) {
 137                                 p_value[j] = tmp_b;
 138                                 p_value[j + 1] = tmp_a;
 139
 140                                 rank_idx[j] = tmp_idx_b;
 141                                 rank_idx[j + 1] = tmp_idx_a;
 142                         }
 143                 }
 144         }
 145
 146         for (i = 0; i < seq_length; i++) {
 147                 p_idx_out[rank_idx[i]] = i + 1;
 148                 /**/
 149         }
 150
 151
 152
 153 }
 154
 155 void
 156 odm_init_mp_driver_status(
 157         struct PHY_DM_STRUCT            *p_dm_odm
 158 )
 159 {
 160 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 161
 162         /* Decide when compile time */
 163 #if (MP_DRIVER == 1)
 164         p_dm_odm->mp_mode = true;
 165 #else
 166         p_dm_odm->mp_mode = false;
 167 #endif
 168
 169 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
 170
 171         struct _ADAPTER *adapter =  p_dm_odm->adapter;
 172
 173         /* Update information every period */
 174         p_dm_odm->mp_mode = (boolean)adapter->registrypriv.mp_mode;
 175
 176 #else
 177
 178         struct rtl8192cd_priv   *priv = p_dm_odm->priv;
 179
 180         p_dm_odm->mp_mode = (boolean)priv->pshare->rf_ft_var.mp_specific;
 181
 182 #endif
 183 }
 184
 185 void
 186 odm_update_mp_driver_status(
 187         struct PHY_DM_STRUCT            *p_dm_odm
 188 )
 189 {
 190 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 191
 192         /* Do nothing. */
 193
 194 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
 195         struct _ADAPTER *adapter =  p_dm_odm->adapter;
 196
 197         /* Update information erery period */
 198         p_dm_odm->mp_mode = (boolean)adapter->registrypriv.mp_mode;
 199
 200 #else
 201
 202         /* Do nothing. */
 203
 204 #endif
 205 }
 206
 207 void
 208 phydm_init_trx_antenna_setting(
 209         struct PHY_DM_STRUCT            *p_dm_odm
 210 )
 211 {
 212         /*#if (RTL8814A_SUPPORT == 1)*/
 213
 214         if (p_dm_odm->support_ic_type & (ODM_RTL8814A)) {
 215                 u8      rx_ant = 0, tx_ant = 0;
 216
 217                 rx_ant = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG(BB_RX_PATH, p_dm_odm), ODM_BIT(BB_RX_PATH, p_dm_odm));
 218                 tx_ant = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG(BB_TX_PATH, p_dm_odm), ODM_BIT(BB_TX_PATH, p_dm_odm));
 219                 p_dm_odm->tx_ant_status = (tx_ant & 0xf);
 220                 p_dm_odm->rx_ant_status = (rx_ant & 0xf);
 221         } else if (p_dm_odm->support_ic_type & (ODM_RTL8723D | ODM_RTL8821C | ODM_RTL8710B)) {/* JJ ADD 20161014 */
 222                 p_dm_odm->tx_ant_status = 0x1;
 223                 p_dm_odm->rx_ant_status = 0x1;
 224
 225         }
 226         /*#endif*/
 227 }
 228
 229 void
 230 phydm_traffic_load_decision(
 231         void    *p_dm_void
 232 )
 233 {
 234         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 235         struct _sw_antenna_switch_              *p_dm_swat_table = &p_dm_odm->dm_swat_table;
 236
 237         /*---TP & Trafic-load calculation---*/
 238
 239         if (p_dm_odm->last_tx_ok_cnt > (*(p_dm_odm->p_num_tx_bytes_unicast)))
 240                 p_dm_odm->last_tx_ok_cnt = (*(p_dm_odm->p_num_tx_bytes_unicast));
 241
 242         if (p_dm_odm->last_rx_ok_cnt > (*(p_dm_odm->p_num_rx_bytes_unicast)))
 243                 p_dm_odm->last_rx_ok_cnt = (*(p_dm_odm->p_num_rx_bytes_unicast));
 244
 245         p_dm_odm->cur_tx_ok_cnt =  *(p_dm_odm->p_num_tx_bytes_unicast) - p_dm_odm->last_tx_ok_cnt;
 246         p_dm_odm->cur_rx_ok_cnt =  *(p_dm_odm->p_num_rx_bytes_unicast) - p_dm_odm->last_rx_ok_cnt;
 247         p_dm_odm->last_tx_ok_cnt =  *(p_dm_odm->p_num_tx_bytes_unicast);
 248         p_dm_odm->last_rx_ok_cnt =  *(p_dm_odm->p_num_rx_bytes_unicast);
 249
 250 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
 251         p_dm_odm->tx_tp = ((p_dm_odm->tx_tp) >> 1) + (u32)(((p_dm_odm->cur_tx_ok_cnt) >> 17) >> 1); /* <<3(8bit), >>20(10^6,M)*/
 252         p_dm_odm->rx_tp = ((p_dm_odm->rx_tp) >> 1) + (u32)(((p_dm_odm->cur_rx_ok_cnt) >> 17) >> 1); /* <<3(8bit), >>20(10^6,M)*/
 253 #else
 254         p_dm_odm->tx_tp = ((p_dm_odm->tx_tp) >> 1) + (u32)(((p_dm_odm->cur_tx_ok_cnt) >> 18) >> 1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/
 255         p_dm_odm->rx_tp = ((p_dm_odm->rx_tp) >> 1) + (u32)(((p_dm_odm->cur_rx_ok_cnt) >> 18) >> 1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/
 256 #endif
 257         p_dm_odm->total_tp = p_dm_odm->tx_tp + p_dm_odm->rx_tp;
 258
 259         /*
 260         ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\n",
 261                 p_dm_odm->cur_tx_ok_cnt, p_dm_odm->cur_rx_ok_cnt, p_dm_odm->last_tx_ok_cnt, p_dm_odm->last_rx_ok_cnt));
 262
 263         ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("tx_tp = %d, rx_tp = %d\n",
 264                 p_dm_odm->tx_tp, p_dm_odm->rx_tp));
 265         */
 266
 267         p_dm_odm->pre_traffic_load = p_dm_odm->traffic_load;
 268
 269         if (p_dm_odm->cur_tx_ok_cnt > 1875000 || p_dm_odm->cur_rx_ok_cnt > 1875000) {           /* ( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/
 270
 271                 p_dm_odm->traffic_load = TRAFFIC_HIGH;
 272                 /**/
 273         } else if (p_dm_odm->cur_tx_ok_cnt > 500000 || p_dm_odm->cur_rx_ok_cnt > 500000) { /*( 0.5M * 8bit ) / 2sec =  2M bits /sec )*/
 274
 275                 p_dm_odm->traffic_load = TRAFFIC_MID;
 276                 /**/
 277         } else if (p_dm_odm->cur_tx_ok_cnt > 100000 || p_dm_odm->cur_rx_ok_cnt > 100000)  { /*( 0.1M * 8bit ) / 2sec =  0.4M bits /sec )*/
 278
 279                 p_dm_odm->traffic_load = TRAFFIC_LOW;
 280                 /**/
 281         } else {
 282
 283                 p_dm_odm->traffic_load = TRAFFIC_ULTRA_LOW;
 284                 /**/
 285         }
 286 }
 287
 288 void
 289 phydm_config_ofdm_tx_path(
 290         struct PHY_DM_STRUCT            *p_dm_odm,
 291         u32                     path
 292 )
 293 {
 294         u8      ofdm_tx_path = 0x33;
 295
 296 #if (RTL8192E_SUPPORT == 1)
 297         if (p_dm_odm->support_ic_type & (ODM_RTL8192E)) {
 298
 299                 if (path == PHYDM_A) {
 300                         odm_set_bb_reg(p_dm_odm, 0x90c, MASKDWORD, 0x81121111);
 301                         /**/
 302                 } else if (path == PHYDM_B) {
 303                         odm_set_bb_reg(p_dm_odm, 0x90c, MASKDWORD, 0x82221222);
 304                         /**/
 305                 } else  if (path == PHYDM_AB) {
 306                         odm_set_bb_reg(p_dm_odm, 0x90c, MASKDWORD, 0x83321333);
 307                         /**/
 308                 }
 309
 310
 311         }
 312 #endif
 313
 314 #if (RTL8812A_SUPPORT == 1)
 315         if (p_dm_odm->support_ic_type & (ODM_RTL8812)) {
 316
 317                 if (path == PHYDM_A) {
 318                         ofdm_tx_path = 0x11;
 319                         /**/
 320                 } else if (path == PHYDM_B) {
 321                         ofdm_tx_path = 0x22;
 322                         /**/
 323                 } else  if (path == PHYDM_AB) {
 324                         ofdm_tx_path = 0x33;
 325                         /**/
 326                 }
 327
 328                 odm_set_bb_reg(p_dm_odm, 0x80c, 0xff00, ofdm_tx_path);
 329         }
 330 #endif
 331 }
 332
 333 void
 334 phydm_config_ofdm_rx_path(
 335         struct PHY_DM_STRUCT            *p_dm_odm,
 336         u32                     path
 337 )
 338 {
 339         u8      ofdm_rx_path = 0;
 340
 341
 342         if (p_dm_odm->support_ic_type & (ODM_RTL8192E)) {
 343 #if (RTL8192E_SUPPORT == 1)
 344                 if (path == PHYDM_A) {
 345                         ofdm_rx_path = 1;
 346                         /**/
 347                 } else if (path == PHYDM_B) {
 348                         ofdm_rx_path = 2;
 349                         /**/
 350                 } else  if (path == PHYDM_AB) {
 351                         ofdm_rx_path = 3;
 352                         /**/
 353                 }
 354
 355                 odm_set_bb_reg(p_dm_odm, 0xC04, 0xff, (((ofdm_rx_path) << 4) | ofdm_rx_path));
 356                 odm_set_bb_reg(p_dm_odm, 0xD04, 0xf, ofdm_rx_path);
 357 #endif
 358         }
 359 #if (RTL8812A_SUPPORT || RTL8822B_SUPPORT)
 360         else if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) {
 361
 362                 if (path == PHYDM_A) {
 363                         ofdm_rx_path = 1;
 364                         /**/
 365                 } else if (path == PHYDM_B) {
 366                         ofdm_rx_path = 2;
 367                         /**/
 368                 } else  if (path == PHYDM_AB) {
 369                         ofdm_rx_path = 3;
 370                         /**/
 371                 }
 372
 373                 odm_set_bb_reg(p_dm_odm, 0x808, MASKBYTE0, ((ofdm_rx_path << 4) | ofdm_rx_path));
 374         }
 375 #endif
 376 }
 377
 378 void
 379 phydm_config_cck_rx_antenna_init(
 380         struct PHY_DM_STRUCT            *p_dm_odm
 381 )
 382 {
 383 #if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1))
 384         if (p_dm_odm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)) {
 385
 386                 /*CCK 2R CCA parameters*/
 387                 odm_set_bb_reg(p_dm_odm, 0xa2c, BIT(18), 1); /*enable 2R Rx path*/
 388                 odm_set_bb_reg(p_dm_odm, 0xa2c, BIT(22), 1); /*enable 2R MRC*/
 389                 odm_set_bb_reg(p_dm_odm, 0xa84, BIT(28), 1); /*1. pdx1[5:0] > 2*PD_lim 2. RXIQ_3 = 0 ( signed )*/
 390                 odm_set_bb_reg(p_dm_odm, 0xa70, BIT(7), 0); /*Concurrent CCA at LSB & USB*/
 391                 odm_set_bb_reg(p_dm_odm, 0xa74, BIT(8), 0); /*RX path diversity enable*/
 392                 odm_set_bb_reg(p_dm_odm, 0xa08, BIT(28), 1); /* r_cck_2nd_sel_eco*/
 393                 odm_set_bb_reg(p_dm_odm, 0xa14, BIT(7), 0); /* r_en_mrc_antsel*/
 394         }
 395 #endif
 396 }
 397
 398 void
 399 phydm_config_cck_rx_path(
 400         struct PHY_DM_STRUCT            *p_dm_odm,
 401         u8                      path,
 402         u8                      path_div_en
 403 )
 404 {
 405         u8      path_div_select = 0;
 406         u8      cck_1_path = 0, cck_2_path = 0;
 407
 408 #if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1))
 409         if (p_dm_odm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)) {
 410
 411                 if (path == PHYDM_A) {
 412                         path_div_select = 0;
 413                         cck_1_path = 0;
 414                         cck_2_path = 0;
 415                 } else if (path == PHYDM_B) {
 416                         path_div_select = 0;
 417                         cck_1_path = 1;
 418                         cck_2_path = 1;
 419                 } else  if (path == PHYDM_AB) {
 420
 421                         if (path_div_en == CCA_PATHDIV_ENABLE)
 422                                 path_div_select = 1;
 423
 424                         cck_1_path = 0;
 425                         cck_2_path = 1;
 426
 427                 }
 428
 429                 odm_set_bb_reg(p_dm_odm, 0xa04, (BIT(27) | BIT(26)), cck_1_path);
 430                 odm_set_bb_reg(p_dm_odm, 0xa04, (BIT(25) | BIT(24)), cck_2_path);
 431                 odm_set_bb_reg(p_dm_odm, 0xa74, BIT(8), path_div_select);
 432
 433         }
 434 #endif
 435 }
 436
 437 void
 438 phydm_config_trx_path(
 439         void            *p_dm_void,
 440         u32             *const dm_value,
 441         u32             *_used,
 442         char                    *output,
 443         u32             *_out_len
 444 )
 445 {
 446         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 447         u32                     pre_support_ability;
 448         u32 used = *_used;
 449         u32 out_len = *_out_len;
 450
 451         /* CCK */
 452         if (dm_value[0] == 0) {
 453
 454                 if (dm_value[1] == 1) { /*TX*/
 455                         if (dm_value[2] == 1)
 456                                 odm_set_bb_reg(p_dm_odm, 0xa04, 0xf0000000, 0x8);
 457                         else if (dm_value[2] == 2)
 458                                 odm_set_bb_reg(p_dm_odm, 0xa04, 0xf0000000, 0x4);
 459                         else if (dm_value[2] == 3)
 460                                 odm_set_bb_reg(p_dm_odm, 0xa04, 0xf0000000, 0xc);
 461                 } else if (dm_value[1] == 2) { /*RX*/
 462
 463                         phydm_config_cck_rx_antenna_init(p_dm_odm);
 464
 465                         if (dm_value[2] == 1)
 466                                 phydm_config_cck_rx_path(p_dm_odm, PHYDM_A, CCA_PATHDIV_DISABLE);
 467                         else  if (dm_value[2] == 2)
 468                                 phydm_config_cck_rx_path(p_dm_odm, PHYDM_B, CCA_PATHDIV_DISABLE);
 469                         else  if (dm_value[2] == 3) {
 470                                 if (dm_value[3] == 1) /*enable path diversity*/
 471                                         phydm_config_cck_rx_path(p_dm_odm, PHYDM_AB, CCA_PATHDIV_ENABLE);
 472                                 else
 473                                         phydm_config_cck_rx_path(p_dm_odm, PHYDM_B, CCA_PATHDIV_DISABLE);
 474                         }
 475                 }
 476         }
 477         /* OFDM */
 478         else if (dm_value[0] == 1) {
 479
 480                 if (dm_value[1] == 1) { /*TX*/
 481                         phydm_config_ofdm_tx_path(p_dm_odm, dm_value[2]);
 482                         /**/
 483                 } else if (dm_value[1] == 2) { /*RX*/
 484                         phydm_config_ofdm_rx_path(p_dm_odm, dm_value[2]);
 485                         /**/
 486                 }
 487         }
 488
 489         PHYDM_SNPRINTF((output + used, out_len - used, "PHYDM Set path [%s] [%s] = [%s%s%s%s]\n",
 490                         (dm_value[0] == 1) ? "OFDM" : "CCK",
 491                         (dm_value[1] == 1) ? "TX" : "RX",
 492                         (dm_value[2] & 0x1) ? "A" : "",
 493                         (dm_value[2] & 0x2) ? "B" : "",
 494                         (dm_value[2] & 0x4) ? "C" : "",
 495                         (dm_value[2] & 0x8) ? "D" : ""
 496                        ));
 497
 498 }
 499
 500 void
 501 phydm_init_cck_setting(
 502         struct PHY_DM_STRUCT            *p_dm_odm
 503 )
 504 {
 505         u32 value_824, value_82c;
 506
 507         p_dm_odm->is_cck_high_power = (boolean) odm_get_bb_reg(p_dm_odm, ODM_REG(CCK_RPT_FORMAT, p_dm_odm), ODM_BIT(CCK_RPT_FORMAT, p_dm_odm));
 508
 509 #if (RTL8192E_SUPPORT == 1)
 510         if (p_dm_odm->support_ic_type & (ODM_RTL8192E)) {
 511 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 512                 phydm_config_cck_rx_antenna_init(p_dm_odm);
 513                 phydm_config_cck_rx_path(p_dm_odm, PHYDM_A, CCA_PATHDIV_DISABLE);
 514 #endif
 515
 516                 /* 0x824[9] = 0x82C[9] = 0xA80[7]  those registers setting should be equal or CCK RSSI report may be incorrect */
 517                 value_824 = odm_get_bb_reg(p_dm_odm, 0x824, BIT(9));
 518                 value_82c = odm_get_bb_reg(p_dm_odm, 0x82c, BIT(9));
 519
 520                 if (value_824 != value_82c)
 521                         odm_set_bb_reg(p_dm_odm, 0x82c, BIT(9), value_824);
 522                 odm_set_bb_reg(p_dm_odm, 0xa80, BIT(7), value_824);
 523                 p_dm_odm->cck_agc_report_type = (boolean)value_824;
 524
 525                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("cck_agc_report_type = (( %d )), ext_lna_gain = (( %d ))\n", p_dm_odm->cck_agc_report_type, p_dm_odm->ext_lna_gain));
 526         }
 527 #endif
 528 /* JJ ADD 20161014 */
 529 #if ((RTL8703B_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8710B_SUPPORT == 1))
 530         if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
 531
 532                 p_dm_odm->cck_agc_report_type = odm_get_bb_reg(p_dm_odm, 0x950, BIT(11)) ? 1 : 0; /*1: 4bit LNA, 0: 3bit LNA */
 533
 534                 if (p_dm_odm->cck_agc_report_type != 1) {
 535                         dbg_print("[Warning] 8703B/8723D/8710B CCK should be 4bit LNA, ie. 0x950[11] = 1\n");
 536                         /**/
 537                 }
 538         }
 539 #endif
 540 /* JJ ADD 20161014 */
 541 #if ((RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8710B_SUPPORT == 1))
 542         if (p_dm_odm->support_ic_type & (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8710B))
 543                 p_dm_odm->cck_new_agc = odm_get_bb_reg(p_dm_odm, 0xa9c, BIT(17)) ? true : false;          /*1: new agc  0: old agc*/
 544         else
 545 #endif
 546                 p_dm_odm->cck_new_agc = false;
 547
 548 }
 549
 550
 551 void
 552 phydm_dynamicsoftmletting(
 553         struct PHY_DM_STRUCT            *p_dm_odm
 554 )
 555 {
 556
 557         u32 ret_val;
 558
 559 #if (RTL8822B_SUPPORT == 1)
 560         if (p_dm_odm->mp_mode == FALSE) {
 561                 if (p_dm_odm->support_ic_type & ODM_RTL8822B) {
 562
 563                         if ((!p_dm_odm->is_linked)|(p_dm_odm->bLinkedcmw500))
 564                                 return;
 565
 566                         if (TRUE == p_dm_odm->bsomlenabled) {
 567                                 ODM_RT_TRACE(p_dm_odm,ODM_COMP_API,ODM_DBG_TRACE,("PHYDM_DynamicSoftMLSetting(): SoML has been enable, skip dynamic SoML switch\n"));
 568                                 return;
 569                         }
 570
 571                         ret_val = odm_get_bb_reg(p_dm_odm, 0xf8c, bMaskByte0);
 572                         ODM_RT_TRACE(p_dm_odm,ODM_COMP_API,ODM_DBG_TRACE,("PHYDM_DynamicSoftMLSetting(): Read 0xF8C = 0x%08X\n",ret_val));
 573
 574                         if (ret_val < 0x16) {
 575                                 ODM_RT_TRACE(p_dm_odm,ODM_COMP_API,ODM_DBG_LOUD,("PHYDM_DynamicSoftMLSetting(): 0xF8C(== 0x%08X) < 0x16, enable SoML\n",ret_val));
 576                                 odm_set_bb_reg(p_dm_odm, 0x19a8, bMaskDWord, 0xc10a0000);
 577                                 p_dm_odm->bsomlenabled = TRUE;
 578                         }
 579                 }
 580         }
 581 #endif
 582
 583 }
 584
 585
 586 void
 587 phydm_init_soft_ml_setting(
 588         struct PHY_DM_STRUCT            *p_dm_odm
 589 )
 590 {
 591 #if (RTL8822B_SUPPORT == 1)
 592         if (p_dm_odm->mp_mode == false) {
 593                 if (p_dm_odm->support_ic_type & ODM_RTL8822B)
 594                         odm_set_bb_reg(p_dm_odm, 0x19a8, MASKDWORD, 0xc10a0000);
 595         }
 596 #endif
 597 }
 598
 599 void
 600 phydm_init_hw_info_by_rfe(
 601         struct PHY_DM_STRUCT            *p_dm_odm
 602 )
 603 {
 604 #if (RTL8822B_SUPPORT == 1)
 605         if (p_dm_odm->support_ic_type & ODM_RTL8822B)
 606                 phydm_init_hw_info_by_rfe_type_8822b(p_dm_odm);
 607 #endif
 608 #if (RTL8821C_SUPPORT == 1)
 609         if (p_dm_odm->support_ic_type & ODM_RTL8821C)
 610                 phydm_init_hw_info_by_rfe_type_8821c(p_dm_odm);
 611 #endif
 612 #if (RTL8197F_SUPPORT == 1)
 613         if (p_dm_odm->support_ic_type & ODM_RTL8197F)
 614                 phydm_init_hw_info_by_rfe_type_8197f(p_dm_odm);
 615 #endif
 616 }
 617
 618 void
 619 odm_common_info_self_init(
 620         struct PHY_DM_STRUCT            *p_dm_odm
 621 )
 622 {
 623         phydm_init_cck_setting(p_dm_odm);
 624         p_dm_odm->rf_path_rx_enable = (u8) odm_get_bb_reg(p_dm_odm, ODM_REG(BB_RX_PATH, p_dm_odm), ODM_BIT(BB_RX_PATH, p_dm_odm));
 625 #if (DM_ODM_SUPPORT_TYPE != ODM_CE)
 626         p_dm_odm->p_is_net_closed = &p_dm_odm->BOOLEAN_temp;
 627
 628         phydm_init_debug_setting(p_dm_odm);
 629 #endif
 630         odm_init_mp_driver_status(p_dm_odm);
 631         phydm_init_trx_antenna_setting(p_dm_odm);
 632         phydm_init_soft_ml_setting(p_dm_odm);
 633
 634         p_dm_odm->phydm_period = PHYDM_WATCH_DOG_PERIOD;
 635         p_dm_odm->phydm_sys_up_time = 0;
 636
 637         if (p_dm_odm->support_ic_type & ODM_IC_1SS)
 638                 p_dm_odm->num_rf_path = 1;
 639         else if (p_dm_odm->support_ic_type & ODM_IC_2SS)
 640                 p_dm_odm->num_rf_path = 2;
 641         else if (p_dm_odm->support_ic_type & ODM_IC_3SS)
 642                 p_dm_odm->num_rf_path = 3;
 643         else if (p_dm_odm->support_ic_type & ODM_IC_4SS)
 644                 p_dm_odm->num_rf_path = 4;
 645
 646         p_dm_odm->tx_rate = 0xFF;
 647
 648         p_dm_odm->number_linked_client = 0;
 649         p_dm_odm->pre_number_linked_client = 0;
 650         p_dm_odm->number_active_client = 0;
 651         p_dm_odm->pre_number_active_client = 0;
 652
 653         p_dm_odm->last_tx_ok_cnt = 0;
 654         p_dm_odm->last_rx_ok_cnt = 0;
 655         p_dm_odm->tx_tp = 0;
 656         p_dm_odm->rx_tp = 0;
 657         p_dm_odm->total_tp = 0;
 658         p_dm_odm->traffic_load = TRAFFIC_LOW;
 659
 660         p_dm_odm->nbi_set_result = 0;
 661         p_dm_odm->is_init_hw_info_by_rfe = false;
 662         p_dm_odm->pre_dbg_priority = BB_DBGPORT_RELEASE;
 663
 664 }
 665
 666 void
 667 odm_common_info_self_update(
 668         struct PHY_DM_STRUCT            *p_dm_odm
 669 )
 670 {
 671         u8      entry_cnt = 0, num_active_client = 0;
 672         u32     i, one_entry_macid = 0, ma_rx_tp = 0;
 673         struct sta_info *p_entry;
 674
 675 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 676
 677         struct _ADAPTER *adapter =  p_dm_odm->adapter;
 678         PMGNT_INFO      p_mgnt_info = &adapter->MgntInfo;
 679
 680         p_entry = p_dm_odm->p_odm_sta_info[0];
 681         if (p_mgnt_info->mAssoc) {
 682                 p_entry->bUsed = true;
 683                 for (i = 0; i < 6; i++)
 684                         p_entry->MacAddr[i] = p_mgnt_info->Bssid[i];
 685         } else if (GetFirstClientPort(adapter)) {
 686                 struct _ADAPTER *p_client_adapter = GetFirstClientPort(adapter);
 687
 688                 p_entry->bUsed = true;
 689                 for (i = 0; i < 6; i++)
 690                         p_entry->MacAddr[i] = p_client_adapter->MgntInfo.Bssid[i];
 691         } else {
 692                 p_entry->bUsed = false;
 693                 for (i = 0; i < 6; i++)
 694                         p_entry->MacAddr[i] = 0;
 695         }
 696
 697         /* STA mode is linked to AP */
 698         if (IS_STA_VALID(p_dm_odm->p_odm_sta_info[0]) && !ACTING_AS_AP(adapter))
 699                 p_dm_odm->bsta_state = true;
 700         else
 701                 p_dm_odm->bsta_state = false;
 702 #endif
 703
 704         /* THis variable cannot be used because it is wrong*/
 705 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
 706         if (*(p_dm_odm->p_band_width) == ODM_BW40M) {
 707                 if (*(p_dm_odm->p_sec_ch_offset) == 1)
 708                         p_dm_odm->control_channel = *(p_dm_odm->p_channel) + 2;
 709                 else if (*(p_dm_odm->p_sec_ch_offset) == 2)
 710                         p_dm_odm->control_channel = *(p_dm_odm->p_channel) - 2;
 711         } else if (*(p_dm_odm->p_band_width) == ODM_BW80M)      {
 712                 if (*(p_dm_odm->p_sec_ch_offset) == 1)
 713                         p_dm_odm->control_channel = *(p_dm_odm->p_channel) + 6;
 714                 else if (*(p_dm_odm->p_sec_ch_offset) == 2)
 715                         p_dm_odm->control_channel = *(p_dm_odm->p_channel) - 6;
 716         } else
 717                 p_dm_odm->control_channel = *(p_dm_odm->p_channel);
 718 #else
 719         if (*(p_dm_odm->p_band_width) == ODM_BW40M) {
 720                 if (*(p_dm_odm->p_sec_ch_offset) == 1)
 721                         p_dm_odm->control_channel = *(p_dm_odm->p_channel) - 2;
 722                 else if (*(p_dm_odm->p_sec_ch_offset) == 2)
 723                         p_dm_odm->control_channel = *(p_dm_odm->p_channel) + 2;
 724         } else
 725                 p_dm_odm->control_channel = *(p_dm_odm->p_channel);
 726 #endif
 727
 728         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
 729                 p_entry = p_dm_odm->p_odm_sta_info[i];
 730                 if (IS_STA_VALID(p_entry)) {
 731                         entry_cnt++;
 732                         if (entry_cnt == 1)
 733                                 one_entry_macid = i;
 734
 735 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
 736                         ma_rx_tp = (p_entry->rx_byte_cnt_low_maw) << 3; /*  low moving average RX  TP   ( bit /sec)*/
 737
 738                         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("ClientTP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp));
 739
 740                         if (ma_rx_tp > ACTIVE_TP_THRESHOLD)
 741                                 num_active_client++;
 742 #endif
 743                 }
 744         }
 745
 746         if (entry_cnt == 1) {
 747                 p_dm_odm->is_one_entry_only = true;
 748                 p_dm_odm->one_entry_macid = one_entry_macid;
 749         } else
 750                 p_dm_odm->is_one_entry_only = false;
 751
 752         p_dm_odm->pre_number_linked_client = p_dm_odm->number_linked_client;
 753         p_dm_odm->pre_number_active_client = p_dm_odm->number_active_client;
 754
 755         p_dm_odm->number_linked_client = entry_cnt;
 756         p_dm_odm->number_active_client = num_active_client;
 757
 758         /* Update MP driver status*/
 759         odm_update_mp_driver_status(p_dm_odm);
 760
 761         /*Traffic load information update*/
 762         phydm_traffic_load_decision(p_dm_odm);
 763
 764         p_dm_odm->phydm_sys_up_time += p_dm_odm->phydm_period;
 765 }
 766
 767 void
 768 odm_common_info_self_reset(
 769         struct PHY_DM_STRUCT            *p_dm_odm
 770 )
 771 {
 772 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
 773         p_dm_odm->phy_dbg_info.num_qry_beacon_pkt = 0;
 774 #endif
 775 }
 776
 777 void *
 778 phydm_get_structure(
 779         struct PHY_DM_STRUCT            *p_dm_odm,
 780         u8                      structure_type
 781 )
 782
 783 {
 784         void    *p_struct = NULL;
 785 #if RTL8195A_SUPPORT
 786         switch (structure_type) {
 787         case    PHYDM_FALSEALMCNT:
 788                 p_struct = &false_alm_cnt;
 789                 break;
 790
 791         case    PHYDM_CFOTRACK:
 792                 p_struct = &dm_cfo_track;
 793                 break;
 794
 795         case    PHYDM_ADAPTIVITY:
 796                 p_struct = &(p_dm_odm->adaptivity);
 797                 break;
 798
 799         default:
 800                 break;
 801         }
 802
 803 #else
 804         switch (structure_type) {
 805         case    PHYDM_FALSEALMCNT:
 806                 p_struct = &(p_dm_odm->false_alm_cnt);
 807                 break;
 808
 809         case    PHYDM_CFOTRACK:
 810                 p_struct = &(p_dm_odm->dm_cfo_track);
 811                 break;
 812
 813         case    PHYDM_ADAPTIVITY:
 814                 p_struct = &(p_dm_odm->adaptivity);
 815                 break;
 816
 817         default:
 818                 break;
 819         }
 820
 821 #endif
 822         return  p_struct;
 823 }
 824
 825 void
 826 odm_hw_setting(
 827         struct PHY_DM_STRUCT            *p_dm_odm
 828 )
 829 {
 830 #if (RTL8821A_SUPPORT == 1)
 831         if (p_dm_odm->support_ic_type & ODM_RTL8821)
 832                 odm_hw_setting_8821a(p_dm_odm);
 833 #endif
 834
 835 #if (RTL8814A_SUPPORT == 1)
 836         if (p_dm_odm->support_ic_type & ODM_RTL8814A)
 837                 phydm_hwsetting_8814a(p_dm_odm);
 838 #endif
 839
 840 #if (RTL8822B_SUPPORT == 1)
 841         if (p_dm_odm->support_ic_type & ODM_RTL8822B)
 842                 phydm_hwsetting_8822b(p_dm_odm);
 843 #endif
 844
 845 #if (RTL8197F_SUPPORT == 1)
 846         if (p_dm_odm->support_ic_type & ODM_RTL8197F)
 847                 phydm_hwsetting_8197f(p_dm_odm);
 848 #endif
 849 }
 850 #if SUPPORTABLITY_PHYDMLIZE
 851 void
 852 phydm_supportability_init(
 853         void            *p_dm_void
 854 )
 855 {
 856         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 857         u32                     support_ability = 0;
 858 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
 859         struct _ADAPTER         *adapter = p_dm_odm->adapter;
 860         PMGNT_INFO              p_mgnt_info = &adapter->MgntInfo;
 861 #endif
 862
 863 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
 864         if (p_dm_odm->support_ic_type != ODM_RTL8821C)
 865                 return;
 866 #endif
 867
 868         switch (p_dm_odm->support_ic_type) {
 869
 870         /*---------------N Series--------------------*/
 871         case    ODM_RTL8188E:
 872                 support_ability |=
 873                         ODM_BB_DIG                              |
 874                         ODM_BB_RA_MASK          |
 875                         ODM_BB_DYNAMIC_TXPWR    |
 876                         ODM_BB_FA_CNT                   |
 877                         ODM_BB_RSSI_MONITOR     |
 878                         ODM_BB_CCK_PD                   |
 879                         ODM_RF_TX_PWR_TRACK     |
 880                         ODM_RF_RX_GAIN_TRACK    |
 881                         ODM_RF_CALIBRATION              |
 882                         ODM_BB_CFO_TRACKING     |
 883                         ODM_BB_NHM_CNT          |
 884                         ODM_BB_PRIMARY_CCA;
 885                 break;
 886
 887         case    ODM_RTL8192E:
 888                 support_ability |=
 889                         ODM_BB_DIG                              |
 890                         ODM_RF_TX_PWR_TRACK     |
 891                         ODM_BB_RA_MASK          |
 892                         ODM_BB_FA_CNT                   |
 893                         ODM_BB_RSSI_MONITOR     |
 894                         ODM_BB_CFO_TRACKING     |
 895                         /*                              ODM_BB_PWR_TRAIN                |*/
 896                         ODM_BB_NHM_CNT          |
 897                         ODM_BB_PRIMARY_CCA;
 898                 break;
 899
 900         case    ODM_RTL8723B:
 901                 support_ability |=
 902                         ODM_BB_DIG                              |
 903                         ODM_BB_RA_MASK          |
 904                         ODM_BB_FA_CNT                   |
 905                         ODM_BB_RSSI_MONITOR     |
 906                         ODM_BB_CCK_PD                   |
 907                         ODM_RF_TX_PWR_TRACK     |
 908                         ODM_RF_RX_GAIN_TRACK    |
 909                         ODM_RF_CALIBRATION              |
 910                         ODM_BB_CFO_TRACKING     |
 911                         /*                              ODM_BB_PWR_TRAIN                |*/
 912                         ODM_BB_NHM_CNT;
 913                 break;
 914
 915         case    ODM_RTL8703B:
 916                 support_ability |=
 917                         ODM_BB_DIG                              |
 918                         ODM_BB_RA_MASK          |
 919                         ODM_BB_FA_CNT                   |
 920                         ODM_BB_RSSI_MONITOR     |
 921                         ODM_BB_CCK_PD                   |
 922                         ODM_BB_CFO_TRACKING     |
 923                         /* ODM_BB_PWR_TRAIN     | */
 924                         ODM_BB_NHM_CNT          |
 925                         ODM_RF_TX_PWR_TRACK     |
 926                         /* ODM_RF_RX_GAIN_TRACK | */
 927                         ODM_RF_CALIBRATION;
 928                 break;
 929
 930         case    ODM_RTL8723D:
 931                 support_ability |=
 932                         ODM_BB_DIG                              |
 933                         ODM_BB_RA_MASK          |
 934                         ODM_BB_FA_CNT                   |
 935                         ODM_BB_RSSI_MONITOR     |
 936                         ODM_BB_CCK_PD                   |
 937                         ODM_BB_CFO_TRACKING     |
 938                         /* ODM_BB_PWR_TRAIN     | */
 939                         ODM_BB_NHM_CNT          |
 940                         ODM_RF_TX_PWR_TRACK;
 941                         /* ODM_RF_RX_GAIN_TRACK | */
 942                         /* ODM_RF_CALIBRATION   | */
 943                 break;
 944 /* JJ ADD 20161014 */
 945         case    ODM_RTL8710B:
 946                 support_ability |=
 947                         ODM_BB_DIG                              |
 948                         ODM_BB_RA_MASK          |
 949                         ODM_BB_FA_CNT                   |
 950                         ODM_BB_RSSI_MONITOR     |
 951                         ODM_BB_CCK_PD                   |
 952                         ODM_BB_CFO_TRACKING     |
 953                         /* ODM_BB_PWR_TRAIN     | */
 954                         ODM_BB_NHM_CNT          |
 955                         ODM_RF_TX_PWR_TRACK;
 956                         /* ODM_RF_RX_GAIN_TRACK | */
 957                         /* ODM_RF_CALIBRATION   | */
 958                 break;
 959
 960         case    ODM_RTL8188F:
 961                 support_ability |=
 962                         ODM_BB_DIG                              |
 963                         ODM_BB_RA_MASK          |
 964                         ODM_BB_FA_CNT                   |
 965                         ODM_BB_RSSI_MONITOR     |
 966                         ODM_BB_CCK_PD                   |
 967                         ODM_BB_CFO_TRACKING     |
 968                         ODM_BB_NHM_CNT          |
 969                         ODM_RF_TX_PWR_TRACK     |
 970                         ODM_RF_CALIBRATION;
 971                 break;
 972
 973         #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
 974         case    ODM_RTL8198F:
 975         case    ODM_RTL8197F:
 976                 support_ability |=
 977                         ODM_BB_DIG                              |
 978                         ODM_BB_RA_MASK          |
 979                         ODM_BB_FA_CNT                   |
 980                         ODM_BB_RSSI_MONITOR     |
 981                         ODM_BB_CCK_PD                   |
 982                         ODM_BB_CFO_TRACKING     |
 983                         ODM_BB_NHM_CNT          |
 984                         ODM_RF_TX_PWR_TRACK     |
 985                         ODM_RF_CALIBRATION;
 986                 break;
 987         #endif
 988
 989         #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
 990         case    ODM_RTL8195A:
 991                 support_ability |=
 992                         ODM_BB_DIG                              |
 993                         ODM_BB_RA_MASK          |
 994                         ODM_BB_FA_CNT                   |
 995                         ODM_BB_RSSI_MONITOR     |
 996                         ODM_BB_CCK_PD                   |
 997                         ODM_BB_CFO_TRACKING     |
 998                         ODM_BB_NHM_CNT          |
 999                         ODM_RF_TX_PWR_TRACK     |
1000                         ODM_RF_CALIBRATION;
1001                 break;
1002         #endif
1003
1004         /*---------------AC Series-------------------*/
1005
1006         case    ODM_RTL8812:
1007         case    ODM_RTL8821:
1008         case    ODM_RTL8881A:
1009                 support_ability |=
1010                         ODM_BB_DIG                              |
1011                         ODM_BB_FA_CNT                   |
1012                         ODM_BB_RSSI_MONITOR     |
1013                         ODM_BB_RA_MASK          |
1014                         ODM_RF_TX_PWR_TRACK     |
1015                         ODM_BB_CFO_TRACKING     |
1016                         /*                              ODM_BB_PWR_TRAIN                |*/
1017                         ODM_BB_DYNAMIC_TXPWR    |
1018                         ODM_BB_NHM_CNT;
1019                 break;
1020
1021         case ODM_RTL8814B:
1022         case ODM_RTL8814A:
1023                 support_ability |=
1024                         ODM_BB_DIG                              |
1025                         ODM_BB_FA_CNT                   |
1026                         ODM_BB_RSSI_MONITOR     |
1027                         ODM_BB_RA_MASK          |
1028                         ODM_RF_TX_PWR_TRACK     |
1029                         ODM_BB_CCK_PD                   |
1030                         ODM_BB_CFO_TRACKING     |
1031                         ODM_BB_DYNAMIC_TXPWR    |
1032                         ODM_BB_NHM_CNT;
1033                 break;
1034
1035         case ODM_RTL8822B:
1036                 support_ability |=
1037                         ODM_BB_DIG                              |
1038                         ODM_BB_FA_CNT                   |
1039                         ODM_BB_CCK_PD                   |
1040                         ODM_BB_CFO_TRACKING     |
1041                         ODM_BB_RATE_ADAPTIVE    |
1042                         ODM_BB_RSSI_MONITOR     |
1043                         ODM_BB_RA_MASK          |
1044                         ODM_RF_TX_PWR_TRACK;
1045                 break;
1046
1047         case ODM_RTL8821C:
1048                 support_ability |=
1049                         ODM_BB_DIG                              |
1050                         ODM_BB_RA_MASK          |
1051                         ODM_BB_CCK_PD                   |
1052                         ODM_BB_FA_CNT                   |
1053                         ODM_BB_RSSI_MONITOR     |
1054                         ODM_BB_RATE_ADAPTIVE    |
1055                         ODM_RF_TX_PWR_TRACK     |
1056 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
1057                         ODM_MAC_EDCA_TURBO      |
1058 #endif
1059                         ODM_BB_CFO_TRACKING;    /* |
1060  *                              ODM_BB_DYNAMIC_TXPWR    |
1061  *                              ODM_BB_NHM_CNT;*/
1062                 break;
1063
1064         default:
1065                 support_ability |=
1066                         ODM_BB_DIG                              |
1067                         ODM_BB_FA_CNT                   |
1068                         ODM_BB_CCK_PD                   |
1069                         ODM_BB_CFO_TRACKING     |
1070                         ODM_BB_RATE_ADAPTIVE    |
1071                         ODM_BB_RSSI_MONITOR     |
1072                         ODM_BB_RA_MASK          |
1073                         ODM_RF_TX_PWR_TRACK;
1074
1075                         dbg_print("[Warning] Supportability Init Warning !!!\n");
1076                 break;
1077
1078         }
1079
1080         if (*(p_dm_odm->p_enable_antdiv))
1081                 support_ability |= ODM_BB_ANT_DIV;
1082
1083         if (*(p_dm_odm->p_enable_adaptivity)) {
1084
1085                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM adaptivity is set to Enabled!!!\n"));
1086
1087                 support_ability |= ODM_BB_ADAPTIVITY;
1088
1089                 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1090                 phydm_adaptivity_info_init(p_dm_odm, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE, p_mgnt_info->RegEnableCarrierSense);
1091                 phydm_adaptivity_info_init(p_dm_odm, PHYDM_ADAPINFO_DCBACKOFF, p_mgnt_info->RegDCbackoff);
1092                 phydm_adaptivity_info_init(p_dm_odm, PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY, p_mgnt_info->RegDmLinkAdaptivity);
1093                 phydm_adaptivity_info_init(p_dm_odm, PHYDM_ADAPINFO_AP_NUM_TH, p_mgnt_info->RegAPNumTH);
1094                 phydm_adaptivity_info_init(p_dm_odm, PHYDM_ADAPINFO_TH_L2H_INI, p_mgnt_info->RegL2HForAdaptivity);
1095                 phydm_adaptivity_info_init(p_dm_odm, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, p_mgnt_info->RegHLDiffForAdaptivity);
1096                 #endif
1097
1098         } else {
1099                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM adaptivity is set to disnabled!!!\n"));
1100                 /**/
1101         }
1102
1103         ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHYDM support_ability = ((0x%x))\n", support_ability));
1104         odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_ABILITY, support_ability);
1105 }
1106 #endif
1107
1108 /*
1109  * 2011/09/21 MH Add to describe different team necessary resource allocate??
1110  *   */
1111 void
1112 odm_dm_init(
1113         struct PHY_DM_STRUCT            *p_dm_odm
1114 )
1115 {
1116 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1117         struct _ADAPTER         *adapter = p_dm_odm->adapter;
1118         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(adapter);
1119 #endif
1120
1121 #if SUPPORTABLITY_PHYDMLIZE
1122         phydm_supportability_init(p_dm_odm);
1123 #endif
1124         odm_common_info_self_init(p_dm_odm);
1125         odm_dig_init(p_dm_odm);
1126         phydm_nhm_counter_statistics_init(p_dm_odm);
1127         phydm_adaptivity_init(p_dm_odm);
1128         phydm_ra_info_init(p_dm_odm);
1129         odm_rate_adaptive_mask_init(p_dm_odm);
1130         odm_cfo_tracking_init(p_dm_odm);
1131 #if PHYDM_SUPPORT_EDCA
1132         odm_edca_turbo_init(p_dm_odm);
1133 #endif
1134         odm_rssi_monitor_init(p_dm_odm);
1135         phydm_rf_init(p_dm_odm);
1136         odm_txpowertracking_init(p_dm_odm);
1137
1138 #if (RTL8822B_SUPPORT == 1)
1139                         if (p_dm_odm->support_ic_type & ODM_RTL8822B)
1140                                 phydm_txcurrentcalibration(p_dm_odm);
1141 #endif
1142
1143         odm_antenna_diversity_init(p_dm_odm);
1144 #if (CONFIG_DYNAMIC_RX_PATH == 1)
1145         phydm_dynamic_rx_path_init(p_dm_odm);
1146 #endif
1147         odm_auto_channel_select_init(p_dm_odm);
1148         odm_path_diversity_init(p_dm_odm);
1149         odm_dynamic_tx_power_init(p_dm_odm);
1150         phydm_init_ra_info(p_dm_odm);
1151 #if (PHYDM_LA_MODE_SUPPORT == 1)
1152         adc_smp_init(p_dm_odm);
1153 #endif
1154
1155 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1156         #ifdef BEAMFORMING_VERSION_1
1157         if (p_hal_data->beamforming_version == BEAMFORMING_VERSION_1)
1158         #endif
1159         {
1160                 phydm_beamforming_init(p_dm_odm);
1161         }
1162 #endif
1163
1164         if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
1165                 #if (defined(CONFIG_BB_POWER_SAVING))
1166                 odm_dynamic_bb_power_saving_init(p_dm_odm);
1167                 #endif
1168
1169                 #if (RTL8188E_SUPPORT == 1)
1170                 if (p_dm_odm->support_ic_type == ODM_RTL8188E) {
1171                         odm_primary_cca_init(p_dm_odm);
1172                         odm_ra_info_init_all(p_dm_odm);
1173                 }
1174                 #endif
1175
1176 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1177
1178                 #if (RTL8723B_SUPPORT == 1)
1179                 if (p_dm_odm->support_ic_type == ODM_RTL8723B)
1180                         odm_sw_ant_detect_init(p_dm_odm);
1181                 #endif
1182
1183                 #if (RTL8192E_SUPPORT == 1)
1184                 if (p_dm_odm->support_ic_type == ODM_RTL8192E)
1185                         odm_primary_cca_check_init(p_dm_odm);
1186                 #endif
1187
1188 #endif
1189
1190         }
1191
1192         #if (CONFIG_PSD_TOOL == 1)
1193         phydm_psd_init(p_dm_odm);
1194         #endif
1195
1196 }
1197
1198 void
1199 odm_dm_reset(
1200         struct PHY_DM_STRUCT            *p_dm_odm
1201 )
1202 {
1203         struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table;
1204
1205         odm_ant_div_reset(p_dm_odm);
1206         phydm_set_edcca_threshold_api(p_dm_odm, p_dm_dig_table->cur_ig_value);
1207 }
1208
1209
1210 void
1211 phydm_support_ability_debug(
1212         void            *p_dm_void,
1213         u32             *const dm_value,
1214         u32                     *_used,
1215         char                    *output,
1216         u32                     *_out_len
1217 )
1218 {
1219         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
1220         u32                     pre_support_ability;
1221         u32 used = *_used;
1222         u32 out_len = *_out_len;
1223
1224         pre_support_ability = p_dm_odm->support_ability ;
1225         PHYDM_SNPRINTF((output + used, out_len - used, "\n%s\n", "================================"));
1226         if (dm_value[0] == 100) {
1227                 PHYDM_SNPRINTF((output + used, out_len - used, "[Supportability] PhyDM Selection\n"));
1228                 PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================"));
1229                 PHYDM_SNPRINTF((output + used, out_len - used, "00. (( %s ))DIG\n", ((p_dm_odm->support_ability & ODM_BB_DIG) ? ("V") : ("."))));
1230                 PHYDM_SNPRINTF((output + used, out_len - used, "01. (( %s ))RA_MASK\n", ((p_dm_odm->support_ability & ODM_BB_RA_MASK) ? ("V") : ("."))));
1231                 PHYDM_SNPRINTF((output + used, out_len - used, "02. (( %s ))DYNAMIC_TXPWR\n", ((p_dm_odm->support_ability & ODM_BB_DYNAMIC_TXPWR) ? ("V") : ("."))));
1232                 PHYDM_SNPRINTF((output + used, out_len - used, "03. (( %s ))FA_CNT\n", ((p_dm_odm->support_ability & ODM_BB_FA_CNT) ? ("V") : ("."))));
1233                 PHYDM_SNPRINTF((output + used, out_len - used, "04. (( %s ))RSSI_MONITOR\n", ((p_dm_odm->support_ability & ODM_BB_RSSI_MONITOR) ? ("V") : ("."))));
1234                 PHYDM_SNPRINTF((output + used, out_len - used, "05. (( %s ))CCK_PD\n", ((p_dm_odm->support_ability & ODM_BB_CCK_PD) ? ("V") : ("."))));
1235                 PHYDM_SNPRINTF((output + used, out_len - used, "06. (( %s ))ANT_DIV\n", ((p_dm_odm->support_ability & ODM_BB_ANT_DIV) ? ("V") : ("."))));
1236                 PHYDM_SNPRINTF((output + used, out_len - used, "08. (( %s ))PWR_TRAIN\n", ((p_dm_odm->support_ability & ODM_BB_PWR_TRAIN) ? ("V") : ("."))));
1237                 PHYDM_SNPRINTF((output + used, out_len - used, "09. (( %s ))RATE_ADAPTIVE\n", ((p_dm_odm->support_ability & ODM_BB_RATE_ADAPTIVE) ? ("V") : ("."))));
1238                 PHYDM_SNPRINTF((output + used, out_len - used, "10. (( %s ))PATH_DIV\n", ((p_dm_odm->support_ability & ODM_BB_PATH_DIV) ? ("V") : ("."))));
1239                 PHYDM_SNPRINTF((output + used, out_len - used, "13. (( %s ))ADAPTIVITY\n", ((p_dm_odm->support_ability & ODM_BB_ADAPTIVITY) ? ("V") : ("."))));
1240                 PHYDM_SNPRINTF((output + used, out_len - used, "14. (( %s ))struct _CFO_TRACKING_\n", ((p_dm_odm->support_ability & ODM_BB_CFO_TRACKING) ? ("V") : ("."))));
1241                 PHYDM_SNPRINTF((output + used, out_len - used, "15. (( %s ))NHM_CNT\n", ((p_dm_odm->support_ability & ODM_BB_NHM_CNT) ? ("V") : ("."))));
1242                 PHYDM_SNPRINTF((output + used, out_len - used, "16. (( %s ))PRIMARY_CCA\n", ((p_dm_odm->support_ability & ODM_BB_PRIMARY_CCA) ? ("V") : ("."))));
1243                 PHYDM_SNPRINTF((output + used, out_len - used, "17. (( %s ))TXBF\n", ((p_dm_odm->support_ability & ODM_BB_TXBF) ? ("V") : ("."))));
1244                 PHYDM_SNPRINTF((output + used, out_len - used, "18. (( %s ))DYNAMIC_ARFR\n", ((p_dm_odm->support_ability & ODM_BB_DYNAMIC_ARFR) ? ("V") : ("."))));
1245                 PHYDM_SNPRINTF((output + used, out_len - used, "20. (( %s ))EDCA_TURBO\n", ((p_dm_odm->support_ability & ODM_MAC_EDCA_TURBO) ? ("V") : ("."))));
1246                 PHYDM_SNPRINTF((output + used, out_len - used, "21. (( %s ))DYNAMIC_RX_PATH\n", ((p_dm_odm->support_ability & ODM_BB_DYNAMIC_RX_PATH) ? ("V") : ("."))));
1247                 PHYDM_SNPRINTF((output + used, out_len - used, "24. (( %s ))TX_PWR_TRACK\n", ((p_dm_odm->support_ability & ODM_RF_TX_PWR_TRACK) ? ("V") : ("."))));
1248                 PHYDM_SNPRINTF((output + used, out_len - used, "25. (( %s ))RX_GAIN_TRACK\n", ((p_dm_odm->support_ability & ODM_RF_RX_GAIN_TRACK) ? ("V") : ("."))));
1249                 PHYDM_SNPRINTF((output + used, out_len - used, "26. (( %s ))RF_CALIBRATION\n", ((p_dm_odm->support_ability & ODM_RF_CALIBRATION) ? ("V") : ("."))));
1250                 PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================"));
1251         }
1252         /*
1253         else if(dm_value[0] == 101)
1254         {
1255                 p_dm_odm->support_ability = 0 ;
1256                 dbg_print("Disable all support_ability components\n");
1257                 PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "Disable all support_ability components"));
1258         }
1259         */
1260         else {
1261
1262                 if (dm_value[1] == 1) { /* enable */
1263                         p_dm_odm->support_ability |= BIT(dm_value[0]) ;
1264                         if (BIT(dm_value[0]) & ODM_BB_PATH_DIV)
1265                                 odm_path_diversity_init(p_dm_odm);
1266                 } else if (dm_value[1] == 2) /* disable */
1267                         p_dm_odm->support_ability &= ~(BIT(dm_value[0])) ;
1268                 else {
1269                         /* dbg_print("\n[Warning!!!]  1:enable,  2:disable \n\n"); */
1270                         PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Warning!!!]  1:enable,  2:disable"));
1271                 }
1272         }
1273         PHYDM_SNPRINTF((output + used, out_len - used, "pre-support_ability  =  0x%x\n",  pre_support_ability));
1274         PHYDM_SNPRINTF((output + used, out_len - used, "Curr-support_ability =  0x%x\n", p_dm_odm->support_ability));
1275         PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================"));
1276 }
1277
1278 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1279 /*
1280  * tmp modify for LC Only
1281  *   */
1282 void
1283 odm_dm_watchdog_lps(
1284         struct PHY_DM_STRUCT            *p_dm_odm
1285 )
1286 {
1287         odm_common_info_self_update(p_dm_odm);
1288         odm_false_alarm_counter_statistics(p_dm_odm);
1289         odm_rssi_monitor_check(p_dm_odm);
1290         odm_dig_by_rssi_lps(p_dm_odm);
1291         odm_cck_packet_detection_thresh(p_dm_odm);
1292         odm_common_info_self_reset(p_dm_odm);
1293
1294         if (*(p_dm_odm->p_is_power_saving) == true)
1295                 return;
1296 }
1297 #endif
1298
1299 void
1300 phydm_watchdog_mp(
1301         struct PHY_DM_STRUCT            *p_dm_odm
1302 )
1303 {
1304 #if (CONFIG_DYNAMIC_RX_PATH == 1)
1305         phydm_dynamic_rx_path_caller(p_dm_odm);
1306 #endif
1307 }
1308 /*
1309  * 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM.
1310  * You can not add any dummy function here, be care, you can only use DM structure
1311  * to perform any new ODM_DM.
1312  *   */
1313 void
1314 odm_dm_watchdog(
1315         struct PHY_DM_STRUCT            *p_dm_odm
1316 )
1317 {
1318         odm_common_info_self_update(p_dm_odm);
1319         phydm_basic_dbg_message(p_dm_odm);
1320         odm_hw_setting(p_dm_odm);
1321
1322 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
1323         {
1324                 struct rtl8192cd_priv *priv             = p_dm_odm->priv;
1325                 if ((priv->auto_channel != 0) && (priv->auto_channel != 2)) /* if struct _ACS_ running, do not do FA/CCA counter read */
1326                         return;
1327         }
1328 #endif
1329         odm_false_alarm_counter_statistics(p_dm_odm);
1330         phydm_noisy_detection(p_dm_odm);
1331
1332         odm_rssi_monitor_check(p_dm_odm);
1333
1334         if (*(p_dm_odm->p_is_power_saving) == true) {
1335                 odm_dig_by_rssi_lps(p_dm_odm);
1336                 phydm_adaptivity(p_dm_odm);
1337 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
1338                 odm_antenna_diversity(p_dm_odm); /*enable AntDiv in PS mode, request from SD4 Jeff*/
1339 #endif
1340                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("DMWatchdog in power saving mode\n"));
1341                 return;
1342         }
1343
1344         phydm_check_adaptivity(p_dm_odm);
1345         odm_update_power_training_state(p_dm_odm);
1346         odm_DIG(p_dm_odm);
1347         phydm_adaptivity(p_dm_odm);
1348         odm_cck_packet_detection_thresh(p_dm_odm);
1349
1350         phydm_ra_info_watchdog(p_dm_odm);
1351 #if PHYDM_SUPPORT_EDCA
1352         odm_edca_turbo_check(p_dm_odm);
1353 #endif
1354         odm_path_diversity(p_dm_odm);
1355         odm_cfo_tracking(p_dm_odm);
1356         odm_dynamic_tx_power(p_dm_odm);
1357         odm_antenna_diversity(p_dm_odm);
1358 #if (CONFIG_DYNAMIC_RX_PATH == 1)
1359         phydm_dynamic_rx_path(p_dm_odm);
1360 #endif
1361
1362 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1363         phydm_beamforming_watchdog(p_dm_odm);
1364 #endif
1365
1366         phydm_rf_watchdog(p_dm_odm);
1367
1368         if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
1369
1370 #if (RTL8188E_SUPPORT == 1)
1371                 if (p_dm_odm->support_ic_type == ODM_RTL8188E)
1372                         odm_dynamic_primary_cca(p_dm_odm);
1373 #endif
1374
1375 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1376
1377 #if (RTL8192E_SUPPORT == 1)
1378                 if (p_dm_odm->support_ic_type == ODM_RTL8192E)
1379                         odm_dynamic_primary_cca_check(p_dm_odm);
1380 #endif
1381 #endif
1382         }
1383
1384 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1385         odm_dtc(p_dm_odm);
1386 #endif
1387
1388         odm_common_info_self_reset(p_dm_odm);
1389
1390 }
1391
1392
1393 /*
1394  * Init /.. Fixed HW value. Only init time.
1395  *   */
1396 void
1397 odm_cmn_info_init(
1398         struct PHY_DM_STRUCT            *p_dm_odm,
1399         enum odm_cmninfo_e      cmn_info,
1400         u32                     value
1401 )
1402 {
1403         /*  */
1404         /* This section is used for init value */
1405         /*  */
1406         switch  (cmn_info) {
1407         /*  */
1408         /* Fixed ODM value. */
1409         /*  */
1410         case    ODM_CMNINFO_ABILITY:
1411                 p_dm_odm->support_ability = (u32)value;
1412                 break;
1413
1414         case    ODM_CMNINFO_RF_TYPE:
1415                 p_dm_odm->rf_type = (u8)value;
1416                 break;
1417
1418         case    ODM_CMNINFO_PLATFORM:
1419                 p_dm_odm->support_platform = (u8)value;
1420                 break;
1421
1422         case    ODM_CMNINFO_INTERFACE:
1423                 p_dm_odm->support_interface = (u8)value;
1424                 break;
1425
1426         case    ODM_CMNINFO_MP_TEST_CHIP:
1427                 p_dm_odm->is_mp_chip = (u8)value;
1428                 break;
1429
1430         case    ODM_CMNINFO_IC_TYPE:
1431                 p_dm_odm->support_ic_type = value;
1432                 break;
1433
1434         case    ODM_CMNINFO_CUT_VER:
1435                 p_dm_odm->cut_version = (u8)value;
1436                 break;
1437
1438         case    ODM_CMNINFO_FAB_VER:
1439                 p_dm_odm->fab_version = (u8)value;
1440                 break;
1441
1442         case    ODM_CMNINFO_RFE_TYPE:
1443                 p_dm_odm->rfe_type = (u8)value;
1444                 phydm_init_hw_info_by_rfe(p_dm_odm);
1445                 break;
1446
1447         case    ODM_CMNINFO_DPK_EN:
1448                 p_dm_odm->dpk_en = (u1Byte)value;
1449                 break;
1450         case    ODM_CMNINFO_RF_ANTENNA_TYPE:
1451                 p_dm_odm->ant_div_type = (u8)value;
1452                 break;
1453
1454         case    ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH:
1455                 p_dm_odm->with_extenal_ant_switch = (u8)value;
1456                 break;
1457
1458         case    ODM_CMNINFO_BE_FIX_TX_ANT:
1459                 p_dm_odm->dm_fat_table.b_fix_tx_ant = (u8)value;
1460                 break;
1461
1462         case    ODM_CMNINFO_BOARD_TYPE:
1463                 if (!p_dm_odm->is_init_hw_info_by_rfe)
1464                         p_dm_odm->board_type = (u8)value;
1465                 break;
1466
1467         case    ODM_CMNINFO_PACKAGE_TYPE:
1468                 if (!p_dm_odm->is_init_hw_info_by_rfe)
1469                         p_dm_odm->package_type = (u8)value;
1470                 break;
1471
1472         case    ODM_CMNINFO_EXT_LNA:
1473                 if (!p_dm_odm->is_init_hw_info_by_rfe)
1474                         p_dm_odm->ext_lna = (u8)value;
1475                 break;
1476
1477         case    ODM_CMNINFO_5G_EXT_LNA:
1478                 if (!p_dm_odm->is_init_hw_info_by_rfe)
1479                         p_dm_odm->ext_lna_5g = (u8)value;
1480                 break;
1481
1482         case    ODM_CMNINFO_EXT_PA:
1483                 if (!p_dm_odm->is_init_hw_info_by_rfe)
1484                         p_dm_odm->ext_pa = (u8)value;
1485                 break;
1486
1487         case    ODM_CMNINFO_5G_EXT_PA:
1488                 if (!p_dm_odm->is_init_hw_info_by_rfe)
1489                         p_dm_odm->ext_pa_5g = (u8)value;
1490                 break;
1491
1492         case    ODM_CMNINFO_GPA:
1493                 if (!p_dm_odm->is_init_hw_info_by_rfe)
1494                         p_dm_odm->type_gpa = (u16)value;
1495                 break;
1496
1497         case    ODM_CMNINFO_APA:
1498                 if (!p_dm_odm->is_init_hw_info_by_rfe)
1499                         p_dm_odm->type_apa = (u16)value;
1500                 break;
1501
1502         case    ODM_CMNINFO_GLNA:
1503                 if (!p_dm_odm->is_init_hw_info_by_rfe)
1504                         p_dm_odm->type_glna = (u16)value;
1505                 break;
1506
1507         case    ODM_CMNINFO_ALNA:
1508                 if (!p_dm_odm->is_init_hw_info_by_rfe)
1509                         p_dm_odm->type_alna = (u16)value;
1510                 break;
1511
1512         case    ODM_CMNINFO_EXT_TRSW:
1513                 if (!p_dm_odm->is_init_hw_info_by_rfe)
1514                         p_dm_odm->ext_trsw = (u8)value;
1515                 break;
1516         case    ODM_CMNINFO_EXT_LNA_GAIN:
1517                 p_dm_odm->ext_lna_gain = (u8)value;
1518                 break;
1519         case    ODM_CMNINFO_PATCH_ID:
1520                 p_dm_odm->patch_id = (u8)value;
1521                 break;
1522         case    ODM_CMNINFO_BINHCT_TEST:
1523                 p_dm_odm->is_in_hct_test = (boolean)value;
1524                 break;
1525         case    ODM_CMNINFO_BWIFI_TEST:
1526                 p_dm_odm->wifi_test = (u8)value;
1527                 break;
1528         case    ODM_CMNINFO_SMART_CONCURRENT:
1529                 p_dm_odm->is_dual_mac_smart_concurrent = (boolean)value;
1530                 break;
1531         case    ODM_CMNINFO_DOMAIN_CODE_2G:
1532                 p_dm_odm->odm_regulation_2_4g = (u8)value;
1533                 break;
1534         case    ODM_CMNINFO_DOMAIN_CODE_5G:
1535                 p_dm_odm->odm_regulation_5g = (u8)value;
1536                 break;
1537         case    ODM_CMNINFO_CONFIG_BB_RF:
1538                 p_dm_odm->config_bbrf = (boolean)value;
1539                 break;
1540         case    ODM_CMNINFO_IQKFWOFFLOAD:
1541                 p_dm_odm->iqk_fw_offload = (u8)value;
1542                 break;
1543         case    ODM_CMNINFO_IQKPAOFF:
1544                 p_dm_odm->rf_calibrate_info.is_iqk_pa_off = (boolean)value;
1545                 break;
1546         case    ODM_CMNINFO_REGRFKFREEENABLE:
1547                 p_dm_odm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value;
1548                 break;
1549         case    ODM_CMNINFO_RFKFREEENABLE:
1550                 p_dm_odm->rf_calibrate_info.rf_kfree_enable = (u8)value;
1551                 break;
1552         case    ODM_CMNINFO_NORMAL_RX_PATH_CHANGE:
1553                 p_dm_odm->normal_rx_path = (u8)value;
1554                 break;
1555         case    ODM_CMNINFO_EFUSE0X3D8:
1556                 p_dm_odm->efuse0x3d8 = (u8)value;
1557                 break;
1558         case    ODM_CMNINFO_EFUSE0X3D7:
1559                 p_dm_odm->efuse0x3d7 = (u8)value;
1560                 break;
1561 #ifdef CONFIG_PHYDM_DFS_MASTER
1562         case    ODM_CMNINFO_DFS_REGION_DOMAIN:
1563                 p_dm_odm->dfs_region_domain = (u8)value;
1564                 break;
1565 #endif
1566         /* To remove the compiler warning, must add an empty default statement to handle the other values. */
1567         default:
1568                 /* do nothing */
1569                 break;
1570
1571         }
1572
1573 }
1574
1575
1576 void
1577 odm_cmn_info_hook(
1578         struct PHY_DM_STRUCT            *p_dm_odm,
1579         enum odm_cmninfo_e      cmn_info,
1580         void                    *p_value
1581 )
1582 {
1583         /*  */
1584         /* Hook call by reference pointer. */
1585         /*  */
1586         switch  (cmn_info) {
1587         /*  */
1588         /* Dynamic call by reference pointer. */
1589         /*  */
1590         case    ODM_CMNINFO_MAC_PHY_MODE:
1591                 p_dm_odm->p_mac_phy_mode = (u8 *)p_value;
1592                 break;
1593
1594         case    ODM_CMNINFO_TX_UNI:
1595                 p_dm_odm->p_num_tx_bytes_unicast = (u64 *)p_value;
1596                 break;
1597
1598         case    ODM_CMNINFO_RX_UNI:
1599                 p_dm_odm->p_num_rx_bytes_unicast = (u64 *)p_value;
1600                 break;
1601
1602         case    ODM_CMNINFO_WM_MODE:
1603                 p_dm_odm->p_wireless_mode = (u8 *)p_value;
1604                 break;
1605
1606         case    ODM_CMNINFO_BAND:
1607                 p_dm_odm->p_band_type = (u8 *)p_value;
1608                 break;
1609
1610         case    ODM_CMNINFO_SEC_CHNL_OFFSET:
1611                 p_dm_odm->p_sec_ch_offset = (u8 *)p_value;
1612                 break;
1613
1614         case    ODM_CMNINFO_SEC_MODE:
1615                 p_dm_odm->p_security = (u8 *)p_value;
1616                 break;
1617
1618         case    ODM_CMNINFO_BW:
1619                 p_dm_odm->p_band_width = (u8 *)p_value;
1620                 break;
1621
1622         case    ODM_CMNINFO_CHNL:
1623                 p_dm_odm->p_channel = (u8 *)p_value;
1624                 break;
1625
1626         case    ODM_CMNINFO_DMSP_GET_VALUE:
1627                 p_dm_odm->p_is_get_value_from_other_mac = (boolean *)p_value;
1628                 break;
1629
1630         case    ODM_CMNINFO_BUDDY_ADAPTOR:
1631                 p_dm_odm->p_buddy_adapter = (struct _ADAPTER **)p_value;
1632                 break;
1633
1634         case    ODM_CMNINFO_DMSP_IS_MASTER:
1635                 p_dm_odm->p_is_master_of_dmsp = (boolean *)p_value;
1636                 break;
1637
1638         case    ODM_CMNINFO_SCAN:
1639                 p_dm_odm->p_is_scan_in_process = (boolean *)p_value;
1640                 break;
1641
1642         case    ODM_CMNINFO_POWER_SAVING:
1643                 p_dm_odm->p_is_power_saving = (boolean *)p_value;
1644                 break;
1645
1646         case    ODM_CMNINFO_ONE_PATH_CCA:
1647                 p_dm_odm->p_one_path_cca = (u8 *)p_value;
1648                 break;
1649
1650         case    ODM_CMNINFO_DRV_STOP:
1651                 p_dm_odm->p_is_driver_stopped = (boolean *)p_value;
1652                 break;
1653
1654         case    ODM_CMNINFO_PNP_IN:
1655                 p_dm_odm->p_is_driver_is_going_to_pnp_set_power_sleep = (boolean *)p_value;
1656                 break;
1657
1658         case    ODM_CMNINFO_INIT_ON:
1659                 p_dm_odm->pinit_adpt_in_progress = (boolean *)p_value;
1660                 break;
1661
1662         case    ODM_CMNINFO_ANT_TEST:
1663                 p_dm_odm->p_antenna_test = (u8 *)p_value;
1664                 break;
1665
1666         case    ODM_CMNINFO_NET_CLOSED:
1667                 p_dm_odm->p_is_net_closed = (boolean *)p_value;
1668                 break;
1669
1670         case    ODM_CMNINFO_FORCED_RATE:
1671                 p_dm_odm->p_forced_data_rate = (u16 *)p_value;
1672                 break;
1673         case    ODM_CMNINFO_ANT_DIV:
1674                 p_dm_odm->p_enable_antdiv = (u8 *)p_value;
1675                 break;
1676         case    ODM_CMNINFO_ADAPTIVITY:
1677                 p_dm_odm->p_enable_adaptivity = (u8 *)p_value;
1678                 break;
1679         case  ODM_CMNINFO_FORCED_IGI_LB:
1680                 p_dm_odm->pu1_forced_igi_lb = (u8 *)p_value;
1681                 break;
1682
1683         case    ODM_CMNINFO_P2P_LINK:
1684                 p_dm_odm->dm_dig_table.is_p2p_in_process = (u8 *)p_value;
1685                 break;
1686
1687         case    ODM_CMNINFO_IS1ANTENNA:
1688                 p_dm_odm->p_is_1_antenna = (boolean *)p_value;
1689                 break;
1690
1691         case    ODM_CMNINFO_RFDEFAULTPATH:
1692                 p_dm_odm->p_rf_default_path = (u8 *)p_value;
1693                 break;
1694
1695         case    ODM_CMNINFO_FCS_MODE:
1696                 p_dm_odm->p_is_fcs_mode_enable = (boolean *)p_value;
1697                 break;
1698         /*add by YuChen for beamforming PhyDM*/
1699         case    ODM_CMNINFO_HUBUSBMODE:
1700                 p_dm_odm->hub_usb_mode = (u8 *)p_value;
1701                 break;
1702         case    ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS:
1703                 p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = (boolean *)p_value;
1704                 break;
1705         case    ODM_CMNINFO_TX_TP:
1706                 p_dm_odm->p_current_tx_tp = (u32 *)p_value;
1707                 break;
1708         case    ODM_CMNINFO_RX_TP:
1709                 p_dm_odm->p_current_rx_tp = (u32 *)p_value;
1710                 break;
1711         case    ODM_CMNINFO_SOUNDING_SEQ:
1712                 p_dm_odm->p_sounding_seq = (u8 *)p_value;
1713                 break;
1714 #ifdef CONFIG_PHYDM_DFS_MASTER
1715         case    ODM_CMNINFO_DFS_MASTER_ENABLE:
1716                 p_dm_odm->dfs_master_enabled = (u8 *)p_value;
1717                 break;
1718 #endif
1719         case    ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC:
1720                 p_dm_odm->dm_fat_table.p_force_tx_ant_by_desc = (u8 *)p_value;
1721                 break;
1722         case    ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA:
1723                 p_dm_odm->dm_fat_table.p_default_s0_s1 = (u8 *)p_value;
1724                 break;
1725
1726         default:
1727                 /*do nothing*/
1728                 break;
1729
1730         }
1731
1732 }
1733
1734
1735 void
1736 odm_cmn_info_ptr_array_hook(
1737         struct PHY_DM_STRUCT            *p_dm_odm,
1738         enum odm_cmninfo_e      cmn_info,
1739         u16                     index,
1740         void                    *p_value
1741 )
1742 {
1743         /*Hook call by reference pointer.*/
1744         switch  (cmn_info) {
1745         /*Dynamic call by reference pointer.    */
1746         case    ODM_CMNINFO_STA_STATUS:
1747                 p_dm_odm->p_odm_sta_info[index] = (struct sta_info *)p_value;
1748
1749                 if (IS_STA_VALID(p_dm_odm->p_odm_sta_info[index]))
1750 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1751                         p_dm_odm->platform2phydm_macid_table[((struct sta_info *)p_value)->AssociatedMacId] = index; /*associated_mac_id are unique bttween different adapter*/
1752 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
1753                         p_dm_odm->platform2phydm_macid_table[((struct sta_info *)p_value)->aid] = index;
1754 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
1755                         p_dm_odm->platform2phydm_macid_table[((struct sta_info *)p_value)->mac_id] = index;
1756 #endif
1757
1758                 break;
1759         /* To remove the compiler warning, must add an empty default statement to handle the other values. */
1760         default:
1761                 /* do nothing */
1762                 break;
1763         }
1764
1765 }
1766
1767
1768 /*
1769  * Update band/CHannel/.. The values are dynamic but non-per-packet.
1770  *   */
1771 void
1772 odm_cmn_info_update(
1773         struct PHY_DM_STRUCT            *p_dm_odm,
1774         u32                     cmn_info,
1775         u64                     value
1776 )
1777 {
1778         /*  */
1779         /* This init variable may be changed in run time. */
1780         /*  */
1781         switch  (cmn_info) {
1782         case ODM_CMNINFO_LINK_IN_PROGRESS:
1783                 p_dm_odm->is_link_in_process = (boolean)value;
1784                 break;
1785
1786         case    ODM_CMNINFO_ABILITY:
1787                 p_dm_odm->support_ability = (u32)value;
1788                 break;
1789
1790         case    ODM_CMNINFO_RF_TYPE:
1791                 p_dm_odm->rf_type = (u8)value;
1792                 break;
1793
1794         case    ODM_CMNINFO_WIFI_DIRECT:
1795                 p_dm_odm->is_wifi_direct = (boolean)value;
1796                 break;
1797
1798         case    ODM_CMNINFO_WIFI_DISPLAY:
1799                 p_dm_odm->is_wifi_display = (boolean)value;
1800                 break;
1801
1802         case    ODM_CMNINFO_LINK:
1803                 p_dm_odm->is_linked = (boolean)value;
1804                 break;
1805
1806         case   ODM_CMNINFO_CMW500LINK:
1807                 p_dm_odm->bLinkedcmw500 = (boolean)value;
1808                 break;
1809
1810         case ODM_CMNINFO_LPSPG:
1811                 p_dm_odm->is_in_lps_pg = (boolean)value;
1812                 break;
1813
1814         case    ODM_CMNINFO_STATION_STATE:
1815                 p_dm_odm->bsta_state = (boolean)value;
1816                 break;
1817
1818         case    ODM_CMNINFO_RSSI_MIN:
1819                 p_dm_odm->rssi_min = (u8)value;
1820                 break;
1821
1822         case    ODM_CMNINFO_DBG_COMP:
1823                 p_dm_odm->debug_components = (u32)value;
1824                 break;
1825
1826         case    ODM_CMNINFO_DBG_LEVEL:
1827                 p_dm_odm->debug_level = (u32)value;
1828                 break;
1829         case    ODM_CMNINFO_RA_THRESHOLD_HIGH:
1830                 p_dm_odm->rate_adaptive.high_rssi_thresh = (u8)value;
1831                 break;
1832
1833         case    ODM_CMNINFO_RA_THRESHOLD_LOW:
1834                 p_dm_odm->rate_adaptive.low_rssi_thresh = (u8)value;
1835                 break;
1836 #if defined(BT_SUPPORT) && (BT_SUPPORT == 1)
1837         /* The following is for BT HS mode and BT coexist mechanism. */
1838         case ODM_CMNINFO_BT_ENABLED:
1839                 p_dm_odm->is_bt_enabled = (boolean)value;
1840                 break;
1841
1842         case ODM_CMNINFO_BT_HS_CONNECT_PROCESS:
1843                 p_dm_odm->is_bt_connect_process = (boolean)value;
1844                 break;
1845
1846         case ODM_CMNINFO_BT_HS_RSSI:
1847                 p_dm_odm->bt_hs_rssi = (u8)value;
1848                 break;
1849
1850         case    ODM_CMNINFO_BT_OPERATION:
1851                 p_dm_odm->is_bt_hs_operation = (boolean)value;
1852                 break;
1853
1854         case    ODM_CMNINFO_BT_LIMITED_DIG:
1855                 p_dm_odm->is_bt_limited_dig = (boolean)value;
1856                 break;
1857
1858         case ODM_CMNINFO_BT_DIG:
1859                 p_dm_odm->bt_hs_dig_val = (u8)value;
1860                 break;
1861
1862         case    ODM_CMNINFO_BT_BUSY:
1863                 p_dm_odm->is_bt_busy = (boolean)value;
1864                 break;
1865
1866         case    ODM_CMNINFO_BT_DISABLE_EDCA:
1867                 p_dm_odm->is_bt_disable_edca_turbo = (boolean)value;
1868                 break;
1869 #endif
1870
1871 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)              /* for repeater mode add by YuChen 2014.06.23 */
1872 #ifdef UNIVERSAL_REPEATER
1873         case    ODM_CMNINFO_VXD_LINK:
1874                 p_dm_odm->vxd_linked = (boolean)value;
1875                 break;
1876 #endif
1877 #endif
1878
1879         case    ODM_CMNINFO_AP_TOTAL_NUM:
1880                 p_dm_odm->ap_total_num = (u8)value;
1881                 break;
1882
1883         case    ODM_CMNINFO_POWER_TRAINING:
1884                 p_dm_odm->is_disable_power_training = (boolean)value;
1885                 break;
1886
1887 #ifdef CONFIG_PHYDM_DFS_MASTER
1888         case    ODM_CMNINFO_DFS_REGION_DOMAIN:
1889                 p_dm_odm->dfs_region_domain = (u8)value;
1890                 break;
1891 #endif
1892
1893 #if 0
1894         case    ODM_CMNINFO_OP_MODE:
1895                 p_dm_odm->op_mode = (u8)value;
1896                 break;
1897
1898         case    ODM_CMNINFO_WM_MODE:
1899                 p_dm_odm->wireless_mode = (u8)value;
1900                 break;
1901
1902         case    ODM_CMNINFO_BAND:
1903                 p_dm_odm->band_type = (u8)value;
1904                 break;
1905
1906         case    ODM_CMNINFO_SEC_CHNL_OFFSET:
1907                 p_dm_odm->sec_ch_offset = (u8)value;
1908                 break;
1909
1910         case    ODM_CMNINFO_SEC_MODE:
1911                 p_dm_odm->security = (u8)value;
1912                 break;
1913
1914         case    ODM_CMNINFO_BW:
1915                 p_dm_odm->band_width = (u8)value;
1916                 break;
1917
1918         case    ODM_CMNINFO_CHNL:
1919                 p_dm_odm->channel = (u8)value;
1920                 break;
1921 #endif
1922         default:
1923                 /* do nothing */
1924                 break;
1925         }
1926
1927
1928 }
1929
1930 u32
1931 phydm_cmn_info_query(
1932         struct PHY_DM_STRUCT                                    *p_dm_odm,
1933         enum phydm_info_query_e                 info_type
1934 )
1935 {
1936         struct _FALSE_ALARM_STATISTICS  *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT);
1937
1938         switch (info_type) {
1939         case PHYDM_INFO_FA_OFDM:
1940                 return false_alm_cnt->cnt_ofdm_fail;
1941
1942         case PHYDM_INFO_FA_CCK:
1943                 return false_alm_cnt->cnt_cck_fail;
1944
1945         case PHYDM_INFO_FA_TOTAL:
1946                 return false_alm_cnt->cnt_all;
1947
1948         case PHYDM_INFO_CCA_OFDM:
1949                 return false_alm_cnt->cnt_ofdm_cca;
1950
1951         case PHYDM_INFO_CCA_CCK:
1952                 return false_alm_cnt->cnt_cck_cca;
1953
1954         case PHYDM_INFO_CCA_ALL:
1955                 return false_alm_cnt->cnt_cca_all;
1956
1957         case PHYDM_INFO_CRC32_OK_VHT:
1958                 return false_alm_cnt->cnt_vht_crc32_ok;
1959
1960         case PHYDM_INFO_CRC32_OK_HT:
1961                 return false_alm_cnt->cnt_ht_crc32_ok;
1962
1963         case PHYDM_INFO_CRC32_OK_LEGACY:
1964                 return false_alm_cnt->cnt_ofdm_crc32_ok;
1965
1966         case PHYDM_INFO_CRC32_OK_CCK:
1967                 return false_alm_cnt->cnt_cck_crc32_ok;
1968
1969         case PHYDM_INFO_CRC32_ERROR_VHT:
1970                 return false_alm_cnt->cnt_vht_crc32_error;
1971
1972         case PHYDM_INFO_CRC32_ERROR_HT:
1973                 return false_alm_cnt->cnt_ht_crc32_error;
1974
1975         case PHYDM_INFO_CRC32_ERROR_LEGACY:
1976                 return false_alm_cnt->cnt_ofdm_crc32_error;
1977
1978         case PHYDM_INFO_CRC32_ERROR_CCK:
1979                 return false_alm_cnt->cnt_cck_crc32_error;
1980
1981         case PHYDM_INFO_EDCCA_FLAG:
1982                 return false_alm_cnt->edcca_flag;
1983
1984         case PHYDM_INFO_OFDM_ENABLE:
1985                 return false_alm_cnt->ofdm_block_enable;
1986
1987         case PHYDM_INFO_CCK_ENABLE:
1988                 return false_alm_cnt->cck_block_enable;
1989
1990         case PHYDM_INFO_DBG_PORT_0:
1991                 return false_alm_cnt->dbg_port0;
1992
1993         default:
1994                 return 0xffffffff;
1995
1996         }
1997 }
1998
1999
2000 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2001 void
2002 odm_init_all_work_items(struct PHY_DM_STRUCT    *p_dm_odm)
2003 {
2004
2005         struct _ADAPTER         *p_adapter = p_dm_odm->adapter;
2006 #if USE_WORKITEM
2007
2008 #if CONFIG_DYNAMIC_RX_PATH
2009         odm_initialize_work_item(p_dm_odm,
2010                          &p_dm_odm->dm_drp_table.phydm_dynamic_rx_path_workitem,
2011                  (RT_WORKITEM_CALL_BACK)phydm_dynamic_rx_path_workitem_callback,
2012                                  (void *)p_adapter,
2013                                  "DynamicRxPathWorkitem");
2014
2015 #endif
2016 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
2017         odm_initialize_work_item(p_dm_odm,
2018                  &p_dm_odm->dm_swat_table.phydm_sw_antenna_switch_workitem,
2019                          (RT_WORKITEM_CALL_BACK)odm_sw_antdiv_workitem_callback,
2020                                  (void *)p_adapter,
2021                                  "AntennaSwitchWorkitem");
2022 #endif
2023 #if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2))
2024         odm_initialize_work_item(p_dm_odm,
2025                          &p_dm_odm->dm_sat_table.hl_smart_antenna_workitem,
2026                  (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback,
2027                                  (void *)p_adapter,
2028                                  "hl_smart_ant_workitem");
2029
2030         odm_initialize_work_item(p_dm_odm,
2031                  &p_dm_odm->dm_sat_table.hl_smart_antenna_decision_workitem,
2032                  (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback,
2033                                  (void *)p_adapter,
2034                                  "hl_smart_ant_decision_workitem");
2035 #endif
2036
2037         odm_initialize_work_item(
2038                 p_dm_odm,
2039                 &(p_dm_odm->path_div_switch_workitem),
2040                 (RT_WORKITEM_CALL_BACK)odm_path_div_chk_ant_switch_workitem_callback,
2041                 (void *)p_adapter,
2042                 "SWAS_WorkItem");
2043
2044         odm_initialize_work_item(
2045                 p_dm_odm,
2046                 &(p_dm_odm->cck_path_diversity_workitem),
2047                 (RT_WORKITEM_CALL_BACK)odm_cck_tx_path_diversity_work_item_callback,
2048                 (void *)p_adapter,
2049                 "CCKTXPathDiversityWorkItem");
2050
2051         odm_initialize_work_item(
2052                 p_dm_odm,
2053                 &(p_dm_odm->mpt_dig_workitem),
2054                 (RT_WORKITEM_CALL_BACK)odm_mpt_dig_work_item_callback,
2055                 (void *)p_adapter,
2056                 "mpt_dig_workitem");
2057
2058         odm_initialize_work_item(
2059                 p_dm_odm,
2060                 &(p_dm_odm->ra_rpt_workitem),
2061                 (RT_WORKITEM_CALL_BACK)odm_update_init_rate_work_item_callback,
2062                 (void *)p_adapter,
2063                 "ra_rpt_workitem");
2064
2065 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
2066         odm_initialize_work_item(
2067                 p_dm_odm,
2068                 &(p_dm_odm->fast_ant_training_workitem),
2069                 (RT_WORKITEM_CALL_BACK)odm_fast_ant_training_work_item_callback,
2070                 (void *)p_adapter,
2071                 "fast_ant_training_workitem");
2072 #endif
2073
2074 #endif /*#if USE_WORKITEM*/
2075
2076 #if (BEAMFORMING_SUPPORT == 1)
2077         odm_initialize_work_item(
2078                 p_dm_odm,
2079                 &(p_dm_odm->beamforming_info.txbf_info.txbf_enter_work_item),
2080                 (RT_WORKITEM_CALL_BACK)hal_com_txbf_enter_work_item_callback,
2081                 (void *)p_adapter,
2082                 "txbf_enter_work_item");
2083
2084         odm_initialize_work_item(
2085                 p_dm_odm,
2086                 &(p_dm_odm->beamforming_info.txbf_info.txbf_leave_work_item),
2087                 (RT_WORKITEM_CALL_BACK)hal_com_txbf_leave_work_item_callback,
2088                 (void *)p_adapter,
2089                 "txbf_leave_work_item");
2090
2091         odm_initialize_work_item(
2092                 p_dm_odm,
2093                 &(p_dm_odm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item),
2094                 (RT_WORKITEM_CALL_BACK)hal_com_txbf_fw_ndpa_work_item_callback,
2095                 (void *)p_adapter,
2096                 "txbf_fw_ndpa_work_item");
2097
2098         odm_initialize_work_item(
2099                 p_dm_odm,
2100                 &(p_dm_odm->beamforming_info.txbf_info.txbf_clk_work_item),
2101                 (RT_WORKITEM_CALL_BACK)hal_com_txbf_clk_work_item_callback,
2102                 (void *)p_adapter,
2103                 "txbf_clk_work_item");
2104
2105         odm_initialize_work_item(
2106                 p_dm_odm,
2107                 &(p_dm_odm->beamforming_info.txbf_info.txbf_rate_work_item),
2108                 (RT_WORKITEM_CALL_BACK)hal_com_txbf_rate_work_item_callback,
2109                 (void *)p_adapter,
2110                 "txbf_rate_work_item");
2111
2112         odm_initialize_work_item(
2113                 p_dm_odm,
2114                 &(p_dm_odm->beamforming_info.txbf_info.txbf_status_work_item),
2115                 (RT_WORKITEM_CALL_BACK)hal_com_txbf_status_work_item_callback,
2116                 (void *)p_adapter,
2117                 "txbf_status_work_item");
2118
2119         odm_initialize_work_item(
2120                 p_dm_odm,
2121                 &(p_dm_odm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item),
2122                 (RT_WORKITEM_CALL_BACK)hal_com_txbf_reset_tx_path_work_item_callback,
2123                 (void *)p_adapter,
2124                 "txbf_reset_tx_path_work_item");
2125
2126         odm_initialize_work_item(
2127                 p_dm_odm,
2128                 &(p_dm_odm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item),
2129                 (RT_WORKITEM_CALL_BACK)hal_com_txbf_get_tx_rate_work_item_callback,
2130                 (void *)p_adapter,
2131                 "txbf_get_tx_rate_work_item");
2132 #endif
2133
2134         odm_initialize_work_item(
2135                 p_dm_odm,
2136                 &(p_dm_odm->adaptivity.phydm_pause_edcca_work_item),
2137                 (RT_WORKITEM_CALL_BACK)phydm_pause_edcca_work_item_callback,
2138                 (void *)p_adapter,
2139                 "phydm_pause_edcca_work_item");
2140
2141         odm_initialize_work_item(
2142                 p_dm_odm,
2143                 &(p_dm_odm->adaptivity.phydm_resume_edcca_work_item),
2144                 (RT_WORKITEM_CALL_BACK)phydm_resume_edcca_work_item_callback,
2145                 (void *)p_adapter,
2146                 "phydm_resume_edcca_work_item");
2147
2148 #if (PHYDM_LA_MODE_SUPPORT == 1)
2149         odm_initialize_work_item(
2150                 p_dm_odm,
2151                 &(p_dm_odm->adcsmp.adc_smp_work_item),
2152                 (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
2153                 (void *)p_adapter,
2154                 "adc_smp_work_item");
2155
2156         odm_initialize_work_item(
2157                 p_dm_odm,
2158                 &(p_dm_odm->adcsmp.adc_smp_work_item_1),
2159                 (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
2160                 (void *)p_adapter,
2161                 "adc_smp_work_item_1");
2162 #endif
2163
2164 }
2165
2166 void
2167 odm_free_all_work_items(struct PHY_DM_STRUCT    *p_dm_odm)
2168 {
2169 #if USE_WORKITEM
2170
2171 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
2172         odm_free_work_item(&(p_dm_odm->dm_swat_table.phydm_sw_antenna_switch_workitem));
2173 #endif
2174
2175 #if CONFIG_DYNAMIC_RX_PATH
2176         odm_free_work_item(&(p_dm_odm->dm_drp_table.phydm_dynamic_rx_path_workitem));
2177 #endif
2178
2179
2180
2181 #if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2))
2182         odm_free_work_item(&(p_dm_odm->dm_sat_table.hl_smart_antenna_workitem));
2183         odm_free_work_item(&(p_dm_odm->dm_sat_table.hl_smart_antenna_decision_workitem));
2184 #endif
2185
2186         odm_free_work_item(&(p_dm_odm->path_div_switch_workitem));
2187         odm_free_work_item(&(p_dm_odm->cck_path_diversity_workitem));
2188 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
2189         odm_free_work_item(&(p_dm_odm->fast_ant_training_workitem));
2190 #endif
2191         odm_free_work_item(&(p_dm_odm->mpt_dig_workitem));
2192         odm_free_work_item(&(p_dm_odm->ra_rpt_workitem));
2193         /*odm_free_work_item((&p_dm_odm->sbdcnt_workitem));*/
2194 #endif
2195
2196 #if (BEAMFORMING_SUPPORT == 1)
2197         odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_enter_work_item));
2198         odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_leave_work_item));
2199         odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item));
2200         odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_clk_work_item));
2201         odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_rate_work_item));
2202         odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_status_work_item));
2203         odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item));
2204         odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item));
2205 #endif
2206
2207         odm_free_work_item((&p_dm_odm->adaptivity.phydm_pause_edcca_work_item));
2208         odm_free_work_item((&p_dm_odm->adaptivity.phydm_resume_edcca_work_item));
2209
2210 #if (PHYDM_LA_MODE_SUPPORT == 1)
2211         odm_free_work_item((&p_dm_odm->adcsmp.adc_smp_work_item));
2212         odm_free_work_item((&p_dm_odm->adcsmp.adc_smp_work_item_1));
2213 #endif
2214
2215 }
2216 #endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
2217
2218 #if 0
2219 void
2220 odm_FindMinimumRSSI(
2221         struct PHY_DM_STRUCT            *p_dm_odm
2222 )
2223 {
2224         u32     i;
2225         u8      rssi_min = 0xFF;
2226
2227         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
2228                 /*              if(p_dm_odm->p_odm_sta_info[i] != NULL) */
2229                 if (IS_STA_VALID(p_dm_odm->p_odm_sta_info[i])) {
2230                         if (p_dm_odm->p_odm_sta_info[i]->rssi_ave < rssi_min)
2231                                 rssi_min = p_dm_odm->p_odm_sta_info[i]->rssi_ave;
2232                 }
2233         }
2234
2235         p_dm_odm->rssi_min = rssi_min;
2236
2237 }
2238
2239 void
2240 odm_IsLinked(
2241         struct PHY_DM_STRUCT            *p_dm_odm
2242 )
2243 {
2244         u32 i;
2245         boolean Linked = false;
2246
2247         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
2248                 if (IS_STA_VALID(p_dm_odm->p_odm_sta_info[i])) {
2249                         Linked = true;
2250                         break;
2251                 }
2252
2253         }
2254
2255         p_dm_odm->is_linked = Linked;
2256 }
2257 #endif
2258
2259 void
2260 odm_init_all_timers(
2261         struct PHY_DM_STRUCT    *p_dm_odm
2262 )
2263 {
2264 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
2265         odm_ant_div_timers(p_dm_odm, INIT_ANTDIV_TIMMER);
2266 #endif
2267
2268 #if (CONFIG_DYNAMIC_RX_PATH == 1)
2269         phydm_dynamic_rx_path_timers(p_dm_odm, INIT_DRP_TIMMER);
2270 #endif
2271
2272 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2273 #ifdef MP_TEST
2274         if (p_dm_odm->priv->pshare->rf_ft_var.mp_specific)
2275                 odm_initialize_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer,
2276                         (void *)odm_mpt_dig_callback, NULL, "mpt_dig_timer");
2277 #endif
2278 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2279         odm_initialize_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer,
2280                      (void *)odm_mpt_dig_callback, NULL, "mpt_dig_timer");
2281 #endif
2282
2283 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2284         odm_initialize_timer(p_dm_odm, &p_dm_odm->path_div_switch_timer,
2285                 (void *)odm_path_div_chk_ant_switch_callback, NULL, "PathDivTimer");
2286         odm_initialize_timer(p_dm_odm, &p_dm_odm->cck_path_diversity_timer,
2287                 (void *)odm_cck_tx_path_diversity_callback, NULL, "cck_path_diversity_timer");
2288         odm_initialize_timer(p_dm_odm, &p_dm_odm->sbdcnt_timer,
2289                              (void *)phydm_sbd_callback, NULL, "SbdTimer");
2290 #if (BEAMFORMING_SUPPORT == 1)
2291         odm_initialize_timer(p_dm_odm, &p_dm_odm->beamforming_info.txbf_info.txbf_fw_ndpa_timer,
2292                 (void *)hal_com_txbf_fw_ndpa_timer_callback, NULL, "txbf_fw_ndpa_timer");
2293 #endif
2294 #endif
2295
2296 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
2297 #if (BEAMFORMING_SUPPORT == 1)
2298         odm_initialize_timer(p_dm_odm, &p_dm_odm->beamforming_info.beamforming_timer,
2299                 (void *)beamforming_sw_timer_callback, NULL, "beamforming_timer");
2300 #endif
2301 #endif
2302 }
2303
2304 void
2305 odm_cancel_all_timers(
2306         struct PHY_DM_STRUCT    *p_dm_odm
2307 )
2308 {
2309 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2310         /*  */
2311         /* 2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in */
2312         /* win7 platform. */
2313         /*  */
2314         HAL_ADAPTER_STS_CHK(p_dm_odm);
2315 #endif
2316
2317 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
2318         odm_ant_div_timers(p_dm_odm, CANCEL_ANTDIV_TIMMER);
2319 #endif
2320
2321 #if (CONFIG_DYNAMIC_RX_PATH == 1)
2322         phydm_dynamic_rx_path_timers(p_dm_odm, CANCEL_DRP_TIMMER);
2323 #endif
2324
2325 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2326 #ifdef MP_TEST
2327         if (p_dm_odm->priv->pshare->rf_ft_var.mp_specific)
2328                 odm_cancel_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer);
2329 #endif
2330 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2331         odm_cancel_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer);
2332 #endif
2333
2334 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2335         odm_cancel_timer(p_dm_odm, &p_dm_odm->path_div_switch_timer);
2336         odm_cancel_timer(p_dm_odm, &p_dm_odm->cck_path_diversity_timer);
2337         odm_cancel_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer);
2338         odm_cancel_timer(p_dm_odm, &p_dm_odm->sbdcnt_timer);
2339 #if (BEAMFORMING_SUPPORT == 1)
2340         odm_cancel_timer(p_dm_odm, &p_dm_odm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
2341 #endif
2342 #endif
2343
2344 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
2345 #if (BEAMFORMING_SUPPORT == 1)
2346         odm_cancel_timer(p_dm_odm, &p_dm_odm->beamforming_info.beamforming_timer);
2347 #endif
2348 #endif
2349
2350 }
2351
2352
2353 void
2354 odm_release_all_timers(
2355         struct PHY_DM_STRUCT    *p_dm_odm
2356 )
2357 {
2358 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
2359         odm_ant_div_timers(p_dm_odm, RELEASE_ANTDIV_TIMMER);
2360 #endif
2361
2362 #if (CONFIG_DYNAMIC_RX_PATH == 1)
2363         phydm_dynamic_rx_path_timers(p_dm_odm, RELEASE_DRP_TIMMER);
2364 #endif
2365
2366 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2367 #ifdef MP_TEST
2368         if (p_dm_odm->priv->pshare->rf_ft_var.mp_specific)
2369                 odm_release_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer);
2370 #endif
2371 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2372         odm_release_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer);
2373 #endif
2374
2375 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2376         odm_release_timer(p_dm_odm, &p_dm_odm->path_div_switch_timer);
2377         odm_release_timer(p_dm_odm, &p_dm_odm->cck_path_diversity_timer);
2378         odm_release_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer);
2379         odm_release_timer(p_dm_odm, &p_dm_odm->sbdcnt_timer);
2380 #if (BEAMFORMING_SUPPORT == 1)
2381         odm_release_timer(p_dm_odm, &p_dm_odm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
2382 #endif
2383 #endif
2384
2385 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
2386 #if (BEAMFORMING_SUPPORT == 1)
2387         odm_release_timer(p_dm_odm, &p_dm_odm->beamforming_info.beamforming_timer);
2388 #endif
2389 #endif
2390 }
2391
2392
2393 /* 3============================================================
2394  * 3 Tx Power Tracking
2395  * 3============================================================ */
2396
2397
2398
2399
2400 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2401 void
2402 odm_init_all_threads(
2403         struct PHY_DM_STRUCT    *p_dm_odm
2404 )
2405 {
2406 #ifdef TPT_THREAD
2407         k_tpt_task_init(p_dm_odm->priv);
2408 #endif
2409 }
2410
2411 void
2412 odm_stop_all_threads(
2413         struct PHY_DM_STRUCT    *p_dm_odm
2414 )
2415 {
2416 #ifdef TPT_THREAD
2417         k_tpt_task_stop(p_dm_odm->priv);
2418 #endif
2419 }
2420 #endif
2421
2422
2423 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2424 /*
2425  * 2011/07/26 MH Add an API for testing IQK fail case.
2426  *   */
2427 boolean
2428 odm_check_power_status(
2429         struct _ADAPTER         *adapter)
2430 {
2431
2432         HAL_DATA_TYPE           *p_hal_data = GET_HAL_DATA(adapter);
2433         struct PHY_DM_STRUCT                    *p_dm_odm = &p_hal_data->DM_OutSrc;
2434         RT_RF_POWER_STATE       rt_state;
2435         PMGNT_INFO                      p_mgnt_info     = &(adapter->MgntInfo);
2436
2437         /* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. */
2438         if (p_mgnt_info->init_adpt_in_progress == true) {
2439                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("odm_check_power_status Return true, due to initadapter\n"));
2440                 return  true;
2441         }
2442
2443         /*  */
2444         /*      2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. */
2445         /*  */
2446         adapter->HalFunc.GetHwRegHandler(adapter, HW_VAR_RF_STATE, (u8 *)(&rt_state));
2447         if (adapter->bDriverStopped || adapter->bDriverIsGoingToPnpSetPowerSleep || rt_state == eRfOff) {
2448                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("odm_check_power_status Return false, due to %d/%d/%d\n",
2449                         adapter->bDriverStopped, adapter->bDriverIsGoingToPnpSetPowerSleep, rt_state));
2450                 return  false;
2451         }
2452         return  true;
2453 }
2454 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
2455 boolean
2456 odm_check_power_status(
2457         struct _ADAPTER         *adapter)
2458 {
2459 #if 0
2460         /* HAL_DATA_TYPE                *p_hal_data = GET_HAL_DATA(adapter); */
2461         struct PHY_DM_STRUCT                    *p_dm_odm = &p_hal_data->DM_OutSrc;
2462         RT_RF_POWER_STATE       rt_state;
2463         PMGNT_INFO                      p_mgnt_info     = &(adapter->MgntInfo);
2464
2465         /*  2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. */
2466         if (p_mgnt_info->init_adpt_in_progress == true) {
2467                 ODM_RT_TRACE(p_dm_odm, COMP_INIT, DBG_LOUD, ("odm_check_power_status Return true, due to initadapter"));
2468                 return  true;
2469         }
2470
2471         /* */
2472         /*      2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. */
2473         /* */
2474         phydm_get_hw_reg_interface(p_dm_odm, HW_VAR_RF_STATE, (u8 *)(&rt_state));
2475         if (adapter->is_driver_stopped || adapter->is_driver_is_going_to_pnp_set_power_sleep || rt_state == eRfOff) {
2476                 ODM_RT_TRACE(p_dm_odm, COMP_INIT, DBG_LOUD, ("odm_check_power_status Return false, due to %d/%d/%d\n",
2477                         adapter->is_driver_stopped, adapter->is_driver_is_going_to_pnp_set_power_sleep, rt_state));
2478                 return  false;
2479         }
2480 #endif
2481         return  true;
2482 }
2483 #endif
2484
2485 /* need to ODM CE Platform
2486  * move to here for ANT detection mechanism using */
2487
2488 u32
2489 odm_convert_to_db(
2490         u32     value)
2491 {
2492         u8 i;
2493         u8 j;
2494         u32 dB;
2495
2496         value = value & 0xFFFF;
2497
2498         for (i = 0; i < 12; i++) {
2499                 if (value <= db_invert_table[i][7])
2500                         break;
2501         }
2502
2503         if (i >= 12) {
2504                 return 96;      /* maximum 96 dB */
2505         }
2506
2507         for (j = 0; j < 8; j++) {
2508                 if (value <= db_invert_table[i][j])
2509                         break;
2510         }
2511
2512         dB = (i << 3) + j + 1;
2513
2514         return dB;
2515 }
2516
2517 u32
2518 odm_convert_to_linear(
2519         u32     value)
2520 {
2521         u8 i;
2522         u8 j;
2523         u32 linear;
2524
2525         /* 1dB~96dB */
2526
2527         value = value & 0xFF;
2528
2529         i = (u8)((value - 1) >> 3);
2530         j = (u8)(value - 1) - (i << 3);
2531
2532         linear = db_invert_table[i][j];
2533
2534         return linear;
2535 }
2536
2537 /*
2538  * ODM multi-port consideration, added by Roger, 2013.10.01.
2539  *   */
2540 void
2541 odm_asoc_entry_init(
2542         struct PHY_DM_STRUCT    *p_dm_odm
2543 )
2544 {
2545 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2546         struct _ADAPTER *p_loop_adapter = GetDefaultAdapter(p_dm_odm->adapter);
2547         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(p_loop_adapter);
2548         struct PHY_DM_STRUCT            *p_dm_out_src = &p_hal_data->DM_OutSrc;
2549         u8      total_assoc_entry_num = 0;
2550         u8      index = 0;
2551         u8      adaptercount = 0;
2552
2553         odm_cmn_info_ptr_array_hook(p_dm_out_src, ODM_CMNINFO_STA_STATUS, 0, &p_loop_adapter->MgntInfo.DefaultPort[0]);
2554         p_loop_adapter->MgntInfo.DefaultPort[0].MultiPortStationIdx = total_assoc_entry_num;
2555
2556         adaptercount += 1;
2557         RT_TRACE(COMP_INIT, DBG_LOUD, ("adaptercount=%d\n", adaptercount));
2558         p_loop_adapter = GetNextExtAdapter(p_loop_adapter);
2559         total_assoc_entry_num += 1;
2560
2561         while (p_loop_adapter) {
2562                 for (index = 0; index < ASSOCIATE_ENTRY_NUM; index++) {
2563                         odm_cmn_info_ptr_array_hook(p_dm_out_src, ODM_CMNINFO_STA_STATUS, total_assoc_entry_num + index, &p_loop_adapter->MgntInfo.AsocEntry[index]);
2564                         p_loop_adapter->MgntInfo.AsocEntry[index].MultiPortStationIdx = total_assoc_entry_num + index;
2565                 }
2566
2567                 total_assoc_entry_num += index;
2568                 if (IS_HARDWARE_TYPE_8188E((p_dm_odm->adapter)))
2569                         p_loop_adapter->RASupport = true;
2570                 adaptercount += 1;
2571                 RT_TRACE(COMP_INIT, DBG_LOUD, ("adaptercount=%d\n", adaptercount));
2572                 p_loop_adapter = GetNextExtAdapter(p_loop_adapter);
2573         }
2574
2575         RT_TRACE(COMP_INIT, DBG_LOUD, ("total_assoc_entry_num = %d\n", total_assoc_entry_num));
2576         if (total_assoc_entry_num < (ODM_ASSOCIATE_ENTRY_NUM - 1)) {
2577
2578                 RT_TRACE(COMP_INIT, DBG_LOUD, ("In hook null\n"));
2579                 for (index = total_assoc_entry_num; index < ODM_ASSOCIATE_ENTRY_NUM; index++)
2580                         odm_cmn_info_ptr_array_hook(p_dm_out_src, ODM_CMNINFO_STA_STATUS, index, NULL);
2581         }
2582 #endif
2583 }
2584
2585 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2586 /* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */
2587 void odm_dtc(struct PHY_DM_STRUCT *p_dm_odm)
2588 {
2589 #ifdef CONFIG_DM_RESP_TXAGC
2590 #define DTC_BASE            35  /* RSSI higher than this value, start to decade TX power */
2591 #define DTC_DWN_BASE       (DTC_BASE-5) /* RSSI lower than this value, start to increase TX power */
2592
2593         /* RSSI vs TX power step mapping: decade TX power */
2594         static const u8 dtc_table_down[] = {
2595                 DTC_BASE,
2596                 (DTC_BASE + 5),
2597                 (DTC_BASE + 10),
2598                 (DTC_BASE + 15),
2599                 (DTC_BASE + 20),
2600                 (DTC_BASE + 25)
2601         };
2602
2603         /* RSSI vs TX power step mapping: increase TX power */
2604         static const u8 dtc_table_up[] = {
2605                 DTC_DWN_BASE,
2606                 (DTC_DWN_BASE - 5),
2607                 (DTC_DWN_BASE - 10),
2608                 (DTC_DWN_BASE - 15),
2609                 (DTC_DWN_BASE - 15),
2610                 (DTC_DWN_BASE - 20),
2611                 (DTC_DWN_BASE - 20),
2612                 (DTC_DWN_BASE - 25),
2613                 (DTC_DWN_BASE - 25),
2614                 (DTC_DWN_BASE - 30),
2615                 (DTC_DWN_BASE - 35)
2616         };
2617
2618         u8 i;
2619         u8 dtc_steps = 0;
2620         u8 sign;
2621         u8 resp_txagc = 0;
2622
2623 #if 0
2624         /* As DIG is disabled, DTC is also disable */
2625         if (!(p_dm_odm->support_ability & ODM_XXXXXX))
2626                 return;
2627 #endif
2628
2629         if (DTC_BASE < p_dm_odm->rssi_min) {
2630                 /* need to decade the CTS TX power */
2631                 sign = 1;
2632                 for (i = 0; i < ARRAY_SIZE(dtc_table_down); i++) {
2633                         if ((dtc_table_down[i] >= p_dm_odm->rssi_min) || (dtc_steps >= 6))
2634                                 break;
2635                         else
2636                                 dtc_steps++;
2637                 }
2638         }
2639 #if 0
2640         else if (DTC_DWN_BASE > p_dm_odm->rssi_min) {
2641                 /* needs to increase the CTS TX power */
2642                 sign = 0;
2643                 dtc_steps = 1;
2644                 for (i = 0; i < ARRAY_SIZE(dtc_table_up); i++) {
2645                         if ((dtc_table_up[i] <= p_dm_odm->rssi_min) || (dtc_steps >= 10))
2646                                 break;
2647                         else
2648                                 dtc_steps++;
2649                 }
2650         }
2651 #endif
2652         else {
2653                 sign = 0;
2654                 dtc_steps = 0;
2655         }
2656
2657         resp_txagc = dtc_steps | (sign << 4);
2658         resp_txagc = resp_txagc | (resp_txagc << 5);
2659         odm_write_1byte(p_dm_odm, 0x06d9, resp_txagc);
2660
2661         ODM_RT_TRACE(p_dm_odm, ODM_COMP_PWR_TRAIN, ODM_DBG_LOUD, ("%s rssi_min:%u, set RESP_TXAGC to %s %u\n",
2662                 __func__, p_dm_odm->rssi_min, sign ? "minus" : "plus", dtc_steps));
2663 #endif /* CONFIG_RESP_TXAGC_ADJUST */
2664 }
2665
2666 #endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
2667
2668 void
2669 odm_update_power_training_state(
2670         struct PHY_DM_STRUCT    *p_dm_odm
2671 )
2672 {
2673 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
2674         struct _FALSE_ALARM_STATISTICS  *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT);
2675         struct _dynamic_initial_gain_threshold_                                         *p_dm_dig_table = &p_dm_odm->dm_dig_table;
2676         u32                                             score = 0;
2677
2678         if (!(p_dm_odm->support_ability & ODM_BB_PWR_TRAIN))
2679                 return;
2680
2681         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state()============>\n"));
2682         p_dm_odm->is_change_state = false;
2683
2684         /* Debug command */
2685         if (p_dm_odm->force_power_training_state) {
2686                 if (p_dm_odm->force_power_training_state == 1 && !p_dm_odm->is_disable_power_training) {
2687                         p_dm_odm->is_change_state = true;
2688                         p_dm_odm->is_disable_power_training = true;
2689                 } else if (p_dm_odm->force_power_training_state == 2 && p_dm_odm->is_disable_power_training) {
2690                         p_dm_odm->is_change_state = true;
2691                         p_dm_odm->is_disable_power_training = false;
2692                 }
2693
2694                 p_dm_odm->PT_score = 0;
2695                 p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm = 0;
2696                 p_dm_odm->phy_dbg_info.num_qry_phy_status_cck = 0;
2697                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): force_power_training_state = %d\n",
2698                                 p_dm_odm->force_power_training_state));
2699                 return;
2700         }
2701
2702         if (!p_dm_odm->is_linked)
2703                 return;
2704
2705         /* First connect */
2706         if ((p_dm_odm->is_linked) && (p_dm_dig_table->is_media_connect_0 == false)) {
2707                 p_dm_odm->PT_score = 0;
2708                 p_dm_odm->is_change_state = true;
2709                 p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm = 0;
2710                 p_dm_odm->phy_dbg_info.num_qry_phy_status_cck = 0;
2711                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): First Connect\n"));
2712                 return;
2713         }
2714
2715         /* Compute score */
2716         if (p_dm_odm->nhm_cnt_0 >= 215)
2717                 score = 2;
2718         else if (p_dm_odm->nhm_cnt_0 >= 190)
2719                 score = 1;                                                      /* unknow state */
2720         else {
2721                 u32     rx_pkt_cnt;
2722
2723                 rx_pkt_cnt = (u32)(p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm) + (u32)(p_dm_odm->phy_dbg_info.num_qry_phy_status_cck);
2724
2725                 if ((false_alm_cnt->cnt_cca_all > 31 && rx_pkt_cnt > 31) && (false_alm_cnt->cnt_cca_all >= rx_pkt_cnt)) {
2726                         if ((rx_pkt_cnt + (rx_pkt_cnt >> 1)) <= false_alm_cnt->cnt_cca_all)
2727                                 score = 0;
2728                         else if ((rx_pkt_cnt + (rx_pkt_cnt >> 2)) <= false_alm_cnt->cnt_cca_all)
2729                                 score = 1;
2730                         else
2731                                 score = 2;
2732                 }
2733                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): rx_pkt_cnt = %d, cnt_cca_all = %d\n",
2734                                 rx_pkt_cnt, false_alm_cnt->cnt_cca_all));
2735         }
2736         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): num_qry_phy_status_ofdm = %d, num_qry_phy_status_cck = %d\n",
2737                 (u32)(p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm), (u32)(p_dm_odm->phy_dbg_info.num_qry_phy_status_cck)));
2738         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): nhm_cnt_0 = %d, score = %d\n",
2739                         p_dm_odm->nhm_cnt_0, score));
2740
2741         /* smoothing */
2742         p_dm_odm->PT_score = (score << 4) + (p_dm_odm->PT_score >> 1) + (p_dm_odm->PT_score >> 2);
2743         score = (p_dm_odm->PT_score + 32) >> 6;
2744         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): PT_score = %d, score after smoothing = %d\n",
2745                         p_dm_odm->PT_score, score));
2746
2747         /* mode decision */
2748         if (score == 2) {
2749                 if (p_dm_odm->is_disable_power_training) {
2750                         p_dm_odm->is_change_state = true;
2751                         p_dm_odm->is_disable_power_training = false;
2752                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): Change state\n"));
2753                 }
2754                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): Enable Power Training\n"));
2755         } else if (score == 0) {
2756                 if (!p_dm_odm->is_disable_power_training) {
2757                         p_dm_odm->is_change_state = true;
2758                         p_dm_odm->is_disable_power_training = true;
2759                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): Change state\n"));
2760                 }
2761                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): Disable Power Training\n"));
2762         }
2763
2764         p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm = 0;
2765         p_dm_odm->phy_dbg_info.num_qry_phy_status_cck = 0;
2766 #endif
2767 }
2768
2769
2770
2771 /*===========================================================*/
2772 /* The following is for compile only*/
2773 /*===========================================================*/
2774 /*#define TARGET_CHNL_NUM_2G_5G 59*/
2775 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2776
2777 u8 get_right_chnl_place_for_iqk(u8 chnl)
2778 {
2779         u8      channel_all[TARGET_CHNL_NUM_2G_5G] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100,
2780                 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165
2781                                                 };
2782         u8      place = chnl;
2783
2784
2785         if (chnl > 14) {
2786                 for (place = 14; place < sizeof(channel_all); place++) {
2787                         if (channel_all[place] == chnl)
2788                                 return place - 13;
2789                 }
2790         }
2791
2792         return 0;
2793 }
2794
2795 #endif
2796 /*===========================================================*/
2797
2798 void
2799 phydm_noisy_detection(
2800         struct PHY_DM_STRUCT    *p_dm_odm
2801 )
2802 {
2803         u32  total_fa_cnt, total_cca_cnt;
2804         u32  score = 0, i, score_smooth;
2805
2806         total_cca_cnt = p_dm_odm->false_alm_cnt.cnt_cca_all;
2807         total_fa_cnt  = p_dm_odm->false_alm_cnt.cnt_all;
2808
2809 #if 0
2810         if (total_fa_cnt * 16 >= total_cca_cnt * 14)    /*  87.5 */
2811                 ;
2812         else if (total_fa_cnt * 16 >= total_cca_cnt * 12) /*  75 */
2813                 ;
2814         else if (total_fa_cnt * 16 >= total_cca_cnt * 10) /*  56.25 */
2815                 ;
2816         else if (total_fa_cnt * 16 >= total_cca_cnt * 8) /*  50 */
2817                 ;
2818         else if (total_fa_cnt * 16 >= total_cca_cnt * 7) /*  43.75 */
2819                 ;
2820         else if (total_fa_cnt * 16 >= total_cca_cnt * 6) /*  37.5 */
2821                 ;
2822         else if (total_fa_cnt * 16 >= total_cca_cnt * 5) /*  31.25% */
2823                 ;
2824         else if (total_fa_cnt * 16 >= total_cca_cnt * 4) /*  25% */
2825                 ;
2826         else if (total_fa_cnt * 16 >= total_cca_cnt * 3) /*  18.75% */
2827                 ;
2828         else if (total_fa_cnt * 16 >= total_cca_cnt * 2) /*  12.5% */
2829                 ;
2830         else if (total_fa_cnt * 16 >= total_cca_cnt * 1) /*  6.25% */
2831                 ;
2832 #endif
2833         for (i = 0; i <= 16; i++) {
2834                 if (total_fa_cnt * 16 >= total_cca_cnt * (16 - i)) {
2835                         score = 16 - i;
2836                         break;
2837                 }
2838         }
2839
2840         /* noisy_decision_smooth = noisy_decision_smooth>>1 + (score<<3)>>1; */
2841         p_dm_odm->noisy_decision_smooth = (p_dm_odm->noisy_decision_smooth >> 1) + (score << 2);
2842
2843         /* Round the noisy_decision_smooth: +"3" comes from (2^3)/2-1 */
2844         score_smooth = (total_cca_cnt >= 300) ? ((p_dm_odm->noisy_decision_smooth + 3) >> 3) : 0;
2845
2846         p_dm_odm->noisy_decision = (score_smooth >= 3) ? 1 : 0;
2847 #if 0
2848         switch (score_smooth) {
2849         case 0:
2850                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2851                         ("[NoisyDetection] total_fa_cnt/total_cca_cnt=0%%\n"));
2852                 break;
2853         case 1:
2854                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2855                         ("[NoisyDetection] total_fa_cnt/total_cca_cnt=6.25%%\n"));
2856                 break;
2857         case 2:
2858                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2859                         ("[NoisyDetection] total_fa_cnt/total_cca_cnt=12.5%%\n"));
2860                 break;
2861         case 3:
2862                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2863                         ("[NoisyDetection] total_fa_cnt/total_cca_cnt=18.75%%\n"));
2864                 break;
2865         case 4:
2866                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2867                         ("[NoisyDetection] total_fa_cnt/total_cca_cnt=25%%\n"));
2868                 break;
2869         case 5:
2870                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2871                         ("[NoisyDetection] total_fa_cnt/total_cca_cnt=31.25%%\n"));
2872                 break;
2873         case 6:
2874                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2875                         ("[NoisyDetection] total_fa_cnt/total_cca_cnt=37.5%%\n"));
2876                 break;
2877         case 7:
2878                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2879                         ("[NoisyDetection] total_fa_cnt/total_cca_cnt=43.75%%\n"));
2880                 break;
2881         case 8:
2882                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2883                         ("[NoisyDetection] total_fa_cnt/total_cca_cnt=50%%\n"));
2884                 break;
2885         case 9:
2886                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2887                         ("[NoisyDetection] total_fa_cnt/total_cca_cnt=56.25%%\n"));
2888                 break;
2889         case 10:
2890                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2891                         ("[NoisyDetection] total_fa_cnt/total_cca_cnt=62.5%%\n"));
2892                 break;
2893         case 11:
2894                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2895                         ("[NoisyDetection] total_fa_cnt/total_cca_cnt=68.75%%\n"));
2896                 break;
2897         case 12:
2898                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2899                         ("[NoisyDetection] total_fa_cnt/total_cca_cnt=75%%\n"));
2900                 break;
2901         case 13:
2902                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2903                         ("[NoisyDetection] total_fa_cnt/total_cca_cnt=81.25%%\n"));
2904                 break;
2905         case 14:
2906                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2907                         ("[NoisyDetection] total_fa_cnt/total_cca_cnt=87.5%%\n"));
2908                 break;
2909         case 15:
2910                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2911                         ("[NoisyDetection] total_fa_cnt/total_cca_cnt=93.75%%\n"));
2912                 break;
2913         case 16:
2914                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2915                         ("[NoisyDetection] total_fa_cnt/total_cca_cnt=100%%\n"));
2916                 break;
2917         default:
2918                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2919                         ("[NoisyDetection] Unknown value!! Need Check!!\n"));
2920         }
2921 #endif
2922         ODM_RT_TRACE(p_dm_odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD,
2923                 ("[NoisyDetection] total_cca_cnt=%d, total_fa_cnt=%d, noisy_decision_smooth=%d, score=%d, score_smooth=%d, p_dm_odm->noisy_decision=%d\n",
2924                 total_cca_cnt, total_fa_cnt, p_dm_odm->noisy_decision_smooth, score, score_smooth, p_dm_odm->noisy_decision));
2925
2926 }
2927
2928 void
2929 phydm_set_ext_switch(
2930         void            *p_dm_void,
2931         u32             *const dm_value,
2932         u32             *_used,
2933         char                    *output,
2934         u32             *_out_len
2935 )
2936 {
2937         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
2938         u32                     used = *_used;
2939         u32                     out_len = *_out_len;
2940         u32                     ext_ant_switch =  dm_value[0];
2941
2942         if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) {
2943
2944                 /*Output Pin Settings*/
2945                 odm_set_mac_reg(p_dm_odm, 0x4C, BIT(23), 0); /*select DPDT_P and DPDT_N as output pin*/
2946                 odm_set_mac_reg(p_dm_odm, 0x4C, BIT(24), 1); /*by WLAN control*/
2947
2948                 odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF, 7); /*DPDT_P = 1b'0*/
2949                 odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF0, 7); /*DPDT_N = 1b'0*/
2950
2951                 if (ext_ant_switch == MAIN_ANT) {
2952                         odm_set_bb_reg(p_dm_odm, 0xCB4, (BIT(29) | BIT(28)), 1);
2953                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("***8821A set ant switch = 2b'01 (Main)\n"));
2954                 } else if (ext_ant_switch == AUX_ANT) {
2955                         odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(29) | BIT(28), 2);
2956                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("***8821A set ant switch = 2b'10 (Aux)\n"));
2957                 }
2958         }
2959 }
2960
2961 void
2962 phydm_csi_mask_enable(
2963         void            *p_dm_void,
2964         u32             enable
2965 )
2966 {
2967         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
2968         u32             reg_value = 0;
2969
2970         reg_value = (enable == CSI_MASK_ENABLE) ? 1 : 0;
2971
2972         if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
2973
2974                 odm_set_bb_reg(p_dm_odm, 0xD2C, BIT(28), reg_value);
2975                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable CSI Mask:  Reg 0xD2C[28] = ((0x%x))\n", reg_value));
2976
2977         } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
2978
2979                 odm_set_bb_reg(p_dm_odm, 0x874, BIT(0), reg_value);
2980                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable CSI Mask:  Reg 0x874[0] = ((0x%x))\n", reg_value));
2981         }
2982
2983 }
2984
2985 void
2986 phydm_clean_all_csi_mask(
2987         void            *p_dm_void
2988 )
2989 {
2990         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
2991
2992         if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
2993
2994                 odm_set_bb_reg(p_dm_odm, 0xD40, MASKDWORD, 0);
2995                 odm_set_bb_reg(p_dm_odm, 0xD44, MASKDWORD, 0);
2996                 odm_set_bb_reg(p_dm_odm, 0xD48, MASKDWORD, 0);
2997                 odm_set_bb_reg(p_dm_odm, 0xD4c, MASKDWORD, 0);
2998
2999         } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
3000
3001                 odm_set_bb_reg(p_dm_odm, 0x880, MASKDWORD, 0);
3002                 odm_set_bb_reg(p_dm_odm, 0x884, MASKDWORD, 0);
3003                 odm_set_bb_reg(p_dm_odm, 0x888, MASKDWORD, 0);
3004                 odm_set_bb_reg(p_dm_odm, 0x88c, MASKDWORD, 0);
3005                 odm_set_bb_reg(p_dm_odm, 0x890, MASKDWORD, 0);
3006                 odm_set_bb_reg(p_dm_odm, 0x894, MASKDWORD, 0);
3007                 odm_set_bb_reg(p_dm_odm, 0x898, MASKDWORD, 0);
3008                 odm_set_bb_reg(p_dm_odm, 0x89c, MASKDWORD, 0);
3009         }
3010 }
3011
3012 void
3013 phydm_set_csi_mask_reg(
3014         void            *p_dm_void,
3015         u32             tone_idx_tmp,
3016         u8              tone_direction
3017 )
3018 {
3019         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
3020         u8              byte_offset, bit_offset;
3021         u32             target_reg;
3022         u8              reg_tmp_value;
3023         u32             tone_num = 64;
3024         u32             tone_num_shift = 0;
3025         u32             csi_mask_reg_p = 0, csi_mask_reg_n = 0;
3026
3027         /* calculate real tone idx*/
3028         if ((tone_idx_tmp % 10) >= 5)
3029                 tone_idx_tmp += 10;
3030
3031         tone_idx_tmp = (tone_idx_tmp / 10);
3032
3033         if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
3034
3035                 tone_num = 64;
3036                 csi_mask_reg_p = 0xD40;
3037                 csi_mask_reg_n = 0xD48;
3038
3039         } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
3040
3041                 tone_num = 128;
3042                 csi_mask_reg_p = 0x880;
3043                 csi_mask_reg_n = 0x890;
3044         }
3045
3046         if (tone_direction == FREQ_POSITIVE) {
3047
3048                 if (tone_idx_tmp >= (tone_num - 1))
3049                         tone_idx_tmp = (tone_num - 1);
3050
3051                 byte_offset = (u8)(tone_idx_tmp >> 3);
3052                 bit_offset = (u8)(tone_idx_tmp & 0x7);
3053                 target_reg = csi_mask_reg_p + byte_offset;
3054
3055         } else {
3056                 tone_num_shift = tone_num;
3057
3058                 if (tone_idx_tmp >= tone_num)
3059                         tone_idx_tmp = tone_num;
3060
3061                 tone_idx_tmp = tone_num - tone_idx_tmp;
3062
3063                 byte_offset = (u8)(tone_idx_tmp >> 3);
3064                 bit_offset = (u8)(tone_idx_tmp & 0x7);
3065                 target_reg = csi_mask_reg_n + byte_offset;
3066         }
3067
3068         reg_tmp_value = odm_read_1byte(p_dm_odm, target_reg);
3069         ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Pre Mask tone idx[%d]:  Reg0x%x = ((0x%x))\n", (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value));
3070         reg_tmp_value |= BIT(bit_offset);
3071         odm_write_1byte(p_dm_odm, target_reg, reg_tmp_value);
3072         ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("New Mask tone idx[%d]:  Reg0x%x = ((0x%x))\n", (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value));
3073 }
3074
3075 void
3076 phydm_set_nbi_reg(
3077         void            *p_dm_void,
3078         u32             tone_idx_tmp,
3079         u32             bw
3080 )
3081 {
3082         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
3083         u32     nbi_table_128[NBI_TABLE_SIZE_128] = {25, 55, 85, 115, 135, 155, 185, 205, 225, 245,             /*1~10*/                /*tone_idx X 10*/
3084                      265, 285, 305, 335, 355, 375, 395, 415, 435, 455,  /*11~20*/
3085                                              485, 505, 525, 555, 585, 615, 635
3086                                                 };                              /*21~27*/
3087
3088         u32     nbi_table_256[NBI_TABLE_SIZE_256] = { 25,   55,   85, 115, 135, 155, 175, 195, 225, 245,        /*1~10*/
3089                 265, 285, 305, 325, 345, 365, 385, 405, 425, 445,       /*11~20*/
3090                 465, 485, 505, 525, 545, 565, 585, 605, 625, 645,       /*21~30*/
3091                 665, 695, 715, 735, 755, 775, 795, 815, 835, 855,       /*31~40*/
3092                 875, 895, 915, 935, 955, 975, 995, 1015, 1035, 1055,    /*41~50*/
3093                       1085, 1105, 1125, 1145, 1175, 1195, 1225, 1255, 1275
3094                                                 };      /*51~59*/
3095
3096         u32     reg_idx = 0;
3097         u32     i;
3098         u8      nbi_table_idx = FFT_128_TYPE;
3099
3100         if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES)
3101
3102                 nbi_table_idx = FFT_128_TYPE;
3103         else if (p_dm_odm->support_ic_type & ODM_IC_11AC_1_SERIES)
3104
3105                 nbi_table_idx = FFT_256_TYPE;
3106         else if (p_dm_odm->support_ic_type & ODM_IC_11AC_2_SERIES) {
3107
3108                 if (bw == 80)
3109                         nbi_table_idx = FFT_256_TYPE;
3110                 else /*20M, 40M*/
3111                         nbi_table_idx = FFT_128_TYPE;
3112         }
3113
3114         if (nbi_table_idx == FFT_128_TYPE) {
3115
3116                 for (i = 0; i < NBI_TABLE_SIZE_128; i++) {
3117                         if (tone_idx_tmp < nbi_table_128[i]) {
3118                                 reg_idx = i + 1;
3119                                 break;
3120                         }
3121                 }
3122
3123         } else if (nbi_table_idx == FFT_256_TYPE) {
3124
3125                 for (i = 0; i < NBI_TABLE_SIZE_256; i++) {
3126                         if (tone_idx_tmp < nbi_table_256[i]) {
3127                                 reg_idx = i + 1;
3128                                 break;
3129                         }
3130                 }
3131         }
3132
3133         if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
3134                 odm_set_bb_reg(p_dm_odm, 0xc40, 0x1f000000, reg_idx);
3135                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Set tone idx:  Reg0xC40[28:24] = ((0x%x))\n", reg_idx));
3136                 /**/
3137         } else {
3138                 odm_set_bb_reg(p_dm_odm, 0x87c, 0xfc000, reg_idx);
3139                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Set tone idx: Reg0x87C[19:14] = ((0x%x))\n", reg_idx));
3140                 /**/
3141         }
3142 }
3143
3144
3145 void
3146 phydm_nbi_enable(
3147         void            *p_dm_void,
3148         u32             enable
3149 )
3150 {
3151         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
3152         u32             reg_value = 0;
3153
3154         reg_value = (enable == NBI_ENABLE) ? 1 : 0;
3155
3156         if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
3157
3158                 odm_set_bb_reg(p_dm_odm, 0xc40, BIT(9), reg_value);
3159                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable NBI Reg0xC40[9] = ((0x%x))\n", reg_value));
3160
3161         } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
3162
3163                 odm_set_bb_reg(p_dm_odm, 0x87c, BIT(13), reg_value);
3164                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable NBI Reg0x87C[13] = ((0x%x))\n", reg_value));
3165         }
3166 }
3167
3168 u8
3169 phydm_calculate_fc(
3170         void            *p_dm_void,
3171         u32             channel,
3172         u32             bw,
3173         u32             second_ch,
3174         u32             *fc_in
3175 )
3176 {
3177         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
3178         u32             fc = *fc_in;
3179         u32             start_ch_per_40m[NUM_START_CH_40M] = {36, 44, 52, 60, 100, 108, 116, 124, 132, 140, 149, 157, 165, 173};
3180         u32             start_ch_per_80m[NUM_START_CH_80M] = {36, 52, 100, 116, 132, 149, 165};
3181         u32             *p_start_ch = &(start_ch_per_40m[0]);
3182         u32             num_start_channel = NUM_START_CH_40M;
3183         u32             channel_offset = 0;
3184         u32             i;
3185
3186         /*2.4G*/
3187         if (channel <= 14 && channel > 0) {
3188
3189                 if (bw == 80)
3190                         return  SET_ERROR;
3191
3192                 fc = 2412 + (channel - 1) * 5;
3193
3194                 if (bw == 40 && (second_ch == PHYDM_ABOVE)) {
3195
3196                         if (channel >= 10) {
3197                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)), Scnd_CH = ((%d)) Error setting\n", channel, second_ch));
3198                                 return  SET_ERROR;
3199                         }
3200                         fc += 10;
3201                 } else if (bw == 40 && (second_ch == PHYDM_BELOW)) {
3202
3203                         if (channel <= 2) {
3204                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)), Scnd_CH = ((%d)) Error setting\n", channel, second_ch));
3205                                 return  SET_ERROR;
3206                         }
3207                         fc -= 10;
3208                 }
3209         }
3210         /*5G*/
3211         else if (channel >= 36 && channel <= 177) {
3212
3213                 if (bw != 20) {
3214
3215                         if (bw == 40) {
3216                                 num_start_channel = NUM_START_CH_40M;
3217                                 p_start_ch = &(start_ch_per_40m[0]);
3218                                 channel_offset = CH_OFFSET_40M;
3219                         } else if (bw == 80) {
3220                                 num_start_channel = NUM_START_CH_80M;
3221                                 p_start_ch = &(start_ch_per_80m[0]);
3222                                 channel_offset = CH_OFFSET_80M;
3223                         }
3224
3225                         for (i = 0; i < num_start_channel; i++) {
3226
3227                                 if (channel < p_start_ch[i + 1]) {
3228                                         channel = p_start_ch[i] + channel_offset;
3229                                         break;
3230                                 }
3231                         }
3232                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Mod_CH = ((%d))\n", channel));
3233                 }
3234
3235                 fc = 5180 + (channel - 36) * 5;
3236
3237         } else {
3238                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)) Error setting\n", channel));
3239                 return  SET_ERROR;
3240         }
3241
3242         *fc_in = fc;
3243
3244         return SET_SUCCESS;
3245 }
3246
3247
3248 u8
3249 phydm_calculate_intf_distance(
3250         void            *p_dm_void,
3251         u32             bw,
3252         u32             fc,
3253         u32             f_interference,
3254         u32             *p_tone_idx_tmp_in
3255 )
3256 {
3257         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
3258         u32             bw_up, bw_low;
3259         u32             int_distance;
3260         u32             tone_idx_tmp;
3261         u8              set_result = SET_NO_NEED;
3262
3263         bw_up = fc + bw / 2;
3264         bw_low = fc - bw / 2;
3265
3266         ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low, fc, bw_up, f_interference));
3267
3268         if ((f_interference >= bw_low) && (f_interference <= bw_up)) {
3269
3270                 int_distance = (fc >= f_interference) ? (fc - f_interference) : (f_interference - fc);
3271                 tone_idx_tmp = (int_distance << 5); /* =10*(int_distance /0.3125) */
3272                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("int_distance = ((%d MHz)) Mhz, tone_idx_tmp = ((%d.%d))\n", int_distance, (tone_idx_tmp / 10), (tone_idx_tmp % 10)));
3273                 *p_tone_idx_tmp_in = tone_idx_tmp;
3274                 set_result = SET_SUCCESS;
3275         }
3276
3277         return  set_result;
3278
3279 }
3280
3281
3282 u8
3283 phydm_csi_mask_setting(
3284         void            *p_dm_void,
3285         u32             enable,
3286         u32             channel,
3287         u32             bw,
3288         u32             f_interference,
3289         u32             second_ch
3290 )
3291 {
3292         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
3293         u32             fc;
3294         u32             int_distance;
3295         u8              tone_direction;
3296         u32             tone_idx_tmp;
3297         u8              set_result = SET_SUCCESS;
3298
3299         if (enable == CSI_MASK_DISABLE) {
3300                 set_result = SET_SUCCESS;
3301                 phydm_clean_all_csi_mask(p_dm_odm);
3302
3303         } else {
3304
3305                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("[Set CSI MASK_] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
3306                         channel, bw, f_interference, (((bw == 20) || (channel > 14)) ? "Don't care" : (second_ch == PHYDM_ABOVE) ? "H" : "L")));
3307
3308                 /*calculate fc*/
3309                 if (phydm_calculate_fc(p_dm_odm, channel, bw, second_ch, &fc) == SET_ERROR)
3310                         set_result = SET_ERROR;
3311
3312                 else {
3313                         /*calculate interference distance*/
3314                         if (phydm_calculate_intf_distance(p_dm_odm, bw, fc, f_interference, &tone_idx_tmp) == SET_SUCCESS) {
3315
3316                                 tone_direction = (f_interference >= fc) ? FREQ_POSITIVE : FREQ_NEGATIVE;
3317                                 phydm_set_csi_mask_reg(p_dm_odm, tone_idx_tmp, tone_direction);
3318                                 set_result = SET_SUCCESS;
3319                         } else
3320                                 set_result = SET_NO_NEED;
3321                 }
3322         }
3323
3324         if (set_result == SET_SUCCESS)
3325                 phydm_csi_mask_enable(p_dm_odm, enable);
3326         else
3327                 phydm_csi_mask_enable(p_dm_odm, CSI_MASK_DISABLE);
3328
3329         return  set_result;
3330 }
3331
3332 u8
3333 phydm_nbi_setting(
3334         void            *p_dm_void,
3335         u32             enable,
3336         u32             channel,
3337         u32             bw,
3338         u32             f_interference,
3339         u32             second_ch
3340 )
3341 {
3342         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
3343         u32             fc;
3344         u32             int_distance;
3345         u32             tone_idx_tmp;
3346         u8              set_result = SET_SUCCESS;
3347         u32             bw_max = 40;
3348
3349         if (enable == NBI_DISABLE)
3350                 set_result = SET_SUCCESS;
3351
3352         else {
3353
3354                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
3355                         channel, bw, f_interference, (((second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "Don't care" : (second_ch == PHYDM_ABOVE) ? "H" : "L")));
3356
3357                 /*calculate fc*/
3358                 if (phydm_calculate_fc(p_dm_odm, channel, bw, second_ch, &fc) == SET_ERROR)
3359                         set_result = SET_ERROR;
3360
3361                 else {
3362                         /*calculate interference distance*/
3363                         if (phydm_calculate_intf_distance(p_dm_odm, bw, fc, f_interference, &tone_idx_tmp) == SET_SUCCESS) {
3364
3365                                 phydm_set_nbi_reg(p_dm_odm, tone_idx_tmp, bw);
3366                                 set_result = SET_SUCCESS;
3367                         } else
3368                                 set_result = SET_NO_NEED;
3369                 }
3370         }
3371
3372         if (set_result == SET_SUCCESS)
3373                 phydm_nbi_enable(p_dm_odm, enable);
3374         else
3375                 phydm_nbi_enable(p_dm_odm, NBI_DISABLE);
3376
3377         return  set_result;
3378 }
3379
3380 void
3381 phydm_api_debug(
3382         void            *p_dm_void,
3383         u32             function_map,
3384         u32             *const dm_value,
3385         u32             *_used,
3386         char                    *output,
3387         u32             *_out_len
3388 )
3389 {
3390         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
3391         u32                     used = *_used;
3392         u32                     out_len = *_out_len;
3393         u32                     channel =  dm_value[1];
3394         u32                     bw =  dm_value[2];
3395         u32                     f_interference =  dm_value[3];
3396         u32                     second_ch =  dm_value[4];
3397         u8                      set_result = 0;
3398
3399         /*PHYDM_API_NBI*/
3400         /*-------------------------------------------------------------------------------------------------------------------------------*/
3401         if (function_map == PHYDM_API_NBI) {
3402
3403                 if (dm_value[0] == 100) {
3404
3405                         PHYDM_SNPRINTF((output + used, out_len - used, "[HELP-NBI]  EN(on=1, off=2)   CH   BW(20/40/80)  f_intf(Mhz)    Scnd_CH(L=1, H=2)\n"));
3406                         return;
3407
3408                 } else if (dm_value[0] == NBI_ENABLE) {
3409
3410                         PHYDM_SNPRINTF((output + used, out_len - used, "[Enable NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
3411                                 channel, bw, f_interference, ((second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "Don't care" : ((second_ch == PHYDM_ABOVE) ? "H" : "L")));
3412                         set_result = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, channel, bw, f_interference, second_ch);
3413
3414                 } else if (dm_value[0] == NBI_DISABLE) {
3415
3416                         PHYDM_SNPRINTF((output + used, out_len - used, "[Disable NBI]\n"));
3417                         set_result = phydm_nbi_setting(p_dm_odm, NBI_DISABLE, channel, bw, f_interference, second_ch);
3418
3419                 } else
3420
3421                         set_result = SET_ERROR;
3422                 PHYDM_SNPRINTF((output + used, out_len - used, "[NBI set result: %s]\n", (set_result == SET_SUCCESS) ? "Success" : ((set_result == SET_NO_NEED) ? "No need" : "Error")));
3423
3424         }
3425
3426         /*PHYDM_CSI_MASK*/
3427         /*-------------------------------------------------------------------------------------------------------------------------------*/
3428         else if (function_map == PHYDM_API_CSI_MASK) {
3429
3430                 if (dm_value[0] == 100) {
3431
3432                         PHYDM_SNPRINTF((output + used, out_len - used, "[HELP-CSI MASK]  EN(on=1, off=2)   CH   BW(20/40/80)  f_intf(Mhz)    Scnd_CH(L=1, H=2)\n"));
3433                         return;
3434
3435                 } else if (dm_value[0] == CSI_MASK_ENABLE) {
3436
3437                         PHYDM_SNPRINTF((output + used, out_len - used, "[Enable CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
3438                                 channel, bw, f_interference, (channel > 14) ? "Don't care" : (((second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "H" : "L")));
3439                         set_result = phydm_csi_mask_setting(p_dm_odm,   CSI_MASK_ENABLE, channel, bw, f_interference, second_ch);
3440
3441                 } else if (dm_value[0] == CSI_MASK_DISABLE) {
3442
3443                         PHYDM_SNPRINTF((output + used, out_len - used, "[Disable CSI MASK]\n"));
3444                         set_result = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_DISABLE, channel, bw, f_interference, second_ch);
3445
3446                 } else
3447
3448                         set_result = SET_ERROR;
3449                 PHYDM_SNPRINTF((output + used, out_len - used, "[CSI MASK set result: %s]\n", (set_result == SET_SUCCESS) ? "Success" : ((set_result == SET_NO_NEED) ? "No need" : "Error")));
3450         }
3451 }