drivers/net/wireless/rockchip_wlan/rtl8723cs/hal/HalPwrSeqCmd.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 /*++
  21 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
  22
  23 Module Name:
  24         HalPwrSeqCmd.c
  25
  26 Abstract:
  27         Implement HW Power sequence configuration CMD handling routine for Realtek devices.
  28
  29 Major Change History:
  30         When       Who               What
  31         ---------- ---------------   -------------------------------
  32         2011-10-26 Lucas            Modify to be compatible with SD4-CE driver.
  33         2011-07-07 Roger            Create.
  34
  35 --*/
  36 #include <HalPwrSeqCmd.h>
  37
  38
  39 /*
  40  *      Description:
  41  *              This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.
  42  *
  43  *      Assumption:
  44  *              We should follow specific format which was released from HW SD.
  45  *
  46  *      2011.07.07, added by Roger.
  47  *   */
  48 u8 HalPwrSeqCmdParsing(
  49         PADAPTER                padapter,
  50         u8                              CutVersion,
  51         u8                              FabVersion,
  52         u8                              InterfaceType,
  53         WLAN_PWR_CFG    PwrSeqCmd[])
  54 {
  55         WLAN_PWR_CFG    PwrCfgCmd = {0};
  56         u8                              bPollingBit = _FALSE;
  57         u32                             AryIdx = 0;
  58         u8                              value = 0;
  59         u32                             offset = 0;
  60         u32                             pollingCount = 0; /* polling autoload done. */
  61         u32                             maxPollingCnt = 5000;
  62
  63         do {
  64                 PwrCfgCmd = PwrSeqCmd[AryIdx];
  65
  66
  67                 /* 2 Only Handle the command whose FAB, CUT, and Interface are matched */
  68                 if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
  69                     (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
  70                     (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)) {
  71                         switch (GET_PWR_CFG_CMD(PwrCfgCmd)) {
  72                         case PWR_CMD_READ:
  73                                 break;
  74
  75                         case PWR_CMD_WRITE:
  76                                 offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
  77
  78 #ifdef CONFIG_SDIO_HCI
  79                                 /*  */
  80                                 /* <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface */
  81                                 /* 2011.07.07. */
  82                                 /*  */
  83                                 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) {
  84                                         /* Read Back SDIO Local value */
  85                                         value = SdioLocalCmd52Read1Byte(padapter, offset);
  86
  87                                         value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
  88                                         value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
  89
  90                                         /* Write Back SDIO Local value */
  91                                         SdioLocalCmd52Write1Byte(padapter, offset, value);
  92                                 } else
  93 #endif
  94                                 {
  95 #ifdef CONFIG_GSPI_HCI
  96                                         if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
  97                                                 offset = SPI_LOCAL_OFFSET | offset;
  98 #endif
  99                                         /* Read the value from system register */
 100                                         value = rtw_read8(padapter, offset);
 101
 102                                         value = value & (~(GET_PWR_CFG_MASK(PwrCfgCmd)));
 103                                         value = value | (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
 104
 105                                         /* Write the value back to sytem register */
 106                                         rtw_write8(padapter, offset, value);
 107                                 }
 108                                 break;
 109
 110                         case PWR_CMD_POLLING:
 111
 112                                 bPollingBit = _FALSE;
 113                                 offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
 114 #ifdef CONFIG_GSPI_HCI
 115                                 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
 116                                         offset = SPI_LOCAL_OFFSET | offset;
 117 #endif
 118                                 do {
 119 #ifdef CONFIG_SDIO_HCI
 120                                         if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
 121                                                 value = SdioLocalCmd52Read1Byte(padapter, offset);
 122                                         else
 123 #endif
 124                                                 value = rtw_read8(padapter, offset);
 125
 126                                         value = value & GET_PWR_CFG_MASK(PwrCfgCmd);
 127                                         if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))
 128                                                 bPollingBit = _TRUE;
 129                                         else
 130                                                 rtw_udelay_os(10);
 131
 132                                         if (pollingCount++ > maxPollingCnt) {
 133                                                 RTW_ERR("HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\n", offset, value);
 134                                                 return _FALSE;
 135                                         }
 136                                 } while (!bPollingBit);
 137
 138                                 break;
 139
 140                         case PWR_CMD_DELAY:
 141                                 if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
 142                                         rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd));
 143                                 else
 144                                         rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd) * 1000);
 145                                 break;
 146
 147                         case PWR_CMD_END:
 148                                 /* When this command is parsed, end the process */
 149                                 return _TRUE;
 150                                 break;
 151
 152                         default:
 153                                 break;
 154                         }
 155                 }
 156
 157                 AryIdx++;/* Add Array Index */
 158         } while (1);
 159
 160         return _TRUE;
 161 }