drivers/net/wireless/rockchip_wlan/rtl8723bu/hal/rtl8723b/rtl8723b_phycfg.c

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *\r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 #define _RTL8723B_PHYCFG_C_\r
  21 \r
  22 #include <rtl8723b_hal.h>\r
  23 \r
  24 \r
  25 /*---------------------------Define Local Constant---------------------------*/\r
  26 /* Channel switch:The size of command tables for switch channel*/\r
  27 #define MAX_PRECMD_CNT 16\r
  28 #define MAX_RFDEPENDCMD_CNT 16\r
  29 #define MAX_POSTCMD_CNT 16\r
  30 \r
  31 #define MAX_DOZE_WAITING_TIMES_9x 64\r
  32 \r
  33 /*---------------------------Define Local Constant---------------------------*/\r
  34 \r
  35 \r
  36 /*------------------------Define global variable-----------------------------*/\r
  37 \r
  38 /*------------------------Define local variable------------------------------*/\r
  39 \r
  40 \r
  41 /*--------------------Define export function prototype-----------------------*/\r
  42 // Please refer to header file\r
  43 /*--------------------Define export function prototype-----------------------*/\r
  44 \r
  45 /*----------------------------Function Body----------------------------------*/\r
  46 //\r
  47 // 1. BB register R/W API\r
  48 //\r
  49 \r
  50 /**\r
  51 * Function:     phy_CalculateBitShift\r
  52 *\r
  53 * OverView:     Get shifted position of the BitMask\r
  54 *\r
  55 * Input:\r
  56 *                       u4Byte          BitMask,\r
  57 *\r
  58 * Output:       none\r
  59 * Return:               u4Byte          Return the shift bit bit position of the mask\r
  60 */\r
  61 static  u32\r
  62 phy_CalculateBitShift(\r
  63         u32 BitMask\r
  64         )\r
  65 {\r
  66         u32 i;\r
  67 \r
  68         for(i=0; i<=31; i++)\r
  69         {\r
  70                 if ( ((BitMask>>i) &  0x1 ) == 1)\r
  71                         break;\r
  72         }\r
  73 \r
  74         return (i);\r
  75 }\r
  76 \r
  77 \r
  78 /**\r
  79 * Function:     PHY_QueryBBReg\r
  80 *\r
  81 * OverView:     Read "sepcific bits" from BB register\r
  82 *\r
  83 * Input:\r
  84 *                       PADAPTER                Adapter,\r
  85 *                       u4Byte                  RegAddr,                //The target address to be readback\r
  86 *                       u4Byte                  BitMask         //The target bit position in the target address\r
  87 *                                                                               //to be readback\r
  88 * Output:       None\r
  89 * Return:               u4Byte                  Data                    //The readback register value\r
  90 * Note:         This function is equal to "GetRegSetting" in PHY programming guide\r
  91 */\r
  92 u32\r
  93 PHY_QueryBBReg_8723B(\r
  94         IN      PADAPTER        Adapter,\r
  95         IN      u32             RegAddr,\r
  96         IN      u32             BitMask\r
  97         )\r
  98 {\r
  99         u32     ReturnValue = 0, OriginalValue, BitShift;\r
 100         u16     BBWaitCounter = 0;\r
 101 \r
 102 #if (DISABLE_BB_RF == 1)\r
 103         return 0;\r
 104 #endif\r
 105 \r
 106         //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx)\n", RegAddr, BitMask));\r
 107 \r
 108         OriginalValue = rtw_read32(Adapter, RegAddr);\r
 109         BitShift = phy_CalculateBitShift(BitMask);\r
 110         ReturnValue = (OriginalValue & BitMask) >> BitShift;\r
 111 \r
 112         return (ReturnValue);\r
 113 \r
 114 }\r
 115 \r
 116 \r
 117 /**\r
 118 * Function:     PHY_SetBBReg\r
 119 *\r
 120 * OverView:     Write "Specific bits" to BB register (page 8~)\r
 121 *\r
 122 * Input:\r
 123 *                       PADAPTER                Adapter,\r
 124 *                       u4Byte                  RegAddr,                //The target address to be modified\r
 125 *                       u4Byte                  BitMask         //The target bit position in the target address\r
 126 *                                                                               //to be modified\r
 127 *                       u4Byte                  Data                    //The new register value in the target bit position\r
 128 *                                                                               //of the target address\r
 129 *\r
 130 * Output:       None\r
 131 * Return:               None\r
 132 * Note:         This function is equal to "PutRegSetting" in PHY programming guide\r
 133 */\r
 134 \r
 135 VOID\r
 136 PHY_SetBBReg_8723B(\r
 137         IN      PADAPTER        Adapter,\r
 138         IN      u32             RegAddr,\r
 139         IN      u32             BitMask,\r
 140         IN      u32             Data\r
 141         )\r
 142 {\r
 143         HAL_DATA_TYPE   *pHalData               = GET_HAL_DATA(Adapter);\r
 144         //u16                   BBWaitCounter   = 0;\r
 145         u32                     OriginalValue, BitShift;\r
 146 \r
 147 #if (DISABLE_BB_RF == 1)\r
 148         return;\r
 149 #endif\r
 150 \r
 151         //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data));\r
 152 \r
 153         if(BitMask!= bMaskDWord){//if not "double word" write\r
 154                 OriginalValue = rtw_read32(Adapter, RegAddr);\r
 155                 BitShift = phy_CalculateBitShift(BitMask);\r
 156                 Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask));\r
 157         }\r
 158 \r
 159         rtw_write32(Adapter, RegAddr, Data);\r
 160 \r
 161 }\r
 162 \r
 163 \r
 164 //\r
 165 // 2. RF register R/W API\r
 166 //\r
 167 \r
 168 /*-----------------------------------------------------------------------------\r
 169  * Function:    phy_FwRFSerialRead()\r
 170  *\r
 171  * Overview:    We support firmware to execute RF-R/W.\r
 172  *\r
 173  * Input:               NONE\r
 174  *\r
 175  * Output:              NONE\r
 176  *\r
 177  * Return:              NONE\r
 178  *\r
 179  * Revised History:\r
 180  *      When            Who             Remark\r
 181  *      01/21/2008      MHC             Create Version 0.\r
 182  *\r
 183  *---------------------------------------------------------------------------*/\r
 184 static  u32\r
 185 phy_FwRFSerialRead(\r
 186         IN      PADAPTER                        Adapter,\r
 187         IN      RF_PATH                 eRFPath,\r
 188         IN      u32                             Offset  )\r
 189 {\r
 190         u32             retValue = 0;\r
 191         //RT_ASSERT(FALSE,("deprecate!\n"));\r
 192         return  (retValue);\r
 193 \r
 194 }       /* phy_FwRFSerialRead */\r
 195 \r
 196 \r
 197 /*-----------------------------------------------------------------------------\r
 198  * Function:    phy_FwRFSerialWrite()\r
 199  *\r
 200  * Overview:    We support firmware to execute RF-R/W.\r
 201  *\r
 202  * Input:               NONE\r
 203  *\r
 204  * Output:              NONE\r
 205  *\r
 206  * Return:              NONE\r
 207  *\r
 208  * Revised History:\r
 209  *      When            Who             Remark\r
 210  *      01/21/2008      MHC             Create Version 0.\r
 211  *\r
 212  *---------------------------------------------------------------------------*/\r
 213 static  VOID\r
 214 phy_FwRFSerialWrite(\r
 215         IN      PADAPTER                        Adapter,\r
 216         IN      RF_PATH                 eRFPath,\r
 217         IN      u32                             Offset,\r
 218         IN      u32                             Data    )\r
 219 {\r
 220         //RT_ASSERT(FALSE,("deprecate!\n"));\r
 221 }\r
 222 \r
 223 static  u32\r
 224 phy_RFSerialRead_8723B(\r
 225         IN      PADAPTER                        Adapter,\r
 226         IN      RF_PATH                 eRFPath,\r
 227         IN      u32                             Offset\r
 228         )\r
 229 {\r
 230         u32                                             retValue = 0;\r
 231         HAL_DATA_TYPE                           *pHalData = GET_HAL_DATA(Adapter);\r
 232         BB_REGISTER_DEFINITION_T        *pPhyReg = &pHalData->PHYRegDef[eRFPath];\r
 233         u32                                             NewOffset;\r
 234         u32                                             tmplong,tmplong2;\r
 235         u8                                      RfPiEnable=0;\r
 236         u4Byte                                          MaskforPhySet=0;\r
 237         int i = 0;\r
 238 \r
 239         //\r
 240         // Make sure RF register offset is correct\r
 241         //\r
 242         Offset &= 0xff;\r
 243 \r
 244         NewOffset = Offset;\r
 245 \r
 246         if(eRFPath == RF_PATH_A)\r
 247         {\r
 248                 tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord);;\r
 249                 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge;  //T65 RF\r
 250                 PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge));   \r
 251         }\r
 252         else\r
 253         {\r
 254                 tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord);\r
 255                 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge;  //T65 RF\r
 256                 PHY_SetBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge));   \r
 257         }\r
 258 \r
 259         tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord);\r
 260         PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));                 \r
 261         PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge);            \r
 262         \r
 263         rtw_udelay_os(10);\r
 264 \r
 265         for(i=0;i<2;i++)\r
 266                 rtw_udelay_os(MAX_STALL_TIME);  \r
 267         rtw_udelay_os(10);\r
 268 \r
 269         if(eRFPath == RF_PATH_A)\r
 270                 RfPiEnable = (u1Byte)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1|MaskforPhySet, BIT8);\r
 271         else if(eRFPath == RF_PATH_B)\r
 272                 RfPiEnable = (u1Byte)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1|MaskforPhySet, BIT8);\r
 273         \r
 274         if(RfPiEnable)\r
 275         {       // Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF\r
 276                 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi|MaskforPhySet, bLSSIReadBackData);\r
 277         \r
 278                 //RT_DISP(FINIT, INIT_RF, ("Readback from RF-PI : 0x%x\n", retValue));\r
 279         }\r
 280         else\r
 281         {       //Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF\r
 282                 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack|MaskforPhySet, bLSSIReadBackData);\r
 283                 \r
 284                 //RT_DISP(FINIT, INIT_RF,("Readback from RF-SI : 0x%x\n", retValue));\r
 285         }\r
 286         return retValue;\r
 287 \r
 288 }\r
 289 \r
 290 /**\r
 291 * Function:     phy_RFSerialWrite_8723B\r
 292 *\r
 293 * OverView:     Write data to RF register (page 8~)\r
 294 *\r
 295 * Input:\r
 296 *                       PADAPTER                Adapter,\r
 297 *                       RF_PATH                 eRFPath,        //Radio path of A/B/C/D\r
 298 *                       u4Byte                  Offset,         //The target address to be read\r
 299 *                       u4Byte                  Data                    //The new register Data in the target bit position\r
 300 *                                                                               //of the target to be read\r
 301 *\r
 302 * Output:       None\r
 303 * Return:               None\r
 304 * Note:         Threre are three types of serial operations:\r
 305 *                       1. Software serial write\r
 306 *                       2. Hardware LSSI-Low Speed Serial Interface\r
 307 *                       3. Hardware HSSI-High speed\r
 308 *                       serial write. Driver need to implement (1) and (2).\r
 309 *                       This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()\r
 310  *\r
 311  * Note:                  For RF8256 only\r
 312  *                       The total count of RTL8256(Zebra4) register is around 36 bit it only employs\r
 313  *                       4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])\r
 314  *                       to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration\r
 315  *                       programming guide" for more details.\r
 316  *                       Thus, we define a sub-finction for RTL8526 register address conversion\r
 317  *                     ===========================================================\r
 318  *                       Register Mode          RegCTL[1]               RegCTL[0]               Note\r
 319  *                                                              (Reg00[12])             (Reg00[10])\r
 320  *                     ===========================================================\r
 321  *                       Reg_Mode0                              0                               x                       Reg 0 ~15(0x0 ~ 0xf)\r
 322  *                     ------------------------------------------------------------------\r
 323  *                       Reg_Mode1                              1                               0                       Reg 16 ~30(0x1 ~ 0xf)\r
 324  *                     ------------------------------------------------------------------\r
 325  *                       Reg_Mode2                              1                               1                       Reg 31 ~ 45(0x1 ~ 0xf)\r
 326  *                     ------------------------------------------------------------------\r
 327  *\r
 328  *      2008/09/02      MH      Add 92S RF definition\r
 329  *\r
 330  *\r
 331  *\r
 332 */\r
 333 static  VOID\r
 334 phy_RFSerialWrite_8723B(\r
 335         IN      PADAPTER                        Adapter,\r
 336         IN      RF_PATH                 eRFPath,\r
 337         IN      u32                             Offset,\r
 338         IN      u32                             Data\r
 339         )\r
 340 {\r
 341         u32                                             DataAndAddr = 0;\r
 342         HAL_DATA_TYPE                           *pHalData = GET_HAL_DATA(Adapter);\r
 343         BB_REGISTER_DEFINITION_T        *pPhyReg = &pHalData->PHYRegDef[eRFPath];\r
 344         u32                                             NewOffset;\r
 345 \r
 346         Offset &= 0xff;\r
 347 \r
 348         //\r
 349         // Shadow Update\r
 350         //\r
 351         //PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data);\r
 352 \r
 353         //\r
 354         // Switch page for 8256 RF IC\r
 355         //\r
 356         NewOffset = Offset;\r
 357 \r
 358         //\r
 359         // Put write addr in [5:0]  and write data in [31:16]\r
 360         //\r
 361         //DataAndAddr = (Data<<16) | (NewOffset&0x3f);\r
 362         DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff;       // T65 RF\r
 363 \r
 364         //\r
 365         // Write Operation\r
 366         //\r
 367         PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);\r
 368         //RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]=0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr));\r
 369 \r
 370 }\r
 371 \r
 372 \r
 373 /**\r
 374 * Function:     PHY_QueryRFReg\r
 375 *\r
 376 * OverView:     Query "Specific bits" to RF register (page 8~)\r
 377 *\r
 378 * Input:\r
 379 *                       PADAPTER                Adapter,\r
 380 *                       RF_PATH                 eRFPath,        //Radio path of A/B/C/D\r
 381 *                       u4Byte                  RegAddr,                //The target address to be read\r
 382 *                       u4Byte                  BitMask         //The target bit position in the target address\r
 383 *                                                                               //to be read\r
 384 *\r
 385 * Output:       None\r
 386 * Return:               u4Byte                  Readback value\r
 387 * Note:         This function is equal to "GetRFRegSetting" in PHY programming guide\r
 388 */\r
 389 u32\r
 390 PHY_QueryRFReg_8723B(\r
 391         IN      PADAPTER                        Adapter,\r
 392         IN      u8                      eRFPath,\r
 393         IN      u32                             RegAddr,\r
 394         IN      u32                             BitMask\r
 395         )\r
 396 {\r
 397         u32 Original_Value, Readback_Value, BitShift;\r
 398 \r
 399 #if (DISABLE_BB_RF == 1)\r
 400         return 0;\r
 401 #endif\r
 402 \r
 403         Original_Value = phy_RFSerialRead_8723B(Adapter, eRFPath, RegAddr);\r
 404 \r
 405         BitShift =  phy_CalculateBitShift(BitMask);\r
 406         Readback_Value = (Original_Value & BitMask) >> BitShift;\r
 407 \r
 408         return (Readback_Value);\r
 409 }\r
 410 \r
 411 /**\r
 412 * Function:     PHY_SetRFReg\r
 413 *\r
 414 * OverView:     Write "Specific bits" to RF register (page 8~)\r
 415 *\r
 416 * Input:\r
 417 *                       PADAPTER                Adapter,\r
 418 *                       RF_PATH                 eRFPath,        //Radio path of A/B/C/D\r
 419 *                       u4Byte                  RegAddr,                //The target address to be modified\r
 420 *                       u4Byte                  BitMask         //The target bit position in the target address\r
 421 *                                                                               //to be modified\r
 422 *                       u4Byte                  Data                    //The new register Data in the target bit position\r
 423 *                                                                               //of the target address\r
 424 *\r
 425 * Output:       None\r
 426 * Return:               None\r
 427 * Note:         This function is equal to "PutRFRegSetting" in PHY programming guide\r
 428 */\r
 429 VOID\r
 430 PHY_SetRFReg_8723B(\r
 431         IN      PADAPTER                        Adapter,\r
 432         IN      u8                              eRFPath,\r
 433         IN      u32                             RegAddr,\r
 434         IN      u32                             BitMask,\r
 435         IN      u32                             Data\r
 436         )\r
 437 {\r
 438         u32             Original_Value, BitShift;\r
 439 \r
 440 #if (DISABLE_BB_RF == 1)\r
 441         return;\r
 442 #endif\r
 443 \r
 444         // RF data is 12 bits only\r
 445         if (BitMask != bRFRegOffsetMask)\r
 446         {\r
 447                 Original_Value = phy_RFSerialRead_8723B(Adapter, eRFPath, RegAddr);\r
 448                 BitShift =  phy_CalculateBitShift(BitMask);\r
 449                 Data = ((Original_Value & (~BitMask)) | (Data<< BitShift));\r
 450         }\r
 451 \r
 452         phy_RFSerialWrite_8723B(Adapter, eRFPath, RegAddr, Data);\r
 453 }\r
 454 \r
 455 \r
 456 //\r
 457 // 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt.\r
 458 //\r
 459 \r
 460 \r
 461 /*-----------------------------------------------------------------------------\r
 462  * Function:    PHY_MACConfig8192C\r
 463  *\r
 464  * Overview:    Condig MAC by header file or parameter file.\r
 465  *\r
 466  * Input:       NONE\r
 467  *\r
 468  * Output:      NONE\r
 469  *\r
 470  * Return:      NONE\r
 471  *\r
 472  * Revised History:\r
 473  *  When                Who             Remark\r
 474  *  08/12/2008  MHC             Create Version 0.\r
 475  *\r
 476  *---------------------------------------------------------------------------*/\r
 477 s32 PHY_MACConfig8723B(PADAPTER Adapter)\r
 478 {\r
 479         int             rtStatus = _SUCCESS;\r
 480         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
 481         s8                      *pszMACRegFile;\r
 482         s8                      sz8723MACRegFile[] = RTL8723B_PHY_MACREG;\r
 483 \r
 484 \r
 485         pszMACRegFile = sz8723MACRegFile;\r
 486 \r
 487         //\r
 488         // Config MAC\r
 489         //\r
 490 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\r
 491         rtStatus = phy_ConfigMACWithParaFile(Adapter, pszMACRegFile);\r
 492         if (rtStatus == _FAIL)\r
 493 #endif\r
 494         {\r
 495 #ifdef CONFIG_EMBEDDED_FWIMG\r
 496                 ODM_ConfigMACWithHeaderFile(&pHalData->odmpriv);\r
 497                 rtStatus = _SUCCESS;\r
 498 #endif//CONFIG_EMBEDDED_FWIMG\r
 499         }\r
 500 \r
 501         return rtStatus;\r
 502 }\r
 503 \r
 504 /**\r
 505 * Function:     phy_InitBBRFRegisterDefinition\r
 506 *\r
 507 * OverView:     Initialize Register definition offset for Radio Path A/B/C/D\r
 508 *\r
 509 * Input:\r
 510 *                       PADAPTER                Adapter,\r
 511 *\r
 512 * Output:       None\r
 513 * Return:               None\r
 514 * Note:         The initialization value is constant and it should never be changes\r
 515 */\r
 516 static  VOID\r
 517 phy_InitBBRFRegisterDefinition(\r
 518         IN      PADAPTER                Adapter\r
 519 )\r
 520 {\r
 521         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);      \r
 522 \r
 523         // RF Interface Sowrtware Control\r
 524         pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870\r
 525         pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)\r
 526 \r
 527         // RF Interface Output (and Enable)\r
 528         pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860\r
 529         pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864\r
 530 \r
 531         // RF Interface (Output and)  Enable\r
 532         pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)\r
 533         pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)\r
 534 \r
 535         pHalData->PHYRegDef[ODM_RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter\r
 536         pHalData->PHYRegDef[ODM_RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;\r
 537 \r
 538         pHalData->PHYRegDef[ODM_RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;  //wire control parameter2\r
 539         pHalData->PHYRegDef[ODM_RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;  //wire control parameter2\r
 540 \r
 541         // Tranceiver Readback LSSI/HSPI mode \r
 542         pHalData->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;\r
 543         pHalData->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;\r
 544         pHalData->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;\r
 545         pHalData->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;\r
 546 \r
 547 }\r
 548 \r
 549 #if (MP_DRIVER == 1)\r
 550 \r
 551 /*-----------------------------------------------------------------------------\r
 552  * Function:    phy_ConfigBBWithMpHeaderFile\r
 553  *\r
 554  * Overview:    Config PHY_REG_MP array\r
 555  *\r
 556  * Input:       NONE\r
 557  *\r
 558  * Output:      NONE\r
 559  *\r
 560  * Return:      NONE\r
 561  *\r
 562  * Revised History:\r
 563  * When                 Who             Remark\r
 564  * 02/04/2010   chiyokolin              Modify to new files.\r
 565  *---------------------------------------------------------------------------*/\r
 566 static int\r
 567 phy_ConfigBBWithMpHeaderFile(\r
 568         IN      PADAPTER                Adapter,\r
 569         IN      u1Byte                  ConfigType)\r
 570 {\r
 571         int i;\r
 572         u32*    Rtl8723BPHY_REGArray_Table_MP;\r
 573         u16     PHY_REGArrayMPLen;\r
 574         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
 575 \r
 576 \r
 577         PHY_REGArrayMPLen = Rtl8723B_PHY_REG_Array_MPLength;\r
 578         Rtl8723BPHY_REGArray_Table_MP = (u32*)Rtl8723B_PHY_REG_Array_MP;\r
 579 \r
 580         if(ConfigType == BaseBand_Config_PHY_REG)\r
 581         {\r
 582                 for(i=0;i<PHY_REGArrayMPLen;i=i+2)\r
 583                 {\r
 584                         if (Rtl8723BPHY_REGArray_Table_MP[i] == 0xfe) {\r
 585                                 #ifdef CONFIG_LONG_DELAY_ISSUE\r
 586                                 rtw_msleep_os(50);\r
 587                                 #else\r
 588                                 rtw_mdelay_os(50);\r
 589                                 #endif\r
 590                         }\r
 591                         else if (Rtl8723BPHY_REGArray_Table_MP[i] == 0xfd)\r
 592                                 rtw_mdelay_os(5);\r
 593                         else if (Rtl8723BPHY_REGArray_Table_MP[i] == 0xfc)\r
 594                                 rtw_mdelay_os(1);\r
 595                         else if (Rtl8723BPHY_REGArray_Table_MP[i] == 0xfb) {\r
 596                                 #ifdef CONFIG_LONG_DELAY_ISSUE\r
 597                                 rtw_msleep_os(50);\r
 598                                 #else\r
 599                                 rtw_mdelay_os(50);\r
 600                                 #endif\r
 601                         }\r
 602                         else if (Rtl8723BPHY_REGArray_Table_MP[i] == 0xfa)\r
 603                                 rtw_mdelay_os(5);\r
 604                         else if (Rtl8723BPHY_REGArray_Table_MP[i] == 0xf9)\r
 605                                 rtw_mdelay_os(1);\r
 606                         PHY_SetBBReg(Adapter, Rtl8723BPHY_REGArray_Table_MP[i], bMaskDWord, Rtl8723BPHY_REGArray_Table_MP[i+1]);\r
 607 \r
 608                         // Add 1us delay between BB/RF register setting.\r
 609                         rtw_mdelay_os(1);\r
 610 \r
 611 //                      RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl8192CPHY_REGArray_Table_MP[%d] is %lx Rtl8192CPHY_REGArray_Table_MP[%d] is %lx \n", i, i+1, Rtl8192CPHY_REGArray_Table_MP[i], Rtl8192CPHY_REGArray_Table_MP[i+1]));\r
 612                 }\r
 613         }\r
 614         else\r
 615         {\r
 616 //              RT_TRACE(COMP_SEND, DBG_LOUD, ("phy_ConfigBBWithMpHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n"));\r
 617         }\r
 618 \r
 619         return _SUCCESS;\r
 620 }       /* phy_ConfigBBWithMpHeaderFile */\r
 621 \r
 622 #endif  // #if (MP_DRIVER == 1)\r
 623 \r
 624 \r
 625 static  int\r
 626 phy_BB8723b_Config_ParaFile(\r
 627         IN      PADAPTER        Adapter\r
 628         )\r
 629 {\r
 630         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);\r
 631         int                     rtStatus = _SUCCESS;\r
 632         u8      sz8723BBRegFile[] = RTL8723B_PHY_REG;\r
 633         u8      sz8723AGCTableFile[] = RTL8723B_AGC_TAB;\r
 634         u8      sz8723BBBRegPgFile[] = RTL8723B_PHY_REG_PG;\r
 635         u8      sz8723BBRegMpFile[] = RTL8723B_PHY_REG_MP;\r
 636         u8      sz8723BRFTxPwrLmtFile[] = RTL8723B_TXPWR_LMT;\r
 637         u8      *pszBBRegFile = NULL, *pszAGCTableFile = NULL, *pszBBRegPgFile = NULL, *pszBBRegMpFile=NULL, *pszRFTxPwrLmtFile = NULL;\r
 638 \r
 639         pszBBRegFile = sz8723BBRegFile ;\r
 640         pszAGCTableFile = sz8723AGCTableFile;\r
 641         pszBBRegPgFile = sz8723BBBRegPgFile;\r
 642         pszBBRegMpFile = sz8723BBRegMpFile;\r
 643         pszRFTxPwrLmtFile = sz8723BRFTxPwrLmtFile;\r
 644 \r
 645         // Read Tx Power Limit File\r
 646         PHY_InitTxPowerLimit( Adapter );\r
 647         if ( Adapter->registrypriv.RegEnableTxPowerLimit == 1 || \r
 648              ( Adapter->registrypriv.RegEnableTxPowerLimit == 2 && pHalData->EEPROMRegulatory == 1 ) )\r
 649         {\r
 650 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\r
 651                 if (PHY_ConfigRFWithPowerLimitTableParaFile( Adapter, pszRFTxPwrLmtFile )== _FAIL)\r
 652 #endif\r
 653                 {\r
 654 #ifdef CONFIG_EMBEDDED_FWIMG\r
 655                         if (HAL_STATUS_SUCCESS != ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, CONFIG_RF_TXPWR_LMT, (ODM_RF_RADIO_PATH_E)0))\r
 656                                 rtStatus = _FAIL;\r
 657 #endif\r
 658                 }\r
 659 \r
 660                 if(rtStatus != _SUCCESS){\r
 661                         DBG_871X("%s():Read Tx power limit fail\n",__func__);\r
 662                         goto phy_BB8190_Config_ParaFile_Fail;\r
 663                 }\r
 664         }\r
 665 \r
 666         //\r
 667         // 1. Read PHY_REG.TXT BB INIT!!\r
 668         //\r
 669 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\r
 670         if (phy_ConfigBBWithParaFile(Adapter, pszBBRegFile, CONFIG_BB_PHY_REG) == _FAIL)\r
 671 #endif\r
 672         {\r
 673 #ifdef CONFIG_EMBEDDED_FWIMG\r
 674                 if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG))\r
 675                         rtStatus = _FAIL;\r
 676 #endif\r
 677         }\r
 678 \r
 679         if(rtStatus != _SUCCESS){\r
 680                 DBG_8192C("%s():Write BB Reg Fail!!", __func__);\r
 681                 goto phy_BB8190_Config_ParaFile_Fail;\r
 682         }\r
 683 \r
 684 #if MP_DRIVER == 1\r
 685         if (Adapter->registrypriv.mp_mode == 1)\r
 686         {\r
 687                 //\r
 688                 // 1.1 Read PHY_REG_MP.TXT BB INIT!!\r
 689                 //\r
 690 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\r
 691                 if (phy_ConfigBBWithMpParaFile(Adapter, pszBBRegMpFile) == _FAIL)\r
 692 #endif\r
 693                 {\r
 694 #ifdef CONFIG_EMBEDDED_FWIMG\r
 695                         if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG_MP))\r
 696                                 rtStatus = _FAIL;\r
 697 #endif\r
 698                 }\r
 699 \r
 700                 if(rtStatus != _SUCCESS){\r
 701                         DBG_8192C("%s():Write BB Reg MP Fail!!", __func__);\r
 702                         goto phy_BB8190_Config_ParaFile_Fail;\r
 703                 }\r
 704         }\r
 705 #endif  // #if (MP_DRIVER == 1)\r
 706 \r
 707         // If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt\r
 708         PHY_InitTxPowerByRate( Adapter );\r
 709         if ( Adapter->registrypriv.RegEnableTxPowerByRate == 1 || \r
 710              ( Adapter->registrypriv.RegEnableTxPowerByRate == 2 && pHalData->EEPROMRegulatory != 2 ) )\r
 711         {\r
 712 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\r
 713                 if (phy_ConfigBBWithPgParaFile(Adapter, pszBBRegPgFile) == _FAIL)\r
 714 #endif\r
 715                 {\r
 716 #ifdef CONFIG_EMBEDDED_FWIMG\r
 717                         if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG_PG))\r
 718                                 rtStatus = _FAIL;\r
 719 #endif\r
 720                 }\r
 721 \r
 722                 if ( pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_EXACT_VALUE )\r
 723                         PHY_TxPowerByRateConfiguration( Adapter );\r
 724 \r
 725                 if ( Adapter->registrypriv.RegEnableTxPowerLimit == 1 || \r
 726                  ( Adapter->registrypriv.RegEnableTxPowerLimit == 2 && pHalData->EEPROMRegulatory == 1 ) )\r
 727                         PHY_ConvertTxPowerLimitToPowerIndex( Adapter );\r
 728 \r
 729                 if(rtStatus != _SUCCESS){\r
 730                         DBG_8192C("%s():BB_PG Reg Fail!!\n",__func__);\r
 731                 }\r
 732         }\r
 733 \r
 734         //\r
 735         // 2. Read BB AGC table Initialization\r
 736         //\r
 737 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\r
 738         if (phy_ConfigBBWithParaFile(Adapter, pszAGCTableFile, CONFIG_BB_AGC_TAB) == _FAIL)\r
 739 #endif\r
 740         {\r
 741 #ifdef CONFIG_EMBEDDED_FWIMG\r
 742                 if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_AGC_TAB))\r
 743                         rtStatus = _FAIL;\r
 744 #endif\r
 745         }\r
 746 \r
 747         if(rtStatus != _SUCCESS){\r
 748                 DBG_8192C("%s():AGC Table Fail\n", __func__);\r
 749                 goto phy_BB8190_Config_ParaFile_Fail;\r
 750         }\r
 751 \r
 752 phy_BB8190_Config_ParaFile_Fail:\r
 753 \r
 754         return rtStatus;\r
 755 }\r
 756 \r
 757 \r
 758 int\r
 759 PHY_BBConfig8723B(\r
 760         IN      PADAPTER        Adapter\r
 761         )\r
 762 {\r
 763         int     rtStatus = _SUCCESS;\r
 764         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
 765         u32     RegVal;\r
 766         u8      TmpU1B=0;\r
 767         u8      value8, CrystalCap;\r
 768 \r
 769         phy_InitBBRFRegisterDefinition(Adapter);\r
 770 \r
 771         // Enable BB and RF\r
 772         RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);\r
 773         rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1));\r
 774 \r
 775         /* switch ant to BT */\r
 776 #ifdef CONFIG_USB_HCI\r
 777         rtw_write32(Adapter, 0x948, 0x0);       // USB use Antenna S0\r
 778 #else\r
 779         if (pHalData->ant_path == ODM_RF_PATH_A)\r
 780                 rtw_write32(Adapter, 0x948, 0x280);\r
 781         else\r
 782                 rtw_write32(Adapter, 0x948, 0x0);\r
 783 #endif\r
 784 \r
 785         rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);\r
 786 \r
 787         rtw_usleep_os(10);\r
 788 \r
 789         PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x1, 0xfffff,0x780); \r
 790 \r
 791 #if 0\r
 792         // 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF.\r
 793         rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x83);\r
 794         rtw_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xdb);\r
 795 #endif\r
 796 \r
 797         rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB);\r
 798 \r
 799         rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, 0x80);\r
 800 \r
 801         //\r
 802         // Config BB and AGC\r
 803         //\r
 804         rtStatus = phy_BB8723b_Config_ParaFile(Adapter);\r
 805 \r
 806         // 0x2C[23:18] = 0x2C[17:12] = CrystalCap\r
 807         CrystalCap = pHalData->CrystalCap & 0x3F;\r
 808         PHY_SetBBReg(Adapter, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap | (CrystalCap << 6)));    \r
 809 \r
 810         return rtStatus;\r
 811 }\r
 812 \r
 813 void phy_LCK_8723B(\r
 814         IN      PADAPTER        Adapter\r
 815         )\r
 816 {\r
 817         PHY_SetRFReg(Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0);\r
 818         PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, 0x8C01);  \r
 819         rtw_mdelay_os(200);\r
 820         PHY_SetRFReg(Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0);      \r
 821 }\r
 822 \r
 823 #if 0\r
 824 // Block & Path enable\r
 825 #define         rOFDMCCKEN_Jaguar               0x808 // OFDM/CCK block enable\r
 826 #define         bOFDMEN_Jaguar                  0x20000000\r
 827 #define         bCCKEN_Jaguar                   0x10000000\r
 828 #define         rRxPath_Jaguar                  0x808   // Rx antenna\r
 829 #define         bRxPath_Jaguar                  0xff\r
 830 #define         rTxPath_Jaguar                  0x80c   // Tx antenna\r
 831 #define         bTxPath_Jaguar                  0x0fffffff\r
 832 #define         rCCK_RX_Jaguar                  0xa04   // for cck rx path selection\r
 833 #define         bCCK_RX_Jaguar                  0x0c000000 \r
 834 #define         rVhtlen_Use_Lsig_Jaguar 0x8c3   // Use LSIG for VHT length\r
 835 VOID\r
 836 PHY_BB8723B_Config_1T(\r
 837         IN PADAPTER Adapter\r
 838         )\r
 839 {\r
 840         // BB OFDM RX Path_A\r
 841         PHY_SetBBReg(Adapter, rRxPath_Jaguar, bRxPath_Jaguar, 0x11);\r
 842         // BB OFDM TX Path_A\r
 843         PHY_SetBBReg(Adapter, rTxPath_Jaguar, bMaskLWord, 0x1111);\r
 844         // BB CCK R/Rx Path_A\r
 845         PHY_SetBBReg(Adapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);\r
 846         // MCS support\r
 847         PHY_SetBBReg(Adapter, 0x8bc, 0xc0000060, 0x4);\r
 848         // RF Path_B HSSI OFF\r
 849         PHY_SetBBReg(Adapter, 0xe00, 0xf, 0x4); \r
 850         // RF Path_B Power Down\r
 851         PHY_SetBBReg(Adapter, 0xe90, bMaskDWord, 0);\r
 852         // ADDA Path_B OFF\r
 853         PHY_SetBBReg(Adapter, 0xe60, bMaskDWord, 0);\r
 854         PHY_SetBBReg(Adapter, 0xe64, bMaskDWord, 0);\r
 855 }\r
 856 #endif\r
 857 \r
 858 int\r
 859 PHY_RFConfig8723B(\r
 860         IN      PADAPTER        Adapter\r
 861         )\r
 862 {\r
 863         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
 864         int             rtStatus = _SUCCESS;\r
 865 \r
 866         //\r
 867         // RF config\r
 868         //\r
 869         rtStatus = PHY_RF6052_Config8723B(Adapter);\r
 870 \r
 871         phy_LCK_8723B(Adapter);\r
 872         //PHY_BB8723B_Config_1T(Adapter);\r
 873 \r
 874         return rtStatus;\r
 875 }\r
 876 \r
 877 /*-----------------------------------------------------------------------------\r
 878  * Function:    PHY_ConfigRFWithParaFile()\r
 879  *\r
 880  * Overview:    This function read RF parameters from general file format, and do RF 3-wire\r
 881  *\r
 882  * Input:       PADAPTER                        Adapter\r
 883  *                      ps1Byte                                 pFileName\r
 884  *                      RF_PATH                         eRFPath\r
 885  *\r
 886  * Output:      NONE\r
 887  *\r
 888  * Return:      RT_STATUS_SUCCESS: configuration file exist\r
 889  *\r
 890  * Note:                Delay may be required for RF configuration\r
 891  *---------------------------------------------------------------------------*/\r
 892 int\r
 893 PHY_ConfigRFWithParaFile_8723B(\r
 894         IN      PADAPTER                        Adapter,\r
 895         IN      u8*                             pFileName,\r
 896         RF_PATH                         eRFPath\r
 897 )\r
 898 {\r
 899         return _SUCCESS;\r
 900 }\r
 901 \r
 902 //****************************************\r
 903 /*-----------------------------------------------------------------------------\r
 904  * Function:    PHY_ConfigRFWithHeaderFile()\r
 905  *\r
 906  * Overview:    This function read RF parameters from general file format, and do RF 3-wire\r
 907  *\r
 908  * Input:       PADAPTER                        Adapter\r
 909  *                      ps1Byte                                 pFileName\r
 910  *                      RF_PATH                         eRFPath\r
 911  *\r
 912  * Output:      NONE\r
 913  *\r
 914  * Return:      RT_STATUS_SUCCESS: configuration file exist\r
 915  *\r
 916  * Note:                Delay may be required for RF configuration\r
 917  *---------------------------------------------------------------------------*/\r
 918 void phy_PowerIndexCheck8723B(\r
 919         IN      PADAPTER                Adapter,\r
 920         IN      u8                      channel,\r
 921         IN OUT u8               *cckPowerLevel,\r
 922         IN OUT u8               *ofdmPowerLevel,\r
 923         IN OUT u8               *BW20PowerLevel,\r
 924         IN OUT u8               *BW40PowerLevel \r
 925         )\r
 926 {\r
 927 \r
 928         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);\r
 929 \r
 930         pHalData->CurrentCckTxPwrIdx = cckPowerLevel[0];\r
 931         pHalData->CurrentOfdm24GTxPwrIdx = ofdmPowerLevel[0];\r
 932         pHalData->CurrentBW2024GTxPwrIdx = BW20PowerLevel[0];\r
 933         pHalData->CurrentBW4024GTxPwrIdx = BW40PowerLevel[0];\r
 934 \r
 935         RT_TRACE(_module_hal_init_c_, _drv_info_, \r
 936                 ("PHY_SetTxPowerLevel8723B(): CurrentCckTxPwrIdx : 0x%x,CurrentOfdm24GTxPwrIdx: 0x%x\n", \r
 937                 pHalData->CurrentCckTxPwrIdx, pHalData->CurrentOfdm24GTxPwrIdx));\r
 938 }\r
 939 \r
 940 /**************************************************************************************************************\r
 941  *   Description: \r
 942  *       The low-level interface to set TxAGC , called by both MP and Normal Driver.\r
 943  *\r
 944  *                                                                                    <20120830, Kordan>\r
 945  **************************************************************************************************************/\r
 946 \r
 947 VOID\r
 948 PHY_SetTxPowerIndex_8723B(\r
 949         IN      PADAPTER                        Adapter,\r
 950         IN      u32                                     PowerIndex,\r
 951         IN      u8                                      RFPath, \r
 952         IN      u8                                      Rate\r
 953         )\r
 954 {\r
 955         if (RFPath == ODM_RF_PATH_A || RFPath == ODM_RF_PATH_B)\r
 956         {\r
 957                 switch (Rate)\r
 958                 {\r
 959                         case MGN_1M:    PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32,      bMaskByte1, PowerIndex); break;\r
 960                         case MGN_2M:    PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte1, PowerIndex); break;\r
 961                         case MGN_5_5M:  PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte2, PowerIndex); break;\r
 962                         case MGN_11M:   PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte3, PowerIndex); break;\r
 963 \r
 964                         case MGN_6M:    PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte0, PowerIndex); break;\r
 965                         case MGN_9M:    PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte1, PowerIndex); break;\r
 966                         case MGN_12M:   PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte2, PowerIndex); break;\r
 967                         case MGN_18M:   PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte3, PowerIndex); break;\r
 968 \r
 969                         case MGN_24M:   PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte0, PowerIndex); break;\r
 970                         case MGN_36M:   PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte1, PowerIndex); break;\r
 971                         case MGN_48M:   PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte2, PowerIndex); break;\r
 972                         case MGN_54M:   PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte3, PowerIndex); break;\r
 973 \r
 974                         case MGN_MCS0:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte0, PowerIndex); break;\r
 975                         case MGN_MCS1:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte1, PowerIndex); break;\r
 976                         case MGN_MCS2:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte2, PowerIndex); break;\r
 977                         case MGN_MCS3:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte3, PowerIndex); break;\r
 978 \r
 979                         case MGN_MCS4:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte0, PowerIndex); break;\r
 980                         case MGN_MCS5:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte1, PowerIndex); break;\r
 981                         case MGN_MCS6:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte2, PowerIndex); break;\r
 982                         case MGN_MCS7:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte3, PowerIndex); break;\r
 983 \r
 984                         default:\r
 985                              DBG_871X("Invalid Rate!!\n");\r
 986                              break;\r
 987                 }\r
 988         }\r
 989         else\r
 990         {\r
 991                 RT_TRACE(_module_hal_init_c_, _drv_err_,("Invalid RFPath!!\n"));\r
 992         }\r
 993 }\r
 994 \r
 995 u8\r
 996 phy_GetCurrentTxNum_8723B(\r
 997         IN      PADAPTER                pAdapter\r
 998         )\r
 999 {\r
1000         return RF_TX_NUM_NONIMPLEMENT;\r
1001 }\r
1002 \r
1003 u8\r
1004 PHY_GetTxPowerIndex_8723B(\r
1005         IN      PADAPTER                        pAdapter,\r
1006         IN      u8                                      RFPath,\r
1007         IN      u8                                      Rate,   \r
1008         IN      CHANNEL_WIDTH           BandWidth,      \r
1009         IN      u8                                      Channel\r
1010         )\r
1011 {\r
1012         PHAL_DATA_TYPE          pHalData = GET_HAL_DATA(pAdapter);\r
1013         s8                                      txPower = 0, powerDiffByRate = 0, limit = 0;\r
1014         BOOLEAN                         bIn24G = _FALSE;\r
1015 \r
1016         //DBG_871X("===>%s\n", __FUNCTION__ );\r
1017         \r
1018         txPower = (s8) PHY_GetTxPowerIndexBase( pAdapter,RFPath, Rate, BandWidth, Channel, &bIn24G );\r
1019         powerDiffByRate = PHY_GetTxPowerByRate( pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, RF_1TX, Rate );\r
1020 \r
1021         limit = PHY_GetTxPowerLimit( pAdapter, pAdapter->registrypriv.RegPwrTblSel, (u8)(!bIn24G), pHalData->CurrentChannelBW, RFPath, Rate, pHalData->CurrentChannel);\r
1022 \r
1023         powerDiffByRate = powerDiffByRate > limit ? limit : powerDiffByRate;\r
1024         txPower += powerDiffByRate;\r
1025         \r
1026         txPower += PHY_GetTxPowerTrackingOffset( pAdapter, RFPath, Rate );\r
1027 \r
1028         if(txPower > MAX_POWER_INDEX)\r
1029                 txPower = MAX_POWER_INDEX;\r
1030 \r
1031         //DBG_871X("Final Tx Power(RF-%c, Channel: %d) = %d(0x%X)\n", ((RFPath==0)?'A':'B'), Channel, txPower, txPower));\r
1032         return (u8) txPower;    \r
1033 }\r
1034 \r
1035 VOID\r
1036 PHY_SetTxPowerLevel8723B(\r
1037         IN      PADAPTER                Adapter,\r
1038         IN      u8                              Channel\r
1039         )\r
1040 {\r
1041         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);\r
1042         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1043         pFAT_T                  pDM_FatTable = &pDM_Odm->DM_FatTable;\r
1044         u8                              RFPath = ODM_RF_PATH_A; \r
1045 \r
1046         if(pHalData->AntDivCfg){// antenna diversity Enable\r
1047                 RFPath = ( (pDM_FatTable->RxIdleAnt == MAIN_ANT) ? ODM_RF_PATH_A : ODM_RF_PATH_B);\r
1048         }\r
1049         else{ // antenna diversity disable\r
1050                 RFPath = pHalData->ant_path;\r
1051         }\r
1052 \r
1053         RT_TRACE(_module_hal_init_c_, _drv_info_,("==>PHY_SetTxPowerLevel8723B()\n"));\r
1054 \r
1055         PHY_SetTxPowerLevelByPath(Adapter, Channel, RFPath);\r
1056 \r
1057         RT_TRACE(_module_hal_init_c_, _drv_info_,("<==PHY_SetTxPowerLevel8723B()\n"));\r
1058 }\r
1059 \r
1060 VOID\r
1061 PHY_GetTxPowerLevel8723B(\r
1062         IN      PADAPTER                Adapter,\r
1063         OUT s32*                                powerlevel\r
1064         )\r
1065 {\r
1066         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
1067         s32                             TxPwrDbm = 13;\r
1068 #if 0\r
1069         RT_TRACE(COMP_TXAGC, DBG_LOUD, ("PHY_GetTxPowerLevel8723B(): TxPowerLevel: %#x\n", TxPwrDbm));\r
1070 \r
1071         if ( pMgntInfo->ClientConfigPwrInDbm != UNSPECIFIED_PWR_DBM )\r
1072                 *powerlevel = pMgntInfo->ClientConfigPwrInDbm;\r
1073         else\r
1074                 *powerlevel = TxPwrDbm;\r
1075 #endif\r
1076 }\r
1077 \r
1078 \r
1079 // <20130321, VincentLan> A workaround to eliminate the 2440MHz & 2480MHz spur of 8723B. (Asked by Rock.)\r
1080 VOID\r
1081 phy_SpurCalibration_8723B(\r
1082         IN      PADAPTER                                        pAdapter,\r
1083         IN      u1Byte                                          ToChannel,\r
1084         IN      u1Byte                                          threshold\r
1085         )\r
1086 {\r
1087         u4Byte          freq[6] = {0xFCCD, 0xFC4D, 0xFFCD, 0xFF4D, 0xFCCD, 0xFF9A}; // {chnl 5, 6, 7, 8, 13, 14}\r
1088         u1Byte          idx = 0;\r
1089         u1Byte          b_doNotch = FALSE;\r
1090         u1Byte          initial_gain;\r
1091         BOOLEAN         bHW_Ctrl = FALSE, bSW_Ctrl = FALSE,bHW_Ctrl_S1 = FALSE, bSW_Ctrl_S1 = FALSE;\r
1092         u4Byte          reg948;\r
1093 \r
1094         // add for notch\r
1095         u4Byte                          wlan_channel, CurrentChannel, Is40MHz;\r
1096         HAL_DATA_TYPE           *pHalData       = GET_HAL_DATA(pAdapter);\r
1097         //PMGNT_INFO                    pMgntInfo = &(pAdapter->MgntInfo);\r
1098         PDM_ODM_T               pDM_Odm = &(pHalData->odmpriv);\r
1099         //PDM_ODM_T                     pDM_Odm = &pHalData->DM_OutSrc;\r
1100 \r
1101         // check threshold\r
1102         if(threshold <= 0x0)\r
1103                 threshold = 0x16;\r
1104 \r
1105         DBG_8192C("===>phy_SpurCalibration_8723B: Channel = %d\n", ToChannel);\r
1106 \r
1107         if (ToChannel == 5)\r
1108                 idx = 0;\r
1109         else if (ToChannel == 6)\r
1110                 idx = 1;\r
1111         else if (ToChannel == 7)\r
1112                 idx = 2;\r
1113         else if (ToChannel == 8)\r
1114                 idx = 3;\r
1115         else if (ToChannel == 13)\r
1116                 idx = 4;\r
1117         else if (ToChannel == 14)\r
1118                 idx = 5;\r
1119         else\r
1120                 idx = 10;\r
1121 \r
1122         reg948 = PHY_QueryBBReg(pAdapter, rS0S1_PathSwitch, bMaskDWord);\r
1123         if((reg948 & BIT6) == 0x0)\r
1124                 bSW_Ctrl = TRUE;\r
1125         else\r
1126                 bHW_Ctrl = TRUE;\r
1127 \r
1128         if(bHW_Ctrl)\r
1129                 bHW_Ctrl_S1 = (PHY_QueryBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3)==0x1)? TRUE:FALSE;\r
1130         else if(bSW_Ctrl)\r
1131                 bSW_Ctrl_S1 = ((reg948 & BIT9) == 0x0)? TRUE:FALSE;\r
1132 \r
1133         // If wlan at S1 (both HW control & SW control) and current channel=5,6,7,8,13,14\r
1134         if ((bHW_Ctrl_S1 || bSW_Ctrl_S1) && (idx <= 5)) \r
1135         {\r
1136                 initial_gain = (u1Byte) (ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0) & 0x7f);\r
1137                 ODM_Write_DIG(pDM_Odm, 0x30);\r
1138                 PHY_SetBBReg(pAdapter, rFPGA0_AnalogParameter4, bMaskDWord, 0xccf000c0);                // disable 3-wire\r
1139 \r
1140                 PHY_SetBBReg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, freq[idx]);                              // Setup PSD\r
1141                 PHY_SetBBReg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, 0x400000 | freq[idx]); // Start PSD      \r
1142 \r
1143                 rtw_msleep_os(30);\r
1144 \r
1145                 if(PHY_QueryBBReg(pAdapter, rFPGA0_PSDReport, bMaskDWord) >= threshold)\r
1146                         b_doNotch = TRUE;\r
1147                 \r
1148                 PHY_SetBBReg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, freq[idx]); // turn off PSD\r
1149                 PHY_SetBBReg(pAdapter, rFPGA0_AnalogParameter4, bMaskDWord, 0xccc000c0);        // enable 3-wire\r
1150                 ODM_Write_DIG(pDM_Odm, initial_gain);\r
1151         }\r
1152 \r
1153         // --- Notch Filter --- Asked by Rock   \r
1154         if (b_doNotch)\r
1155         {\r
1156                 CurrentChannel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);  \r
1157                 wlan_channel   = CurrentChannel & 0x0f;                                             //Get center frequency\r
1158 \r
1159                 switch(wlan_channel)                                                                                            //Set notch filter                              \r
1160                 {\r
1161                         case 5:\r
1162                         case 13:\r
1163                                 ODM_SetBBReg(pDM_Odm, 0xC40, BIT28|BIT27|BIT26|BIT25|BIT24, 0xB);\r
1164                                 ODM_SetBBReg(pDM_Odm, 0xC40, BIT9, 0x1);                        //enable notch filter\r
1165                                 ODM_SetBBReg(pDM_Odm, 0xD40, bMaskDWord, 0x06000000);\r
1166                                 ODM_SetBBReg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);\r
1167                                 ODM_SetBBReg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);\r
1168                                 ODM_SetBBReg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000000);\r
1169                                 ODM_SetBBReg(pDM_Odm, 0xD2C, BIT28, 0x1);                       //enable CSI mask\r
1170                                 break;\r
1171                         case 6:\r
1172                                 ODM_SetBBReg(pDM_Odm, 0xC40, BIT28|BIT27|BIT26|BIT25|BIT24, 0x4);\r
1173                                 ODM_SetBBReg(pDM_Odm, 0xC40, BIT9, 0x1);                                //enable notch filter\r
1174                                 ODM_SetBBReg(pDM_Odm, 0xD40, bMaskDWord, 0x00000600);\r
1175                                 ODM_SetBBReg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);\r
1176                                 ODM_SetBBReg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);\r
1177                                 ODM_SetBBReg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000000);\r
1178                                 ODM_SetBBReg(pDM_Odm, 0xD2C, BIT28, 0x1);                       //enable CSI mask\r
1179                                 break;\r
1180                         case 7:\r
1181                                 ODM_SetBBReg(pDM_Odm, 0xC40, BIT28|BIT27|BIT26|BIT25|BIT24, 0x3);\r
1182                                 ODM_SetBBReg(pDM_Odm, 0xC40, BIT9, 0x1);                        //enable notch filter\r
1183                                 ODM_SetBBReg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);\r
1184                                 ODM_SetBBReg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);\r
1185                                 ODM_SetBBReg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);\r
1186                                 ODM_SetBBReg(pDM_Odm, 0xD4C, bMaskDWord, 0x06000000);\r
1187                                 ODM_SetBBReg(pDM_Odm, 0xD2C, BIT28, 0x1);                       //enable CSI mask\r
1188                                 break;\r
1189                         case 8:\r
1190                                 ODM_SetBBReg(pDM_Odm, 0xC40, BIT28|BIT27|BIT26|BIT25|BIT24, 0xA);\r
1191                                 ODM_SetBBReg(pDM_Odm, 0xC40, BIT9, 0x1);                        //enable notch filter\r
1192                                 ODM_SetBBReg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);\r
1193                                 ODM_SetBBReg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);\r
1194                                 ODM_SetBBReg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);\r
1195                                 ODM_SetBBReg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000380);\r
1196                                 ODM_SetBBReg(pDM_Odm, 0xD2C, BIT28, 0x1);                       //enable CSI mask\r
1197                                 break;\r
1198                         case 14:\r
1199                                 ODM_SetBBReg(pDM_Odm, 0xC40, BIT28|BIT27|BIT26|BIT25|BIT24, 0x5);\r
1200                                 ODM_SetBBReg(pDM_Odm, 0xC40, BIT9, 0x1);                                //enable notch filter\r
1201                                 ODM_SetBBReg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);\r
1202                                 ODM_SetBBReg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);\r
1203                                 ODM_SetBBReg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);\r
1204                                 ODM_SetBBReg(pDM_Odm, 0xD4C, bMaskDWord, 0x00180000);\r
1205                                 ODM_SetBBReg(pDM_Odm, 0xD2C, BIT28, 0x1);                       //enable CSI mask\r
1206                                 break;\r
1207                         default:\r
1208                                 ODM_SetBBReg(pDM_Odm, 0xC40, BIT9, 0x0);                                //disable notch filter\r
1209                                 ODM_SetBBReg(pDM_Odm, 0xD2C, BIT28, 0x0);                       //disable CSI mask      function\r
1210                                 break;\r
1211                 }//switch(wlan_channel) \r
1212                 return;\r
1213         }\r
1214 \r
1215         ODM_SetBBReg(pDM_Odm, 0xC40, BIT9, 0x0);                     //disable notch filter\r
1216         ODM_SetBBReg(pDM_Odm, 0xD2C, BIT28, 0x0);                    //disable CSI mask\r
1217 \r
1218 }\r
1219 \r
1220 VOID\r
1221 phy_SetRegBW_8723B(\r
1222         IN      PADAPTER                Adapter,\r
1223         CHANNEL_WIDTH   CurrentBW\r
1224 )       \r
1225 {\r
1226         u16     RegRfMod_BW, u2tmp = 0;\r
1227         RegRfMod_BW = rtw_read16(Adapter, REG_TRXPTCL_CTL_8723B);\r
1228 \r
1229         switch(CurrentBW)\r
1230         {\r
1231                 case CHANNEL_WIDTH_20:\r
1232                         rtw_write16(Adapter, REG_TRXPTCL_CTL_8723B, (RegRfMod_BW & 0xFE7F)); // BIT 7 = 0, BIT 8 = 0\r
1233                         break;\r
1234 \r
1235                 case CHANNEL_WIDTH_40:\r
1236                         u2tmp = RegRfMod_BW | BIT7;\r
1237                         rtw_write16(Adapter, REG_TRXPTCL_CTL_8723B, (u2tmp & 0xFEFF)); // BIT 7 = 1, BIT 8 = 0\r
1238                         break;\r
1239 \r
1240                 case CHANNEL_WIDTH_80:\r
1241                         u2tmp = RegRfMod_BW | BIT8;\r
1242                         rtw_write16(Adapter, REG_TRXPTCL_CTL_8723B, (u2tmp & 0xFF7F)); // BIT 7 = 0, BIT 8 = 1\r
1243                         break;\r
1244 \r
1245                 default:\r
1246                         DBG_871X("phy_PostSetBWMode8723B():     unknown Bandwidth: %#X\n",CurrentBW);\r
1247                         break;\r
1248         }\r
1249 }\r
1250 \r
1251 u8 \r
1252 phy_GetSecondaryChnl_8723B(\r
1253         IN      PADAPTER        Adapter\r
1254 )\r
1255 {\r
1256         u8      SCSettingOf40 = 0, SCSettingOf20 = 0;\r
1257         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);\r
1258 \r
1259         RT_TRACE(_module_hal_init_c_, _drv_info_,("SCMapping: VHT Case: pHalData->CurrentChannelBW %d, pHalData->nCur80MhzPrimeSC %d, pHalData->nCur40MhzPrimeSC %d \n",pHalData->CurrentChannelBW,pHalData->nCur80MhzPrimeSC,pHalData->nCur40MhzPrimeSC));\r
1260         if(pHalData->CurrentChannelBW== CHANNEL_WIDTH_80)\r
1261         {\r
1262                 if(pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)\r
1263                         SCSettingOf40 = VHT_DATA_SC_40_LOWER_OF_80MHZ;\r
1264                 else if(pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)\r
1265                         SCSettingOf40 = VHT_DATA_SC_40_UPPER_OF_80MHZ;\r
1266                 else\r
1267                         RT_TRACE(_module_hal_init_c_, _drv_err_,("SCMapping: Not Correct Primary40MHz Setting \n"));\r
1268                 \r
1269                 if((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))\r
1270                         SCSettingOf20 = VHT_DATA_SC_20_LOWEST_OF_80MHZ;\r
1271                 else if((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))\r
1272                         SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;\r
1273                 else if((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))\r
1274                         SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;\r
1275                 else if((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))\r
1276                         SCSettingOf20 = VHT_DATA_SC_20_UPPERST_OF_80MHZ;\r
1277                 else\r
1278                         RT_TRACE(_module_hal_init_c_, _drv_err_,("SCMapping: Not Correct Primary40MHz Setting \n"));\r
1279         }\r
1280         else if(pHalData->CurrentChannelBW == CHANNEL_WIDTH_40)\r
1281         {\r
1282                 RT_TRACE(_module_hal_init_c_, _drv_info_,("SCMapping: VHT Case: pHalData->CurrentChannelBW %d, pHalData->nCur40MhzPrimeSC %d \n",pHalData->CurrentChannelBW,pHalData->nCur40MhzPrimeSC));\r
1283 \r
1284                 if(pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)\r
1285                         SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;\r
1286                 else if(pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)\r
1287                         SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;\r
1288                 else\r
1289                         RT_TRACE(_module_hal_init_c_, _drv_err_,("SCMapping: Not Correct Primary40MHz Setting \n"));\r
1290         }\r
1291 \r
1292         RT_TRACE(_module_hal_init_c_, _drv_info_,("SCMapping: SC Value %x \n", ( (SCSettingOf40 << 4) | SCSettingOf20)));\r
1293         return  ( (SCSettingOf40 << 4) | SCSettingOf20);\r
1294 }\r
1295 \r
1296 VOID\r
1297 phy_PostSetBwMode8723B(\r
1298         IN      PADAPTER        Adapter\r
1299 )\r
1300 {\r
1301         u1Byte                  SubChnlNum = 0;\r
1302         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
1303 \r
1304 \r
1305         //3 Set Reg668 Reg440 BW\r
1306         phy_SetRegBW_8723B(Adapter, pHalData->CurrentChannelBW);\r
1307 \r
1308         //3 Set Reg483\r
1309         SubChnlNum = phy_GetSecondaryChnl_8723B(Adapter);\r
1310         rtw_write8(Adapter, REG_DATA_SC_8723B, SubChnlNum);\r
1311         \r
1312         //3//\r
1313         //3//<2>Set PHY related register\r
1314         //3//\r
1315         switch(pHalData->CurrentChannelBW)\r
1316         {\r
1317                 /* 20 MHz channel*/\r
1318                 case CHANNEL_WIDTH_20:\r
1319                         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0);\r
1320                         \r
1321                         PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);\r
1322                         \r
1323 //                      PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 1);\r
1324                         \r
1325                         PHY_SetBBReg(Adapter, rOFDM0_TxPseudoNoiseWgt, (BIT31|BIT30), 0x0);\r
1326                         break;\r
1327 \r
1328 \r
1329                 /* 40 MHz channel*/\r
1330                 case CHANNEL_WIDTH_40:\r
1331                         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1);\r
1332                         \r
1333                         PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);\r
1334                         \r
1335                         // Set Control channel to upper or lower. These settings are required only for 40MHz\r
1336                         PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1));\r
1337                 \r
1338                         PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);\r
1339                         \r
1340 //                      PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 0);\r
1341                         \r
1342                         PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC==HAL_PRIME_CHNL_OFFSET_LOWER)?2:1);\r
1343                         \r
1344                         break;\r
1345 \r
1346 \r
1347                         \r
1348                 default:\r
1349                         /*RT_TRACE(COMP_DBG, DBG_LOUD, ("phy_SetBWMode8723B(): unknown Bandwidth: %#X\n"\\r
1350                                                 ,pHalData->CurrentChannelBW));*/\r
1351                         break;\r
1352                         \r
1353         }\r
1354 \r
1355         //3<3>Set RF related register\r
1356         PHY_RF6052SetBandwidth8723B(Adapter, pHalData->CurrentChannelBW);\r
1357 }\r
1358 \r
1359 VOID\r
1360 phy_SwChnl8723B(        \r
1361         IN      PADAPTER                                        pAdapter\r
1362         )\r
1363 {\r
1364         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1365         u8                      channelToSW = pHalData->CurrentChannel;\r
1366 \r
1367         if(pHalData->rf_chip == RF_PSEUDO_11N)\r
1368         {\r
1369                 //RT_TRACE(COMP_MLME,DBG_LOUD,("phy_SwChnl8723B: return for PSEUDO \n"));\r
1370                 return;\r
1371         }\r
1372         pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff00) | channelToSW  );\r
1373         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0] );\r
1374         PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0] );\r
1375 \r
1376         DBG_8192C("===>phy_SwChnl8723B: Channel = %d\n", channelToSW);\r
1377         //phy_SpurCalibration_8723B(pAdapter, channelToSW, 0x16);\r
1378 }\r
1379 \r
1380 VOID\r
1381 phy_SwChnlAndSetBwMode8723B(\r
1382         IN  PADAPTER            Adapter\r
1383 )\r
1384 {\r
1385         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);\r
1386 \r
1387         //RT_TRACE(COMP_SCAN, DBG_LOUD, ("phy_SwChnlAndSetBwMode8723B(): bSwChnl %d, bSetChnlBW %d \n", pHalData->bSwChnl, pHalData->bSetChnlBW));\r
1388         if ( Adapter->bNotifyChannelChange )\r
1389         {\r
1390                 DBG_871X( "[%s] bSwChnl=%d, ch=%d, bSetChnlBW=%d, bw=%d\n", \r
1391                         __FUNCTION__, \r
1392                         pHalData->bSwChnl,\r
1393                         pHalData->CurrentChannel,\r
1394                         pHalData->bSetChnlBW,\r
1395                         pHalData->CurrentChannelBW);\r
1396         }\r
1397 \r
1398         if((Adapter->bDriverStopped) || (Adapter->bSurpriseRemoved))\r
1399         {\r
1400                 return;\r
1401         }\r
1402 \r
1403         if(pHalData->bSwChnl)\r
1404         {\r
1405                 phy_SwChnl8723B(Adapter);\r
1406                 pHalData->bSwChnl = _FALSE;\r
1407         }       \r
1408 \r
1409         if(pHalData->bSetChnlBW)\r
1410         {\r
1411                 phy_PostSetBwMode8723B(Adapter);\r
1412                 pHalData->bSetChnlBW = _FALSE;\r
1413         }       \r
1414 \r
1415         PHY_SetTxPowerLevel8723B(Adapter, pHalData->CurrentChannel);\r
1416 }\r
1417 \r
1418 VOID\r
1419 PHY_HandleSwChnlAndSetBW8723B(\r
1420         IN      PADAPTER                        Adapter,\r
1421         IN      BOOLEAN                         bSwitchChannel,\r
1422         IN      BOOLEAN                         bSetBandWidth,\r
1423         IN      u8                                      ChannelNum,\r
1424         IN      CHANNEL_WIDTH   ChnlWidth,\r
1425         IN      EXTCHNL_OFFSET  ExtChnlOffsetOf40MHz,\r
1426         IN      EXTCHNL_OFFSET  ExtChnlOffsetOf80MHz,\r
1427         IN      u8                                      CenterFrequencyIndex1\r
1428 )\r
1429 {\r
1430         //static BOOLEAN                bInitialzed = _FALSE;\r
1431         PHAL_DATA_TYPE          pHalData = GET_HAL_DATA(Adapter);\r
1432         u8                                      tmpChannel = pHalData->CurrentChannel;\r
1433         CHANNEL_WIDTH   tmpBW= pHalData->CurrentChannelBW;\r
1434         u8                                      tmpnCur40MhzPrimeSC = pHalData->nCur40MhzPrimeSC;\r
1435         u8                                      tmpnCur80MhzPrimeSC = pHalData->nCur80MhzPrimeSC;\r
1436         u8                                      tmpCenterFrequencyIndex1 =pHalData->CurrentCenterFrequencyIndex1;\r
1437         struct mlme_ext_priv    *pmlmeext = &Adapter->mlmeextpriv;\r
1438 \r
1439         //DBG_871X("=> PHY_HandleSwChnlAndSetBW8812: bSwitchChannel %d, bSetBandWidth %d \n",bSwitchChannel,bSetBandWidth);\r
1440 \r
1441         //check is swchnl or setbw\r
1442         if(!bSwitchChannel && !bSetBandWidth)\r
1443         {\r
1444                 DBG_871X("PHY_HandleSwChnlAndSetBW8812:  not switch channel and not set bandwidth \n");\r
1445                 return;\r
1446         }\r
1447 \r
1448         //skip change for channel or bandwidth is the same\r
1449         if(bSwitchChannel)\r
1450         {\r
1451                 //if(pHalData->CurrentChannel != ChannelNum)\r
1452                 {\r
1453                         if (HAL_IsLegalChannel(Adapter, ChannelNum))\r
1454                                 pHalData->bSwChnl = _TRUE;\r
1455                 }\r
1456         }\r
1457 \r
1458         if(bSetBandWidth)\r
1459         {\r
1460                 #if 0\r
1461                 if(bInitialzed == _FALSE)\r
1462                 {\r
1463                         bInitialzed = _TRUE;\r
1464                         pHalData->bSetChnlBW = _TRUE;\r
1465                 }\r
1466                 else if((pHalData->CurrentChannelBW != ChnlWidth) ||(pHalData->nCur40MhzPrimeSC != ExtChnlOffsetOf40MHz) || (pHalData->CurrentCenterFrequencyIndex1!= CenterFrequencyIndex1))\r
1467                 {\r
1468                         pHalData->bSetChnlBW = _TRUE;\r
1469                 }\r
1470                 #else\r
1471                         pHalData->bSetChnlBW = _TRUE;\r
1472                 #endif\r
1473         }\r
1474 \r
1475         if(!pHalData->bSetChnlBW && !pHalData->bSwChnl)\r
1476         {\r
1477                 //DBG_871X("<= PHY_HandleSwChnlAndSetBW8812: bSwChnl %d, bSetChnlBW %d \n",pHalData->bSwChnl,pHalData->bSetChnlBW);\r
1478                 return;\r
1479         }\r
1480 \r
1481 \r
1482         if(pHalData->bSwChnl)\r
1483         {\r
1484                 pHalData->CurrentChannel=ChannelNum;\r
1485                 pHalData->CurrentCenterFrequencyIndex1 = ChannelNum;\r
1486         }\r
1487         \r
1488 \r
1489         if(pHalData->bSetChnlBW)\r
1490         {\r
1491                 pHalData->CurrentChannelBW = ChnlWidth;\r
1492 #if 0\r
1493                 if(ExtChnlOffsetOf40MHz==EXTCHNL_OFFSET_LOWER)\r
1494                         pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;\r
1495                 else if(ExtChnlOffsetOf40MHz==EXTCHNL_OFFSET_UPPER)\r
1496                         pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;\r
1497                 else\r
1498                         pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\r
1499 \r
1500                 if(ExtChnlOffsetOf80MHz==EXTCHNL_OFFSET_LOWER)\r
1501                         pHalData->nCur80MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;\r
1502                 else if(ExtChnlOffsetOf80MHz==EXTCHNL_OFFSET_UPPER)\r
1503                         pHalData->nCur80MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;\r
1504                 else\r
1505                         pHalData->nCur80MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\r
1506 #else\r
1507                 pHalData->nCur40MhzPrimeSC = ExtChnlOffsetOf40MHz;\r
1508                 pHalData->nCur80MhzPrimeSC = ExtChnlOffsetOf80MHz;\r
1509 #endif\r
1510 \r
1511                 pHalData->CurrentCenterFrequencyIndex1 = CenterFrequencyIndex1;         \r
1512         }\r
1513 \r
1514         //Switch workitem or set timer to do switch channel or setbandwidth operation\r
1515         if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))\r
1516         {\r
1517                 phy_SwChnlAndSetBwMode8723B(Adapter);\r
1518         }\r
1519         else\r
1520         {\r
1521                 if(pHalData->bSwChnl)\r
1522                 {\r
1523                         pHalData->CurrentChannel = tmpChannel;\r
1524                         pHalData->CurrentCenterFrequencyIndex1 = tmpChannel;\r
1525                 }       \r
1526                 if(pHalData->bSetChnlBW)\r
1527                 {\r
1528                         pHalData->CurrentChannelBW = tmpBW;\r
1529                         pHalData->nCur40MhzPrimeSC = tmpnCur40MhzPrimeSC;\r
1530                         pHalData->nCur80MhzPrimeSC = tmpnCur80MhzPrimeSC;\r
1531                         pHalData->CurrentCenterFrequencyIndex1 = tmpCenterFrequencyIndex1;\r
1532                 }\r
1533         }\r
1534 \r
1535         //DBG_871X("Channel %d ChannelBW %d ",pHalData->CurrentChannel, pHalData->CurrentChannelBW);\r
1536         //DBG_871X("40MhzPrimeSC %d 80MhzPrimeSC %d ",pHalData->nCur40MhzPrimeSC, pHalData->nCur80MhzPrimeSC);\r
1537         //DBG_871X("CenterFrequencyIndex1 %d \n",pHalData->CurrentCenterFrequencyIndex1);\r
1538 \r
1539         //DBG_871X("<= PHY_HandleSwChnlAndSetBW8812: bSwChnl %d, bSetChnlBW %d \n",pHalData->bSwChnl,pHalData->bSetChnlBW);\r
1540 \r
1541 }\r
1542 \r
1543 VOID\r
1544 PHY_SetBWMode8723B(\r
1545         IN      PADAPTER                                        Adapter,\r
1546         IN      CHANNEL_WIDTH   Bandwidth,      // 20M or 40M\r
1547         IN      unsigned char   Offset          // Upper, Lower, or Don't care\r
1548 )\r
1549 {\r
1550         PHAL_DATA_TYPE          pHalData = GET_HAL_DATA(Adapter);\r
1551 \r
1552         PHY_HandleSwChnlAndSetBW8723B(Adapter, _FALSE, _TRUE, pHalData->CurrentChannel, Bandwidth, Offset, Offset, pHalData->CurrentChannel);\r
1553 }\r
1554 \r
1555 VOID\r
1556 PHY_SwChnl8723B(        // Call after initialization\r
1557         IN      PADAPTER        Adapter,\r
1558         IN      u8              channel\r
1559         )\r
1560 {\r
1561         PHY_HandleSwChnlAndSetBW8723B(Adapter, _TRUE, _FALSE, channel, 0, 0, 0, channel);\r
1562 }\r
1563 \r
1564 VOID\r
1565 PHY_SetSwChnlBWMode8723B(\r
1566         IN      PADAPTER                        Adapter,\r
1567         IN      u8                                      channel,\r
1568         IN      CHANNEL_WIDTH   Bandwidth,\r
1569         IN      u8                                      Offset40,\r
1570         IN      u8                                      Offset80\r
1571 )\r
1572 {\r
1573         //DBG_871X("%s()===>\n",__FUNCTION__);\r
1574 \r
1575         PHY_HandleSwChnlAndSetBW8723B(Adapter, _TRUE, _TRUE, channel, Bandwidth, Offset40, Offset80, channel);\r
1576 \r
1577         //DBG_871X("<==%s()\n",__FUNCTION__);\r
1578 }\r
1579 \r
1580 static VOID\r
1581 _PHY_DumpRFReg_8723B(IN PADAPTER        pAdapter)\r
1582 {\r
1583         u32 rfRegValue,rfRegOffset;\r
1584 \r
1585         RT_TRACE(_module_hal_init_c_, _drv_info_, ("_PHY_DumpRFReg_8723B()====>\n"));\r
1586 \r
1587         for(rfRegOffset = 0x00;rfRegOffset<=0x30;rfRegOffset++){\r
1588                 rfRegValue = PHY_QueryRFReg_8723B(pAdapter,RF_PATH_A, rfRegOffset, bMaskDWord);\r
1589                 RT_TRACE(_module_hal_init_c_, _drv_info_, (" 0x%02x = 0x%08x\n",rfRegOffset,rfRegValue));\r
1590         }\r
1591         RT_TRACE(_module_hal_init_c_, _drv_info_, ("<===== _PHY_DumpRFReg_8723B()\n"));\r
1592 }\r
1593 \r
1594 \r