drivers/net/wireless/rockchip_wlan/rtl8723bu/hal/OUTSRC/phydm.h

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *                                        \r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 \r
  21 \r
  22 #ifndef __HALDMOUTSRC_H__\r
  23 #define __HALDMOUTSRC_H__\r
  24 \r
  25 //============================================================\r
  26 // include files\r
  27 //============================================================\r
  28 #include "phydm_DIG.h"\r
  29 #include "phydm_EdcaTurboCheck.h"\r
  30 #include "phydm_PathDiv.h"\r
  31 #include "phydm_DynamicBBPowerSaving.h"\r
  32 #include "phydm_RaInfo.h"\r
  33 #include "phydm_DynamicTxPower.h"\r
  34 #include "phydm_CfoTracking.h"\r
  35 #include "phydm_ACS.h"\r
  36 #include "phydm_PowerTracking.h"\r
  37 #include "PhyDM_Adaptivity.h"\r
  38 #include "phydm_NoiseMonitor.h"\r
  39 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))\r
  40 #include "phydm_RXHP.h"\r
  41 #endif\r
  42 \r
  43 //============================================================\r
  44 // Definition \r
  45 //============================================================\r
  46 //\r
  47 // 2011/09/22 MH Define all team supprt ability.\r
  48 //\r
  49 \r
  50 //\r
  51 // 2011/09/22 MH Define for all teams. Please Define the constan in your precomp header.\r
  52 //\r
  53 //#define               DM_ODM_SUPPORT_AP                       0\r
  54 //#define               DM_ODM_SUPPORT_ADSL                     0\r
  55 //#define               DM_ODM_SUPPORT_CE                       0\r
  56 //#define               DM_ODM_SUPPORT_MP                       1\r
  57 \r
  58 //\r
  59 // 2011/09/28 MH Define ODM SW team support flag.\r
  60 //\r
  61 \r
  62 \r
  63 \r
  64 //\r
  65 // Antenna Switch Relative Definition.\r
  66 //\r
  67 \r
  68 //\r
  69 // 20100503 Joseph:\r
  70 // Add new function SwAntDivCheck8192C().\r
  71 // This is the main function of Antenna diversity function before link.\r
  72 // Mainly, it just retains last scan result and scan again.\r
  73 // After that, it compares the scan result to see which one gets better RSSI.\r
  74 // It selects antenna with better receiving power and returns better scan result.\r
  75 //\r
  76 #define TP_MODE         0\r
  77 #define RSSI_MODE               1\r
  78 #define TRAFFIC_LOW     0\r
  79 #define TRAFFIC_HIGH    1\r
  80 #define NONE                    0\r
  81 \r
  82 \r
  83 //============================================================\r
  84 //3 Tx Power Tracking\r
  85 //3============================================================\r
  86 \r
  87 \r
  88 //============================================================\r
  89 //3 PSD Handler\r
  90 //3============================================================\r
  91 \r
  92 #define AFH_PSD         1       //0:normal PSD scan, 1: only do 20 pts PSD\r
  93 #define MODE_40M                0       //0:20M, 1:40M\r
  94 #define PSD_TH2         3  \r
  95 #define PSD_CHMIN               20   // Minimum channel number for BT AFH\r
  96 #define SIR_STEP_SIZE   3\r
  97 #define   Smooth_Size_1         5\r
  98 #define Smooth_TH_1     3\r
  99 #define   Smooth_Size_2         10\r
 100 #define Smooth_TH_2     4\r
 101 #define   Smooth_Size_3         20\r
 102 #define Smooth_TH_3     4\r
 103 #define   Smooth_Step_Size 5\r
 104 #define Adaptive_SIR    1\r
 105 #if(RTL8723_FPGA_VERIFICATION == 1)\r
 106 #define PSD_RESCAN              1\r
 107 #else\r
 108 #define PSD_RESCAN              4\r
 109 #endif\r
 110 #define PSD_SCAN_INTERVAL       700 //ms\r
 111 \r
 112 \r
 113 \r
 114 //8723A High Power IGI Setting\r
 115 #define         DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22\r
 116 #define                 DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28\r
 117 #define         DM_DIG_HIGH_PWR_THRESHOLD       0x3a\r
 118 #define         DM_DIG_LOW_PWR_THRESHOLD        0x14\r
 119 \r
 120 //ANT Test\r
 121 #define                 ANTTESTALL              0x00            //Ant A or B will be Testing   \r
 122 #define         ANTTESTA                0x01            //Ant A will be Testing \r
 123 #define         ANTTESTB                0x02            //Ant B will be testing\r
 124 \r
 125 //for 8723A Ant Definition--2012--06--07 due to different IC may be different ANT define\r
 126 #define         MAIN_ANT                1               //Ant A or Ant Main\r
 127 #define         AUX_ANT         2               //AntB or Ant Aux\r
 128 #define         MAX_ANT         3               // 3 for AP using\r
 129 \r
 130 \r
 131 //Antenna Diversity Type\r
 132 #define SW_ANTDIV       0\r
 133 #define HW_ANTDIV       1\r
 134 //============================================================\r
 135 // structure and define\r
 136 //============================================================\r
 137 \r
 138 //\r
 139 // 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement.\r
 140 // We need to remove to other position???\r
 141 //\r
 142 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))\r
 143 typedef         struct rtl8192cd_priv {\r
 144         u1Byte          temp;\r
 145 \r
 146 }rtl8192cd_priv, *prtl8192cd_priv;\r
 147 #endif\r
 148 \r
 149 \r
 150 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
 151 typedef         struct _ADAPTER{\r
 152         u1Byte          temp;\r
 153         #ifdef AP_BUILD_WORKAROUND\r
 154         HAL_DATA_TYPE*          temp2;\r
 155         prtl8192cd_priv         priv;\r
 156         #endif\r
 157 }ADAPTER, *PADAPTER;\r
 158 #endif\r
 159 \r
 160 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
 161 \r
 162 typedef         struct _WLAN_STA{\r
 163         u1Byte          temp;\r
 164 } WLAN_STA, *PRT_WLAN_STA;\r
 165 \r
 166 #endif\r
 167 \r
 168 //Remove DIG by Yuchen\r
 169 \r
 170 //Remoce BB power saving by Yuchn\r
 171 \r
 172 //Remove DIG by yuchen\r
 173 \r
 174 typedef struct _Dynamic_Primary_CCA{\r
 175         u1Byte          PriCCA_flag;\r
 176         u1Byte          intf_flag;\r
 177         u1Byte          intf_type;  \r
 178         u1Byte          DupRTS_flag;\r
 179         u1Byte          Monitor_flag;\r
 180         u1Byte          CH_offset;\r
 181         u1Byte                  MF_state;\r
 182 }Pri_CCA_T, *pPri_CCA_T;\r
 183 \r
 184 //Remove RA_T,*pRA_T by RS_James\r
 185 \r
 186 typedef struct _RX_High_Power_\r
 187 {\r
 188         u1Byte          RXHP_flag;\r
 189         u1Byte          PSD_func_trigger;\r
 190         u1Byte          PSD_bitmap_RXHP[80];\r
 191         u1Byte          Pre_IGI;\r
 192         u1Byte          Cur_IGI;\r
 193         u1Byte          Pre_pw_th;\r
 194         u1Byte          Cur_pw_th;\r
 195         BOOLEAN         First_time_enter;\r
 196         BOOLEAN         RXHP_enable;\r
 197         u1Byte          TP_Mode;\r
 198         RT_TIMER        PSDTimer;\r
 199 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)    \r
 200         #if USE_WORKITEM\r
 201         RT_WORK_ITEM            PSDTimeWorkitem;\r
 202         #endif\r
 203 #endif\r
 204 \r
 205 }RXHP_T, *pRXHP_T;\r
 206         \r
 207 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE))\r
 208 #define ASSOCIATE_ENTRY_NUM                                     32 // Max size of AsocEntry[].\r
 209 #define ODM_ASSOCIATE_ENTRY_NUM                         ASSOCIATE_ENTRY_NUM\r
 210 \r
 211 #elif(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
 212 #define ASSOCIATE_ENTRY_NUM                                     NUM_STAT\r
 213 #define ODM_ASSOCIATE_ENTRY_NUM                         ASSOCIATE_ENTRY_NUM+1\r
 214 \r
 215 #else\r
 216 //\r
 217 // 2012/01/12 MH Revise for compatiable with other SW team. \r
 218 // 0 is for STA 1-n is for AP clients.\r
 219 //\r
 220 #define ODM_ASSOCIATE_ENTRY_NUM                         ASSOCIATE_ENTRY_NUM+1// Default port only one\r
 221 #endif\r
 222 \r
 223 //#ifdef CONFIG_ANTENNA_DIVERSITY\r
 224 // This indicates two different the steps. \r
 225 // In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air.\r
 226 // In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK\r
 227 // with original RSSI to determine if it is necessary to switch antenna.\r
 228 #define SWAW_STEP_PEAK          0\r
 229 #define SWAW_STEP_DETERMINE     1\r
 230 \r
 231 #define TP_MODE         0\r
 232 #define RSSI_MODE               1\r
 233 #define TRAFFIC_LOW     0\r
 234 #define TRAFFIC_HIGH    1\r
 235 #define TRAFFIC_UltraLOW        2\r
 236 \r
 237 typedef struct _SW_Antenna_Switch_\r
 238 {\r
 239         u1Byte          Double_chk_flag;\r
 240         u1Byte          try_flag;\r
 241         s4Byte          PreRSSI;\r
 242         u1Byte          CurAntenna;\r
 243         u1Byte          PreAntenna;\r
 244         u1Byte          RSSI_Trying;\r
 245         u1Byte          TestMode;\r
 246         u1Byte          bTriggerAntennaSwitch;\r
 247         u1Byte          SelectAntennaMap;\r
 248         u1Byte          RSSI_target;    \r
 249         u1Byte          reset_idx;\r
 250         u2Byte          Single_Ant_Counter;\r
 251         u2Byte          Dual_Ant_Counter;\r
 252         u2Byte          Aux_FailDetec_Counter;\r
 253         u2Byte          Retry_Counter;\r
 254 \r
 255         // Before link Antenna Switch check\r
 256         u1Byte          SWAS_NoLink_State;\r
 257         u4Byte          SWAS_NoLink_BK_Reg860;\r
 258         u4Byte          SWAS_NoLink_BK_Reg92c;\r
 259         u4Byte          SWAS_NoLink_BK_Reg948;\r
 260         BOOLEAN         ANTA_ON;        //To indicate Ant A is or not\r
 261         BOOLEAN         ANTB_ON;        //To indicate Ant B is on or not\r
 262         BOOLEAN         Pre_Aux_FailDetec;\r
 263         BOOLEAN         RSSI_AntDect_bResult;   \r
 264         u1Byte          Ant5G;\r
 265         u1Byte          Ant2G;\r
 266 \r
 267         s4Byte          RSSI_sum_A;\r
 268         s4Byte          RSSI_sum_B;\r
 269         s4Byte          RSSI_cnt_A;\r
 270         s4Byte          RSSI_cnt_B;\r
 271 \r
 272         u8Byte          lastTxOkCnt;\r
 273         u8Byte          lastRxOkCnt;\r
 274         u8Byte          TXByteCnt_A;\r
 275         u8Byte          TXByteCnt_B;\r
 276         u8Byte          RXByteCnt_A;\r
 277         u8Byte          RXByteCnt_B;\r
 278         u1Byte          TrafficLoad;\r
 279         u1Byte          Train_time;\r
 280         u1Byte          Train_time_flag;\r
 281         RT_TIMER        SwAntennaSwitchTimer;\r
 282 #if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)    \r
 283         RT_TIMER        SwAntennaSwitchTimer_8723B;\r
 284         u4Byte          PktCnt_SWAntDivByCtrlFrame;\r
 285         BOOLEAN         bSWAntDivByCtrlFrame;\r
 286 #endif\r
 287         \r
 288 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)    \r
 289         #if USE_WORKITEM\r
 290         RT_WORK_ITEM                    SwAntennaSwitchWorkitem;\r
 291 #if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)    \r
 292         RT_WORK_ITEM                    SwAntennaSwitchWorkitem_8723B;\r
 293         #endif\r
 294 #endif\r
 295 #endif\r
 296 /* CE Platform use\r
 297 #ifdef CONFIG_SW_ANTENNA_DIVERSITY\r
 298         _timer SwAntennaSwitchTimer; \r
 299         u8Byte lastTxOkCnt;\r
 300         u8Byte lastRxOkCnt;\r
 301         u8Byte TXByteCnt_A;\r
 302         u8Byte TXByteCnt_B;\r
 303         u8Byte RXByteCnt_A;\r
 304         u8Byte RXByteCnt_B;\r
 305         u1Byte DoubleComfirm;\r
 306         u1Byte TrafficLoad;\r
 307         //SW Antenna Switch\r
 308 \r
 309 \r
 310 #endif\r
 311 */\r
 312 #ifdef CONFIG_HW_ANTENNA_DIVERSITY\r
 313         //Hybrid Antenna Diversity\r
 314         u4Byte          CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM+1];\r
 315         u4Byte          CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM+1];\r
 316         u4Byte          OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM+1];\r
 317         u4Byte          OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM+1];\r
 318         u4Byte          RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM+1];\r
 319         u4Byte          RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM+1];\r
 320         u1Byte          TxAnt[ASSOCIATE_ENTRY_NUM+1];\r
 321         u1Byte          TargetSTA;\r
 322         u1Byte          antsel;\r
 323         u1Byte          RxIdleAnt;\r
 324 \r
 325 #endif\r
 326         \r
 327 }SWAT_T, *pSWAT_T;\r
 328 //#endif\r
 329 \r
 330 // Edca Remove by YuChen\r
 331 \r
 332 //ODM_RATE_ADAPTIVE Remove by RS_James\r
 333 \r
 334 \r
 335 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
 336 \r
 337 \r
 338 #ifdef ADSL_AP_BUILD_WORKAROUND\r
 339 #define MAX_TOLERANCE                   5\r
 340 #define IQK_DELAY_TIME                  1               //ms\r
 341 #endif\r
 342 \r
 343 //\r
 344 // Indicate different AP vendor for IOT issue.\r
 345 //\r
 346 typedef enum _HT_IOT_PEER\r
 347 {\r
 348         HT_IOT_PEER_UNKNOWN                     = 0,\r
 349         HT_IOT_PEER_REALTEK                     = 1,\r
 350         HT_IOT_PEER_REALTEK_92SE                = 2,\r
 351         HT_IOT_PEER_BROADCOM            = 3,\r
 352         HT_IOT_PEER_RALINK                      = 4,\r
 353         HT_IOT_PEER_ATHEROS                     = 5,\r
 354         HT_IOT_PEER_CISCO                               = 6,\r
 355         HT_IOT_PEER_MERU                                = 7,    \r
 356         HT_IOT_PEER_MARVELL                     = 8,\r
 357         HT_IOT_PEER_REALTEK_SOFTAP      = 9,// peer is RealTek SOFT_AP, by Bohn, 2009.12.17\r
 358         HT_IOT_PEER_SELF_SOFTAP                 = 10, // Self is SoftAP\r
 359         HT_IOT_PEER_AIRGO                               = 11,\r
 360         HT_IOT_PEER_INTEL                               = 12, \r
 361         HT_IOT_PEER_RTK_APCLIENT                = 13, \r
 362         HT_IOT_PEER_REALTEK_81XX                = 14,   \r
 363         HT_IOT_PEER_REALTEK_WOW                 = 15,   \r
 364         HT_IOT_PEER_MAX                                 = 16\r
 365 }HT_IOT_PEER_E, *PHTIOT_PEER_E;\r
 366 #endif//#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
 367 \r
 368 #define         DM_Type_ByFW                    0\r
 369 #define         DM_Type_ByDriver                1\r
 370 \r
 371 //\r
 372 // Declare for common info\r
 373 //\r
 374 #define MAX_PATH_NUM_92CS               2\r
 375 #define MAX_PATH_NUM_8188E              1\r
 376 #define MAX_PATH_NUM_8192E              2\r
 377 #define MAX_PATH_NUM_8723B              1\r
 378 #define MAX_PATH_NUM_8812A              2\r
 379 #define MAX_PATH_NUM_8821A              1\r
 380 #define MAX_PATH_NUM_8814A              4\r
 381 #define MAX_PATH_NUM_8822B              2\r
 382 \r
 383 \r
 384 #define IQK_THRESHOLD                   8\r
 385 #define DPK_THRESHOLD                   4\r
 386 \r
 387 typedef struct _ODM_Phy_Status_Info_\r
 388 {\r
 389         //\r
 390         // Be care, if you want to add any element please insert between \r
 391         // RxPWDBAll & SignalStrength.\r
 392         //\r
 393 #if (DM_ODM_SUPPORT_TYPE &  (ODM_WIN))\r
 394         u4Byte          RxPWDBAll;      \r
 395 #else\r
 396         u1Byte          RxPWDBAll;      \r
 397 #endif\r
 398 \r
 399         u1Byte          SignalQuality;                  // in 0-100 index. \r
 400         s1Byte          RxMIMOSignalQuality[4]; //per-path's EVM\r
 401         u1Byte          RxMIMOEVMdbm[4];                //per-path's EVM dbm\r
 402 \r
 403         u1Byte          RxMIMOSignalStrength[4];// in 0~100 index\r
 404 \r
 405         u2Byte          Cfo_short[4];                   // per-path's Cfo_short\r
 406         u2Byte          Cfo_tail[4];                    // per-path's Cfo_tail\r
 407         \r
 408 #if (DM_ODM_SUPPORT_TYPE &  (ODM_WIN|ODM_CE))\r
 409         s1Byte          RxPower;                                // in dBm Translate from PWdB\r
 410         s1Byte          RecvSignalPower;                // Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures.\r
 411         u1Byte          BTRxRSSIPercentage;     \r
 412         u1Byte          SignalStrength;                 // in 0-100 index.\r
 413  \r
 414         s1Byte          RxPwr[4];                               //per-path's pwdb\r
 415 #endif\r
 416         u1Byte          RxSNR[4];                               //per-path's SNR        \r
 417         u1Byte          BandWidth;\r
 418         u1Byte          btCoexPwrAdjust;\r
 419 }ODM_PHY_INFO_T,*PODM_PHY_INFO_T;\r
 420 \r
 421 \r
 422 typedef struct _ODM_Per_Pkt_Info_\r
 423 {\r
 424         //u1Byte                Rate;   \r
 425         u1Byte          DataRate;\r
 426         u1Byte          StationID;\r
 427         BOOLEAN         bPacketMatchBSSID;\r
 428         BOOLEAN         bPacketToSelf;\r
 429         BOOLEAN         bPacketBeacon;\r
 430         BOOLEAN         bToSelf;\r
 431 }ODM_PACKET_INFO_T,*PODM_PACKET_INFO_T;\r
 432 \r
 433 \r
 434 typedef struct _ODM_Phy_Dbg_Info_\r
 435 {\r
 436         //ODM Write,debug info\r
 437         s1Byte          RxSNRdB[4];\r
 438         u4Byte          NumQryPhyStatus;\r
 439         u4Byte          NumQryPhyStatusCCK;\r
 440         u4Byte          NumQryPhyStatusOFDM;\r
 441         u1Byte          NumQryBeaconPkt;\r
 442         //Others\r
 443         s4Byte          RxEVM[4];       \r
 444         \r
 445 }ODM_PHY_DBG_INFO_T;\r
 446 \r
 447 \r
 448 typedef struct _ODM_Mac_Status_Info_\r
 449 {\r
 450         u1Byte  test;\r
 451         \r
 452 }ODM_MAC_INFO;\r
 453 \r
 454 \r
 455 typedef enum tag_Dynamic_ODM_Support_Ability_Type\r
 456 {\r
 457         // BB Team\r
 458         ODM_DIG                         = 0x00000001,\r
 459         ODM_HIGH_POWER          = 0x00000002,\r
 460         ODM_CCK_CCA_TH          = 0x00000004,\r
 461         ODM_FA_STATISTICS               = 0x00000008,\r
 462         ODM_RAMASK                      = 0x00000010,\r
 463         ODM_RSSI_MONITOR                = 0x00000020,\r
 464         ODM_SW_ANTDIV           = 0x00000040,\r
 465         ODM_HW_ANTDIV           = 0x00000080,\r
 466         ODM_BB_PWRSV                    = 0x00000100,\r
 467         ODM_2TPATHDIV                   = 0x00000200,\r
 468         ODM_1TPATHDIV                   = 0x00000400,\r
 469         ODM_PSD2AFH                     = 0x00000800\r
 470 }ODM_Ability_E;\r
 471 \r
 472 //\r
 473 // 2011/20/20 MH For MP driver RT_WLAN_STA =  STA_INFO_T\r
 474 // Please declare below ODM relative info in your STA info structure.\r
 475 //\r
 476 #if 1\r
 477 typedef         struct _ODM_STA_INFO{\r
 478         // Driver Write\r
 479         BOOLEAN         bUsed;                          // record the sta status link or not?\r
 480         //u1Byte                WirelessMode;           // \r
 481         u1Byte          IOTPeer;                        // Enum value.  HT_IOT_PEER_E\r
 482 \r
 483         // ODM Write\r
 484         //1 PHY_STATUS_INFO\r
 485         u1Byte          RSSI_Path[4];           // \r
 486         u1Byte          RSSI_Ave;\r
 487         u1Byte          RXEVM[4];\r
 488         u1Byte          RXSNR[4];\r
 489 \r
 490         // ODM Write\r
 491         //1 TX_INFO (may changed by IC)\r
 492         //TX_INFO_T             pTxInfo;                                // Define in IC folder. Move lower layer.\r
 493 #if 0\r
 494         u1Byte          ANTSEL_A;                       //in Jagar: 4bit; others: 2bit\r
 495         u1Byte          ANTSEL_B;                       //in Jagar: 4bit; others: 2bit\r
 496         u1Byte          ANTSEL_C;                       //only in Jagar: 4bit\r
 497         u1Byte          ANTSEL_D;                       //only in Jagar: 4bit\r
 498         u1Byte          TX_ANTL;                        //not in Jagar: 2bit\r
 499         u1Byte          TX_ANT_HT;                      //not in Jagar: 2bit\r
 500         u1Byte          TX_ANT_CCK;                     //not in Jagar: 2bit\r
 501         u1Byte          TXAGC_A;                        //not in Jagar: 4bit\r
 502         u1Byte          TXAGC_B;                        //not in Jagar: 4bit\r
 503         u1Byte          TXPWR_OFFSET;           //only in Jagar: 3bit\r
 504         u1Byte          TX_ANT;                         //only in Jagar: 4bit for TX_ANTL/TX_ANTHT/TX_ANT_CCK\r
 505 #endif\r
 506 \r
 507         //\r
 508         //      Please use compile flag to disabe the strcutrue for other IC except 88E.\r
 509         //      Move To lower layer.\r
 510         //\r
 511         // ODM Write Wilson will handle this part(said by Luke.Lee)\r
 512         //TX_RPT_T              pTxRpt;                         // Define in IC folder. Move lower layer.\r
 513 #if 0   \r
 514         //1 For 88E RA (don't redefine the naming)\r
 515         u1Byte          rate_id;\r
 516         u1Byte          rate_SGI;\r
 517         u1Byte          rssi_sta_ra;\v\r
 518 \r
 519         u1Byte          SGI_enable;\r
 520         u1Byte          Decision_rate;\r
 521         u1Byte          Pre_rate;\r
 522         u1Byte          Active;\r
 523 \r
 524         // Driver write Wilson handle.\r
 525         //1 TX_RPT (don't redefine the naming)\r
 526         u2Byte          RTY[4];                         // ???\r
 527         u2Byte          TOTAL;                          // ???\r
 528         u2Byte          DROP;                           // ???\r
 529         //\r
 530         // Please use compile flag to disabe the strcutrue for other IC except 88E.\r
 531         //\r
 532 #endif\r
 533 \r
 534 }ODM_STA_INFO_T, *PODM_STA_INFO_T;\r
 535 #endif\r
 536 \r
 537 //\r
 538 // 2011/10/20 MH Define Common info enum for all team.\r
 539 //\r
 540 typedef enum _ODM_Common_Info_Definition\r
 541 {\r
 542 //-------------REMOVED CASE-----------//\r
 543         //ODM_CMNINFO_CCK_HP,\r
 544         //ODM_CMNINFO_RFPATH_ENABLE,            // Define as ODM write???       \r
 545         //ODM_CMNINFO_BT_COEXIST,                               // ODM_BT_COEXIST_E\r
 546         //ODM_CMNINFO_OP_MODE,                          // ODM_OPERATION_MODE_E\r
 547 //-------------REMOVED CASE-----------//\r
 548 \r
 549         //\r
 550         // Fixed value:\r
 551         //\r
 552 \r
 553         //-----------HOOK BEFORE REG INIT-----------//\r
 554         ODM_CMNINFO_PLATFORM = 0,\r
 555         ODM_CMNINFO_ABILITY,                                    // ODM_ABILITY_E\r
 556         ODM_CMNINFO_INTERFACE,                          // ODM_INTERFACE_E\r
 557         ODM_CMNINFO_MP_TEST_CHIP,\r
 558         ODM_CMNINFO_IC_TYPE,                                    // ODM_IC_TYPE_E\r
 559         ODM_CMNINFO_CUT_VER,                                    // ODM_CUT_VERSION_E\r
 560         ODM_CMNINFO_FAB_VER,                                    // ODM_FAB_E\r
 561         ODM_CMNINFO_RF_TYPE,                                    // ODM_RF_PATH_E or ODM_RF_TYPE_E?\r
 562         ODM_CMNINFO_RFE_TYPE, \r
 563         ODM_CMNINFO_BOARD_TYPE,                         // ODM_BOARD_TYPE_E\r
 564         ODM_CMNINFO_PACKAGE_TYPE,\r
 565         ODM_CMNINFO_EXT_LNA,                                    // TRUE\r
 566         ODM_CMNINFO_5G_EXT_LNA, \r
 567         ODM_CMNINFO_EXT_PA,\r
 568         ODM_CMNINFO_5G_EXT_PA,\r
 569         ODM_CMNINFO_GPA,\r
 570         ODM_CMNINFO_APA,\r
 571         ODM_CMNINFO_GLNA,\r
 572         ODM_CMNINFO_ALNA,\r
 573         ODM_CMNINFO_EXT_TRSW,\r
 574         ODM_CMNINFO_PATCH_ID,                           //CUSTOMER ID\r
 575         ODM_CMNINFO_BINHCT_TEST,\r
 576         ODM_CMNINFO_BWIFI_TEST,\r
 577         ODM_CMNINFO_SMART_CONCURRENT,\r
 578         ODM_CMNINFO_DOMAIN_CODE_2G,\r
 579         ODM_CMNINFO_DOMAIN_CODE_5G,\r
 580         ODM_CMNINFO_IQKFWOFFLOAD,\r
 581         //-----------HOOK BEFORE REG INIT-----------//  \r
 582 \r
 583 \r
 584         //\r
 585         // Dynamic value:\r
 586         //\r
 587 //--------- POINTER REFERENCE-----------//\r
 588         ODM_CMNINFO_MAC_PHY_MODE,                       // ODM_MAC_PHY_MODE_E\r
 589         ODM_CMNINFO_TX_UNI,\r
 590         ODM_CMNINFO_RX_UNI,\r
 591         ODM_CMNINFO_WM_MODE,                            // ODM_WIRELESS_MODE_E\r
 592         ODM_CMNINFO_BAND,                                       // ODM_BAND_TYPE_E\r
 593         ODM_CMNINFO_SEC_CHNL_OFFSET,            // ODM_SEC_CHNL_OFFSET_E\r
 594         ODM_CMNINFO_SEC_MODE,                           // ODM_SECURITY_E\r
 595         ODM_CMNINFO_BW,                                         // ODM_BW_E\r
 596         ODM_CMNINFO_CHNL,\r
 597         ODM_CMNINFO_FORCED_RATE,\r
 598         \r
 599         ODM_CMNINFO_DMSP_GET_VALUE,\r
 600         ODM_CMNINFO_BUDDY_ADAPTOR,\r
 601         ODM_CMNINFO_DMSP_IS_MASTER,\r
 602         ODM_CMNINFO_SCAN,\r
 603         ODM_CMNINFO_POWER_SAVING,\r
 604         ODM_CMNINFO_ONE_PATH_CCA,                       // ODM_CCA_PATH_E\r
 605         ODM_CMNINFO_DRV_STOP,\r
 606         ODM_CMNINFO_PNP_IN,\r
 607         ODM_CMNINFO_INIT_ON,\r
 608         ODM_CMNINFO_ANT_TEST,\r
 609         ODM_CMNINFO_NET_CLOSED,\r
 610         //ODM_CMNINFO_RTSTA_AID,                                // For win driver only?\r
 611         ODM_CMNINFO_FORCED_IGI_LB,\r
 612         ODM_CMNINFO_P2P_LINK,\r
 613         ODM_CMNINFO_FCS_MODE,\r
 614         ODM_CMNINFO_IS1ANTENNA,\r
 615         ODM_CMNINFO_RFDEFAULTPATH,\r
 616 //--------- POINTER REFERENCE-----------//\r
 617 \r
 618 //------------CALL BY VALUE-------------//\r
 619         ODM_CMNINFO_WIFI_DIRECT,\r
 620         ODM_CMNINFO_WIFI_DISPLAY,\r
 621         ODM_CMNINFO_LINK_IN_PROGRESS,                   \r
 622         ODM_CMNINFO_LINK,\r
 623         ODM_CMNINFO_STATION_STATE,\r
 624         ODM_CMNINFO_RSSI_MIN,\r
 625         ODM_CMNINFO_DBG_COMP,                           // u8Byte\r
 626         ODM_CMNINFO_DBG_LEVEL,                          // u4Byte\r
 627         ODM_CMNINFO_RA_THRESHOLD_HIGH,          // u1Byte\r
 628         ODM_CMNINFO_RA_THRESHOLD_LOW,           // u1Byte\r
 629         ODM_CMNINFO_RF_ANTENNA_TYPE,            // u1Byte\r
 630         ODM_CMNINFO_BT_ENABLED,\r
 631         ODM_CMNINFO_BT_HS_CONNECT_PROCESS,\r
 632         ODM_CMNINFO_BT_HS_RSSI,\r
 633         ODM_CMNINFO_BT_OPERATION,\r
 634         ODM_CMNINFO_BT_LIMITED_DIG,                                     //Need to Limited Dig or not\r
 635         ODM_CMNINFO_BT_DISABLE_EDCA,\r
 636 #if(DM_ODM_SUPPORT_TYPE & ODM_AP)               // for repeater mode add by YuChen 2014.06.\r
 637 #ifdef UNIVERSAL_REPEATER\r
 638         ODM_CMNINFO_VXD_LINK,\r
 639 #endif\r
 640 #endif\r
 641         \r
 642 //------------CALL BY VALUE-------------//\r
 643 \r
 644         //\r
 645         // Dynamic ptr array hook itms.\r
 646         //\r
 647         ODM_CMNINFO_STA_STATUS,\r
 648         ODM_CMNINFO_PHY_STATUS,\r
 649         ODM_CMNINFO_MAC_STATUS,\r
 650         \r
 651         ODM_CMNINFO_MAX,\r
 652 \r
 653 \r
 654 }ODM_CMNINFO_E;\r
 655 \r
 656 //\r
 657 // 2011/10/20 MH Define ODM support ability.  ODM_CMNINFO_ABILITY\r
 658 //\r
 659 typedef enum _ODM_Support_Ability_Definition\r
 660 {\r
 661         //\r
 662         // BB ODM section BIT 0-19\r
 663         //\r
 664         ODM_BB_DIG                                      = BIT0,\r
 665         ODM_BB_RA_MASK                          = BIT1,\r
 666         ODM_BB_DYNAMIC_TXPWR            = BIT2,\r
 667         ODM_BB_FA_CNT                                   = BIT3,\r
 668         ODM_BB_RSSI_MONITOR                     = BIT4,\r
 669         ODM_BB_CCK_PD                                   = BIT5,\r
 670         ODM_BB_ANT_DIV                          = BIT6,\r
 671         ODM_BB_PWR_SAVE                         = BIT7,\r
 672         ODM_BB_PWR_TRAIN                                = BIT8,\r
 673         ODM_BB_RATE_ADAPTIVE                    = BIT9,\r
 674         ODM_BB_PATH_DIV                         = BIT10,\r
 675         ODM_BB_PSD                                      = BIT11,\r
 676         ODM_BB_RXHP                                     = BIT12,\r
 677         ODM_BB_ADAPTIVITY                               = BIT13,\r
 678         ODM_BB_CFO_TRACKING                     = BIT14,\r
 679         ODM_BB_NHM_CNT                          = BIT15,\r
 680         ODM_BB_PRIMARY_CCA                      = BIT16,\r
 681         \r
 682         //\r
 683         // MAC DM section BIT 20-23\r
 684         //\r
 685         ODM_MAC_EDCA_TURBO                      = BIT20,\r
 686         ODM_MAC_EARLY_MODE                      = BIT21,\r
 687         \r
 688         //\r
 689         // RF ODM section BIT 24-31\r
 690         //\r
 691         ODM_RF_TX_PWR_TRACK                     = BIT24,\r
 692         ODM_RF_RX_GAIN_TRACK                    = BIT25,\r
 693         ODM_RF_CALIBRATION                              = BIT26,\r
 694         \r
 695 }ODM_ABILITY_E;\r
 696 \r
 697 //      ODM_CMNINFO_INTERFACE\r
 698 typedef enum tag_ODM_Support_Interface_Definition\r
 699 {\r
 700         ODM_ITRF_PCIE   =       0x1,\r
 701         ODM_ITRF_USB    =       0x2,\r
 702         ODM_ITRF_SDIO   =       0x4,\r
 703         ODM_ITRF_ALL    =       0x7,\r
 704 }ODM_INTERFACE_E;\r
 705 \r
 706 // ODM_CMNINFO_IC_TYPE\r
 707 typedef enum tag_ODM_Support_IC_Type_Definition\r
 708 {\r
 709         ODM_RTL8192S    =       BIT0,\r
 710         ODM_RTL8192C    =       BIT1,\r
 711         ODM_RTL8192D    =       BIT2,\r
 712         ODM_RTL8723A    =       BIT3,\r
 713         ODM_RTL8188E    =       BIT4,\r
 714         ODM_RTL8812     =       BIT5,\r
 715         ODM_RTL8821     =       BIT6,\r
 716         ODM_RTL8192E    =       BIT7,   \r
 717         ODM_RTL8723B    =       BIT8,\r
 718         ODM_RTL8814A    =       BIT9,   \r
 719         ODM_RTL8881A    =       BIT10,\r
 720         ODM_RTL8821B    =       BIT11,\r
 721         ODM_RTL8822B    =       BIT12,\r
 722         ODM_RTL8703B    =       BIT13\r
 723 }ODM_IC_TYPE_E;\r
 724 \r
 725 #define ODM_IC_11N_SERIES               (ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8703B)\r
 726 #define ODM_IC_11AC_SERIES              (ODM_RTL8812|ODM_RTL8821|ODM_RTL8814A|ODM_RTL8881A|ODM_RTL8821B|ODM_RTL8822B)\r
 727 \r
 728 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
 729 \r
 730 #ifdef RTK_AC_SUPPORT\r
 731 #define ODM_IC_11AC_SERIES_SUPPORT              1\r
 732 #else\r
 733 #define ODM_IC_11AC_SERIES_SUPPORT              0\r
 734 #endif\r
 735 \r
 736 #define ODM_IC_11N_SERIES_SUPPORT                       1\r
 737 #define ODM_CONFIG_BT_COEXIST                           0\r
 738 \r
 739 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 740 \r
 741 #define ODM_IC_11AC_SERIES_SUPPORT              1\r
 742 #define ODM_IC_11N_SERIES_SUPPORT                       1\r
 743 #define ODM_CONFIG_BT_COEXIST                           1\r
 744 \r
 745 #else \r
 746 \r
 747 #if((RTL8192C_SUPPORT == 1) || (RTL8192D_SUPPORT == 1) || (RTL8723A_SUPPORT == 1) || (RTL8188E_SUPPORT == 1) ||\\r
 748 (RTL8723B_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8195A_SUPPORT == 1))\r
 749 #define ODM_IC_11N_SERIES_SUPPORT                       1\r
 750 #define ODM_IC_11AC_SERIES_SUPPORT              0\r
 751 #else\r
 752 #define ODM_IC_11N_SERIES_SUPPORT                       0\r
 753 #define ODM_IC_11AC_SERIES_SUPPORT              1\r
 754 #endif\r
 755 \r
 756 #ifdef CONFIG_BT_COEXIST\r
 757 #define ODM_CONFIG_BT_COEXIST                           1\r
 758 #else\r
 759 #define ODM_CONFIG_BT_COEXIST                           0\r
 760 #endif\r
 761 \r
 762 #endif\r
 763 \r
 764 \r
 765 //ODM_CMNINFO_CUT_VER\r
 766 typedef enum tag_ODM_Cut_Version_Definition\r
 767 {\r
 768         ODM_CUT_A               =       0,\r
 769         ODM_CUT_B               =       1,\r
 770         ODM_CUT_C               =       2,\r
 771         ODM_CUT_D               =       3,\r
 772         ODM_CUT_E               =       4,\r
 773         ODM_CUT_F               =       5,\r
 774 \r
 775         ODM_CUT_I               =       8,\r
 776         ODM_CUT_J               =       9,\r
 777         ODM_CUT_K               =       10,     \r
 778         ODM_CUT_TEST    =       15,\r
 779 }ODM_CUT_VERSION_E;\r
 780 \r
 781 // ODM_CMNINFO_FAB_VER\r
 782 typedef enum tag_ODM_Fab_Version_Definition\r
 783 {\r
 784         ODM_TSMC        =       0,\r
 785         ODM_UMC         =       1,\r
 786 }ODM_FAB_E;\r
 787 \r
 788 // ODM_CMNINFO_RF_TYPE\r
 789 //\r
 790 // For example 1T2R (A+AB = BIT0|BIT4|BIT5)\r
 791 //\r
 792 typedef enum tag_ODM_RF_Path_Bit_Definition\r
 793 {\r
 794         ODM_RF_TX_A     =       BIT0,\r
 795         ODM_RF_TX_B     =       BIT1,\r
 796         ODM_RF_TX_C     =       BIT2,\r
 797         ODM_RF_TX_D     =       BIT3,\r
 798         ODM_RF_RX_A     =       BIT4,\r
 799         ODM_RF_RX_B     =       BIT5,\r
 800         ODM_RF_RX_C     =       BIT6,\r
 801         ODM_RF_RX_D     =       BIT7,\r
 802 }ODM_RF_PATH_E;\r
 803 \r
 804 \r
 805 typedef enum tag_ODM_RF_Type_Definition\r
 806 {\r
 807         ODM_1T1R        =       0,\r
 808         ODM_1T2R        =       1,\r
 809         ODM_2T2R        =       2,\r
 810         ODM_2T3R        =       3,\r
 811         ODM_2T4R        =       4,\r
 812         ODM_3T3R        =       5,\r
 813         ODM_3T4R        =       6,\r
 814         ODM_4T4R        =       7,\r
 815 }ODM_RF_TYPE_E;\r
 816 \r
 817 \r
 818 //\r
 819 // ODM Dynamic common info value definition\r
 820 //\r
 821 \r
 822 //typedef enum _MACPHY_MODE_8192D{\r
 823 //      SINGLEMAC_SINGLEPHY,\r
 824 //      DUALMAC_DUALPHY,\r
 825 //      DUALMAC_SINGLEPHY,\r
 826 //}MACPHY_MODE_8192D,*PMACPHY_MODE_8192D;\r
 827 // Above is the original define in MP driver. Please use the same define. THX.\r
 828 typedef enum tag_ODM_MAC_PHY_Mode_Definition\r
 829 {\r
 830         ODM_SMSP        = 0,\r
 831         ODM_DMSP        = 1,\r
 832         ODM_DMDP        = 2,\r
 833 }ODM_MAC_PHY_MODE_E;\r
 834 \r
 835 \r
 836 typedef enum tag_BT_Coexist_Definition\r
 837 {       \r
 838         ODM_BT_BUSY             = 1,\r
 839         ODM_BT_ON                       = 2,\r
 840         ODM_BT_OFF              = 3,\r
 841         ODM_BT_NONE             = 4,\r
 842 }ODM_BT_COEXIST_E;\r
 843 \r
 844 // ODM_CMNINFO_OP_MODE\r
 845 typedef enum tag_Operation_Mode_Definition\r
 846 {\r
 847         ODM_NO_LINK             = BIT0,\r
 848         ODM_LINK                        = BIT1,\r
 849         ODM_SCAN                        = BIT2,\r
 850         ODM_POWERSAVE   = BIT3,\r
 851         ODM_AP_MODE             = BIT4,\r
 852         ODM_CLIENT_MODE = BIT5,\r
 853         ODM_AD_HOC              = BIT6,\r
 854         ODM_WIFI_DIRECT = BIT7,\r
 855         ODM_WIFI_DISPLAY        = BIT8,\r
 856 }ODM_OPERATION_MODE_E;\r
 857 \r
 858 // ODM_CMNINFO_WM_MODE\r
 859 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_CE))\r
 860 typedef enum tag_Wireless_Mode_Definition\r
 861 {\r
 862         ODM_WM_UNKNOW     = 0x0,\r
 863         ODM_WM_B                  = BIT0,\r
 864         ODM_WM_G                  = BIT1,\r
 865         ODM_WM_A                  = BIT2,\r
 866         ODM_WM_N24G           = BIT3,\r
 867         ODM_WM_N5G             = BIT4,\r
 868         ODM_WM_AUTO           = BIT5,\r
 869         ODM_WM_AC                = BIT6,\r
 870 }ODM_WIRELESS_MODE_E;\r
 871 #else\r
 872 typedef enum tag_Wireless_Mode_Definition\r
 873 {\r
 874         ODM_WM_UNKNOWN  = 0x00,\r
 875         ODM_WM_A                        = BIT0,\r
 876         ODM_WM_B                        = BIT1,\r
 877         ODM_WM_G                        = BIT2,\r
 878         ODM_WM_AUTO             = BIT3,\r
 879         ODM_WM_N24G             = BIT4,\r
 880         ODM_WM_N5G              = BIT5,\r
 881         ODM_WM_AC_5G    = BIT6,\r
 882         ODM_WM_AC_24G   = BIT7,\r
 883         ODM_WM_AC_ONLY          = BIT8,\r
 884         ODM_WM_MAX              = BIT9\r
 885 }ODM_WIRELESS_MODE_E;\r
 886 #endif\r
 887 \r
 888 // ODM_CMNINFO_BAND\r
 889 typedef enum tag_Band_Type_Definition\r
 890 {\r
 891     ODM_BAND_2_4G = 0,\r
 892     ODM_BAND_5G,\r
 893     ODM_BAND_ON_BOTH,\r
 894     ODM_BANDMAX\r
 895 \r
 896 }ODM_BAND_TYPE_E;\r
 897 \r
 898 // ODM_CMNINFO_SEC_CHNL_OFFSET\r
 899 typedef enum tag_Secondary_Channel_Offset_Definition\r
 900 {\r
 901         ODM_DONT_CARE   = 0,\r
 902         ODM_BELOW               = 1,\r
 903         ODM_ABOVE                       = 2\r
 904 }ODM_SEC_CHNL_OFFSET_E;\r
 905 \r
 906 // ODM_CMNINFO_SEC_MODE\r
 907 typedef enum tag_Security_Definition\r
 908 {\r
 909         ODM_SEC_OPEN                    = 0,\r
 910         ODM_SEC_WEP40           = 1,\r
 911         ODM_SEC_TKIP                    = 2,\r
 912         ODM_SEC_RESERVE                 = 3,\r
 913         ODM_SEC_AESCCMP                 = 4,\r
 914         ODM_SEC_WEP104          = 5,\r
 915         ODM_WEP_WPA_MIXED    = 6, // WEP + WPA\r
 916         ODM_SEC_SMS4                    = 7,\r
 917 }ODM_SECURITY_E;\r
 918 \r
 919 // ODM_CMNINFO_BW\r
 920 typedef enum tag_Bandwidth_Definition\r
 921 {       \r
 922         ODM_BW20M               = 0,\r
 923         ODM_BW40M               = 1,\r
 924         ODM_BW80M               = 2,\r
 925         ODM_BW160M              = 3,\r
 926         ODM_BW10M               = 4,\r
 927 }ODM_BW_E;\r
 928 \r
 929 \r
 930 // ODM_CMNINFO_BOARD_TYPE\r
 931 // For non-AC-series IC , ODM_BOARD_5G_EXT_PA and ODM_BOARD_5G_EXT_LNA are ignored\r
 932 // For AC-series IC, external PA & LNA can be indivisuallly added on 2.4G and/or 5G \r
 933 typedef enum tag_Board_Definition\r
 934 {\r
 935     ODM_BOARD_DEFAULT   = 0,      // The DEFAULT case.\r
 936     ODM_BOARD_MINICARD  = BIT(0), // 0 = non-mini card, 1= mini card.\r
 937     ODM_BOARD_SLIM      = BIT(1), // 0 = non-slim card, 1 = slim card\r
 938     ODM_BOARD_BT        = BIT(2), // 0 = without BT card, 1 = with BT\r
 939     ODM_BOARD_EXT_PA    = BIT(3), // 0 = no 2G ext-PA, 1 = existing 2G ext-PA\r
 940     ODM_BOARD_EXT_LNA   = BIT(4), // 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA\r
 941     ODM_BOARD_EXT_TRSW  = BIT(5), // 0 = no ext-TRSW, 1 = existing ext-TRSW\r
 942     ODM_BOARD_EXT_PA_5G = BIT(6), // 0 = no 5G ext-PA, 1 = existing 5G ext-PA\r
 943     ODM_BOARD_EXT_LNA_5G= BIT(7), // 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA\r
 944 }ODM_BOARD_TYPE_E;\r
 945 \r
 946 typedef enum tag_ODM_Package_Definition\r
 947 {\r
 948     ODM_PACKAGE_DEFAULT          = 0,     \r
 949     ODM_PACKAGE_QFN68        = BIT(0), \r
 950     ODM_PACKAGE_TFBGA90      = BIT(1), \r
 951     ODM_PACKAGE_TFBGA79      = BIT(2),  \r
 952 }ODM_Package_TYPE_E;\r
 953 \r
 954 typedef enum tag_ODM_TYPE_GPA_Definition\r
 955 {\r
 956     TYPE_GPA0 = 0,        \r
 957     TYPE_GPA1 = BIT(1)|BIT(0)\r
 958 }ODM_TYPE_GPA_E;\r
 959 \r
 960 typedef enum tag_ODM_TYPE_APA_Definition\r
 961 {\r
 962     TYPE_APA0 = 0,        \r
 963     TYPE_APA1 = BIT(1)|BIT(0)\r
 964 }ODM_TYPE_APA_E;\r
 965 \r
 966 typedef enum tag_ODM_TYPE_GLNA_Definition\r
 967 {\r
 968     TYPE_GLNA0 = 0,       \r
 969     TYPE_GLNA1 = BIT(2)|BIT(0),\r
 970     TYPE_GLNA2 = BIT(3)|BIT(1),\r
 971     TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)\r
 972 }ODM_TYPE_GLNA_E;\r
 973 \r
 974 typedef enum tag_ODM_TYPE_ALNA_Definition\r
 975 {\r
 976     TYPE_ALNA0 = 0,       \r
 977     TYPE_ALNA1 = BIT(2)|BIT(0),\r
 978     TYPE_ALNA2 = BIT(3)|BIT(1),\r
 979     TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)\r
 980 }ODM_TYPE_ALNA_E;\r
 981 \r
 982 // ODM_CMNINFO_ONE_PATH_CCA\r
 983 typedef enum tag_CCA_Path\r
 984 {\r
 985         ODM_CCA_2R                      = 0,\r
 986         ODM_CCA_1R_A            = 1,\r
 987         ODM_CCA_1R_B            = 2,\r
 988 }ODM_CCA_PATH_E;\r
 989 \r
 990 \r
 991 typedef struct _ODM_RA_Info_\r
 992 {\r
 993         u1Byte RateID;\r
 994         u4Byte RateMask;\r
 995         u4Byte RAUseRate;\r
 996         u1Byte RateSGI;\r
 997         u1Byte RssiStaRA;\r
 998         u1Byte PreRssiStaRA;\r
 999         u1Byte SGIEnable;\r
1000         u1Byte DecisionRate;\r
1001         u1Byte PreRate;\r
1002         u1Byte HighestRate;\r
1003         u1Byte LowestRate;\r
1004         u4Byte NscUp;\r
1005         u4Byte NscDown;\r
1006         u2Byte RTY[5];\r
1007         u4Byte TOTAL;\r
1008         u2Byte DROP;\r
1009         u1Byte Active;\r
1010         u2Byte RptTime;\r
1011         u1Byte RAWaitingCounter;\r
1012         u1Byte RAPendingCounter;        \r
1013 #if 1 //POWER_TRAINING_ACTIVE == 1 // For compile  pass only~!\r
1014         u1Byte PTActive;  // on or off\r
1015         u1Byte PTTryState;  // 0 trying state, 1 for decision state\r
1016         u1Byte PTStage;  // 0~6\r
1017         u1Byte PTStopCount; //Stop PT counter\r
1018         u1Byte PTPreRate;  // if rate change do PT\r
1019         u1Byte PTPreRssi; // if RSSI change 5% do PT\r
1020         u1Byte PTModeSS;  // decide whitch rate should do PT\r
1021         u1Byte RAstage;  // StageRA, decide how many times RA will be done between PT\r
1022         u1Byte PTSmoothFactor;\r
1023 #endif\r
1024 } ODM_RA_INFO_T,*PODM_RA_INFO_T;\r
1025 \r
1026 //Remove struct  PATHDIV_PARA to odm_PathDiv.h \r
1027 \r
1028 //move to PowerTracking.h by YuChen\r
1029 \r
1030 //\r
1031 // ODM Dynamic common info value definition\r
1032 //\r
1033 \r
1034 typedef struct _FAST_ANTENNA_TRAINNING_\r
1035 {\r
1036         u1Byte  Bssid[6];\r
1037         u1Byte  antsel_rx_keep_0;\r
1038         u1Byte  antsel_rx_keep_1;\r
1039         u1Byte  antsel_rx_keep_2;\r
1040         u1Byte  antsel_rx_keep_3;\r
1041         u4Byte  antSumRSSI[7];\r
1042         u4Byte  antRSSIcnt[7];\r
1043         u4Byte  antAveRSSI[7];\r
1044         u1Byte  FAT_State;\r
1045         u4Byte  TrainIdx;\r
1046         u1Byte  antsel_a[ODM_ASSOCIATE_ENTRY_NUM];\r
1047         u1Byte  antsel_b[ODM_ASSOCIATE_ENTRY_NUM];\r
1048         u1Byte  antsel_c[ODM_ASSOCIATE_ENTRY_NUM];\r
1049         u4Byte  MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];\r
1050         u4Byte  AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];\r
1051         u4Byte  MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];\r
1052         u4Byte  AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];\r
1053         u1Byte  RxIdleAnt;\r
1054         BOOLEAN bBecomeLinked;\r
1055         u4Byte  MinMaxRSSI;\r
1056         u1Byte  idx_AntDiv_counter_2G;\r
1057         u1Byte  idx_AntDiv_counter_5G;\r
1058         u4Byte  AntDiv_2G_5G;\r
1059         u4Byte    CCK_counter_main;\r
1060         u4Byte    CCK_counter_aux;      \r
1061         u4Byte    OFDM_counter_main;\r
1062         u4Byte    OFDM_counter_aux;     \r
1063 \r
1064 \r
1065         u4Byte    CCK_CtrlFrame_Cnt_main;\r
1066         u4Byte    CCK_CtrlFrame_Cnt_aux;\r
1067         u4Byte    OFDM_CtrlFrame_Cnt_main;\r
1068         u4Byte    OFDM_CtrlFrame_Cnt_aux;\r
1069         u4Byte  MainAnt_CtrlFrame_Sum;\r
1070         u4Byte  AuxAnt_CtrlFrame_Sum;\r
1071         u4Byte  MainAnt_CtrlFrame_Cnt;\r
1072         u4Byte  AuxAnt_CtrlFrame_Cnt;\r
1073 \r
1074 }FAT_T,*pFAT_T;\r
1075 \r
1076 typedef enum _FAT_STATE\r
1077 {\r
1078         FAT_NORMAL_STATE                        = 0,\r
1079         FAT_TRAINING_STATE              = 1,\r
1080 }FAT_STATE_E, *PFAT_STATE_E;\r
1081 \r
1082 typedef enum _ANT_DIV_TYPE\r
1083 {\r
1084         NO_ANTDIV                       = 0xFF, \r
1085         CG_TRX_HW_ANTDIV                = 0x01,\r
1086         CGCS_RX_HW_ANTDIV       = 0x02,\r
1087         FIXED_HW_ANTDIV         = 0x03,\r
1088         CG_TRX_SMART_ANTDIV     = 0x04,\r
1089         CGCS_RX_SW_ANTDIV       = 0x05,\r
1090         S0S1_SW_ANTDIV          = 0x06 //8723B intrnal switch S0 S1\r
1091 }ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E;\r
1092 \r
1093 \r
1094 typedef struct _ODM_PATH_DIVERSITY_\r
1095 {\r
1096         u1Byte  RespTxPath;\r
1097         u1Byte  PathSel[ODM_ASSOCIATE_ENTRY_NUM];\r
1098         u4Byte  PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM];\r
1099         u4Byte  PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM];\r
1100         u4Byte  PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM];\r
1101         u4Byte  PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM];\r
1102 }PATHDIV_T, *pPATHDIV_T;\r
1103 \r
1104 \r
1105 typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE{\r
1106         PHY_REG_PG_RELATIVE_VALUE = 0,\r
1107         PHY_REG_PG_EXACT_VALUE = 1\r
1108 } PHY_REG_PG_TYPE;\r
1109 \r
1110 \r
1111 //\r
1112 // Antenna detection information from single tone mechanism, added by Roger, 2012.11.27.\r
1113 //\r
1114 typedef struct _ANT_DETECTED_INFO{\r
1115         BOOLEAN                 bAntDetected;\r
1116         u4Byte                  dBForAntA;\r
1117         u4Byte                  dBForAntB;\r
1118         u4Byte                  dBForAntO;\r
1119 }ANT_DETECTED_INFO, *PANT_DETECTED_INFO;\r
1120 \r
1121 //\r
1122 // 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration.\r
1123 //\r
1124 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
1125 #if (RT_PLATFORM != PLATFORM_LINUX)\r
1126 typedef \r
1127 #endif\r
1128 struct DM_Out_Source_Dynamic_Mechanism_Structure\r
1129 #else// for AP,ADSL,CE Team\r
1130 typedef  struct DM_Out_Source_Dynamic_Mechanism_Structure\r
1131 #endif\r
1132 {\r
1133         //RT_TIMER      FastAntTrainingTimer;\r
1134         //\r
1135         //      Add for different team use temporarily\r
1136         //\r
1137         PADAPTER                Adapter;                // For CE/NIC team\r
1138         prtl8192cd_priv priv;                   // For AP/ADSL team\r
1139         // WHen you use Adapter or priv pointer, you must make sure the pointer is ready.\r
1140         BOOLEAN                 odm_ready;\r
1141 \r
1142 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))\r
1143         rtl8192cd_priv          fake_priv;\r
1144 #endif\r
1145 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
1146         // ADSL_AP_BUILD_WORKAROUND\r
1147         ADAPTER                 fake_adapter;\r
1148 #endif\r
1149         \r
1150         PHY_REG_PG_TYPE         PhyRegPgValueType;\r
1151         u1Byte                          PhyRegPgVersion;\r
1152 \r
1153         u8Byte                  DebugComponents;\r
1154         u4Byte                  DebugLevel;\r
1155         \r
1156         u4Byte                  NumQryPhyStatusAll;     //CCK + OFDM\r
1157         u4Byte                  LastNumQryPhyStatusAll; \r
1158         u4Byte                  RxPWDBAve;\r
1159         BOOLEAN                 MPDIG_2G;               //off MPDIG\r
1160         u1Byte                  Times_2G;\r
1161         \r
1162 //------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//\r
1163         BOOLEAN                 bCckHighPower; \r
1164         u1Byte                  RFPathRxEnable;         // ODM_CMNINFO_RFPATH_ENABLE\r
1165         u1Byte                  ControlChannel;\r
1166 //------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//\r
1167 \r
1168 //--------REMOVED COMMON INFO----------//\r
1169         //u1Byte                                PseudoMacPhyMode;\r
1170         //BOOLEAN                       *BTCoexist;\r
1171         //BOOLEAN                       PseudoBtCoexist;\r
1172         //u1Byte                                OPMode;\r
1173         //BOOLEAN                       bAPMode;\r
1174         //BOOLEAN                       bClientMode;\r
1175         //BOOLEAN                       bAdHocMode;\r
1176         //BOOLEAN                       bSlaveOfDMSP;\r
1177 //--------REMOVED COMMON INFO----------//\r
1178 \r
1179 \r
1180 //1  COMMON INFORMATION\r
1181 \r
1182         //\r
1183         // Init Value\r
1184         //\r
1185 //-----------HOOK BEFORE REG INIT-----------//  \r
1186         // ODM Platform info AP/ADSL/CE/MP = 1/2/3/4\r
1187         u1Byte                  SupportPlatform;                \r
1188         // ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K\r
1189         u4Byte                  SupportAbility;\r
1190         // ODM PCIE/USB/SDIO = 1/2/3\r
1191         u1Byte                  SupportInterface;                       \r
1192         // ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/...\r
1193         u4Byte                  SupportICType;  \r
1194         // Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/...\r
1195         u1Byte                  CutVersion;\r
1196         // Fab Version TSMC/UMC = 0/1\r
1197         u1Byte                  FabVersion;\r
1198         // RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/...\r
1199         u1Byte                  RFType;\r
1200         u1Byte                  RFEType;        \r
1201         // Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/...\r
1202         u1Byte                  BoardType;\r
1203         u1Byte                  PackageType;\r
1204         u1Byte                  TypeGLNA;\r
1205         u1Byte                  TypeGPA;\r
1206         u1Byte                  TypeALNA;\r
1207         u1Byte                  TypeAPA;\r
1208         // with external LNA  NO/Yes = 0/1\r
1209         u1Byte                  ExtLNA;\r
1210         u1Byte                  ExtLNA5G;\r
1211         // with external PA  NO/Yes = 0/1\r
1212         u1Byte                  ExtPA;\r
1213         u1Byte                  ExtPA5G;\r
1214         // with external TRSW  NO/Yes = 0/1\r
1215         u1Byte                  ExtTRSW;\r
1216         u1Byte                  PatchID; //Customer ID\r
1217         BOOLEAN                 bInHctTest;\r
1218         BOOLEAN                 bWIFITest;\r
1219 \r
1220         BOOLEAN                 bDualMacSmartConcurrent;\r
1221         u4Byte                  BK_SupportAbility;\r
1222         u1Byte                  AntDivType;\r
1223 \r
1224         u1Byte                  odm_Regulation2_4G;\r
1225         u1Byte                  odm_Regulation5G;\r
1226         u1Byte                  IQKFWOffload;\r
1227 //-----------HOOK BEFORE REG INIT-----------//  \r
1228 \r
1229         //\r
1230         // Dynamic Value\r
1231         //      \r
1232 //--------- POINTER REFERENCE-----------//\r
1233 \r
1234         u1Byte                  u1Byte_temp;\r
1235         BOOLEAN                 BOOLEAN_temp;\r
1236         PADAPTER                PADAPTER_temp;\r
1237         \r
1238         // MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2\r
1239         u1Byte                  *pMacPhyMode;\r
1240         //TX Unicast byte count\r
1241         u8Byte                  *pNumTxBytesUnicast;\r
1242         //RX Unicast byte count\r
1243         u8Byte                  *pNumRxBytesUnicast;\r
1244         // Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3\r
1245         u1Byte                  *pWirelessMode; //ODM_WIRELESS_MODE_E\r
1246         // Frequence band 2.4G/5G = 0/1\r
1247         u1Byte                  *pBandType;\r
1248         // Secondary channel offset don't_care/below/above = 0/1/2\r
1249         u1Byte                  *pSecChOffset;\r
1250         // Security mode Open/WEP/AES/TKIP = 0/1/2/3\r
1251         u1Byte                  *pSecurity;\r
1252         // BW info 20M/40M/80M = 0/1/2\r
1253         u1Byte                  *pBandWidth;\r
1254         // Central channel location Ch1/Ch2/....\r
1255         u1Byte                  *pChannel;      //central channel number\r
1256         BOOLEAN                 DPK_Done;\r
1257         // Common info for 92D DMSP\r
1258         \r
1259         BOOLEAN                 *pbGetValueFromOtherMac;\r
1260         PADAPTER                *pBuddyAdapter;\r
1261         BOOLEAN                 *pbMasterOfDMSP; //MAC0: master, MAC1: slave\r
1262         // Common info for Status\r
1263         BOOLEAN                 *pbScanInProcess;\r
1264         BOOLEAN                 *pbPowerSaving;\r
1265         // CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E.\r
1266         u1Byte                  *pOnePathCCA;\r
1267         //pMgntInfo->AntennaTest\r
1268         u1Byte                  *pAntennaTest;\r
1269         BOOLEAN                 *pbNet_closed;\r
1270         //u1Byte                        *pAidMap;\r
1271         u1Byte                  *pu1ForcedIgiLb;\r
1272         BOOLEAN                 *pIsFcsModeEnable;\r
1273 //--------- For 8723B IQK-----------//\r
1274         BOOLEAN                 *pIs1Antenna;\r
1275         u1Byte                  *pRFDefaultPath;\r
1276         // 0:S1, 1:S0\r
1277         \r
1278 //--------- POINTER REFERENCE-----------//\r
1279         pu2Byte                 pForcedDataRate;\r
1280 //------------CALL BY VALUE-------------//\r
1281         BOOLEAN                 bLinkInProcess;\r
1282         BOOLEAN                 bWIFI_Direct;\r
1283         BOOLEAN                 bWIFI_Display;\r
1284         BOOLEAN                 bLinked;\r
1285         BOOLEAN                 bsta_state;\r
1286         u1Byte                  RSSI_Min;       \r
1287         u1Byte          InterfaceIndex; // Add for 92D  dual MAC: 0--Mac0 1--Mac1\r
1288         BOOLEAN         bIsMPChip;\r
1289         BOOLEAN                 bOneEntryOnly;\r
1290         BOOLEAN                 mp_mode;\r
1291         // Common info for BTDM\r
1292         BOOLEAN                 bBtEnabled;                     // BT is enabled\r
1293         BOOLEAN                 bBtConnectProcess;      // BT HS is under connection progress.\r
1294         u1Byte                  btHsRssi;                               // BT HS mode wifi rssi value.\r
1295         BOOLEAN                 bBtHsOperation;         // BT HS mode is under progress\r
1296         BOOLEAN                 bBtDisableEdcaTurbo;    // Under some condition, don't enable the EDCA Turbo\r
1297         BOOLEAN                 bBtLimitedDig;                  // BT is busy.\r
1298 //------------CALL BY VALUE-------------//\r
1299         u1Byte                  RSSI_A;\r
1300         u1Byte                  RSSI_B;\r
1301         u1Byte                  RSSI_C;\r
1302         u1Byte                  RSSI_D;\r
1303         u8Byte                  RSSI_TRSW;      \r
1304         u8Byte                  RSSI_TRSW_H;\r
1305         u8Byte                  RSSI_TRSW_L;    \r
1306         u8Byte                  RSSI_TRSW_iso;\r
1307 \r
1308         u1Byte                  RxRate;\r
1309         BOOLEAN                 bNoisyState;\r
1310         u1Byte                  TxRate;\r
1311         u1Byte                  LinkedInterval;\r
1312         u1Byte                  preChannel;\r
1313         u4Byte                  TxagcOffsetValueA;\r
1314         BOOLEAN                 IsTxagcOffsetPositiveA;\r
1315         u4Byte                  TxagcOffsetValueB;\r
1316         BOOLEAN                 IsTxagcOffsetPositiveB;\r
1317         u8Byte                  lastTxOkCnt;\r
1318         u8Byte                  lastRxOkCnt;\r
1319         u4Byte                  BbSwingOffsetA;\r
1320         BOOLEAN                 IsBbSwingOffsetPositiveA;\r
1321         u4Byte                  BbSwingOffsetB;\r
1322         BOOLEAN                 IsBbSwingOffsetPositiveB;\r
1323         s1Byte                  TH_L2H_ini;\r
1324         s1Byte                  TH_EDCCA_HL_diff;\r
1325         s1Byte                  IGI_Base;\r
1326         u1Byte                  IGI_target;\r
1327         BOOLEAN                 ForceEDCCA;\r
1328         u1Byte                  AdapEn_RSSI;\r
1329         s1Byte                  Force_TH_H;\r
1330         s1Byte                  Force_TH_L;\r
1331         u1Byte                  IGI_LowerBound;\r
1332         u1Byte                  antdiv_rssi;\r
1333         u1Byte                  AntType;\r
1334         u1Byte                  pre_AntType;\r
1335         u1Byte                  antdiv_period;\r
1336         u1Byte                  antdiv_select;  \r
1337         u1Byte                  NdpaPeriod;\r
1338         BOOLEAN                 H2C_RARpt_connect;\r
1339 \r
1340         // add by Yu Cehn for adaptivtiy\r
1341         BOOLEAN                 adaptivity_flag;\r
1342         u1Byte                  tolerance_cnt;\r
1343         u8Byte                  NHMCurTxOkcnt;\r
1344         u8Byte                  NHMCurRxOkcnt;\r
1345         u8Byte                  NHMLastTxOkcnt;\r
1346         u8Byte                  NHMLastRxOkcnt;\r
1347         u1Byte                  NHMWait;\r
1348         s1Byte                  H2L_lb;\r
1349         s1Byte                  L2H_lb;\r
1350         u1Byte                  Adaptivity_IGI_upper;\r
1351         u2Byte                  NHM_cnt_0;\r
1352         u2Byte                  NHM_cnt_1;\r
1353         BOOLEAN                 Carrier_Sense_enable;\r
1354         BOOLEAN                 bFirstLink;\r
1355         BOOLEAN                 bCheck;\r
1356         BOOLEAN                 EDCCA_enable_state;\r
1357         BOOLEAN                 NHM_enable;\r
1358         BOOLEAN                 DynamicLinkAdaptivity;\r
1359         BOOLEAN                 bAdaOn;\r
1360 \r
1361         ODM_NOISE_MONITOR noise_level;//[ODM_MAX_CHANNEL_NUM];\r
1362         //\r
1363         //2 Define STA info.\r
1364         // _ODM_STA_INFO\r
1365         // 2012/01/12 MH For MP, we need to reduce one array pointer for default port.??\r
1366         PSTA_INFO_T             pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];\r
1367 \r
1368 #if (RATE_ADAPTIVE_SUPPORT == 1)\r
1369         u2Byte                  CurrminRptTime;\r
1370         ODM_RA_INFO_T   RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //See HalMacID support\r
1371 #endif\r
1372         //\r
1373         // 2012/02/14 MH Add to share 88E ra with other SW team.\r
1374         // We need to colelct all support abilit to a proper area.\r
1375         //\r
1376         BOOLEAN                         RaSupport88E;\r
1377 \r
1378         // Define ...........\r
1379 \r
1380         // Latest packet phy info (ODM write)\r
1381         ODM_PHY_DBG_INFO_T       PhyDbgInfo;\r
1382         //PHY_INFO_88E          PhyInfo;\r
1383 \r
1384         // Latest packet phy info (ODM write)\r
1385         ODM_MAC_INFO            *pMacInfo;\r
1386         //MAC_INFO_88E          MacInfo;\r
1387 \r
1388         // Different Team independt structure??\r
1389 \r
1390         //\r
1391         //TX_RTP_CMN            TX_retrpo;\r
1392         //TX_RTP_88E            TX_retrpo;\r
1393         //TX_RTP_8195           TX_retrpo;\r
1394 \r
1395         //\r
1396         //ODM Structure\r
1397         //\r
1398         FAT_T                                           DM_FatTable;\r
1399         DIG_T                                           DM_DigTable;\r
1400         PS_T                                            DM_PSTable;\r
1401         Pri_CCA_T                                       DM_PriCCA;\r
1402 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
1403         RXHP_T                                          DM_RXHP_Table;\r
1404 #endif\r
1405         RA_T                                            DM_RA_Table;  \r
1406         FALSE_ALARM_STATISTICS          FalseAlmCnt;\r
1407         FALSE_ALARM_STATISTICS          FlaseAlmCntBuddyAdapter;\r
1408         //#ifdef CONFIG_ANTENNA_DIVERSITY\r
1409         SWAT_T                                          DM_SWAT_Table;\r
1410         BOOLEAN                                         RSSI_test;\r
1411         CFO_TRACKING                                    DM_CfoTrack;\r
1412         ACS                                                     DM_ACS;\r
1413         //#endif \r
1414         \r
1415 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
1416         //Path Div Struct\r
1417         PATHDIV_PARA    pathIQK;\r
1418 #endif  \r
1419 \r
1420         EDCA_T          DM_EDCA_Table;\r
1421         u4Byte          WMMEDCA_BE;\r
1422         PATHDIV_T       DM_PathDiv;\r
1423         // Copy from SD4 structure\r
1424         //\r
1425         // ==================================================\r
1426         //\r
1427 \r
1428         //common\r
1429         //u1Byte                DM_Type;        \r
1430         //u1Byte    PSD_Report_RXHP[80];   // Add By Gary\r
1431         //u1Byte    PSD_func_flag;               // Add By Gary\r
1432         //for DIG\r
1433         //u1Byte                bDMInitialGainEnable;\r
1434         //u1Byte                binitialized; // for dm_initial_gain_Multi_STA use.\r
1435         //for Antenna diversity\r
1436         //u8    AntDivCfg;// 0:OFF , 1:ON, 2:by efuse\r
1437         //PSTA_INFO_T RSSI_target;\r
1438 \r
1439         BOOLEAN                 *pbDriverStopped;\r
1440         BOOLEAN                 *pbDriverIsGoingToPnpSetPowerSleep;\r
1441         BOOLEAN                 *pinit_adpt_in_progress;\r
1442 \r
1443         //PSD\r
1444         BOOLEAN                 bUserAssignLevel;\r
1445         RT_TIMER                PSDTimer;\r
1446         u1Byte                  RSSI_BT;                        //come from BT\r
1447         BOOLEAN                 bPSDinProcess;\r
1448         BOOLEAN                 bPSDactive;\r
1449         BOOLEAN                 bDMInitialGainEnable;\r
1450 \r
1451         //MPT DIG\r
1452         RT_TIMER                MPT_DIGTimer;\r
1453         \r
1454         //for rate adaptive, in fact,  88c/92c fw will handle this\r
1455         u1Byte                  bUseRAMask;\r
1456 \r
1457         ODM_RATE_ADAPTIVE       RateAdaptive;\r
1458 \r
1459         ANT_DETECTED_INFO       AntDetectedInfo; // Antenna detected information for RSSI tool\r
1460 \r
1461         ODM_RF_CAL_T    RFCalibrateInfo;\r
1462         \r
1463         //\r
1464         // TX power tracking\r
1465         //\r
1466         u1Byte                  BbSwingIdxOfdm[MAX_RF_PATH];\r
1467         u1Byte                  BbSwingIdxOfdmCurrent;\r
1468         u1Byte                  BbSwingIdxOfdmBase[MAX_RF_PATH];\r
1469         BOOLEAN                 BbSwingFlagOfdm;\r
1470         u1Byte                  BbSwingIdxCck;\r
1471         u1Byte                  BbSwingIdxCckCurrent;\r
1472         u1Byte                  BbSwingIdxCckBase;\r
1473         u1Byte                  DefaultOfdmIndex;\r
1474         u1Byte                  DefaultCckIndex;        \r
1475         BOOLEAN                 BbSwingFlagCck;\r
1476         \r
1477         s1Byte                  Absolute_OFDMSwingIdx[MAX_RF_PATH];   \r
1478         s1Byte                  Remnant_OFDMSwingIdx[MAX_RF_PATH];   \r
1479         s1Byte                  Remnant_CCKSwingIdx;\r
1480         s1Byte                  Modify_TxAGC_Value;       //Remnat compensate value at TxAGC \r
1481         BOOLEAN                 Modify_TxAGC_Flag_PathA;\r
1482         BOOLEAN                 Modify_TxAGC_Flag_PathB;\r
1483         BOOLEAN                 Modify_TxAGC_Flag_PathC;\r
1484         BOOLEAN                 Modify_TxAGC_Flag_PathD;\r
1485         BOOLEAN                 Modify_TxAGC_Flag_PathA_CCK;\r
1486         \r
1487         s1Byte                  KfreeOffset[MAX_RF_PATH];\r
1488 \r
1489         //\r
1490         // Dynamic ATC switch\r
1491         //\r
1492 \r
1493 #if (DM_ODM_SUPPORT_TYPE &  (ODM_WIN|ODM_CE))   \r
1494         //\r
1495         // Power Training\r
1496         //\r
1497         BOOLEAN                 bDisablePowerTraining;\r
1498         u1Byte                  ForcePowerTrainingState;\r
1499         BOOLEAN                 bChangeState;\r
1500         u4Byte                  PT_score;\r
1501         u8Byte                  OFDM_RX_Cnt;\r
1502         u8Byte                  CCK_RX_Cnt;\r
1503 #endif\r
1504 \r
1505         //\r
1506         // ODM system resource.\r
1507         //\r
1508 \r
1509         // ODM relative time.\r
1510         RT_TIMER                                PathDivSwitchTimer;\r
1511         //2011.09.27 add for Path Diversity\r
1512         RT_TIMER                                CCKPathDiversityTimer;\r
1513         RT_TIMER        FastAntTrainingTimer;\r
1514         \r
1515         // ODM relative workitem.\r
1516 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1517         #if USE_WORKITEM\r
1518         RT_WORK_ITEM                    PathDivSwitchWorkitem;\r
1519         RT_WORK_ITEM                    CCKPathDiversityWorkitem;\r
1520         RT_WORK_ITEM                    FastAntTrainingWorkitem;\r
1521         RT_WORK_ITEM                    MPT_DIGWorkitem;\r
1522         RT_WORK_ITEM                    RaRptWorkitem;\r
1523         #endif\r
1524 #endif\r
1525 \r
1526         #if (BEAMFORMING_SUPPORT == 1)\r
1527         RT_BEAMFORMING_INFO BeamformingInfo;\r
1528         #endif \r
1529 \r
1530 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
1531         \r
1532 #if (RT_PLATFORM != PLATFORM_LINUX)\r
1533 } DM_ODM_T, *PDM_ODM_T;         // DM_Dynamic_Mechanism_Structure\r
1534 #else\r
1535 };\r
1536 #endif  \r
1537 \r
1538 #else// for AP,ADSL,CE Team\r
1539 } DM_ODM_T, *PDM_ODM_T;         // DM_Dynamic_Mechanism_Structure\r
1540 #endif\r
1541 \r
1542 \r
1543 \r
1544 #if 1 //92c-series\r
1545 #define ODM_RF_PATH_MAX 2\r
1546 #else //jaguar - series\r
1547 #define ODM_RF_PATH_MAX 4\r
1548 #endif\r
1549 \r
1550 typedef enum _PhyDM_Structure_Type{\r
1551         PHYDM_FALSEALMCNT,\r
1552         PHYDM_CFOTRACK,\r
1553         PHYDM_ROMINFO,\r
1554         \r
1555 }PhyDM_Structure_Type;\r
1556 \r
1557 typedef enum _ODM_RF_RADIO_PATH {\r
1558     ODM_RF_PATH_A = 0,   //Radio Path A\r
1559     ODM_RF_PATH_B = 1,   //Radio Path B\r
1560     ODM_RF_PATH_C = 2,   //Radio Path C\r
1561     ODM_RF_PATH_D = 3,   //Radio Path D\r
1562     ODM_RF_PATH_AB,\r
1563     ODM_RF_PATH_AC,\r
1564     ODM_RF_PATH_AD,\r
1565     ODM_RF_PATH_BC,\r
1566     ODM_RF_PATH_BD,\r
1567     ODM_RF_PATH_CD,\r
1568     ODM_RF_PATH_ABC,\r
1569     ODM_RF_PATH_ACD,\r
1570     ODM_RF_PATH_BCD,\r
1571     ODM_RF_PATH_ABCD,\r
1572   //  ODM_RF_PATH_MAX,    //Max RF number 90 support\r
1573 } ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E;\r
1574 \r
1575  typedef enum _ODM_RF_CONTENT{\r
1576         odm_radioa_txt = 0x1000,\r
1577         odm_radiob_txt = 0x1001,\r
1578         odm_radioc_txt = 0x1002,\r
1579         odm_radiod_txt = 0x1003\r
1580 } ODM_RF_CONTENT;\r
1581 \r
1582 typedef enum _ODM_BB_Config_Type{\r
1583     CONFIG_BB_PHY_REG,   \r
1584     CONFIG_BB_AGC_TAB,   \r
1585     CONFIG_BB_AGC_TAB_2G,\r
1586     CONFIG_BB_AGC_TAB_5G, \r
1587     CONFIG_BB_PHY_REG_PG,  \r
1588     CONFIG_BB_PHY_REG_MP,\r
1589     CONFIG_BB_AGC_TAB_DIFF,\r
1590 } ODM_BB_Config_Type, *PODM_BB_Config_Type;\r
1591 \r
1592 typedef enum _ODM_RF_Config_Type{ \r
1593         CONFIG_RF_RADIO,\r
1594     CONFIG_RF_TXPWR_LMT,\r
1595 } ODM_RF_Config_Type, *PODM_RF_Config_Type;\r
1596 \r
1597 typedef enum _ODM_FW_Config_Type{\r
1598     CONFIG_FW_NIC,\r
1599     CONFIG_FW_NIC_2,\r
1600     CONFIG_FW_AP,\r
1601     CONFIG_FW_MP,\r
1602     CONFIG_FW_WoWLAN,\r
1603     CONFIG_FW_WoWLAN_2,\r
1604     CONFIG_FW_AP_WoWLAN,\r
1605     CONFIG_FW_BT,\r
1606 } ODM_FW_Config_Type;\r
1607 \r
1608 // Status code\r
1609 #if (DM_ODM_SUPPORT_TYPE != ODM_WIN)\r
1610 typedef enum _RT_STATUS{\r
1611         RT_STATUS_SUCCESS,\r
1612         RT_STATUS_FAILURE,\r
1613         RT_STATUS_PENDING,\r
1614         RT_STATUS_RESOURCE,\r
1615         RT_STATUS_INVALID_CONTEXT,\r
1616         RT_STATUS_INVALID_PARAMETER,\r
1617         RT_STATUS_NOT_SUPPORT,\r
1618         RT_STATUS_OS_API_FAILED,\r
1619 }RT_STATUS,*PRT_STATUS;\r
1620 #endif // end of RT_STATUS definition\r
1621 \r
1622 #ifdef REMOVE_PACK\r
1623 #pragma pack()\r
1624 #endif\r
1625 \r
1626 //#include "odm_function.h"\r
1627 \r
1628 //3===========================================================\r
1629 //3 DIG\r
1630 //3===========================================================\r
1631 \r
1632 //Remove DIG by Yuchen\r
1633 \r
1634 //3===========================================================\r
1635 //3 AGC RX High Power Mode\r
1636 //3===========================================================\r
1637 #define          LNA_Low_Gain_1                      0x64\r
1638 #define          LNA_Low_Gain_2                      0x5A\r
1639 #define          LNA_Low_Gain_3                      0x58\r
1640 \r
1641 #define          FA_RXHP_TH1                           5000\r
1642 #define          FA_RXHP_TH2                           1500\r
1643 #define          FA_RXHP_TH3                             800\r
1644 #define          FA_RXHP_TH4                             600\r
1645 #define          FA_RXHP_TH5                             500\r
1646 \r
1647 //3===========================================================\r
1648 //3 EDCA\r
1649 //3===========================================================\r
1650 \r
1651 //3===========================================================\r
1652 //3 Dynamic Tx Power\r
1653 //3===========================================================\r
1654 //Dynamic Tx Power Control Threshold\r
1655 \r
1656 //Remove By YuChen\r
1657 \r
1658 //3===========================================================\r
1659 //3 Tx Power Tracking\r
1660 //3===========================================================\r
1661 #if 0 //mask this, since these have been defined in typdef.h, vivi\r
1662 #define OFDM_TABLE_SIZE         43\r
1663 #define CCK_TABLE_SIZE          33\r
1664 #endif  \r
1665 \r
1666 \r
1667 //3===========================================================\r
1668 //3 Rate Adaptive\r
1669 //3===========================================================\r
1670 //Remove to odm_RaInfo.h by RS_James\r
1671 \r
1672 //3===========================================================\r
1673 //3 BB Power Save\r
1674 //3===========================================================\r
1675 \r
1676 typedef enum tag_1R_CCA_Type_Definition\r
1677 {\r
1678         CCA_1R =0,\r
1679         CCA_2R = 1,\r
1680         CCA_MAX = 2,\r
1681 }DM_1R_CCA_E;\r
1682 \r
1683 typedef enum tag_RF_Type_Definition\r
1684 {\r
1685         RF_Save =0,\r
1686         RF_Normal = 1,\r
1687         RF_MAX = 2,\r
1688 }DM_RF_E;\r
1689 \r
1690 //3===========================================================\r
1691 //3 Antenna Diversity\r
1692 //3===========================================================\r
1693 typedef enum tag_SW_Antenna_Switch_Definition\r
1694 {\r
1695         Antenna_A = 1,\r
1696         Antenna_B = 2,  \r
1697         Antenna_MAX = 3,\r
1698 }DM_SWAS_E;\r
1699 \r
1700 \r
1701 // Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28.\r
1702 #define MAX_ANTENNA_DETECTION_CNT       10 \r
1703 \r
1704 //\r
1705 // Extern Global Variables.\r
1706 //\r
1707 //remove PT by YuChen\r
1708 //\r
1709 // check Sta pointer valid or not\r
1710 //\r
1711 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
1712 #define IS_STA_VALID(pSta)              (pSta && pSta->expire_to)\r
1713 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
1714 #define IS_STA_VALID(pSta)              (pSta && pSta->bUsed)\r
1715 #else\r
1716 #define IS_STA_VALID(pSta)              (pSta)\r
1717 #endif\r
1718 // 20100514 Joseph: Add definition for antenna switching test after link.\r
1719 // This indicates two different the steps. \r
1720 // In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air.\r
1721 // In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK\r
1722 // with original RSSI to determine if it is necessary to switch antenna.\r
1723 #define SWAW_STEP_PEAK          0\r
1724 #define SWAW_STEP_DETERMINE     1\r
1725 \r
1726 //Remove DIG by yuchen\r
1727 \r
1728 \r
1729 \r
1730 \r
1731 //Remove BB power saving by Yuchen\r
1732 \r
1733 \r
1734 \r
1735 \r
1736                                                 \r
1737 //ODM_RAStateCheck() Remove by RS_James\r
1738 \r
1739 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_AP|ODM_ADSL))\r
1740 //============================================================\r
1741 // function prototype\r
1742 //============================================================\r
1743 //#define DM_ChangeDynamicInitGainThresh                ODM_ChangeDynamicInitGainThresh\r
1744 //void  ODM_ChangeDynamicInitGainThresh(IN      PADAPTER        pAdapter,\r
1745 //                                                                                      IN      INT32           DM_Type,\r
1746 //                                                                                      IN      INT32           DM_Value);\r
1747 \r
1748 //Remove DIG by yuchen\r
1749 \r
1750 \r
1751 BOOLEAN\r
1752 ODM_CheckPowerStatus(\r
1753         IN      PADAPTER                Adapter\r
1754         );\r
1755 \r
1756 \r
1757 //Remove ODM_RateAdaptiveStateApInit() by RS_James\r
1758 \r
1759 //Remove Edca by YuChen\r
1760 \r
1761 #endif\r
1762 \r
1763 #if((DM_ODM_SUPPORT_TYPE==ODM_WIN)||(DM_ODM_SUPPORT_TYPE==ODM_CE))\r
1764 \r
1765 u4Byte ConvertTo_dB(u4Byte Value);\r
1766 \r
1767 u4Byte\r
1768 GetPSDData(\r
1769         PDM_ODM_T       pDM_Odm,\r
1770         unsigned int    point,\r
1771         u1Byte initial_gain_psd);\r
1772 \r
1773 #endif\r
1774 \r
1775 //Remove ODM_Get_Rate_Bitmap() by RS_James      \r
1776 \r
1777 \r
1778 #if (BEAMFORMING_SUPPORT == 1)\r
1779 BEAMFORMING_CAP\r
1780 Beamforming_GetEntryBeamCapByMacId(\r
1781  IN PMGNT_INFO pMgntInfo,\r
1782  IN u1Byte  MacId\r
1783  );\r
1784 #endif\r
1785 \r
1786 VOID \r
1787 ODM_DMInit(\r
1788  IN     PDM_ODM_T       pDM_Odm\r
1789 );\r
1790 \r
1791 VOID\r
1792 ODM_DMReset(\r
1793         IN      PDM_ODM_T       pDM_Odm\r
1794         );\r
1795 \r
1796 VOID\r
1797 ODM_DMWatchdog(\r
1798         IN              PDM_ODM_T                       pDM_Odm                 // For common use in the future\r
1799         );\r
1800 \r
1801 VOID\r
1802 ODM_CmnInfoInit(\r
1803         IN              PDM_ODM_T               pDM_Odm,\r
1804         IN              ODM_CMNINFO_E   CmnInfo,\r
1805         IN              u4Byte                  Value   \r
1806         );\r
1807 \r
1808 VOID\r
1809 ODM_CmnInfoHook(\r
1810         IN              PDM_ODM_T               pDM_Odm,\r
1811         IN              ODM_CMNINFO_E   CmnInfo,\r
1812         IN              PVOID                   pValue  \r
1813         );\r
1814 \r
1815 VOID\r
1816 ODM_CmnInfoPtrArrayHook(\r
1817         IN              PDM_ODM_T               pDM_Odm,\r
1818         IN              ODM_CMNINFO_E   CmnInfo,\r
1819         IN              u2Byte                  Index,\r
1820         IN              PVOID                   pValue  \r
1821         );\r
1822 \r
1823 VOID\r
1824 ODM_CmnInfoUpdate(\r
1825         IN              PDM_ODM_T               pDM_Odm,\r
1826         IN              u4Byte                  CmnInfo,\r
1827         IN              u8Byte                  Value   \r
1828         );\r
1829 \r
1830 VOID \r
1831 ODM_InitAllTimers(\r
1832     IN PDM_ODM_T        pDM_Odm \r
1833     );\r
1834 \r
1835 VOID \r
1836 ODM_CancelAllTimers(\r
1837     IN PDM_ODM_T    pDM_Odm \r
1838     );\r
1839 \r
1840 VOID\r
1841 ODM_ReleaseAllTimers(\r
1842     IN PDM_ODM_T        pDM_Odm \r
1843     );\r
1844 \r
1845 VOID\r
1846 ODM_ResetIQKResult(\r
1847     IN PDM_ODM_T pDM_Odm \r
1848     );\r
1849 \r
1850 \r
1851 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1852 VOID ODM_InitAllWorkItems(IN PDM_ODM_T  pDM_Odm );\r
1853 VOID ODM_FreeAllWorkItems(IN PDM_ODM_T  pDM_Odm );\r
1854 \r
1855 \r
1856 //===========================================//\r
1857 // Neil Chen----2011--06--15--\r
1858 \r
1859 //3 Path Diversity\r
1860 //===========================================================\r
1861 \r
1862 #define TP_MODE                0\r
1863 #define RSSI_MODE                      1\r
1864 #define TRAFFIC_LOW            0\r
1865 #define TRAFFIC_HIGH           1\r
1866 \r
1867 //#define   PATHDIV_ENABLE       1\r
1868 \r
1869 //#define dm_PathDiv_RSSI_Check ODM_PathDivChkPerPktRssi\r
1870 \r
1871 u8Byte\r
1872 PlatformDivision64(\r
1873         IN u8Byte       x,\r
1874         IN u8Byte       y\r
1875 );\r
1876 \r
1877 \r
1878 // 20100514 Joseph: Add definition for antenna switching test after link.\r
1879 // This indicates two different the steps. \r
1880 // In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air.\r
1881 // In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK\r
1882 // with original RSSI to determine if it is necessary to switch antenna.\r
1883 #define SWAW_STEP_PEAK          0\r
1884 #define SWAW_STEP_DETERMINE     1\r
1885 \r
1886 //====================================================\r
1887 //3 PathDiV End\r
1888 //====================================================\r
1889 \r
1890 //#define PathDivCheckBeforeLink8192C   ODM_PathDiversityBeforeLink92C\r
1891 \r
1892 #define DM_ChangeDynamicInitGainThresh          ODM_ChangeDynamicInitGainThresh\r
1893 //void  ODM_ChangeDynamicInitGainThresh(IN      PADAPTER        pAdapter,\r
1894 //                                                                                      IN      INT32           DM_Type,\r
1895 //                                                                                      IN      INT32           DM_Value);\r
1896 //\r
1897 \r
1898 typedef enum tag_DIG_Connect_Definition\r
1899 {\r
1900         DIG_STA_DISCONNECT = 0, \r
1901         DIG_STA_CONNECT = 1,\r
1902         DIG_STA_BEFORE_CONNECT = 2,\r
1903         DIG_MultiSTA_DISCONNECT = 3,\r
1904         DIG_MultiSTA_CONNECT = 4,\r
1905         DIG_CONNECT_MAX\r
1906 }DM_DIG_CONNECT_E;\r
1907 \r
1908 \r
1909 //\r
1910 // 2012/01/12 MH Check afapter status. Temp fix BSOD.\r
1911 //\r
1912 #define HAL_ADAPTER_STS_CHK(pDM_Odm)\\r
1913         if (pDM_Odm->Adapter == NULL)\\r
1914         {\\r
1915                 return;\\r
1916         }\\r
1917 \r
1918 \r
1919 //\r
1920 // For new definition in MP temporarily fro power tracking,\r
1921 //\r
1922 #define odm_TXPowerTrackingDirectCall(_Adapter) \\r
1923         IS_HARDWARE_TYPE_8192D(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_92D(_Adapter) : \\r
1924         IS_HARDWARE_TYPE_8192C(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_92C(_Adapter) : \\r
1925         IS_HARDWARE_TYPE_8723A(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_8723A(_Adapter) :\\r
1926         ODM_TXPowerTrackingCallback_ThermalMeter(_Adapter)\r
1927 \r
1928 \r
1929 \r
1930 #endif  // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1931 \r
1932 \r
1933 #if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE))\r
1934 \r
1935 VOID\r
1936 ODM_SingleDualAntennaDefaultSetting(\r
1937         IN              PDM_ODM_T               pDM_Odm\r
1938         );\r
1939 \r
1940 BOOLEAN\r
1941 ODM_SingleDualAntennaDetection(\r
1942         IN              PDM_ODM_T               pDM_Odm,\r
1943         IN              u1Byte                  mode\r
1944         );\r
1945 \r
1946 #endif  // #if((DM_ODM_SUPPORT_TYPE==ODM_WIN)||(DM_ODM_SUPPORT_TYPE==ODM_CE))\r
1947 VOID\r
1948 ODM_UpdateNoisyState(\r
1949         IN      PDM_ODM_T       pDM_Odm,\r
1950         IN      BOOLEAN         bNoisyStateFromC2H\r
1951 );\r
1952 \r
1953 u4Byte\r
1954 Set_RA_DM_Ratrbitmap_by_Noisy(\r
1955         IN      PDM_ODM_T       pDM_Odm,\r
1956         IN      WIRELESS_MODE   WirelessMode,\r
1957         IN      u4Byte                  ratr_bitmap,\r
1958         IN      u1Byte                  rssi_level\r
1959 );\r
1960 \r
1961 VOID\r
1962 ODM_UpdateInitRate(\r
1963         IN      PDM_ODM_T       pDM_Odm,\r
1964         IN      u1Byte          Rate\r
1965         );\r
1966 \r
1967 VOID\r
1968 ODM_InitializeTimer(\r
1969         IN      PDM_ODM_T                       pDM_Odm,\r
1970         IN      PRT_TIMER                       pTimer, \r
1971         IN      RT_TIMER_CALL_BACK      CallBackFunc, \r
1972         IN      PVOID                           pContext,\r
1973         IN      const char*                     szID\r
1974 );\r
1975 \r
1976 VOID\r
1977 ODM_CancelAllTimers(\r
1978         IN PDM_ODM_T    pDM_Odm \r
1979 );\r
1980 \r
1981 VOID\r
1982 ODM_ReleaseAllTimers(\r
1983         IN PDM_ODM_T    pDM_Odm \r
1984 );\r
1985 \r
1986 //Remove ODM_DynamicARFBSelect() by RS_James\r
1987 \r
1988 PVOID\r
1989 PhyDM_Get_Structure(\r
1990         IN              PDM_ODM_T               pDM_Odm,\r
1991         IN              u1Byte                  Structure_Type\r
1992 );\r
1993 \r
1994 \r
1995 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1996 void odm_dtc(PDM_ODM_T pDM_Odm);\r
1997 #endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */\r
1998 \r
1999 #endif\r
2000 \r