drivers/net/wireless/rockchip_wlan/rtl8723bu/hal/OUTSRC/PhyDM_Adaptivity.c

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *\r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 \r
  21 //============================================================\r
  22 // include files\r
  23 //============================================================\r
  24 #include "Mp_Precomp.h"\r
  25 #include "phydm_precomp.h"\r
  26 \r
  27 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
  28 #if WPP_SOFTWARE_TRACE\r
  29 #include "PhyDM_Adaptivity.tmh"\r
  30 #endif\r
  31 #endif\r
  32 \r
  33 \r
  34 VOID\r
  35 Phydm_CheckAdaptivity(\r
  36         IN              PVOID                   pDM_VOID\r
  37 )\r
  38 {\r
  39         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
  40         PADAPTIVITY_STATISTICS  Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);\r
  41         \r
  42         if (pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY) {\r
  43 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
  44                 if (pDM_Odm->APTotalNum > Adaptivity->APNumTH) {\r
  45                         pDM_Odm->Adaptivity_enable = FALSE;\r
  46                         pDM_Odm->adaptivity_flag = FALSE;\r
  47                         Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f);\r
  48                         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("AP total num > %d!!, disable adaptivity\n", Adaptivity->APNumTH));\r
  49                 } else\r
  50 #endif\r
  51                 {\r
  52                         if (Adaptivity->DynamicLinkAdaptivity == TRUE) {\r
  53                                 if (pDM_Odm->bLinked && Adaptivity->bCheck == FALSE) {\r
  54                                         Phydm_NHMCounterStatistics(pDM_Odm);\r
  55                                         Phydm_CheckEnvironment(pDM_Odm);\r
  56                                 } else if (!pDM_Odm->bLinked)\r
  57                                         Adaptivity->bCheck = FALSE;\r
  58                         } else {\r
  59                                 pDM_Odm->Adaptivity_enable = TRUE;\r
  60 \r
  61                                 if (pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8195A))\r
  62                                         pDM_Odm->adaptivity_flag = FALSE;\r
  63                                 else\r
  64                                         pDM_Odm->adaptivity_flag = TRUE;\r
  65                         }\r
  66                 }\r
  67         } else {\r
  68                 pDM_Odm->Adaptivity_enable = FALSE;\r
  69                 pDM_Odm->adaptivity_flag = FALSE;\r
  70         }\r
  71 \r
  72         \r
  73 \r
  74 }\r
  75 \r
  76 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
  77 BOOLEAN\r
  78 Phydm_CheckChannelPlan(\r
  79         IN              PVOID                   pDM_VOID\r
  80 )\r
  81 {\r
  82         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
  83         PADAPTER                pAdapter        = pDM_Odm->Adapter;\r
  84         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
  85         PMGNT_INFO              pMgntInfo = &(pAdapter->MgntInfo);\r
  86         \r
  87         if (pMgntInfo->RegEnableAdaptivity == 2) {\r
  88                 if (pDM_Odm->Carrier_Sense_enable == FALSE) {           /*check domain Code for Adaptivity or CarrierSense*/\r
  89                         if ((*pDM_Odm->pBandType == ODM_BAND_5G) &&\r
  90                             !(pDM_Odm->odm_Regulation5G == REGULATION_ETSI || pDM_Odm->odm_Regulation5G == REGULATION_WW)) {\r
  91                                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 5G domain code : %d\n", pDM_Odm->odm_Regulation5G));\r
  92                                 return TRUE;\r
  93                         } else if ((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&\r
  94                                    !(pDM_Odm->odm_Regulation2_4G == REGULATION_ETSI || pDM_Odm->odm_Regulation2_4G == REGULATION_WW)) {\r
  95                                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 2.4G domain code : %d\n", pDM_Odm->odm_Regulation2_4G));\r
  96                                 return TRUE;\r
  97 \r
  98                         } else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G)) {\r
  99                                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity neither 2G nor 5G band, return\n"));\r
 100                                 return TRUE;\r
 101                         }\r
 102                 } else {\r
 103                         if ((*pDM_Odm->pBandType == ODM_BAND_5G) &&\r
 104                             !(pDM_Odm->odm_Regulation5G == REGULATION_MKK || pDM_Odm->odm_Regulation5G == REGULATION_WW)) {\r
 105                                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 5G domain code : %d\n", pDM_Odm->odm_Regulation5G));\r
 106                                 return TRUE;\r
 107                         }\r
 108 \r
 109                         else if ((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&\r
 110                                    !(pDM_Odm->odm_Regulation2_4G == REGULATION_MKK  || pDM_Odm->odm_Regulation2_4G == REGULATION_WW)) {\r
 111                                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 2.4G domain code : %d\n", pDM_Odm->odm_Regulation2_4G));\r
 112                                 return TRUE;\r
 113 \r
 114                         } else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G)) {\r
 115                                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense neither 2G nor 5G band, return\n"));\r
 116                                 return TRUE;\r
 117                         }\r
 118                 }\r
 119         }\r
 120 \r
 121         return FALSE;\r
 122 \r
 123 }\r
 124 #endif\r
 125 \r
 126 VOID\r
 127 Phydm_NHMCounterStatisticsInit(\r
 128         IN              PVOID                   pDM_VOID\r
 129 )\r
 130 {\r
 131         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 132 \r
 133         if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {\r
 134                 /*PHY parameters initialize for n series*/\r
 135                 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N + 2, 0xC350);                     /*0x894[31:16]=0x0xC350 Time duration for NHM unit: us, 0xc350=200ms*/\r
 136                 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N + 2, 0xffff);          /*0x890[31:16]=0xffff           th_9, th_10*/\r
 137                 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50);                /*0x898=0xffffff52                      th_3, th_2, th_1, th_0*/\r
 138                 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff);                /*0x89c=0xffffffff                      th_7, th_6, th_5, th_4*/\r
 139                 ODM_SetBBReg(pDM_Odm, ODM_REG_FPGA0_IQK_11N, bMaskByte0, 0xff);         /*0xe28[7:0]=0xff                       th_8*/\r
 140                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10 | BIT9 | BIT8, 0x1);      /*0x890[10:8]=1                 ignoreCCA ignore PHYTXON enable CCX*/\r
 141                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT7, 0x1);                     /*0xc0c[7]=1                            max power among all RX ants*/\r
 142         }\r
 143 #if (RTL8195A_SUPPORT == 0)\r
 144         else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {\r
 145                 /*PHY parameters initialize for ac series*/\r
 146                 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC + 2, 0xC350);                    /*0x990[31:16]=0xC350   Time duration for NHM unit: us, 0xc350=200ms*/\r
 147                 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC + 2, 0xffff);         /*0x994[31:16]=0xffff           th_9, th_10*/\r
 148                 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50);       /*0x998=0xffffff52                      th_3, th_2, th_1, th_0*/\r
 149                 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff);       /*0x99c=0xffffffff                      th_7, th_6, th_5, th_4*/\r
 150                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, 0xff);          /*0x9a0[7:0]=0xff                       th_8*/\r
 151                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8 | BIT9 | BIT10, 0x1); /*0x994[10:8]=1                     ignoreCCA ignore PHYTXON        enable CCX*/\r
 152                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_9E8_11AC, BIT0, 0x1);                         /*0x9e8[7]=1                            max power among all RX ants*/\r
 153 \r
 154         }\r
 155 #endif\r
 156 }\r
 157 \r
 158 VOID\r
 159 Phydm_NHMCounterStatistics(\r
 160         IN              PVOID                   pDM_VOID\r
 161 )\r
 162 {\r
 163         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 164 \r
 165         if (!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))\r
 166                 return;\r
 167 \r
 168         /*Get NHM report*/\r
 169         Phydm_GetNHMCounterStatistics(pDM_Odm);\r
 170 \r
 171         /*Reset NHM counter*/\r
 172         Phydm_NHMCounterStatisticsReset(pDM_Odm);\r
 173 }\r
 174 \r
 175 VOID\r
 176 Phydm_GetNHMCounterStatistics(\r
 177         IN              PVOID                   pDM_VOID\r
 178 )\r
 179 {\r
 180         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 181         u4Byte          value32 = 0;\r
 182 #if (RTL8195A_SUPPORT == 0)\r
 183         if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
 184                 value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11AC, bMaskDWord);\r
 185         else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
 186 #endif\r
 187                 value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11N, bMaskDWord);\r
 188 \r
 189         pDM_Odm->NHM_cnt_0 = (u1Byte)(value32 & bMaskByte0);\r
 190         pDM_Odm->NHM_cnt_1 = (u1Byte)((value32 & bMaskByte1) >> 8);\r
 191 \r
 192 }\r
 193 \r
 194 VOID\r
 195 Phydm_NHMCounterStatisticsReset(\r
 196         IN              PVOID                   pDM_VOID\r
 197 )\r
 198 {\r
 199         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 200 \r
 201         if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {\r
 202                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 0);\r
 203                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 1);\r
 204         }\r
 205 #if (RTL8195A_SUPPORT == 0)\r
 206         else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {\r
 207                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 0);\r
 208                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 1);\r
 209         }\r
 210 \r
 211 #endif\r
 212 \r
 213 }\r
 214 \r
 215 VOID\r
 216 Phydm_SetEDCCAThreshold(\r
 217         IN      PVOID   pDM_VOID,\r
 218         IN      s1Byte  H2L,\r
 219         IN      s1Byte  L2H\r
 220 )\r
 221 {\r
 222         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 223 \r
 224         if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {\r
 225                 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskByte0, (u1Byte)L2H);\r
 226                 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskByte2, (u1Byte)H2L);\r
 227         }\r
 228 #if (RTL8195A_SUPPORT == 0)\r
 229         else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {\r
 230                 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskByte0, (u1Byte)L2H);\r
 231                 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskByte1, (u1Byte)H2L);\r
 232         }\r
 233 #endif\r
 234 \r
 235 }\r
 236 \r
 237 VOID\r
 238 Phydm_SetTRxMux(\r
 239         IN      PVOID                           pDM_VOID,\r
 240         IN      PhyDM_Trx_MUX_Type      txMode,\r
 241         IN      PhyDM_Trx_MUX_Type      rxMode\r
 242 )\r
 243 {\r
 244         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 245 \r
 246         if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {\r
 247                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT3 | BIT2 | BIT1, txMode);                  /*set TXmod to standby mode to remove outside noise affect*/\r
 248                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT22 | BIT21 | BIT20, rxMode);               /*set RXmod to standby mode to remove outside noise affect*/\r
 249                 if (pDM_Odm->RFType > ODM_1T1R) {\r
 250                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT3 | BIT2 | BIT1, txMode);                /*set TXmod to standby mode to remove outside noise affect*/\r
 251                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT22 | BIT21 | BIT20, rxMode);     /*set RXmod to standby mode to remove outside noise affect*/\r
 252                 }\r
 253         }\r
 254 #if (RTL8195A_SUPPORT == 0)\r
 255         else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {\r
 256                 ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT11 | BIT10 | BIT9 | BIT8, txMode);                         /*set TXmod to standby mode to remove outside noise affect*/\r
 257                 ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT7 | BIT6 | BIT5 | BIT4, rxMode);                           /*set RXmod to standby mode to remove outside noise affect*/\r
 258                 if (pDM_Odm->RFType > ODM_1T1R) {\r
 259                         ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT11 | BIT10 | BIT9 | BIT8, txMode);               /*set TXmod to standby mode to remove outside noise affect*/\r
 260                         ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT7 | BIT6 | BIT5 | BIT4, rxMode);                 /*set RXmod to standby mode to remove outside noise affect*/\r
 261                 }\r
 262         }\r
 263 #endif\r
 264 \r
 265 }\r
 266 \r
 267 VOID\r
 268 Phydm_MACEDCCAState(\r
 269         IN      PVOID                                   pDM_VOID,\r
 270         IN      PhyDM_MACEDCCA_Type             State\r
 271 )\r
 272 {\r
 273         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 274         if (State == PhyDM_IGNORE_EDCCA) {\r
 275                 ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 1);     /*ignore EDCCA  reg520[15]=1*/\r
 276                 ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 0);                  /*reg524[11]=0*/\r
 277         } else {        /*don't set MAC ignore EDCCA signal*/\r
 278                 ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 0);     /*don't ignore EDCCA     reg520[15]=0\14*/\r
 279                 ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 1);                  /*reg524[11]=1  */\r
 280         }\r
 281         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("EDCCA enable State = %d\n", State));\r
 282 \r
 283 }\r
 284 \r
 285 BOOLEAN\r
 286 Phydm_CalNHMcnt(\r
 287         IN              PVOID           pDM_VOID\r
 288 )\r
 289 {\r
 290         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 291         u2Byte                  Base = 0;\r
 292 \r
 293         Base = pDM_Odm->NHM_cnt_0 + pDM_Odm->NHM_cnt_1;\r
 294 \r
 295         if (Base != 0) {\r
 296                 pDM_Odm->NHM_cnt_0 = ((pDM_Odm->NHM_cnt_0) << 8) / Base;\r
 297                 pDM_Odm->NHM_cnt_1 = ((pDM_Odm->NHM_cnt_1) << 8) / Base;\r
 298         }\r
 299         if ((pDM_Odm->NHM_cnt_0 - pDM_Odm->NHM_cnt_1) >= 100)\r
 300                 return TRUE;                    /*clean environment*/\r
 301         else\r
 302                 return FALSE;           /*noisy environment*/\r
 303 \r
 304 }\r
 305 \r
 306 \r
 307 VOID\r
 308 Phydm_CheckEnvironment(\r
 309         IN      PVOID   pDM_VOID\r
 310 )\r
 311 {\r
 312         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 313         PADAPTIVITY_STATISTICS  Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);\r
 314         BOOLEAN         isCleanEnvironment = FALSE;\r
 315 \r
 316         if (Adaptivity->bFirstLink == TRUE) {\r
 317                 if (pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8195A))\r
 318                         pDM_Odm->adaptivity_flag = FALSE;\r
 319                 else\r
 320                         pDM_Odm->adaptivity_flag = TRUE;\r
 321 \r
 322                 Adaptivity->bFirstLink = FALSE;\r
 323                 return;\r
 324         } else {\r
 325                 if (Adaptivity->NHMWait < 3) {          /*Start enter NHM after 4 NHMWait*/\r
 326                         Adaptivity->NHMWait++;\r
 327                         Phydm_NHMCounterStatistics(pDM_Odm);\r
 328                         return;\r
 329                 } else {\r
 330                         Phydm_NHMCounterStatistics(pDM_Odm);\r
 331                         isCleanEnvironment = Phydm_CalNHMcnt(pDM_Odm);\r
 332                         if (isCleanEnvironment == TRUE) {\r
 333 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
 334                                 pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup;                       /*mode 1*/\r
 335                                 pDM_Odm->TH_EDCCA_HL_diff = Adaptivity->TH_EDCCA_HL_diff_backup;\r
 336 #endif\r
 337                                 pDM_Odm->Adaptivity_enable = TRUE;\r
 338 \r
 339                                 if (pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8195A))\r
 340                                         pDM_Odm->adaptivity_flag = FALSE;\r
 341                                 else\r
 342                                         pDM_Odm->adaptivity_flag = TRUE;\r
 343                         } else {\r
 344 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))\r
 345                                 Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f);\r
 346 #else\r
 347                                 pDM_Odm->TH_L2H_ini = Adaptivity->TH_L2H_ini_mode2;                     /*for AP mode 2*/\r
 348                                 pDM_Odm->TH_EDCCA_HL_diff = Adaptivity->TH_EDCCA_HL_diff_mode2;\r
 349 #endif\r
 350                                 pDM_Odm->adaptivity_flag = FALSE;\r
 351                                 pDM_Odm->Adaptivity_enable = FALSE;\r
 352                         }\r
 353                         Adaptivity->NHMWait = 0;\r
 354                         Adaptivity->bFirstLink = TRUE;\r
 355                         Adaptivity->bCheck = TRUE;\r
 356                 }\r
 357 \r
 358         }\r
 359 \r
 360 \r
 361 }\r
 362 \r
 363 VOID\r
 364 Phydm_SearchPwdBLowerBound(\r
 365         IN              PVOID           pDM_VOID\r
 366 )\r
 367 {\r
 368         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 369         PADAPTIVITY_STATISTICS  Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);\r
 370         u4Byte                  value32 = 0;\r
 371         u1Byte                  cnt, IGI_Pause = 0x7f, IGI_Resume = 0x20, IGI = 0x45;           /*IGI = 0x50 for cal EDCCA lower bound*/\r
 372         u1Byte                  txEdcca1 = 0, txEdcca0 = 0;\r
 373         BOOLEAN                 bAdjust = TRUE;\r
 374         s1Byte                  TH_L2H_dmc, TH_H2L_dmc, IGI_target = 0x32;\r
 375         s1Byte                  Diff;\r
 376 \r
 377         Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);\r
 378         ODM_Write_DIG(pDM_Odm, IGI_Pause);\r
 379 \r
 380         Diff = IGI_target - (s1Byte)IGI;\r
 381         TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;\r
 382         if (TH_L2H_dmc > 10)\r
 383                 TH_L2H_dmc = 10;\r
 384         TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;\r
 385 \r
 386         Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);\r
 387         ODM_delay_ms(5);\r
 388 \r
 389         while (bAdjust) {\r
 390                 for (cnt = 0; cnt < 20; cnt++) {\r
 391                         if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
 392                                 value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11N, bMaskDWord);\r
 393 #if (RTL8195A_SUPPORT == 0)\r
 394                         else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
 395                                 value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC, bMaskDWord);\r
 396 #endif\r
 397                         if (value32 & BIT30 && (pDM_Odm->SupportICType & (ODM_RTL8723A | ODM_RTL8723B | ODM_RTL8188E)))\r
 398                                 txEdcca1 = txEdcca1 + 1;\r
 399                         else if (value32 & BIT29)\r
 400                                 txEdcca1 = txEdcca1 + 1;\r
 401                         else\r
 402                                 txEdcca0 = txEdcca0 + 1;\r
 403                 }\r
 404 \r
 405                 if (txEdcca1 > 1) {\r
 406                         IGI = IGI - 1;\r
 407                         TH_L2H_dmc = TH_L2H_dmc + 1;\r
 408                         if (TH_L2H_dmc > 10)\r
 409                                 TH_L2H_dmc = 10;\r
 410                         TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;\r
 411 \r
 412                         Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);\r
 413                         if (TH_L2H_dmc == 10) {\r
 414                                 bAdjust = FALSE;\r
 415                                 Adaptivity->H2L_lb = TH_H2L_dmc;\r
 416                                 Adaptivity->L2H_lb = TH_L2H_dmc;\r
 417                                 pDM_Odm->Adaptivity_IGI_upper = IGI;\r
 418                         }\r
 419 \r
 420                         txEdcca1 = 0;\r
 421                         txEdcca0 = 0;\r
 422 \r
 423                 } else {\r
 424                         bAdjust = FALSE;\r
 425                         Adaptivity->H2L_lb = TH_H2L_dmc;\r
 426                         Adaptivity->L2H_lb = TH_L2H_dmc;\r
 427                         pDM_Odm->Adaptivity_IGI_upper = IGI;\r
 428                         txEdcca1 = 0;\r
 429                         txEdcca0 = 0;\r
 430                 }\r
 431         }\r
 432 \r
 433         pDM_Odm->Adaptivity_IGI_upper = pDM_Odm->Adaptivity_IGI_upper - pDM_Odm->DCbackoff;\r
 434         Adaptivity->H2L_lb = Adaptivity->H2L_lb + pDM_Odm->DCbackoff;\r
 435         Adaptivity->L2H_lb = Adaptivity->L2H_lb + pDM_Odm->DCbackoff;\r
 436 \r
 437         Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE);\r
 438         ODM_Write_DIG(pDM_Odm, IGI_Resume);\r
 439         Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f);                           /*resume to no link state*/\r
 440 }\r
 441 \r
 442 VOID\r
 443 Phydm_AdaptivityInit(\r
 444         IN      PVOID           pDM_VOID\r
 445 )\r
 446 {\r
 447         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 448         PADAPTIVITY_STATISTICS  Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);\r
 449 #if(DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 450         PADAPTER                pAdapter        = pDM_Odm->Adapter;\r
 451         PMGNT_INFO              pMgntInfo = &(pAdapter->MgntInfo);\r
 452         pDM_Odm->Carrier_Sense_enable = (BOOLEAN)pMgntInfo->RegEnableCarrierSense;\r
 453         pDM_Odm->DCbackoff = (u1Byte)pMgntInfo->RegDCbackoff;\r
 454         Adaptivity->DynamicLinkAdaptivity = (BOOLEAN)pMgntInfo->RegDmLinkAdaptivity;\r
 455         Adaptivity->APNumTH = (u1Byte)pMgntInfo->RegAPNumTH;\r
 456 #elif(DM_ODM_SUPPORT_TYPE == ODM_CE)\r
 457         pDM_Odm->Carrier_Sense_enable = (pDM_Odm->Adapter->registrypriv.adaptivity_mode != 0) ? TRUE : FALSE;\r
 458         pDM_Odm->DCbackoff = pDM_Odm->Adapter->registrypriv.adaptivity_dc_backoff;\r
 459         Adaptivity->DynamicLinkAdaptivity = (pDM_Odm->Adapter->registrypriv.adaptivity_dml != 0) ? TRUE : FALSE;\r
 460 #endif\r
 461 \r
 462 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))\r
 463 \r
 464         if (pDM_Odm->Carrier_Sense_enable == FALSE) {\r
 465 #if(DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 466                 if (pMgntInfo->RegL2HForAdaptivity != 0)\r
 467                         pDM_Odm->TH_L2H_ini = pMgntInfo->RegL2HForAdaptivity;\r
 468                 else\r
 469 #endif\r
 470                 {\r
 471                         pDM_Odm->TH_L2H_ini = 0xf5;\r
 472                 }\r
 473         } else {\r
 474 #if(DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 475                 if (pMgntInfo->RegL2HForAdaptivity != 0)\r
 476                         pDM_Odm->TH_L2H_ini = pMgntInfo->RegL2HForAdaptivity;\r
 477                 else\r
 478 #endif\r
 479                         pDM_Odm->TH_L2H_ini = 0xa;\r
 480         }\r
 481 \r
 482 #if(DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 483         if (pMgntInfo->RegHLDiffForAdaptivity != 0)\r
 484                 pDM_Odm->TH_EDCCA_HL_diff = pMgntInfo->RegHLDiffForAdaptivity;\r
 485         else\r
 486 #endif\r
 487                 pDM_Odm->TH_EDCCA_HL_diff = 7;\r
 488 \r
 489         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("TH_L2H_ini = 0x%x, TH_EDCCA_HL_diff = 0x%x\n", pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff));\r
 490 \r
 491 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
 492         prtl8192cd_priv priv = pDM_Odm->priv;\r
 493 \r
 494         if (pDM_Odm->Carrier_Sense_enable) {\r
 495                 pDM_Odm->TH_L2H_ini = 0xa;\r
 496                 pDM_Odm->TH_EDCCA_HL_diff = 7;\r
 497         } else {\r
 498                 pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup;       /*set by mib*/\r
 499                 pDM_Odm->TH_EDCCA_HL_diff = 7;\r
 500         }\r
 501 \r
 502         Adaptivity->TH_L2H_ini_mode2 = 20;\r
 503         Adaptivity->TH_EDCCA_HL_diff_mode2 = 8;\r
 504         Adaptivity->TH_EDCCA_HL_diff_backup = pDM_Odm->TH_EDCCA_HL_diff;\r
 505         if (priv->pshare->rf_ft_var.adaptivity_enable == 2)\r
 506                 Adaptivity->DynamicLinkAdaptivity = TRUE;\r
 507         else\r
 508                 Adaptivity->DynamicLinkAdaptivity = FALSE;\r
 509 \r
 510 #endif\r
 511 \r
 512         pDM_Odm->Adaptivity_IGI_upper = 0;\r
 513         pDM_Odm->Adaptivity_enable = FALSE;     /*use this flag to decide enable or disable*/\r
 514         \r
 515         Adaptivity->IGI_Base = 0x32;\r
 516         Adaptivity->IGI_target = 0x1c;\r
 517         Adaptivity->H2L_lb = 0;\r
 518         Adaptivity->L2H_lb = 0;\r
 519         Adaptivity->NHMWait = 0;\r
 520         Adaptivity->bCheck = FALSE;\r
 521         Adaptivity->bFirstLink = TRUE;\r
 522 \r
 523         Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);\r
 524 \r
 525         /*Search pwdB lower bound*/\r
 526         if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
 527                 ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11N, bMaskDWord, 0x208);\r
 528 #if (RTL8195A_SUPPORT == 0)\r
 529         else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
 530                 ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC, bMaskDWord, 0x209);\r
 531 #endif\r
 532 \r
 533 #if (RTL8195A_SUPPORT == 1)\r
 534         if (pDM_Odm->SupportICType & ODM_RTL8195A) {\r
 535                 ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DOWN_OPT_11N, BIT12 | BIT11 | BIT10, 0x7);          /*interfernce need > 2^x us, and then EDCCA will be 1*/\r
 536                 ODM_SetBBReg(pDM_Odm, DOM_REG_EDCCA_DCNF_11N, BIT21 | BIT20, 0x1);              /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/\r
 537         }\r
 538 #else\r
 539         if (pDM_Odm->SupportICType & ODM_RTL8814A) {            /*8814a no need to find pwdB lower bound, maybe*/\r
 540                 ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DOWN_OPT, BIT30 | BIT29 | BIT28, 0x7);              /*interfernce need > 2^x us, and then EDCCA will be 1*/\r
 541                 ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_POWER_CAL, BIT5, 1);                                                /*0:mean, 1:max pwdB*/\r
 542                 ODM_SetBBReg(pDM_Odm, ODM_REG_ACBB_EDCCA_ENHANCE, BIT29 | BIT28, 0x1);          /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/\r
 543         } else\r
 544                 Phydm_SearchPwdBLowerBound(pDM_Odm);\r
 545 #endif\r
 546 \r
 547 }\r
 548 \r
 549 \r
 550 VOID\r
 551 Phydm_Adaptivity(\r
 552         IN              PVOID                   pDM_VOID,\r
 553         IN              u1Byte                  IGI\r
 554 )\r
 555 {\r
 556         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 557         s1Byte                  TH_L2H_dmc, TH_H2L_dmc;\r
 558         s1Byte                  Diff, IGI_target;\r
 559         PADAPTIVITY_STATISTICS  Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);\r
 560 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 561         PADAPTER                pAdapter        = pDM_Odm->Adapter;\r
 562         BOOLEAN                 bFwCurrentInPSMode = FALSE;\r
 563         PMGNT_INFO              pMgntInfo = &(pAdapter->MgntInfo);\r
 564 \r
 565         pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));\r
 566 \r
 567         /*Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.*/\r
 568         if (bFwCurrentInPSMode)\r
 569                 return;\r
 570 #endif\r
 571 \r
 572         if (!(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY)) {\r
 573                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Go to odm_DynamicEDCCA()\n"));\r
 574                 /*Add by Neil Chen to enable edcca to MP Platform */\r
 575 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 576                 /*Adjust EDCCA.*/\r
 577                 if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
 578                         Phydm_DynamicEDCCA(pDM_Odm);\r
 579 #endif\r
 580                 return;\r
 581         }\r
 582         \r
 583 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 584         if (Phydm_CheckChannelPlan(pDM_Odm))\r
 585                 return;\r
 586         if (pDM_Odm->APTotalNum > Adaptivity->APNumTH)\r
 587                 return;\r
 588 #endif\r
 589 \r
 590         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("odm_Adaptivity() =====>\n"));\r
 591         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d\n",\r
 592                          Adaptivity->IGI_Base, pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff));\r
 593 #if (RTL8195A_SUPPORT == 0)\r
 594         if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {\r
 595                 /*fix AC series when enable EDCCA hang issue*/\r
 596                 ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 1); /*ADC_mask disable*/\r
 597                 ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 0); /*ADC_mask enable*/\r
 598         }\r
 599 #endif\r
 600         if (*pDM_Odm->pBandWidth == ODM_BW20M)          /*CHANNEL_WIDTH_20*/\r
 601                 IGI_target = Adaptivity->IGI_Base;\r
 602         else if (*pDM_Odm->pBandWidth == ODM_BW40M)\r
 603                 IGI_target = Adaptivity->IGI_Base + 2;\r
 604 #if (RTL8195A_SUPPORT == 0)\r
 605         else if (*pDM_Odm->pBandWidth == ODM_BW80M)\r
 606                 IGI_target = Adaptivity->IGI_Base + 2;\r
 607 #endif\r
 608         else\r
 609                 IGI_target = Adaptivity->IGI_Base;\r
 610         Adaptivity->IGI_target = (u1Byte) IGI_target;\r
 611 \r
 612         if (*pDM_Odm->pChannel >= 149) {                        /*Band4 -> for AP : mode2*/\r
 613 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 614         s1Byte  L2H_nolink_Band4 = 0x7f, H2L_nolink_Band4 = 0x7f;\r
 615                 if (pDM_Odm->bLinked) {\r
 616                         if (pDM_Odm->SupportICType & ODM_RTL8814A) {\r
 617                                 L2H_nolink_Band4 = (s1Byte)Adaptivity->TH_L2H_ini_mode2 + IGI_target;\r
 618                                 H2L_nolink_Band4 = L2H_nolink_Band4 - Adaptivity->TH_EDCCA_HL_diff_mode2;\r
 619                         } else {\r
 620                                 Diff = IGI_target - (s1Byte)IGI;\r
 621                                 L2H_nolink_Band4 = Adaptivity->TH_L2H_ini_mode2 + Diff;\r
 622                                 if (L2H_nolink_Band4 > 10)\r
 623                                         L2H_nolink_Band4 = 10;\r
 624                                 H2L_nolink_Band4 = L2H_nolink_Band4 - Adaptivity->TH_EDCCA_HL_diff_mode2;\r
 625                         }\r
 626                 } else {\r
 627                         L2H_nolink_Band4 = 0x7f;\r
 628                         H2L_nolink_Band4 = 0x7f;\r
 629                 }\r
 630                 Phydm_SetEDCCAThreshold(pDM_Odm, H2L_nolink_Band4, L2H_nolink_Band4);\r
 631                 return;\r
 632 #endif\r
 633         }\r
 634 \r
 635         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("BandWidth=%s, IGI_target=0x%x, DynamicLinkAdaptivity = %d\n",\r
 636                          (*pDM_Odm->pBandWidth == ODM_BW80M) ? "80M" : ((*pDM_Odm->pBandWidth == ODM_BW40M) ? "40M" : "20M"), IGI_target, Adaptivity->DynamicLinkAdaptivity));\r
 637         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("RSSI_min = %d, AdapIGIUpper= 0x%x, adaptivity_flag = %d, Adaptivity_enable = %d\n",\r
 638                          pDM_Odm->RSSI_Min, pDM_Odm->Adaptivity_IGI_upper, pDM_Odm->adaptivity_flag, pDM_Odm->Adaptivity_enable));\r
 639 \r
 640         if ((Adaptivity->DynamicLinkAdaptivity == TRUE) && (!pDM_Odm->bLinked) && (pDM_Odm->Adaptivity_enable == FALSE)) {\r
 641                 Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f);\r
 642                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("In DynamicLink mode(noisy) and No link, Turn off EDCCA!!\n"));\r
 643                 return;\r
 644         }\r
 645 #if (!(DM_ODM_SUPPORT_TYPE & ODM_AP))\r
 646         else if ((Adaptivity->DynamicLinkAdaptivity == TRUE) && (pDM_Odm->Adaptivity_enable == FALSE)) {\r
 647                 Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f);\r
 648                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("In DynamicLink mode(noisy) disable EDCCA, return!!\n"));\r
 649                 return;\r
 650         }\r
 651 #endif\r
 652 \r
 653         if (pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8195A)) {\r
 654                 TH_L2H_dmc = (s1Byte)pDM_Odm->TH_L2H_ini + IGI_target;\r
 655                 TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;\r
 656         }\r
 657 #if (RTL8195A_SUPPORT == 0)\r
 658         else    {\r
 659                 Diff = IGI_target - (s1Byte)IGI;\r
 660                 TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;\r
 661                 if (TH_L2H_dmc > 10)\r
 662                         TH_L2H_dmc = 10;\r
 663 \r
 664                 TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;\r
 665 \r
 666                 /*replace lower bound to prevent EDCCA always equal 1*/\r
 667                 if (TH_H2L_dmc < Adaptivity->H2L_lb)\r
 668                         TH_H2L_dmc = Adaptivity->H2L_lb;\r
 669                 if (TH_L2H_dmc < Adaptivity->L2H_lb)\r
 670                         TH_L2H_dmc = Adaptivity->L2H_lb;\r
 671         }\r
 672 #endif\r
 673         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n", IGI, TH_L2H_dmc, TH_H2L_dmc));\r
 674         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity_IGI_upper=0x%x, H2L_lb = 0x%x, L2H_lb = 0x%x\n", pDM_Odm->Adaptivity_IGI_upper, Adaptivity->H2L_lb, Adaptivity->L2H_lb));\r
 675 \r
 676         Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);\r
 677         return;\r
 678 }\r
 679 \r
 680 \r
 681 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 682 \r
 683 VOID\r
 684 Phydm_AdaptivityBSOD(\r
 685         IN              PVOID           pDM_VOID\r
 686 )\r
 687 {\r
 688         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 689         PADAPTER                pAdapter = pDM_Odm->Adapter;\r
 690         PMGNT_INFO              pMgntInfo = &(pAdapter->MgntInfo);\r
 691         u1Byte                  count = 0;\r
 692         u4Byte                  u4Value;\r
 693 \r
 694         /*\r
 695         1. turn off RF (TRX Mux in standby mode)\r
 696         2. H2C mac id drop\r
 697         3. ignore EDCCA\r
 698         4. wait for clear FIFO\r
 699         5. don't ignore EDCCA\r
 700         6. turn on RF (TRX Mux in TRx mdoe)\r
 701         7. H2C mac id resume\r
 702         */\r
 703 \r
 704         RT_TRACE(COMP_MLME, DBG_WARNING, ("MAC id drop packet!!!!!\n"));\r
 705 \r
 706         pAdapter->dropPktByMacIdCnt++;\r
 707         pMgntInfo->bDropPktInProgress = TRUE;\r
 708 \r
 709         pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_MAX_Q_PAGE_NUM, (pu1Byte)(&u4Value));\r
 710         RT_TRACE(COMP_INIT, DBG_LOUD, ("Queue Reserved Page Number = 0x%08x\n", u4Value));\r
 711         pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_AVBL_Q_PAGE_NUM, (pu1Byte)(&u4Value));\r
 712         RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page Number = 0x%08x\n", u4Value));\r
 713 \r
 714 #if 1\r
 715 \r
 716         /*Standby mode*/\r
 717         Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);\r
 718         ODM_Write_DIG(pDM_Odm, 0x20);\r
 719 \r
 720         /*H2C mac id drop*/\r
 721         MacIdIndicateDisconnect(pAdapter);\r
 722 \r
 723         /*Ignore EDCCA*/\r
 724         Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);\r
 725 \r
 726         delay_ms(50);\r
 727         count = 5;\r
 728 \r
 729 #else\r
 730 \r
 731         do {\r
 732 \r
 733                 u8Byte          diffTime, curTime, oldestTime;\r
 734                 u1Byte          queueIdx\r
 735 \r
 736                 //3 Standby mode\r
 737                 Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);\r
 738                 ODM_Write_DIG(pDM_Odm, 0x20);\r
 739 \r
 740                 //3 H2C mac id drop\r
 741                 MacIdIndicateDisconnect(pAdapter);\r
 742 \r
 743                 //3 Ignore EDCCA\r
 744                 Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);\r
 745 \r
 746                 count++;\r
 747                 delay_ms(10);\r
 748 \r
 749                 // Check latest packet\r
 750                 curTime = PlatformGetCurrentTime();\r
 751                 oldestTime = 0xFFFFFFFFFFFFFFFF;\r
 752 \r
 753                 for (queueIdx = 0; queueIdx < MAX_TX_QUEUE; queueIdx++) {\r
 754                         if (!IS_DATA_QUEUE(queueIdx))\r
 755                                 continue;\r
 756 \r
 757                         if (!pAdapter->bTcbBusyQEmpty[queueIdx]) {\r
 758                                 RT_TRACE(COMP_MLME, DBG_WARNING, ("oldestTime = %llu\n", oldestTime));\r
 759                                 RT_TRACE(COMP_MLME, DBG_WARNING, ("Q[%d] = %llu\n", queueIdx, pAdapter->firstTcbSysTime[queueIdx]));\r
 760                                 if (pAdapter->firstTcbSysTime[queueIdx] < oldestTime)\r
 761                                         oldestTime = pAdapter->firstTcbSysTime[queueIdx];\r
 762                         }\r
 763                 }\r
 764 \r
 765                 diffTime = curTime - oldestTime;\r
 766 \r
 767                 RT_TRACE(COMP_MLME, DBG_WARNING, ("diff s = %llu\n", (diffTime / 1000000)));\r
 768 \r
 769         } while (((diffTime / 1000000) >= 4) && (oldestTime != 0xFFFFFFFFFFFFFFFF));\r
 770 #endif\r
 771 \r
 772         /*Resume EDCCA*/\r
 773         Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);\r
 774 \r
 775         /*Turn on TRx mode*/\r
 776         Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE);\r
 777         ODM_Write_DIG(pDM_Odm, 0x20);\r
 778 \r
 779         /*Resume H2C macid*/\r
 780         MacIdRecoverMediaStatus(pAdapter);\r
 781 \r
 782         pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_AVBL_Q_PAGE_NUM, (pu1Byte)(&u4Value));\r
 783         RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page Number = 0x%08x\n", u4Value));\r
 784 \r
 785         pMgntInfo->bDropPktInProgress = FALSE;\r
 786         RT_TRACE(COMP_MLME, DBG_WARNING, ("End of MAC id drop packet, spent %dms\n", count * 10));\r
 787 \r
 788 }\r
 789 \r
 790 VOID\r
 791 Phydm_EnableEDCCA(\r
 792         IN              PVOID                                   pDM_VOID\r
 793 )\r
 794 {\r
 795 \r
 796         /*This should be moved out of OUTSRC*/\r
 797         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 798         PADAPTER                pAdapter        = pDM_Odm->Adapter;\r
 799         /*Enable EDCCA. The value is suggested by SD3 Wilson.*/\r
 800 \r
 801         /*Revised for ASUS 11b/g performance issues, suggested by BB Neil, 2012.04.13.*/\r
 802         if ((pDM_Odm->SupportICType == ODM_RTL8723A) && (IS_WIRELESS_MODE_G(pAdapter))) {\r
 803                 ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold, 0x00);\r
 804                 ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold + 2, 0xFD);\r
 805         } else {\r
 806                 ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold, 0x03);\r
 807                 ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold + 2, 0x00);\r
 808         }\r
 809 }\r
 810 \r
 811 VOID\r
 812 Phydm_DisableEDCCA(\r
 813         IN              PVOID                                   pDM_VOID\r
 814 )\r
 815 {\r
 816         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 817         ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold, 0x7f);\r
 818         ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold + 2, 0x7f);\r
 819 }\r
 820 \r
 821 VOID\r
 822 Phydm_DynamicEDCCA(\r
 823         IN              PVOID                                   pDM_VOID\r
 824 )\r
 825 {\r
 826         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 827         PADAPTER                pAdapter        = pDM_Odm->Adapter;\r
 828         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 829         u1Byte                  RegC50, RegC58;\r
 830 \r
 831 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
 832         BOOLEAN                 bFwCurrentInPSMode = FALSE;\r
 833 \r
 834         pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));\r
 835 \r
 836         /*Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.*/\r
 837         if (bFwCurrentInPSMode)\r
 838                 return;\r
 839 #endif\r
 840 \r
 841         /*2013/11/14 Ken According to BB team Jame's suggestion, we need to disable soft AP mode EDCCA.*/\r
 842         /*2014/01/08 MH For Miracst AP mode test. We need to disable EDCCA. Otherwise, we may stop*/\r
 843         /*to send beacon in noisy environment or platform.*/\r
 844 \r
 845         if (ACTING_AS_AP(pAdapter) || ACTING_AS_AP(GetFirstAPAdapter(pAdapter))) {\r
 846                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("At least One Port as AP disable EDCCA\n"));\r
 847                 Phydm_DisableEDCCA(pDM_Odm);\r
 848                 if (pHalData->bPreEdccaEnable)\r
 849                         Phydm_DisableEDCCA(pDM_Odm);\r
 850                 pHalData->bPreEdccaEnable = FALSE;\r
 851                 return;\r
 852         }\r
 853 \r
 854         RegC50 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0);\r
 855         RegC58 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0);\r
 856 \r
 857 \r
 858         if ((RegC50 > 0x28 && RegC58 > 0x28) ||\r
 859             ((pDM_Odm->SupportICType == ODM_RTL8723A && IS_WIRELESS_MODE_G(pAdapter) && RegC50 > 0x26)) ||\r
 860             (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 > 0x28)) {\r
 861                 if (!pHalData->bPreEdccaEnable) {\r
 862                         Phydm_EnableEDCCA(pDM_Odm);\r
 863                         pHalData->bPreEdccaEnable = TRUE;\r
 864                 }\r
 865 \r
 866         } else if ((RegC50 < 0x25 && RegC58 < 0x25) || (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 < 0x25)) {\r
 867                 if (pHalData->bPreEdccaEnable) {\r
 868                         Phydm_DisableEDCCA(pDM_Odm);\r
 869                         pHalData->bPreEdccaEnable = FALSE;\r
 870                 }\r
 871         }\r
 872 }\r
 873 \r
 874 #endif\r