2 * Broadcom HND chip & on-chip-interconnect-related definitions.
4 * Copyright (C) 1999-2016, Broadcom Corporation
6 * Unless you and Broadcom execute a separate written software license
7 * agreement governing use of this software, this software is licensed to you
8 * under the terms of the GNU General Public License version 2 (the "GPL"),
9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
10 * following added to such license:
12 * As a special exception, the copyright holders of this software give you
13 * permission to link this software with independent modules, and to copy and
14 * distribute the resulting executable under terms of your choice, provided that
15 * you also meet, for each linked independent module, the terms and conditions of
16 * the license of that module. An independent module is a module which is not
17 * derived from this software. The special exception does not apply to any
18 * modifications of the software.
20 * Notwithstanding the above, under no circumstances may you combine this
21 * software in any way with any other Broadcom software provided under a license
22 * other than the GPL, without Broadcom's express prior written consent.
25 * <<Broadcom-WL-IPTag/Open:>>
27 * $Id: hndsoc.h 517544 2014-11-26 00:40:42Z $
33 /* Include the soci specific files */
38 * SOC Interconnect Address Map.
39 * All regions may not exist on all chips.
41 #define SI_SDRAM_BASE 0x00000000 /* Physical SDRAM */
42 #define SI_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
43 #define SI_PCI_MEM_SZ (64 * 1024 * 1024)
44 #define SI_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
45 #define SI_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
46 #define SI_SDRAM_R2 0x80000000 /* Region 2 for sdram (512 MB) */
48 #define SI_ENUM_BASE 0x18000000 /* Enumeration space base */
50 #define SI_WRAP_BASE 0x18100000 /* Wrapper space base */
51 #define SI_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
54 #define SI_MAXCORES 32 /* NorthStar has more cores */
55 #endif /* SI_MAXCORES */
57 #define SI_MAXBR 4 /* Max bridges (this is arbitrary, for software
58 * convenience and could be changed if we
59 * make any larger chips
62 #define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */
63 #define SI_FASTRAM_SWAPPED 0x19800000
65 #define SI_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
66 #define SI_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
67 #define SI_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */
68 #define SI_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
69 #define SI_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
70 #define SI_FLASH_WINDOW 0x01000000 /* Flash XIP Window */
72 #define SI_NS_NANDFLASH 0x1c000000 /* NorthStar NAND flash base */
73 #define SI_NS_NORFLASH 0x1e000000 /* NorthStar NOR flash base */
74 #define SI_NS_ROM 0xfffd0000 /* NorthStar ROM */
75 #define SI_NS_FLASH_WINDOW 0x02000000 /* Flash XIP Window */
77 #define SI_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */
78 #define SI_ARMCR4_ROM 0x000f0000 /* ARM Cortex-R4 ROM */
79 #define SI_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */
80 #define SI_ARM7S_SRAM2 0x80000000 /* ARM7TDMI-S SRAM Region 2 */
81 #define SI_ARMCA7_ROM 0x00000000 /* ARM Cortex-A7 ROM */
82 #define SI_ARMCA7_RAM 0x00200000 /* ARM Cortex-A7 RAM */
83 #define SI_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */
84 #define SI_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */
86 #define SI_SFLASH 0x14000000
87 #define SI_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
88 #define SI_PCI_DMA2 0x80000000 /* Client Mode sb2pcitranslation2 (1 GB) */
89 #define SI_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
90 #define SI_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2
91 * (2 ZettaBytes), low 32 bits
93 #define SI_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2
94 * (2 ZettaBytes), high 32 bits
97 #define SI_BCM53573_NANDFLASH 0x30000000 /* 53573 NAND flash base */
98 #define SI_BCM53573_NORFLASH 0x1c000000 /* 53573 NOR flash base */
100 #define SI_BCM53573_NORFLASH_WINDOW 0x01000000 /* only support 16M direct access for
101 * 3-byte address modes in spi flash
103 #define SI_BCM53573_BOOTDEV_MASK 0x3
104 #define SI_BCM53573_BOOTDEV_NOR 0x0
106 #define SI_BCM53573_DDRTYPE_MASK 0x10
107 #define SI_BCM53573_DDRTYPE_DDR3 0x10
109 /* APB bridge code */
110 #define APB_BRIDGE_ID 0x135 /* APB Bridge 0, 1, etc. */
113 #define NODEV_CORE_ID 0x700 /* Invalid coreid */
114 #define CC_CORE_ID 0x800 /* chipcommon core */
115 #define ILINE20_CORE_ID 0x801 /* iline20 core */
116 #define SRAM_CORE_ID 0x802 /* sram core */
117 #define SDRAM_CORE_ID 0x803 /* sdram core */
118 #define PCI_CORE_ID 0x804 /* pci core */
119 #define MIPS_CORE_ID 0x805 /* mips core */
120 #define ENET_CORE_ID 0x806 /* enet mac core */
121 #define CODEC_CORE_ID 0x807 /* v90 codec core */
122 #define USB_CORE_ID 0x808 /* usb 1.1 host/device core */
123 #define ADSL_CORE_ID 0x809 /* ADSL core */
124 #define ILINE100_CORE_ID 0x80a /* iline100 core */
125 #define IPSEC_CORE_ID 0x80b /* ipsec core */
126 #define UTOPIA_CORE_ID 0x80c /* utopia core */
127 #define PCMCIA_CORE_ID 0x80d /* pcmcia core */
128 #define SOCRAM_CORE_ID 0x80e /* internal memory core */
129 #define MEMC_CORE_ID 0x80f /* memc sdram core */
130 #define OFDM_CORE_ID 0x810 /* OFDM phy core */
131 #define EXTIF_CORE_ID 0x811 /* external interface core */
132 #define D11_CORE_ID 0x812 /* 802.11 MAC core */
133 #define APHY_CORE_ID 0x813 /* 802.11a phy core */
134 #define BPHY_CORE_ID 0x814 /* 802.11b phy core */
135 #define GPHY_CORE_ID 0x815 /* 802.11g phy core */
136 #define MIPS33_CORE_ID 0x816 /* mips3302 core */
137 #define USB11H_CORE_ID 0x817 /* usb 1.1 host core */
138 #define USB11D_CORE_ID 0x818 /* usb 1.1 device core */
139 #define USB20H_CORE_ID 0x819 /* usb 2.0 host core */
140 #define USB20D_CORE_ID 0x81a /* usb 2.0 device core */
141 #define SDIOH_CORE_ID 0x81b /* sdio host core */
142 #define ROBO_CORE_ID 0x81c /* roboswitch core */
143 #define ATA100_CORE_ID 0x81d /* parallel ATA core */
144 #define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */
145 #define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */
146 #define PCIE_CORE_ID 0x820 /* pci express core */
147 #define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */
148 #define SRAMC_CORE_ID 0x822 /* SRAM controller core */
149 #define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */
150 #define ARM11_CORE_ID 0x824 /* ARM 1176 core */
151 #define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */
152 #define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */
153 #define PMU_CORE_ID 0x827 /* PMU core */
154 #define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */
155 #define SDIOD_CORE_ID 0x829 /* SDIO device core */
156 #define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */
157 #define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */
158 #define MIPS74K_CORE_ID 0x82c /* mips 74k core */
159 #define GMAC_CORE_ID 0x82d /* Gigabit MAC core */
160 #define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */
161 #define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */
162 #define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */
163 #define SC_CORE_ID 0x831 /* shared common core */
164 #define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */
165 #define SPIH_CORE_ID 0x833 /* SPI host core */
166 #define I2S_CORE_ID 0x834 /* I2S core */
167 #define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */
168 #define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */
170 #define ACPHY_CORE_ID 0x83b /* Dot11 ACPHY */
171 #define PCIE2_CORE_ID 0x83c /* pci express Gen2 core */
172 #define USB30D_CORE_ID 0x83d /* usb 3.0 device core */
173 #define ARMCR4_CORE_ID 0x83e /* ARM CR4 CPU */
174 #define GCI_CORE_ID 0x840 /* GCI Core */
175 #define M2MDMA_CORE_ID 0x844 /* memory to memory dma */
176 #define CMEM_CORE_ID 0x846 /* CNDS DDR2/3 memory controller */
177 #define ARMCA7_CORE_ID 0x847 /* ARM CA7 CPU */
178 #define SYSMEM_CORE_ID 0x849 /* System memory core */
179 #define APB_BRIDGE_CORE_ID 0x135 /* APB bridge core ID */
180 #define AXI_CORE_ID 0x301 /* AXI/GPV core ID */
181 #define EROM_CORE_ID 0x366 /* EROM core ID */
182 #define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */
183 #define DEF_AI_COMP 0xfff /* Default component, in ai chips it maps all
184 * unused address ranges
187 #define CC_4706_CORE_ID 0x500 /* chipcommon core */
188 #define NS_PCIEG2_CORE_ID 0x501 /* PCIE Gen 2 core */
189 #define NS_DMA_CORE_ID 0x502 /* DMA core */
190 #define NS_SDIO3_CORE_ID 0x503 /* SDIO3 core */
191 #define NS_USB20_CORE_ID 0x504 /* USB2.0 core */
192 #define NS_USB30_CORE_ID 0x505 /* USB3.0 core */
193 #define NS_A9JTAG_CORE_ID 0x506 /* ARM Cortex A9 JTAG core */
194 #define NS_DDR23_CORE_ID 0x507 /* Denali DDR2/DDR3 memory controller */
195 #define NS_ROM_CORE_ID 0x508 /* ROM core */
196 #define NS_NAND_CORE_ID 0x509 /* NAND flash controller core */
197 #define NS_QSPI_CORE_ID 0x50a /* SPI flash controller core */
198 #define NS_CCB_CORE_ID 0x50b /* ChipcommonB core */
199 #define SOCRAM_4706_CORE_ID 0x50e /* internal memory core */
200 #define NS_SOCRAM_CORE_ID SOCRAM_4706_CORE_ID
201 #define ARMCA9_CORE_ID 0x510 /* ARM Cortex A9 core (ihost) */
202 #define NS_IHOST_CORE_ID ARMCA9_CORE_ID /* ARM Cortex A9 core (ihost) */
203 #define GMAC_COMMON_4706_CORE_ID 0x5dc /* Gigabit MAC core */
204 #define GMAC_4706_CORE_ID 0x52d /* Gigabit MAC core */
205 #define AMEMC_CORE_ID 0x52e /* DDR1/2 memory controller core */
206 #define ALTA_CORE_ID 0x534 /* I2S core */
207 #define DDR23_PHY_CORE_ID 0x5dd
209 #define SI_PCI1_MEM 0x40000000 /* Host Mode sb2pcitranslation0 (64 MB) */
210 #define SI_PCI1_CFG 0x44000000 /* Host Mode sb2pcitranslation1 (64 MB) */
211 #define SI_PCIE1_DMA_H32 0xc0000000 /* PCIE Client Mode sb2pcitranslation2
212 * (2 ZettaBytes), high 32 bits
214 #define CC_4706B0_CORE_REV 0x8000001f /* chipcommon core */
215 #define SOCRAM_4706B0_CORE_REV 0x80000005 /* internal memory core */
216 #define GMAC_4706B0_CORE_REV 0x80000000 /* Gigabit MAC core */
217 #define NS_PCIEG2_CORE_REV_B0 0x7 /* NS-B0 PCIE Gen 2 core rev */
219 /* There are TWO constants on all HND chips: SI_ENUM_BASE above,
220 * and chipcommon being the first core:
223 /* SOC Interconnect types (aka chip types) */
229 /* Common core control flags */
230 #define SICF_BIST_EN 0x8000
231 #define SICF_PME_EN 0x4000
232 #define SICF_CORE_BITS 0x3ffc
233 #define SICF_FGC 0x0002
234 #define SICF_CLOCK_EN 0x0001
236 /* Common core status flags */
237 #define SISF_BIST_DONE 0x8000
238 #define SISF_BIST_ERROR 0x4000
239 #define SISF_GATED_CLK 0x2000
240 #define SISF_DMA64 0x1000
241 #define SISF_CORE_BITS 0x0fff
243 /* Norstar core status flags */
244 #define SISF_NS_BOOTDEV_MASK 0x0003 /* ROM core */
245 #define SISF_NS_BOOTDEV_NOR 0x0000 /* ROM core */
246 #define SISF_NS_BOOTDEV_NAND 0x0001 /* ROM core */
247 #define SISF_NS_BOOTDEV_ROM 0x0002 /* ROM core */
248 #define SISF_NS_BOOTDEV_OFFLOAD 0x0003 /* ROM core */
249 #define SISF_NS_SKUVEC_MASK 0x000c /* ROM core */
251 /* A register that is common to all cores to
252 * communicate w/PMU regarding clock control.
254 #define SI_CLK_CTL_ST 0x1e0 /* clock control and status */
255 #define SI_PWR_CTL_ST 0x1e8 /* For memory clock gating */
257 /* clk_ctl_st register */
258 #define CCS_FORCEALP 0x00000001 /* force ALP request */
259 #define CCS_FORCEHT 0x00000002 /* force HT request */
260 #define CCS_FORCEILP 0x00000004 /* force ILP request */
261 #define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
262 #define CCS_HTAREQ 0x00000010 /* HT Avail Request */
263 #define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */
264 #define CCS_HQCLKREQ 0x00000040 /* HQ Clock Required */
265 #define CCS_USBCLKREQ 0x00000100 /* USB Clock Req */
266 #define CCS_SECICLKREQ 0x00000100 /* SECI Clock Req */
267 #define CCS_ARMFASTCLOCKREQ 0x00000100 /* ARM CR4/CA7 fast clock request */
268 #define CCS_AVBCLKREQ 0x00000400 /* AVB Clock enable request */
269 #define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */
270 #define CCS_ERSRC_REQ_SHIFT 8
271 #define CCS_ALPAVAIL 0x00010000 /* ALP is available */
272 #define CCS_HTAVAIL 0x00020000 /* HT is available */
273 #define CCS_BP_ON_APL 0x00040000 /* RO: Backplane is running on ALP clock */
274 #define CCS_BP_ON_HT 0x00080000 /* RO: Backplane is running on HT clock */
275 #define CCS_ARMFASTCLOCKSTATUS 0x01000000 /* Fast CPU clock is running */
276 #define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */
277 #define CCS_ERSRC_STS_SHIFT 24
279 #define CCS0_HTAVAIL 0x00010000 /* HT avail in chipc and pcmcia on 4328a0 */
280 #define CCS0_ALPAVAIL 0x00020000 /* ALP avail in chipc and pcmcia on 4328a0 */
282 /* Not really related to SOC Interconnect, but a couple of software
283 * conventions for the use the flash space:
286 /* Minumum amount of flash we support */
287 #define FLASH_MIN 0x00020000 /* Minimum flash size */
289 /* A boot/binary may have an embedded block that describes its size */
290 #define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
291 #define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
292 #define BISZ_MAGIC_IDX 0 /* Word 0: magic */
293 #define BISZ_TXTST_IDX 1 /* 1: text start */
294 #define BISZ_TXTEND_IDX 2 /* 2: text end */
295 #define BISZ_DATAST_IDX 3 /* 3: data start */
296 #define BISZ_DATAEND_IDX 4 /* 4: data end */
297 #define BISZ_BSSST_IDX 5 /* 5: bss start */
298 #define BISZ_BSSEND_IDX 6 /* 6: bss end */
299 #define BISZ_SIZE 7 /* descriptor size in 32-bit integers */
301 /* Boot/Kernel related defintion and functions */
302 #define SOC_BOOTDEV_ROM 0x00000001
303 #define SOC_BOOTDEV_PFLASH 0x00000002
304 #define SOC_BOOTDEV_SFLASH 0x00000004
305 #define SOC_BOOTDEV_NANDFLASH 0x00000008
307 #define SOC_KNLDEV_NORFLASH 0x00000002
308 #define SOC_KNLDEV_NANDFLASH 0x00000004
310 #if !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__)
311 int soc_boot_dev(void *sih);
312 int soc_knl_dev(void *sih);
313 #endif /* !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__) */
315 #endif /* _HNDSOC_H */