drivers/net/wireless/rockchip_wlan/esp8089/esp_driver/spi_sif_esp.c

   1 /*
   2  * Copyright (c) 2010 -2014 Espressif System.
   3  *
   4  *   spi serial i/f driver
   5  *    - sdio device control routines
   6  *    - sync/async DMA/PIO read/write
   7  *
   8  */
   9 #ifdef ESP_USE_SPI
  10
  11 #include <linux/module.h>
  12 #include <net/mac80211.h>
  13 #include <linux/time.h>
  14 #include <linux/pm.h>
  15 #include <linux/spi/spi.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/kthread.h>
  18
  19
  20 #include "esp_pub.h"
  21 #include "esp_sif.h"
  22 #include "esp_sip.h"
  23 #include "esp_debug.h"
  24 #include "slc_host_register.h"
  25 #include "esp_version.h"
  26 #include "esp_ctrl.h"
  27 #include "esp_file.h"
  28 #ifdef USE_EXT_GPIO
  29 #include "esp_ext.h"
  30 #endif /* USE_EXT_GPIO */
  31
  32
  33 #ifdef ESP_PREALLOC
  34 extern u8 *esp_get_lspi_buf(void);
  35 extern void esp_put_lspi_buf(u8 **p);
  36 #endif
  37
  38 #define SPI_BLOCK_SIZE              (512)
  39
  40 #define MAX_BUF_SIZE        (48*1024)
  41
  42 static unsigned char *buf_addr = NULL;
  43 static unsigned char *tx_cmd;
  44 static unsigned char *rx_cmd;
  45 static unsigned char *check_buf = NULL;
  46 static unsigned char *ff_buf = NULL;
  47
  48 unsigned int crc_ta_8[256]={
  49                                 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7,
  50                                 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef,
  51                                 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6,
  52                                 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de,
  53                                 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485,
  54                                 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d,
  55                                 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4,
  56                                 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc,
  57                                 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823,
  58                                 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b,
  59                                 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12,
  60                                 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a,
  61                                 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41,
  62                                 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49,
  63                                 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70,
  64                                 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78,
  65                                 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f,
  66                                 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067,
  67                                 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e,
  68                                 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256,
  69                                 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d,
  70                                 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
  71                                 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c,
  72                                 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634,
  73                                 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab,
  74                                 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3,
  75                                 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a,
  76                                 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92,
  77                                 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9,
  78                                 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1,
  79                                 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8,
  80                                 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0
  81                                 };
  82
  83
  84 unsigned int crc_cal_by_byte(unsigned char* ptr, int len)
  85 {
  86     unsigned short crc = 0;
  87
  88     while(len-- != 0)
  89     {
  90         unsigned int high = (unsigned int)(crc >> 8);
  91         crc <<= 8;
  92         crc ^= crc_ta_8[high^*ptr];
  93         ptr++;
  94     }
  95
  96     return crc;
  97 }
  98
  99 struct task_struct *sif_irq_thread;
 100
 101 #define ESP_DMA_IBUFSZ   2048
 102
 103 //unsigned int esp_msg_level = 0;
 104 unsigned int esp_msg_level = ESP_DBG_ERROR | ESP_SHOW;
 105
 106 static struct semaphore esp_powerup_sem;
 107
 108 static enum esp_sdio_state sif_sdio_state;
 109 struct esp_spi_ctrl *sif_sctrl = NULL;
 110 static struct esp_spi_resp spi_resp;
 111
 112 #ifdef ESP_ANDROID_LOGGER
 113 bool log_off = false;
 114 #endif /* ESP_ANDROID_LOGGER */
 115
 116 #ifdef REQUEST_RTC_IRQ
 117 extern int request_rtc_irq(void);
 118 #endif
 119
 120 #include "spi_stub.c"
 121
 122 struct esp_spi_resp *sif_get_spi_resp(void)
 123 {
 124     return &spi_resp;
 125 }
 126
 127 void sif_lock_bus(struct esp_pub *epub)
 128 {
 129         EPUB_FUNC_CHECK(epub, _exit);
 130
 131         spi_bus_lock(EPUB_TO_FUNC(epub)->master);
 132 _exit:
 133         return;
 134 }
 135
 136 void sif_unlock_bus(struct esp_pub *epub)
 137 {
 138         EPUB_FUNC_CHECK(epub, _exit);
 139
 140         spi_bus_unlock(EPUB_TO_FUNC(epub)->master);
 141 _exit:
 142         return;
 143 }
 144
 145 int sif_spi_write_then_read(struct spi_device *spi, unsigned char* bufwrite, int sizesend, unsigned char* bufread, int sizeread)
 146 {
 147         int error;
 148
 149         error = spi_write_then_read(spi, bufwrite,sizesend, bufread, sizeread);
 150
 151         if (error) {
 152                 esp_dbg(ESP_DBG_ERROR, "%s: failed, error: %d\n",
 153                         __func__, error);
 154                 return error;
 155         }
 156
 157         return 0;
 158 }
 159
 160 int sif_spi_write_async_read(struct spi_device *spi, unsigned char* bufwrite,unsigned char* bufread,int size)
 161 {
 162         struct spi_transfer xfer = {
 163               .rx_buf           = bufread,
 164                 .tx_buf         = bufwrite,
 165                 .len            = size,
 166                 .bits_per_word  = 8,
 167                 .speed_hz       = SPI_FREQ,
 168         };
 169         struct spi_message msg;
 170         int error;
 171
 172         spi_message_init(&msg);
 173         spi_message_add_tail(&xfer, &msg);
 174
 175         error = spi_sync_locked(spi, &msg);
 176         if (error) {
 177                 esp_dbg(ESP_DBG_ERROR, "spierr %s: failed, error: %d\n",
 178                         __func__, error);
 179                 return error;
 180         }
 181
 182         return 0;
 183 }
 184
 185 int sif_spi_write_raw(struct spi_device *spi, unsigned char* buf, int size)
 186 {
 187         int err;
 188         struct spi_transfer xfer = {
 189                 .tx_buf         = buf,
 190                 .len            = size,
 191                 .bits_per_word  = 8,
 192                 .speed_hz       = SPI_FREQ,
 193         };
 194         struct spi_message msg;
 195
 196         spi_message_init(&msg);
 197         spi_message_add_tail(&xfer, &msg);
 198
 199         err = spi_sync_locked(spi, &msg);
 200
 201         if (err) {
 202                 esp_dbg(ESP_DBG_ERROR, "%s: failed, error: %d\n",
 203                         __func__, err);
 204                 return err;
 205         }
 206
 207         return 0;
 208 }
 209
 210 int sif_spi_read_raw(struct spi_device *spi, unsigned char* buf, int size)
 211 {
 212         memset(buf,0xff,size);
 213         return sif_spi_write_async_read(spi,buf,buf,size);
 214 }
 215
 216 int sif_spi_write_bytes(struct spi_device *spi, unsigned int addr, unsigned char *src,int count, int dummymode)
 217 {
 218     int i;
 219     int pos,len;
 220     unsigned char *tx_data = (unsigned char*)src;
 221     int err_ret = 0;
 222     u32 timeout = 200;
 223     spi_resp.data_resp_size_w = ((((((count>>5)+1) *75)) +44)>>3) +1;
 224
 225     if (spi == NULL) {
 226         ESSERT(0);
 227         err_ret = -EINVAL;
 228         goto goto_err;
 229     }
 230
 231     if(count > 512 )
 232     {
 233         err_ret = -1;
 234         goto goto_err;
 235     }
 236
 237     tx_cmd[0]=0x75;
 238
 239     if( addr >= (1<<17) )
 240     {
 241         err_ret = -2;
 242         goto goto_err;
 243
 244     }
 245     else
 246     {
 247         tx_cmd[1]=0x90|0x04|(addr>>15);    //0x94;
 248         tx_cmd[2]=addr>>7;
 249
 250         if(count == 512 )
 251         {
 252             tx_cmd[3]=( addr<<1|0x0 );
 253             tx_cmd[4]= 0x00;     //0x08;
 254         }
 255         else
 256         {
 257             tx_cmd[3]=( addr<<1|(count>>8 & 0x01) );
 258             tx_cmd[4]= count & 0xff;     //0x08;
 259         }
 260     }
 261
 262     tx_cmd[5]=0x01;
 263     pos = 5+1;
 264
 265     //Add cmd respon
 266     memset(tx_cmd+pos,0xff,CMD_RESP_SIZE);
 267     pos =pos+ CMD_RESP_SIZE;
 268
 269     //Add token
 270     tx_cmd[pos]=0xFE;
 271     pos = pos+1;
 272
 273     //Add data
 274     memcpy(tx_cmd+pos,tx_data,count);
 275     pos = pos+count;
 276
 277     //Add data respon
 278     memset(tx_cmd+pos,0xff,spi_resp.data_resp_size_w);
 279     pos = pos+ spi_resp.data_resp_size_w ;
 280
 281
 282     if(pos <128)
 283     {
 284         len = 128-pos;
 285         memset(tx_cmd+pos,0xff,len);
 286     }
 287     else
 288     {
 289         if( pos%8 )
 290         {
 291             len = (8 - pos%8);
 292             memset(tx_cmd+pos,0xff,len);
 293         }
 294         else
 295             len = 0;
 296     }
 297
 298     sif_spi_write_async_read(spi, tx_cmd,tx_cmd,pos+len);
 299
 300     pos = 5+1;
 301     for(i=0;i<CMD_RESP_SIZE;i++)
 302     {
 303         if(tx_cmd[pos+i] == 0x00 && tx_cmd[pos+i-1] == 0xff)
 304         {
 305             if(tx_cmd[pos+i+1] == 0x00 && tx_cmd[pos+i+2] == 0xff)
 306                 break;
 307         }
 308     }
 309
 310     if(i>spi_resp.max_cmd_resp_size)
 311     {
 312         spi_resp.max_cmd_resp_size = i;
 313     }
 314
 315     if(i>=CMD_RESP_SIZE)
 316     {
 317         esp_dbg(ESP_DBG_ERROR, "byte write cmd resp 0x00 no recv\n");
 318         err_ret = -3;
 319         goto goto_err;
 320     }
 321
 322     pos = pos+CMD_RESP_SIZE+count+1;
 323     for(i=0;i<spi_resp.data_resp_size_w;i++)
 324     {
 325         if(tx_cmd[pos+i] == 0xE5)
 326         {
 327             //esp_dbg(ESP_DBG_ERROR, "0xE5 pos:%d",i);
 328             for(i++;i<spi_resp.data_resp_size_w ;i++)
 329             {
 330                 if( tx_cmd[pos+i] == 0xFF)
 331                 {
 332        //     esp_dbg(ESP_DBG_ERROR, "find ff pos = %d,i = %d\n",pos+i,i);
 333
 334                     if(i>spi_resp.max_dataW_resp_size)
 335                     {
 336                         spi_resp.max_dataW_resp_size = i;
 337                        // printk(KERN_ERR "new data write MAX 0xFF pos:%d",spi_resp.max_dataW_resp_size);
 338                     }
 339
 340                     //esp_dbg(ESP_DBG_ERROR, "0xFF pos:%d",i);
 341                     break;
 342                 }
 343             }
 344             break;
 345         }
 346     }
 347     if(i>=spi_resp.data_resp_size_w)
 348     {
 349         if(dummymode == 0)
 350             esp_dbg(ESP_DBG, "normal byte write data no-busy wait byte 0xff no recv at the first time\n");
 351
 352         timeout = 200;
 353         do {
 354             timeout --;
 355             //memset(check_buf,0x00,256);
 356
 357             sif_spi_read_raw(spi, check_buf, 256);
 358         } while( memcmp(check_buf,ff_buf,256) != 0 && timeout >0 ) ;
 359
 360         if(timeout == 0)
 361         {
 362             esp_dbg(ESP_DBG_ERROR, "spierr byte write data no-busy wait byte 0xff no recv \n");
 363             err_ret = -4;
 364             goto goto_err;
 365         }
 366     }
 367
 368 goto_err:
 369     return err_ret;
 370 }
 371
 372 int sif_spi_write_blocks(struct spi_device *spi, unsigned int addr,unsigned char *src, int count)
 373 {
 374     int err_ret = 0;
 375     int i,j;
 376     int n;
 377     int pos,len;
 378     unsigned char *tx_data = (unsigned char*)src;
 379     int find_w_rsp = 0;
 380     int timeout = 200;
 381
 382     if (spi == NULL) {
 383         ESSERT(0);
 384         err_ret = -EINVAL;
 385         goto goto_err;
 386     }
 387
 388     tx_cmd[0]=0x75;
 389
 390     if( count <=0 )
 391     {
 392         err_ret = -1;
 393         goto goto_err;
 394     }
 395
 396     if( addr >= (1<<17) )
 397     {
 398         err_ret = -2;
 399         goto goto_err;
 400     }
 401     else
 402     {
 403         tx_cmd[1]=0x90|0x0C|(addr>>15);
 404         tx_cmd[2]=addr>>7;
 405
 406         if(count >= 512 )
 407         {
 408             tx_cmd[3]=( addr<<1|0x0 );
 409             tx_cmd[4]= 0x00;
 410         }
 411         else
 412         {
 413             tx_cmd[3]=( addr<<1|(count>>8 & 0x01) );
 414             tx_cmd[4]= count & 0xff ;
 415         }
 416     }
 417     tx_cmd[5]=0x01;
 418
 419     pos = 5+1;
 420     //Add cmd respon
 421     memset(tx_cmd+pos,0xff,CMD_RESP_SIZE);
 422     pos =pos+ CMD_RESP_SIZE;
 423     if(count < 3)
 424     {
 425         for(j=0;j<count;j++)
 426         {
 427             //Add token
 428             tx_cmd[pos]=0xFC;
 429             pos = pos+1;
 430             //Add data
 431             memcpy(tx_cmd+pos,tx_data+j*SPI_BLOCK_SIZE, SPI_BLOCK_SIZE);
 432             pos = pos+SPI_BLOCK_SIZE;
 433             //Add data respon
 434             if( j==(count- 1) )
 435             {
 436                 memset(tx_cmd+pos , 0xff , spi_resp.block_w_data_resp_size_final);
 437                 pos = pos+ spi_resp.block_w_data_resp_size_final;
 438                 continue;
 439             }
 440             memset(tx_cmd+pos , 0xff , BLOCK_W_DATA_RESP_SIZE_EACH);
 441             pos = pos+ BLOCK_W_DATA_RESP_SIZE_EACH;
 442         }
 443
 444         if( pos%8 )
 445         {
 446             len = (8 - pos%8);
 447             memset(tx_cmd+pos,0xff,len);
 448         }
 449         else
 450             len = 0;
 451
 452         sif_spi_write_async_read(spi, tx_cmd,tx_cmd,pos+len);
 453
 454         //Judge Write cmd resp, and 1st block data resp.
 455         pos = 5+1;
 456         for(i=0;i<CMD_RESP_SIZE;i++)
 457         {
 458             if(tx_cmd[pos+i] == 0x00 && tx_cmd[pos+i-1] == 0xff)
 459             {
 460                 if(tx_cmd[pos+i+1] == 0x00 && tx_cmd[pos+i+2] == 0xff)
 461                     break;
 462             }
 463
 464         }
 465
 466         if(i>spi_resp.max_cmd_resp_size)
 467         {
 468             spi_resp.max_cmd_resp_size = i;
 469         }
 470
 471         if(i>=CMD_RESP_SIZE)
 472         {
 473             esp_dbg(ESP_DBG_ERROR, "spierr 1st block write cmd resp 0x00 no recv, %d\n", count);
 474             err_ret = -3;
 475             goto goto_err;
 476         }
 477
 478         pos = pos+CMD_RESP_SIZE;
 479
 480         for(j=0;j<count;j++)
 481         {
 482             find_w_rsp = 0;
 483             //Judge block data resp
 484             pos = pos+1;
 485             pos = pos+SPI_BLOCK_SIZE;
 486
 487             if( j==(count-1) )
 488                 n = spi_resp.block_w_data_resp_size_final;
 489             else
 490                 n= BLOCK_W_DATA_RESP_SIZE_EACH;
 491
 492             for(i =0 ;i<4;i++)
 493             {
 494                 if((tx_cmd[pos+i] & 0x0F) == 0x05)
 495                 {
 496                     find_w_rsp = 1;
 497                     break;
 498                 }
 499             }
 500
 501             if(find_w_rsp == 1)
 502             {
 503                 if(memcmp(tx_cmd+pos+n-4,ff_buf,4) != 0)
 504                 {
 505
 506                     esp_dbg(ESP_DBG, "block write  sleep 1\n");
 507                     if(j == count-1)
 508                     {
 509                         timeout = 200;
 510                         do {
 511                             timeout --;
 512                             //memset(check_buf,0x00,256);
 513
 514                             sif_spi_read_raw(spi, check_buf, 256);
 515                         } while( memcmp(check_buf,ff_buf,256) != 0 && timeout >0 ) ;
 516
 517                         if(timeout == 0)
 518                         {
 519                             err_ret = -7;
 520                             esp_dbg(ESP_DBG_ERROR, "spierr block write data no-busy wait byte 0xff no recv \n");
 521                             goto goto_err;
 522                         }
 523                     }
 524                     else
 525                     {
 526                         err_ret = -5;
 527                         esp_dbg(ESP_DBG_ERROR, "spierr %s block%d write data not-busy wait error, %d\n", __func__, j+1, count);
 528                         goto goto_err;
 529                     }
 530                 }
 531             }
 532             else
 533             {
 534                 err_ret = -6;
 535                 esp_dbg(ESP_DBG_ERROR, "spierr %s block%d write data no data res error, %d\n", __func__, j+1, count);
 536                 goto goto_err;
 537             }
 538
 539             pos = pos+n;
 540         }
 541     }
 542     else
 543     {
 544         for(j=0;j<2;j++)
 545         {
 546             //Add token
 547             tx_cmd[pos]=0xFC;
 548             pos = pos+1;
 549
 550             //Add data
 551             memcpy(tx_cmd+pos,tx_data+j*SPI_BLOCK_SIZE, SPI_BLOCK_SIZE);
 552             pos = pos+SPI_BLOCK_SIZE;
 553
 554             memset(tx_cmd+pos , 0xff , BLOCK_W_DATA_RESP_SIZE_EACH);
 555             pos = pos+ BLOCK_W_DATA_RESP_SIZE_EACH;
 556         }
 557
 558         if( pos%8 )
 559         {
 560             len = (8 - pos%8);
 561             memset(tx_cmd+pos,0xff,len);
 562         }
 563         else
 564             len = 0;
 565
 566         sif_spi_write_async_read(spi, tx_cmd,tx_cmd,pos+len);
 567
 568         //Judge Write cmd resp, and 1st block data resp.
 569         pos = 5+1;
 570         for(i=0;i<CMD_RESP_SIZE;i++)
 571         {
 572             if(tx_cmd[pos+i] == 0x00 && tx_cmd[pos+i-1] == 0xff)
 573             {
 574                 if(tx_cmd[pos+i+1] == 0x00 && tx_cmd[pos+i+2] == 0xff)
 575                     break;
 576             }
 577
 578         }
 579
 580         if(i>spi_resp.max_cmd_resp_size)
 581         {
 582             spi_resp.max_cmd_resp_size = i;
 583         }
 584
 585         if(i>=CMD_RESP_SIZE)
 586         {
 587             esp_dbg(ESP_DBG_ERROR, "spierr 1st block write cmd resp 0x00 no recv, %d\n", count);
 588             err_ret = -3;
 589             goto goto_err;
 590         }
 591
 592         pos = pos+CMD_RESP_SIZE;
 593
 594         for(j=0;j<2;j++)
 595         {
 596             find_w_rsp = 0;
 597             //Judge block data resp
 598             pos = pos+1;
 599             pos = pos+SPI_BLOCK_SIZE;
 600
 601             n = BLOCK_W_DATA_RESP_SIZE_EACH;
 602
 603             for(i =0 ;i<4;i++)
 604             {
 605                 if((tx_cmd[pos+i] & 0x0F) == 0x05)
 606                 {
 607                     find_w_rsp = 1;
 608                     break;
 609                 }
 610             }
 611
 612             if(find_w_rsp == 1)
 613             {
 614                 if(memcmp(tx_cmd+pos+n-4,ff_buf,4) != 0 )
 615                 {
 616                     esp_dbg(ESP_DBG, "block write data during sleep \n");
 617
 618                     if(j == 1)
 619                     {
 620                         timeout = 200;
 621                         do {
 622                             timeout --;
 623
 624                             sif_spi_read_raw(spi, check_buf, 256);
 625                         } while( memcmp(check_buf,ff_buf,256) != 0 && timeout >0 ) ;
 626
 627                         if(timeout == 0)
 628                         {
 629                             err_ret = -7;
 630                             esp_dbg(ESP_DBG_ERROR, "spierr block write data no-busy wait byte 0xff no recv \n");
 631                             goto goto_err;
 632                         }
 633                     }
 634                     else
 635                     {
 636                         err_ret = -5;
 637                         esp_dbg(ESP_DBG_ERROR, "spierr %s block%d write data not-busy wait error, %d\n", __func__, j+1, count);
 638                         goto goto_err;
 639                     }
 640                 }
 641             }
 642             else
 643             {
 644                 err_ret = -6;
 645                 esp_dbg(ESP_DBG_ERROR, "spierr %s block%d write data no data res error, %d\n", __func__, j+1, count);
 646                 goto goto_err;
 647             }
 648
 649             pos = pos+n;
 650         }
 651
 652
 653         pos = 0;
 654         for(j=2;j<count;j++)
 655         {
 656             //Add token
 657             tx_cmd[pos]=0xFC;
 658             pos = 1+pos ;
 659             //Add data
 660             memcpy(tx_cmd+pos,tx_data+j*SPI_BLOCK_SIZE, SPI_BLOCK_SIZE);
 661             pos = pos+SPI_BLOCK_SIZE;
 662             //Add data respon
 663             if(j == count-1)
 664             {
 665                 memset(tx_cmd+pos , 0xff ,spi_resp.block_w_data_resp_size_final);
 666                 pos = pos+spi_resp.block_w_data_resp_size_final;
 667                 continue;
 668             }
 669             memset(tx_cmd+pos , 0xff , BLOCK_W_DATA_RESP_SIZE_EACH);
 670             pos = pos+ BLOCK_W_DATA_RESP_SIZE_EACH;
 671         }
 672
 673         if( pos%8 )
 674         {
 675             len = (8 - pos%8);
 676             memset(tx_cmd+pos,0xff,len);
 677         }
 678         else
 679             len = 0;
 680
 681         sif_spi_write_async_read(spi, tx_cmd,tx_cmd,pos+len);
 682
 683         pos = 0;
 684         for(j=2;j<count;j++)
 685         {
 686             find_w_rsp = 0;
 687             //Judge block data resp
 688             pos = pos+1;
 689             pos = pos+SPI_BLOCK_SIZE;
 690
 691             if( j==(count-1) )
 692                 n = spi_resp.block_w_data_resp_size_final;
 693             else
 694                 n= BLOCK_W_DATA_RESP_SIZE_EACH;
 695
 696             for(i =0 ;i<4;i++)
 697             {
 698                 if((tx_cmd[pos+i] & 0x0F) == 0x05)
 699                 {
 700                     find_w_rsp = 1;
 701                     break;
 702                 }
 703             }
 704
 705             if(find_w_rsp == 1)
 706             {
 707                 if(memcmp(tx_cmd+pos+n-4,ff_buf,4) != 0)
 708                 {
 709                     err_ret = -5;
 710                     esp_dbg(ESP_DBG_ERROR, "spierr %s block%d write data not-busy wait error, %d\n", __func__, j+1, count);
 711                     goto goto_err;
 712                 }
 713             }
 714             else
 715             {
 716                 err_ret = -6;
 717                 esp_dbg(ESP_DBG_ERROR, "spierr %s block%d write data no data res error, %d\n", __func__, j+1, count);
 718                 goto goto_err;
 719             }
 720
 721             pos = pos+n;
 722         }
 723     }
 724
 725 goto_err:
 726
 727     return err_ret;
 728 }
 729
 730 int sif_spi_write_mix_nosync(struct spi_device *spi, unsigned int addr, unsigned char *buf, int len, int dummymode)
 731 {
 732         int blk_cnt;
 733         int remain_len;
 734         int err;
 735         do {
 736                 blk_cnt = len/SPI_BLOCK_SIZE;
 737                 remain_len = len%SPI_BLOCK_SIZE;
 738
 739                 if (blk_cnt > 0) {
 740                         err  = sif_spi_write_blocks(spi, addr, buf, blk_cnt);
 741                         if (err)
 742                                 return err;
 743                 }
 744
 745                 if (remain_len > 0) {
 746                         err = sif_spi_write_bytes(spi, addr, (buf + (blk_cnt*SPI_BLOCK_SIZE)), remain_len, dummymode);
 747                         if (err)
 748                                 return err;
 749                 }
 750         } while(0);
 751         return 0;
 752
 753 }
 754
 755 int sif_spi_write_mix_sync(struct spi_device *spi, unsigned int addr, unsigned char *buf, int len, int dummymode)
 756 {
 757         int err;
 758
 759         spi_bus_lock(spi->master);
 760         err = sif_spi_write_mix_nosync(spi, addr, buf, len, dummymode);
 761         spi_bus_unlock(spi->master);
 762
 763         return err;
 764 }
 765
 766 int sif_spi_epub_write_mix_nosync(struct esp_pub *epub, unsigned int addr, unsigned char *buf,int len, int dummymode)
 767 {
 768         struct esp_spi_ctrl *sctrl = NULL;
 769         struct spi_device *spi = NULL;
 770
 771         if (epub == NULL) {
 772                 ESSERT(0);
 773                 return -EINVAL;
 774         }
 775         sctrl = (struct esp_spi_ctrl *)epub->sif;
 776         spi = sctrl->spi;
 777         if (spi == NULL) {
 778                 ESSERT(0);
 779                 return -EINVAL;
 780         }
 781
 782         return sif_spi_write_mix_nosync(spi, addr, buf, len, dummymode);
 783 }
 784
 785 int sif_spi_epub_write_mix_sync(struct esp_pub *epub, unsigned int addr, unsigned char *buf,int len, int dummymode)
 786 {
 787         struct esp_spi_ctrl *sctrl = NULL;
 788         struct spi_device *spi = NULL;
 789
 790         if (epub == NULL) {
 791                 ESSERT(0);
 792                 return -EINVAL;
 793         }
 794         sctrl = (struct esp_spi_ctrl *)epub->sif;
 795         spi = sctrl->spi;
 796         if (spi == NULL) {
 797                 ESSERT(0);
 798                 return -EINVAL;
 799         }
 800
 801         return sif_spi_write_mix_sync(spi, addr, buf, len, dummymode);
 802 }
 803
 804 int sif_spi_read_bytes(struct spi_device *spi, unsigned int addr,unsigned char *dst, int count, int dummymode)
 805 {
 806     int pos,total_num,len;
 807     int i;
 808     unsigned char *rx_data = (unsigned char *)dst;
 809     int err_ret = 0;
 810     unsigned short crc = 0;
 811     char test_crc[2];
 812     int unexp_byte = 0;
 813
 814     u32 timeout = 200;
 815     int find_start_token = 0;
 816     spi_resp.data_resp_size_r = ((((((count>>2)+1) *25)>>5)*21+16)>>3) +1  ;
 817
 818     if (spi == NULL) {
 819         ESSERT(0);
 820         err_ret = -EINVAL;
 821         goto goto_err;
 822     }
 823
 824     rx_cmd[0]=0x75;
 825
 826     if(count > 512 )
 827     {
 828         err_ret = -1;
 829         goto goto_err;
 830     }
 831
 832     if( addr >= (1<<17) )
 833     {
 834         err_ret = -2;
 835         goto goto_err;
 836     }
 837     else
 838     {
 839         rx_cmd[1]=0x10|0x04|(addr>>15);    //0x94;
 840         rx_cmd[2]=addr>>7;
 841
 842         if(count == 512 )
 843         {
 844             rx_cmd[3]=( addr<<1|0x0 );
 845             rx_cmd[4]= 0x00;     //0x08;
 846         }
 847         else
 848         {
 849             rx_cmd[3]=( addr<<1|(count>>8 & 0x01) );
 850             rx_cmd[4]= count & 0xff;     //0x08;
 851         }
 852     }
 853
 854     rx_cmd[5]=0x01;
 855
 856     total_num = CMD_RESP_SIZE+spi_resp.data_resp_size_r+count+2;
 857     memset(rx_cmd+6 , 0xFF ,total_num);
 858
 859     if(6+total_num <128)
 860     {
 861         len =128 -6 -total_num;
 862         memset(rx_cmd+6+total_num,0xff,len);
 863     }
 864     else
 865     {
 866
 867         if( (6+total_num)%8 )
 868         {
 869             len = (8 - (6+total_num)%8);
 870             memset(rx_cmd+6+total_num,0xff,len);
 871         }
 872         else
 873             len = 0;
 874
 875     }
 876
 877     sif_spi_write_async_read(spi, rx_cmd,rx_cmd,6+total_num+len);
 878
 879     pos = 5+1;
 880     for(i=0;i<CMD_RESP_SIZE;i++)
 881     {
 882         if(rx_cmd[pos+i] == 0x00 && rx_cmd[pos+i-1] == 0xff)
 883         {
 884             if(rx_cmd[pos+i+1] == 0x00 && rx_cmd[pos+i+2] == 0xff)
 885                 break;
 886         }
 887     }
 888
 889     if(i>spi_resp.max_cmd_resp_size)
 890     {
 891         spi_resp.max_cmd_resp_size = i;
 892         //printk(KERN_ERR "new cmd write MAX 0xFF pos:%d",spi_resp.max_cmd_resp_size);
 893     }
 894
 895
 896     if(i>=CMD_RESP_SIZE)
 897     {
 898         esp_dbg(ESP_DBG_ERROR, "spierr byte read cmd resp 0x00 no recv\n");
 899         /***********error info************************/
 900         /*
 901            char t = pos;
 902            while ( t < pos+32) {
 903            printk(KERN_ERR "rx:[0x%02x] ", rx_cmd[t]);
 904            t++;
 905            if ((t-pos)%8 == 0)
 906            printk(KERN_ERR "\n");
 907            }
 908            */
 909         err_ret = -3;
 910         goto goto_err;
 911     }
 912     //esp_dbg(ESP_DBG_ERROR, "0x00 pos:%d",pos+i);
 913     pos = pos+i+2;
 914
 915     for(i=0;i<spi_resp.data_resp_size_r;i++)
 916     {
 917         if(rx_cmd[pos+i]==0xFE)
 918         {
 919
 920             find_start_token = 1;
 921             if(i>spi_resp.max_dataR_resp_size)
 922             {
 923                 spi_resp.max_dataR_resp_size = i;
 924                 //printk(KERN_ERR "new data read MAX 0xFE pos:%d",spi_resp.max_dataR_resp_size);
 925             }
 926             break;
 927         }
 928         else if(rx_cmd[pos+i] != 0xff)
 929         {
 930             unexp_byte ++;
 931             if(unexp_byte == 1)
 932                 esp_dbg(ESP_DBG, " 1 normal byte read not 0xFF or 0xFE  at the first time,count = %d,addr =%x \n",count,addr);
 933         }
 934     }
 935
 936     if(find_start_token == 0)
 937     {
 938         if(dummymode == 0)
 939             esp_dbg(ESP_DBG, " normal byte read start token 0xFE  not recv at the first time,count = %d,addr =%x \n",count,addr);
 940
 941         pos = pos +spi_resp.data_resp_size_r;
 942
 943         for(i=0;i< 6+total_num+len-pos;i++)
 944         {
 945             if(rx_cmd[pos+i]==0xFE)
 946             {
 947                 sif_spi_read_raw(spi,rx_cmd,((count+4)>256)?(count+4):256);
 948                // sif_spi_read_raw(spi, check_buf, 256);
 949                 find_start_token = 1;
 950                 err_ret = -4;
 951                 goto goto_err;
 952             }
 953             else if(rx_cmd[pos+i] !=0xff)
 954             {
 955                 unexp_byte ++;
 956                 if(unexp_byte == 1)
 957                     esp_dbg(ESP_DBG, "2 normal byte read not 0xFF or 0xFE  at the first time,count = %d,addr =%x \n",count,addr);
 958             }
 959
 960         }
 961
 962         timeout = 200;
 963         do {
 964             timeout --;
 965
 966             sif_spi_read_raw(spi, check_buf, 256);
 967             for(i=0;i<256;i++)
 968             {
 969                 if(check_buf[i] ==0xFE)
 970                 {
 971                     find_start_token = 1;
 972                     sif_spi_read_raw(spi,rx_cmd,((count+4)>256)?(count+4):256);
 973
 974                     break;
 975                 }
 976             }
 977         } while( find_start_token != 1 && timeout >0 ) ;
 978
 979         if(timeout == 0)
 980         {
 981             esp_dbg(ESP_DBG_ERROR, "spierr byte read start token 0xFE no recv ,count = %d,addr =%x \n",count,addr);
 982         }
 983         err_ret = -5;
 984
 985         goto goto_err;
 986     }
 987
 988     //esp_dbg(ESP_DBG_ERROR, "0xFE pos:%d",pos+i);
 989     pos = pos+i+1;
 990     memcpy(rx_data,rx_cmd+pos,count);
 991
 992     crc = crc_cal_by_byte(rx_data,count);
 993
 994     test_crc[0] = crc & 0xff;
 995     test_crc[1] = (crc >>8) &0xff ;
 996
 997     if(test_crc[1] != rx_cmd[pos+count] || test_crc[0] != rx_cmd[pos+count+1] )
 998     {
 999         esp_dbg(ESP_DBG, "crc test_crc0  %x\n",test_crc[0]);
1000         esp_dbg(ESP_DBG, "crc test_crc1  %x\n",test_crc[1]);
1001         esp_dbg(ESP_DBG, "crc rx_data-2  %x\n",rx_cmd[pos+count]);
1002         esp_dbg(ESP_DBG, "crc rx_data-1  %x\n",rx_cmd[pos+count+1] );
1003
1004         esp_dbg(ESP_DBG, "crc err\n");
1005
1006         esp_dbg(ESP_DBG_ERROR, "spierr crc count = %d,addr =%x \n",count,addr);
1007
1008         err_ret = -6;
1009         goto goto_err;
1010
1011     }
1012
1013 goto_err:
1014
1015     return err_ret;
1016 }
1017
1018 int sif_spi_read_blocks(struct spi_device *spi, unsigned int addr, unsigned char *dst, int count)
1019 {
1020     int err_ret = 0;
1021     int pos,len;
1022     int i,j;
1023     unsigned char *rx_data = (unsigned char *)dst;
1024     int total_num;
1025     u32 timeout = 200;
1026     int find_start_token = 0;
1027     unsigned short crc = 0;
1028     char test_crc[2];
1029
1030     if (spi == NULL) {
1031         ESSERT(0);
1032         err_ret = -EINVAL;
1033         goto goto_err;
1034     }
1035
1036     rx_cmd[0]=0x75;
1037
1038     if( count <=0 )
1039     {
1040         err_ret = -1;
1041         goto goto_err;
1042     }
1043     if( addr >= (1<<17) )
1044     {
1045         err_ret = -2;
1046         goto goto_err;
1047     }
1048     else
1049     {
1050         rx_cmd[1]=0x10|0x0C|(addr>>15);
1051         rx_cmd[2]=addr>>7;
1052
1053         if(count >= 512 )
1054         {
1055             rx_cmd[3]=( addr<<1|0x0 );
1056             rx_cmd[4]= 0x00;
1057         }
1058         else
1059         {
1060             rx_cmd[3]=( addr<<1|(count>>8 & 0x01) );
1061             rx_cmd[4]= count & 0xff;
1062         }
1063     }
1064     rx_cmd[5]=0x01;
1065     total_num = CMD_RESP_SIZE+spi_resp.block_r_data_resp_size_final+SPI_BLOCK_SIZE+ 2 + (count-1)*(BLOCK_R_DATA_RESP_SIZE_EACH+SPI_BLOCK_SIZE+2);
1066     memset(rx_cmd+6, 0xFF ,total_num);
1067
1068     if( (6+total_num)%8 )
1069     {
1070         len = (8 - (6+total_num)%8);
1071         memset(rx_cmd+6+total_num,0xff,len);
1072     }
1073     else
1074         len = 0;
1075
1076     sif_spi_write_async_read(spi, rx_cmd,rx_cmd,6+total_num+len );
1077
1078     pos = 5+1;
1079     for(i=0;i<CMD_RESP_SIZE;i++)
1080     {
1081         if(rx_cmd[pos+i] == 0x00 && rx_cmd[pos+i-1] == 0xff)
1082         {
1083             if(rx_cmd[pos+i+1] == 0x00 && rx_cmd[pos+i+2] == 0xff)
1084                 break;
1085         }
1086     }
1087
1088     if(i>spi_resp.max_cmd_resp_size)
1089     {
1090         spi_resp.max_cmd_resp_size = i;
1091         //printk(KERN_ERR "new cmd write MAX 0xFF pos:%d",spi_resp.max_cmd_resp_size);
1092     }
1093
1094     if(i>=CMD_RESP_SIZE)
1095     {
1096         esp_dbg(ESP_DBG_ERROR, "spierr block read cmd resp 0x00 no recv\n");
1097
1098         err_ret = -3;
1099         goto goto_err;
1100     }
1101
1102     pos = pos+i+2;
1103
1104     for(i=0;i<spi_resp.block_r_data_resp_size_final;i++)
1105     {
1106         if(rx_cmd[pos+i]==0xFE)
1107         {
1108             //esp_dbg(ESP_DBG_ERROR, "0xFE pos:%d",i);
1109             find_start_token = 1;
1110             if(i>spi_resp.max_block_dataR_resp_size)
1111             {
1112                 spi_resp.max_block_dataR_resp_size = i;
1113                 //printk(KERN_ERR "new block data read MAX 0xFE pos:%d\n",spi_resp.max_block_dataR_resp_size);
1114             }
1115
1116             break;
1117         }
1118     }
1119
1120     if( find_start_token == 0)
1121     {
1122         esp_dbg(ESP_DBG, "1st block read data resp 0xFE no recv,count = %d\n",count);
1123         pos = pos +spi_resp.block_r_data_resp_size_final;
1124         for(i=0;i< 6+total_num+len-pos;i++)
1125         {
1126             if(rx_cmd[pos+i]==0xFE)
1127             {
1128                 sif_spi_read_raw(spi, check_buf, total_num+len);
1129                 find_start_token = 1;
1130                 err_ret = -4;
1131                 goto goto_err;
1132             }
1133         }
1134
1135         timeout = 200;
1136         do {
1137             esp_dbg(ESP_DBG_ERROR, "block read  sleep ,count = %d\n",count);
1138             timeout --;
1139             sif_spi_read_raw(spi, check_buf, 256);
1140             for(i=0;i<256;i++)
1141             {
1142                 if(check_buf[i] ==0xFE)
1143                 {
1144                     find_start_token= 1;
1145                     sif_spi_read_raw(spi, rx_cmd, total_num+len);
1146                     break;
1147                 }
1148             }
1149         } while( find_start_token != 1 && timeout >0 ) ;
1150         if(timeout == 0)
1151         {
1152             err_ret = -8;
1153             esp_dbg(ESP_DBG_ERROR, "spierr block read start token 0xFE no recv\n");
1154         }else
1155         {
1156             err_ret = -5;
1157         }
1158         goto goto_err;
1159     }
1160
1161     pos = pos+i+1;
1162
1163     memcpy(rx_data,rx_cmd+pos,SPI_BLOCK_SIZE);
1164
1165     crc = crc_cal_by_byte(rx_data,512);
1166
1167     test_crc[0] = crc & 0xff;
1168     test_crc[1] = (crc >>8) &0xff ;
1169
1170     if(test_crc[1] != rx_cmd[pos+SPI_BLOCK_SIZE] || test_crc[0] != rx_cmd[pos+SPI_BLOCK_SIZE+1] )
1171     {
1172         esp_dbg(ESP_DBG, "crc test_crc0  %x\n",test_crc[0]);
1173         esp_dbg(ESP_DBG, "crc test_crc1  %x\n",test_crc[1]);
1174         esp_dbg(ESP_DBG, "crc rx_data-2  %x\n",rx_cmd[pos+SPI_BLOCK_SIZE]);
1175         esp_dbg(ESP_DBG, "crc rx_data-1  %x\n",rx_cmd[pos+SPI_BLOCK_SIZE+1] );
1176
1177         esp_dbg(ESP_DBG_ERROR, "spierr crc err block = 1,count = %d\n",count);
1178
1179         err_ret = -6;
1180         goto goto_err;
1181
1182     }
1183
1184     pos = pos +SPI_BLOCK_SIZE + 2;
1185
1186     for(j=1;j<count;j++)
1187     {
1188
1189         for(i=0;i<BLOCK_R_DATA_RESP_SIZE_EACH;i++)
1190         {
1191             if(rx_cmd[pos+i]==0xFE)
1192             {
1193                 //esp_dbg(ESP_DBG_ERROR, "0xFE pos:%d",i);
1194                 if(i>spi_resp.max_block_dataR_resp_size)
1195                 {
1196                     spi_resp.max_block_dataR_resp_size = i;
1197                     //printk(KERN_ERR "new block data read MAX 0xFE pos:%d",spi_resp.max_block_dataR_resp_size);
1198                 }
1199
1200                 break;
1201             }
1202         }
1203         if(i>=BLOCK_R_DATA_RESP_SIZE_EACH)
1204         {
1205             esp_dbg(ESP_DBG_ERROR, "spierr block%d read data token 0xFE no recv,total:%d\n",j+1,count);
1206             err_ret = -7;
1207             goto goto_err;
1208         }
1209
1210         pos = pos+i+1;
1211
1212         memcpy(rx_data+j*SPI_BLOCK_SIZE,rx_cmd+pos,SPI_BLOCK_SIZE);
1213
1214         crc = crc_cal_by_byte(rx_data+j*SPI_BLOCK_SIZE ,512);
1215
1216         test_crc[0] = crc & 0xff;
1217         test_crc[1] = (crc >>8) &0xff ;
1218
1219         if(test_crc[1] != rx_cmd[pos+SPI_BLOCK_SIZE] || test_crc[0] != rx_cmd[pos+SPI_BLOCK_SIZE+1] )
1220         {
1221             esp_dbg(ESP_DBG, "crc test_crc0  %x\n",test_crc[0]);
1222             esp_dbg(ESP_DBG, "crc test_crc1  %x\n",test_crc[1]);
1223             esp_dbg(ESP_DBG, "crc rx_data-2  %x\n",rx_cmd[pos+SPI_BLOCK_SIZE]);
1224             esp_dbg(ESP_DBG, "crc rx_data-1  %x\n",rx_cmd[pos+SPI_BLOCK_SIZE+1] );
1225
1226             esp_dbg(ESP_DBG_ERROR, "spierr crc err,count = %d,block =%d\n",count,j+1);
1227
1228             err_ret = -6;
1229             goto goto_err;
1230         }
1231
1232         pos = pos +SPI_BLOCK_SIZE + 2;
1233     }
1234
1235 goto_err:
1236
1237     return err_ret;
1238 }
1239
1240 int sif_spi_read_mix_nosync(struct spi_device *spi, unsigned int addr, unsigned char *buf, int len, int dummymode)
1241 {
1242         int blk_cnt;
1243         int remain_len;
1244         int err = 0;
1245         int retry = 20;
1246
1247         do{
1248                 blk_cnt = len/SPI_BLOCK_SIZE;
1249                 remain_len = len%SPI_BLOCK_SIZE;
1250
1251                 if (blk_cnt > 0) {
1252
1253                         retry = 20;
1254                         do {
1255                                 if(retry < 20)
1256                                         mdelay(10);
1257                                 retry--;
1258                                 check_buf[0] = 1<<2;
1259                                 err  = sif_spi_read_blocks(spi, addr, buf, blk_cnt);
1260                                 if(err == 0)
1261                                 {
1262                                         sif_spi_write_bytes(spi,SLC_HOST_CONF_W4 + 2,check_buf,1,0);
1263                                 } else if(err == -4 ||err == -5 ||err == -6||err == -7 ||err == -8)
1264                                 {
1265                                         struct esp_spi_ctrl *sctrl = spi_get_drvdata(spi);
1266                                         if(sctrl != NULL) {
1267                                                 sif_ack_target_read_err(sctrl->epub);
1268                                         }
1269                                 } else if(err == -3)
1270                                 {
1271                                         continue;
1272                                 } else
1273                                 {
1274                                         break;
1275                                 }
1276
1277                         }while(retry > 0 && err != 0);
1278                         if(err != 0 && retry == 0)
1279                                 esp_dbg(ESP_DBG_ERROR, "spierr 20 times retry block read fail\n");
1280
1281                         if(err)
1282                                 return err;
1283                 }
1284
1285                 if (remain_len > 0) {
1286                         if(dummymode == 0 )
1287                         {
1288                                 retry = 20;
1289                                 do{
1290                                         if(retry <20)
1291                                                 mdelay(10);
1292                                         retry--;
1293                                         err = sif_spi_read_bytes(spi, addr, (buf + (blk_cnt*SPI_BLOCK_SIZE)), remain_len, dummymode);
1294                                 }while(retry >0 && err != 0);
1295
1296                                 if(err != 0 &&  retry == 0)
1297                                         esp_dbg(ESP_DBG_ERROR, "spierr 20 times retry byte read fail\n");
1298                         }
1299                         else
1300                         {
1301                                 err = sif_spi_read_bytes(spi, addr, (buf + (blk_cnt*SPI_BLOCK_SIZE)), remain_len, dummymode);
1302                         }
1303                         if (err)
1304                                 return err;
1305                 }
1306         } while(0);
1307         return 0;
1308 }
1309
1310 int sif_spi_read_mix_sync(struct spi_device *spi, unsigned int addr, unsigned char *buf, int len, int dummymode)
1311 {
1312         int err;
1313
1314         spi_bus_lock(spi->master);
1315         err = sif_spi_read_mix_nosync(spi, addr, buf, len, dummymode);
1316         spi_bus_unlock(spi->master);
1317
1318         return err;
1319 }
1320
1321 int sif_spi_epub_read_mix_nosync(struct esp_pub *epub, unsigned int addr, unsigned char *buf,int len, int dummymode)
1322 {
1323         struct esp_spi_ctrl *sctrl = NULL;
1324         struct spi_device *spi = NULL;
1325
1326         if (epub == NULL) {
1327                 ESSERT(0);
1328                 return -EINVAL;
1329         }
1330         sctrl = (struct esp_spi_ctrl *)epub->sif;
1331         spi = sctrl->spi;
1332         if (spi == NULL) {
1333                 ESSERT(0);
1334                 return -EINVAL;
1335         }
1336
1337         return sif_spi_read_mix_nosync(spi, addr, buf, len, dummymode);
1338 }
1339
1340 int sif_spi_epub_read_mix_sync(struct esp_pub *epub, unsigned int addr, unsigned char *buf,int len, int dummymode)
1341 {
1342         struct esp_spi_ctrl *sctrl = NULL;
1343         struct spi_device *spi = NULL;
1344
1345         if (epub == NULL) {
1346                 ESSERT(0);
1347                 return -EINVAL;
1348         }
1349         sctrl = (struct esp_spi_ctrl *)epub->sif;
1350         spi = sctrl->spi;
1351         if (spi == NULL) {
1352                 ESSERT(0);
1353                 return -EINVAL;
1354         }
1355
1356         return sif_spi_read_mix_sync(spi, addr, buf, len, dummymode);
1357 }
1358
1359 int sif_spi_read_sync(struct esp_pub *epub, unsigned char *buf, int len, int dummymode)
1360 {
1361         struct esp_spi_ctrl *sctrl = NULL;
1362         struct spi_device *spi = NULL;
1363         u32 read_len;
1364
1365         if (epub == NULL || buf == NULL) {
1366                 ESSERT(0);
1367                 return -EINVAL;
1368         }
1369         sctrl = (struct esp_spi_ctrl *)epub->sif;
1370         spi = sctrl->spi;
1371         if (spi == NULL) {
1372                 ESSERT(0);
1373                 return -EINVAL;
1374         }
1375
1376         switch(sctrl->target_id) {
1377         case 0x100:
1378                 read_len = len;
1379                 break;
1380         case 0x600:
1381                 read_len = roundup(len, sctrl->slc_blk_sz);
1382                 break;
1383         default:
1384                 read_len = len;
1385                 break;
1386         }
1387
1388         return sif_spi_read_mix_sync(spi, sctrl->slc_window_end_addr - 2 - (len), buf, read_len, dummymode);
1389 }
1390
1391 int sif_spi_write_sync(struct esp_pub *epub, unsigned char *buf, int len, int dummymode)
1392 {
1393         struct esp_spi_ctrl *sctrl = NULL;
1394         struct spi_device *spi = NULL;
1395         u32 write_len;
1396
1397         if (epub == NULL || buf == NULL) {
1398                 ESSERT(0);
1399                 return -EINVAL;
1400         }
1401         sctrl = (struct esp_spi_ctrl *)epub->sif;
1402         spi = sctrl->spi;
1403         if (spi == NULL) {
1404                 ESSERT(0);
1405                 return -EINVAL;
1406         }
1407
1408         switch(sctrl->target_id) {
1409         case 0x100:
1410                 write_len = len;
1411                 break;
1412         case 0x600:
1413                 write_len = roundup(len, sctrl->slc_blk_sz);
1414                 break;
1415         default:
1416                 write_len = len;
1417                 break;
1418         }
1419         return sif_spi_write_mix_sync(spi, sctrl->slc_window_end_addr - (len), buf, write_len, dummymode);
1420 }
1421
1422 int sif_spi_read_nosync(struct esp_pub *epub, unsigned char *buf, int len, int dummymode, bool noround)
1423 {
1424         struct esp_spi_ctrl *sctrl = NULL;
1425         struct spi_device *spi = NULL;
1426         u32 read_len;
1427
1428         if (epub == NULL || buf == NULL) {
1429                 ESSERT(0);
1430                 return -EINVAL;
1431         }
1432         sctrl = (struct esp_spi_ctrl *)epub->sif;
1433         spi = sctrl->spi;
1434         if (spi == NULL) {
1435                 ESSERT(0);
1436                 return -EINVAL;
1437         }
1438
1439         switch(sctrl->target_id) {
1440         case 0x100:
1441                 read_len = len;
1442                 break;
1443         case 0x600:
1444                 if (!noround)
1445                         read_len = roundup(len, sctrl->slc_blk_sz);
1446                 else
1447                         read_len = len;
1448                 break;
1449         default:
1450                 read_len = len;
1451                 break;
1452         }
1453
1454         return sif_spi_read_mix_nosync(spi, sctrl->slc_window_end_addr - 2 - (len), buf, read_len, dummymode);
1455 }
1456
1457 int sif_spi_write_nosync(struct esp_pub *epub, unsigned char *buf, int len, int dummymode)
1458 {
1459         struct esp_spi_ctrl *sctrl = NULL;
1460         struct spi_device *spi = NULL;
1461         u32 write_len;
1462
1463         if (epub == NULL || buf == NULL) {
1464                 ESSERT(0);
1465                 return -EINVAL;
1466         }
1467         sctrl = (struct esp_spi_ctrl *)epub->sif;
1468         spi = sctrl->spi;
1469         if (spi == NULL) {
1470                 ESSERT(0);
1471                 return -EINVAL;
1472         }
1473
1474         switch(sctrl->target_id) {
1475         case 0x100:
1476                 write_len = len;
1477                 break;
1478         case 0x600:
1479                 write_len = roundup(len, sctrl->slc_blk_sz);
1480                 break;
1481         default:
1482                 write_len = len;
1483                 break;
1484         }
1485         return sif_spi_write_mix_nosync(spi, sctrl->slc_window_end_addr - (len), buf, write_len, dummymode);
1486 }
1487
1488 int sif_spi_protocol_init(struct spi_device *spi)
1489 {
1490         unsigned char spi_proto_ini_status = 0;
1491         unsigned char rx_buf1[10];
1492         unsigned char tx_buf1[10];
1493         unsigned char dummy_tx_buf[10];
1494         memset(dummy_tx_buf,0xff,sizeof(dummy_tx_buf));
1495         do
1496         {
1497                  if( spi_proto_ini_status == 0 )
1498                  {
1499                         int fail_count = 0;
1500                         do
1501                         {
1502                                 tx_buf1[0]=0x40;
1503                                 tx_buf1[1]=0x00;
1504                                 tx_buf1[2]=0x00;
1505                                 tx_buf1[3]=0x00;
1506                                 tx_buf1[4]=0x00;
1507                                 tx_buf1[5]=0x95;
1508                                 //printf("CMD0 \n");
1509                                 sif_spi_write_raw(spi, tx_buf1, 6);
1510                                 sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1511                                           //  esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1512              //   ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1513                                 mdelay(100);
1514                                 if(fail_count++ > 10)
1515                                         return -ETIMEDOUT;
1516                         }while( rx_buf1[2] != 0x01 );
1517                         //  }while(1);
1518                  }
1519                 else if( spi_proto_ini_status == 1 )
1520                 {
1521                         tx_buf1[0]=0x45;
1522                         tx_buf1[1]=0x00;
1523                         tx_buf1[2]=0x20;               //0x04;
1524                         tx_buf1[3]=0x00;
1525                         tx_buf1[4]=0x00;
1526                         tx_buf1[5]=0x01;
1527                         //spi_err("CMD 5 1st\n");
1528                         sif_spi_write_raw(spi, tx_buf1, 6);
1529                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1530                                      //  esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1531               //  ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1532                  }
1533                 else if( spi_proto_ini_status == 2 )
1534                 {
1535                         tx_buf1[0]=0x45;
1536                         tx_buf1[1]=0x00;
1537                         tx_buf1[2]=0x20;
1538                         tx_buf1[3]=0x00;
1539                         tx_buf1[4]=0x00;
1540                         tx_buf1[5]=0x01;
1541                         //spi_err("CMD5 2nd\n");
1542                         sif_spi_write_raw(spi, tx_buf1, 6);
1543                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1544                                      //  esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1545              //   ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1546                }
1547                else if( spi_proto_ini_status == 3 )                  //CMD 52   addr 0x2,   data 0x02;
1548                 {
1549                         tx_buf1[0]=0x74;
1550                         tx_buf1[1]=0x80;
1551                         tx_buf1[2]=0x00;
1552                         tx_buf1[3]=0x04;
1553                         tx_buf1[4]=0x02;
1554                         tx_buf1[5]=0x01;
1555                         //spi_err("CMD52 Write  addr 02 \n");
1556                         sif_spi_write_raw(spi, tx_buf1, 6);
1557                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1558                                     //   esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1559              //   ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1560                  }
1561                 else if( spi_proto_ini_status == 4 )
1562                 {
1563                         tx_buf1[0]=0x74;
1564                         tx_buf1[1]=0x80;
1565                         tx_buf1[2]=0x00;
1566                         tx_buf1[3]=0x08;
1567                         tx_buf1[4]=0x03;
1568                         tx_buf1[5]=0x01;
1569                         //spi_err("CMD52 Write  addr 04 \n");
1570                         sif_spi_write_raw(spi, tx_buf1, 6);
1571                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1572                                     //   esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1573               //  ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1574                  }
1575                 else if( spi_proto_ini_status == 5 )
1576                 {
1577                         tx_buf1[0]=0x74;
1578                         tx_buf1[1]=0x00;
1579                         tx_buf1[2]=0x00;
1580                         tx_buf1[3]=0x04;
1581                         tx_buf1[4]=0x00;
1582                         tx_buf1[5]=0x01;
1583                         //spi_err("CMD52 Read  addr 0x2 \n");
1584                         sif_spi_write_raw(spi, tx_buf1, 6);
1585                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1586                                     //   esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1587              //   ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1588
1589                  }
1590                  else if( spi_proto_ini_status == 6 )
1591                 {
1592                         tx_buf1[0]=0x74;
1593                         tx_buf1[1]=0x00;
1594                         tx_buf1[2]=0x00;
1595                         tx_buf1[3]=0x08;
1596                         tx_buf1[4]=0x00;
1597                         tx_buf1[5]=0x01;
1598                         //spi_err("CMD52 Read addr 0x4 \n");
1599                         sif_spi_write_raw(spi, tx_buf1, 6);
1600                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1601                                      //  esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1602               //  ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1603                  }
1604                  else if (spi_proto_ini_status>6 && spi_proto_ini_status<15)
1605                 {
1606                         tx_buf1[0]=0x74;
1607                         tx_buf1[1]=0x10;
1608                         tx_buf1[2]=0x00;
1609                         tx_buf1[3]=0xF0+2*(spi_proto_ini_status-7);
1610                         tx_buf1[4]=0x00;
1611                         tx_buf1[5]=0x01;
1612                         sif_spi_write_raw(spi, tx_buf1, 6);
1613                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1614                                     //   esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1615             //    ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1616                  }
1617                 else if (spi_proto_ini_status==15)
1618                 {
1619                         //spi_err("CMD52 Write  Reg addr 0x110 \n");
1620                         tx_buf1[0]=0x74;
1621                         tx_buf1[1]=0x80;              //func0 should be
1622                         tx_buf1[2]=0x02;
1623                         tx_buf1[3]=0x20;
1624                         tx_buf1[4]=(unsigned char)(SPI_BLOCK_SIZE & 0xff);                       //0x02;
1625                         tx_buf1[5]=0x01;
1626                         sif_spi_write_raw(spi, tx_buf1, 6);
1627                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1628                                     //   esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1629               //  ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1630
1631                         //spi_err("CMD52 Write Reg addr 0x111 \n");
1632                         tx_buf1[0]=0x74;
1633                         tx_buf1[1]=0x80;
1634                         tx_buf1[2]=0x02;
1635                         tx_buf1[3]=0x22;
1636                         tx_buf1[4]=(unsigned char)(SPI_BLOCK_SIZE>>8);                      //0x00;
1637                         tx_buf1[5]=0x01;
1638                         sif_spi_write_raw(spi, tx_buf1, 6);
1639                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1640                                     //   esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1641               //  ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1642
1643                         //spi_err("CMD52 Write Reg addr 0x111 \n");   /* set boot mode */
1644                         tx_buf1[0]=0x74;
1645                         tx_buf1[1]=0x80;
1646                         tx_buf1[2]=0x41;
1647                         tx_buf1[3]=0xe0;
1648                         tx_buf1[4]=0x01;          //0x00;
1649                         tx_buf1[5]=0x01;
1650                         sif_spi_write_raw(spi, tx_buf1, 6);
1651                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1652                                        esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1653                 ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1654
1655                 }
1656                 else if (spi_proto_ini_status==16)
1657                 {
1658 #if 0
1659                         //printf("CMD52 Write  Reg addr 0x40 \n");
1660                         tx_buf1[0]=0x74;
1661                         tx_buf1[1]=0x90;
1662                         tx_buf1[2]=0x00;
1663                         tx_buf1[3]=0x80;
1664                         tx_buf1[4]=0x91;                       //0x02;
1665                         tx_buf1[5]=0x01;
1666                         sif_spi_write_raw(spi, tx_buf1, 6);
1667                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1668                 esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1669                 ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1670
1671                         //sif_spi_read_bytes( 0x0c,rx_buf1, 4);
1672
1673                         //printf("CMD52 Write  Reg addr 0x3c \n");
1674                         tx_buf1[0]=0x74;
1675                         tx_buf1[1]=0x90;
1676                         tx_buf1[2]=0x00;
1677                         tx_buf1[3]=0x78;
1678                         tx_buf1[4]=0x3f;
1679                         tx_buf1[5]=0x01;
1680                         sif_spi_write_raw(spi, tx_buf1, 6);
1681                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1682                         esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1683                 ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1684
1685                                                                 //printf("CMD52 Write  Reg addr 0x3d \n");
1686                         tx_buf1[0]=0x74;
1687                         tx_buf1[1]=0x90;
1688                         tx_buf1[2]=0x00;
1689                         tx_buf1[3]=0x7a;
1690                         tx_buf1[4]=0x34;                        //0x02;
1691                         tx_buf1[5]=0x01;
1692                         sif_spi_write_raw(spi, tx_buf1, 6);
1693                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1694                         esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1695                 ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1696
1697                                                                // printf("CMD52 Write  Reg addr 0x3e \n");
1698                         tx_buf1[0]=0x74;
1699                         tx_buf1[1]=0x90;
1700                         tx_buf1[2]=0x00;
1701                         tx_buf1[3]=0x7c;
1702                         tx_buf1[4]=0xfe;                       //0x02;
1703                         tx_buf1[5]=0x01;
1704                         sif_spi_write_raw(spi, tx_buf1, 6);
1705                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1706                         esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1707                 ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1708
1709                                                                 //printf("CMD52 Write  Reg addr 0x3f \n");
1710                         tx_buf1[0]=0x74;
1711                         tx_buf1[1]=0x90;
1712                         tx_buf1[2]=0x00;
1713                         tx_buf1[3]=0x7e;
1714                         tx_buf1[4]=0x00;                       //0x02;
1715                         tx_buf1[5]=0x01;
1716                         sif_spi_write_raw(spi, tx_buf1, 6);
1717                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1718                         esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1719                 ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1720
1721                                                                 //printf("CMD52 Write  Reg addr 0x40 \n");
1722                         tx_buf1[0]=0x74;
1723                         tx_buf1[1]=0x90;
1724                         tx_buf1[2]=0x00;
1725                         tx_buf1[3]=0x80;
1726                         tx_buf1[4]=0xd1;                      //0x02;
1727                         tx_buf1[5]=0x01;
1728                         sif_spi_write_raw(spi, tx_buf1, 6);
1729                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1730                         esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1731                 ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1732
1733                         tx_buf1[0]=0x74;
1734                         tx_buf1[1]=0x90;
1735                         tx_buf1[2]=0x00;
1736                         tx_buf1[3]=0x52;
1737                         tx_buf1[4]=0x30;                      //0x02;
1738                         tx_buf1[5]=0x01;
1739                         sif_spi_write_raw(spi, tx_buf1, 6);
1740                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1741                         esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1742                 ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1743
1744 #endif
1745                 }
1746                 else
1747                 {
1748                         break;
1749                }
1750                                             //  mdelay(500);
1751                    spi_proto_ini_status++;
1752         } while (1);
1753         return 0;
1754 }
1755
1756 static int spi_irq_thread(void *data)
1757 {
1758         struct spi_device *spi = (struct spi_device *)data;
1759
1760         do {
1761                 sif_dsr(spi);
1762
1763                 set_current_state(TASK_INTERRUPTIBLE);
1764                 sif_platform_irq_mask(0);
1765
1766                 if (!kthread_should_stop())
1767                         schedule();
1768
1769                 set_current_state(TASK_RUNNING);
1770
1771         } while (!kthread_should_stop());
1772         return 0;
1773 }
1774
1775 int sif_setup_irq_thread(struct spi_device *spi)
1776 {
1777         sif_irq_thread = kthread_run(spi_irq_thread, spi, "kspiirqd/eagle");
1778         if (IS_ERR(sif_irq_thread)) {
1779                 esp_dbg(ESP_DBG_ERROR, "setup irq thread error!\n");
1780                 return -1;
1781         }
1782         return 0;
1783 }
1784
1785 static irqreturn_t sif_irq_handler(int irq, void *dev_id)
1786 {
1787         sif_platform_irq_mask(1);
1788
1789         if (sif_platform_is_irq_occur()) {
1790                 wake_up_process(sif_irq_thread);
1791         } else {
1792                 sif_platform_irq_mask(0);
1793                 return IRQ_NONE;
1794         }
1795
1796         return IRQ_HANDLED;
1797 }
1798
1799 void sif_enable_irq(struct esp_pub *epub)
1800 {
1801         int err;
1802         struct esp_spi_ctrl *sctrl = NULL;
1803         struct spi_device *spi = NULL;
1804
1805         if (epub == NULL) {
1806                 ESSERT(0);
1807                 return;
1808         }
1809         sctrl = (struct esp_spi_ctrl *)epub->sif;
1810         spi = sctrl->spi;
1811         if (spi == NULL) {
1812                 ESSERT(0);
1813                 return;
1814         }
1815
1816         mdelay(100);
1817
1818         sif_platform_irq_init();
1819         err = sif_setup_irq_thread(spi);
1820         if (err) {
1821                 esp_dbg(ESP_DBG_ERROR, "%s setup sif irq failed\n", __func__);
1822                 return;
1823         }
1824
1825 /******************compat with other device in some shared irq system ********************/
1826
1827 #ifdef  REQUEST_IRQ_SHARED
1828 #if   defined(REQUEST_IRQ_RISING)
1829         err = request_irq(sif_platform_get_irq_no(), sif_irq_handler, IRQF_TRIGGER_RISING | IRQF_SHARED, "esp_spi_irq", spi);
1830 #elif defined(REQUEST_IRQ_FALLING)
1831         err = request_irq(sif_platform_get_irq_no(), sif_irq_handler, IRQF_TRIGGER_FALLING | IRQF_SHARED, "esp_spi_irq", spi);
1832 #elif defined(REQUEST_IRQ_LOWLEVEL)
1833         err = request_irq(sif_platform_get_irq_no(), sif_irq_handler, IRQF_TRIGGER_LOW | IRQF_SHARED, "esp_spi_irq", spi);
1834 #elif defined(REQUEST_IRQ_HIGHLEVEL)
1835         err = request_irq(sif_platform_get_irq_no(), sif_irq_handler, IRQF_TRIGGER_HIGH | IRQF_SHARED, "esp_spi_irq", spi);
1836 #else   /* default */
1837         err = request_irq(sif_platform_get_irq_no(), sif_irq_handler, IRQF_TRIGGER_LOW | IRQF_SHARED, "esp_spi_irq", spi);
1838 #endif /* TRIGGER MODE */
1839 #else
1840         err = request_irq(sif_platform_get_irq_no(), sif_irq_handler, IRQF_TRIGGER_LOW, "esp_spi_irq", spi);
1841 #endif /* ESP_IRQ_SHARED */
1842
1843         if (err) {
1844                 esp_dbg(ESP_DBG_ERROR, "sif %s failed\n", __func__);
1845                 return ;
1846         }
1847 #ifdef IRQ_WAKE_HOST
1848         enable_irq_wake(sif_platform_get_irq_no());
1849 #endif
1850         atomic_set(&sctrl->irq_installed, 1);
1851 }
1852
1853 void sif_disable_irq(struct esp_pub *epub)
1854 {
1855         int i = 0;
1856         struct esp_spi_ctrl *sctrl = NULL;
1857         struct spi_device *spi = NULL;
1858
1859         if (epub == NULL) {
1860                 ESSERT(0);
1861                 return;
1862         }
1863         sctrl = (struct esp_spi_ctrl *)epub->sif;
1864         spi = sctrl->spi;
1865         if (spi == NULL) {
1866                 ESSERT(0);
1867                 return;
1868         }
1869
1870         if (atomic_read(&sctrl->irq_installed) == 0)
1871                 return;
1872
1873         while (atomic_read(&sctrl->irq_handling)) {
1874                 schedule_timeout(HZ / 100);
1875                 if (i++ >= 400) {
1876                         esp_dbg(ESP_DBG_ERROR, "%s force to stop irq\n", __func__);
1877                         break;
1878                 }
1879         }
1880
1881         free_irq(sif_platform_get_irq_no(), spi);
1882         kthread_stop(sif_irq_thread);
1883
1884         sif_platform_irq_deinit();
1885
1886         atomic_set(&sctrl->irq_installed, 0);
1887 }
1888
1889
1890 int esp_setup_spi(struct spi_device *spi)
1891 {
1892 #ifndef ESP_PREALLOC
1893         int retry = 10;
1894 #endif
1895         /**** alloc buffer for spi io */
1896         if (sif_sdio_state == ESP_SDIO_STATE_FIRST_INIT) {
1897 #ifdef ESP_PREALLOC
1898                 if ((buf_addr = esp_get_lspi_buf()) == NULL)
1899                         goto _err_buf_addr;
1900 #else
1901                 while ((buf_addr = (unsigned char *)kmalloc (MAX_BUF_SIZE, GFP_KERNEL)) == NULL) {
1902                                 if (--retry < 0)
1903                                         goto _err_buf_addr;
1904                 }
1905 #endif
1906                 if ((check_buf = (unsigned char *)kmalloc (256, GFP_KERNEL)) == NULL)
1907                                         goto _err_check_buf;
1908
1909                 if ((ff_buf = (unsigned char *)kmalloc (256, GFP_KERNEL)) == NULL)
1910                                         goto _err_ff_buf;
1911
1912                 memset(ff_buf,0xff,256);
1913
1914                 tx_cmd = buf_addr;
1915                 rx_cmd = buf_addr;
1916         }
1917         spi_resp.max_dataW_resp_size = 0;
1918         spi_resp.max_dataR_resp_size = 0;
1919         spi_resp.max_block_dataW_resp_size = 0;
1920         spi_resp.max_block_dataR_resp_size = 0;
1921         spi_resp.max_cmd_resp_size = 0;
1922         if( sif_get_ate_config() != 5)
1923         {
1924                 spi_resp.data_resp_size_w = DATA_RESP_SIZE_W;
1925                 spi_resp.data_resp_size_r = DATA_RESP_SIZE_R;
1926                 spi_resp.block_w_data_resp_size_final = BLOCK_W_DATA_RESP_SIZE_FINAL;
1927                 spi_resp.block_r_data_resp_size_final = BLOCK_R_DATA_RESP_SIZE_1ST;
1928         } else {
1929                 spi_resp.data_resp_size_w = 1000;
1930                 spi_resp.data_resp_size_r = 1000;
1931                 spi_resp.block_w_data_resp_size_final = 1000;
1932                 spi_resp.block_r_data_resp_size_final = 1000;
1933         }
1934
1935         return 0;
1936
1937 _err_ff_buf:
1938         if (check_buf) {
1939                 kfree(check_buf);
1940                 check_buf = NULL;
1941         }
1942 _err_check_buf:
1943         if (buf_addr) {
1944 #ifdef ESP_PREALLOC
1945                 esp_put_lspi_buf(&buf_addr);
1946 #else
1947                 kfree(buf_addr);
1948 #endif
1949                 buf_addr = NULL;
1950         }
1951 _err_buf_addr:
1952         return -ENOMEM;
1953 }
1954
1955
1956 static int esp_spi_probe(struct spi_device *spi);
1957 static int esp_spi_remove(struct spi_device *spi);
1958
1959 static int esp_spi_probe(struct spi_device *spi)
1960 {
1961         int err;
1962         struct esp_pub *epub;
1963         struct esp_spi_ctrl *sctrl;
1964
1965         esp_dbg(ESP_DBG_ERROR, "%s enter\n", __func__);
1966
1967         err = esp_setup_spi(spi);
1968         if (err) {
1969                 esp_dbg(ESP_DBG_ERROR, "%s setup_spi error[%d]\n", __func__, err);
1970                 if(sif_sdio_state == ESP_SDIO_STATE_FIRST_INIT)
1971                         goto _err_spi;
1972                 else
1973                         goto _err_second_init;
1974         }
1975         esp_dbg(ESP_DBG_ERROR, "%s init_protocol\n", __func__);
1976         err = sif_spi_protocol_init(spi);
1977         if(err){
1978                 if(sif_sdio_state == ESP_SDIO_STATE_FIRST_INIT)
1979                         goto _err_spi;
1980                 else
1981                         goto _err_second_init;
1982         }
1983
1984         if(sif_sdio_state == ESP_SDIO_STATE_FIRST_INIT){
1985                 sctrl = kzalloc(sizeof(struct esp_spi_ctrl), GFP_KERNEL);
1986
1987                 if (sctrl == NULL) {
1988                         err = -ENOMEM;
1989                         goto _err_spi;
1990                 }
1991
1992                 /* temp buffer reserved for un-dma-able request */
1993                 sctrl->dma_buffer = kzalloc(ESP_DMA_IBUFSZ, GFP_KERNEL);
1994
1995                 if (sctrl->dma_buffer == NULL) {
1996                         err = -ENOMEM;
1997                         goto _err_last;
1998                 }
1999                 sif_sctrl = sctrl;
2000                 sctrl->slc_blk_sz = SIF_SLC_BLOCK_SIZE;
2001
2002                 epub = esp_pub_alloc_mac80211(&spi->dev);
2003
2004                 if (epub == NULL) {
2005                         esp_dbg(ESP_DBG_ERROR, "no mem for epub \n");
2006                         err = -ENOMEM;
2007                         goto _err_dma;
2008                 }
2009                 epub->sif = (void *)sctrl;
2010                 sctrl->epub = epub;
2011
2012 #ifdef USE_EXT_GPIO
2013                 if (sif_get_ate_config() == 0) {
2014                         err = ext_gpio_init(epub);
2015                         if (err) {
2016                                 esp_dbg(ESP_DBG_ERROR, "ext_irq_work_init failed %d\n", err);
2017                                 goto _err_epub;
2018                         }
2019                 }
2020 #endif
2021         } else {
2022                 sctrl = sif_sctrl;
2023                 sif_sctrl = NULL;
2024                 epub = sctrl->epub;
2025                 SET_IEEE80211_DEV(epub->hw, &spi->dev);
2026                 epub->dev = &spi->dev;
2027         }
2028
2029         epub->sdio_state = sif_sdio_state;
2030
2031         sctrl->spi = spi;
2032         spi_set_drvdata(spi, sctrl);
2033
2034         if (err){
2035                 if(sif_sdio_state == ESP_SDIO_STATE_FIRST_INIT)
2036                         goto _err_ext_gpio;
2037                 else
2038                         goto _err_second_init;
2039         }
2040         check_target_id(epub);
2041
2042         err = esp_pub_init_all(epub);
2043
2044         if (err) {
2045                 esp_dbg(ESP_DBG_ERROR, "esp_init_all failed: %d\n", err);
2046                 if(sif_sdio_state == ESP_SDIO_STATE_FIRST_INIT){
2047                         err = 0;
2048                         goto _err_first_init;
2049                 }
2050                 if(sif_sdio_state == ESP_SDIO_STATE_SECOND_INIT)
2051                         goto _err_second_init;
2052         }
2053
2054         esp_dbg(ESP_DBG_TRACE, " %s return  %d\n", __func__, err);
2055         if(sif_sdio_state == ESP_SDIO_STATE_FIRST_INIT){
2056                 esp_dbg(ESP_DBG_ERROR, "first normal exit\n");
2057                 sif_sdio_state = ESP_SDIO_STATE_FIRST_NORMAL_EXIT;
2058                 up(&esp_powerup_sem);
2059         }
2060
2061         return err;
2062 _err_ext_gpio:
2063 #ifdef USE_EXT_GPIO
2064         if (sif_get_ate_config() == 0)
2065                 ext_gpio_deinit();
2066 _err_epub:
2067 #endif
2068         esp_pub_dealloc_mac80211(epub);
2069 _err_dma:
2070         kfree(sctrl->dma_buffer);
2071 _err_last:
2072         kfree(sctrl);
2073 _err_spi:
2074         if (buf_addr) {
2075 #ifdef ESP_PREALLOC
2076                 esp_put_lspi_buf(&buf_addr);
2077 #else
2078                 kfree(buf_addr);
2079 #endif
2080                 buf_addr = NULL;
2081                 tx_cmd = NULL;
2082                 rx_cmd = NULL;
2083         }
2084         if (check_buf) {
2085                 kfree(check_buf);
2086                 check_buf = NULL;
2087         }
2088         if (ff_buf) {
2089                 kfree(ff_buf);
2090                 ff_buf = NULL;
2091         }
2092
2093 _err_first_init:
2094         if(sif_sdio_state == ESP_SDIO_STATE_FIRST_INIT){
2095                 esp_dbg(ESP_DBG_ERROR, "first error exit\n");
2096                 sif_sdio_state = ESP_SDIO_STATE_FIRST_ERROR_EXIT;
2097                 up(&esp_powerup_sem);
2098         }
2099         return err;
2100 _err_second_init:
2101         sif_sdio_state = ESP_SDIO_STATE_SECOND_ERROR_EXIT;
2102         esp_spi_remove(spi);
2103         return err;
2104 }
2105
2106 static int esp_spi_remove(struct spi_device *spi)
2107 {
2108         struct esp_spi_ctrl *sctrl = NULL;
2109
2110         esp_dbg(ESP_SHOW, "%s \n", __func__);
2111
2112         sctrl = spi_get_drvdata(spi);
2113
2114         if (sctrl == NULL) {
2115                 esp_dbg(ESP_DBG_ERROR, "%s no sctrl\n", __func__);
2116                 return -EINVAL;
2117         }
2118
2119         do {
2120                 if (sctrl->epub == NULL) {
2121                         esp_dbg(ESP_DBG_ERROR, "%s epub null\n", __func__);
2122                         break;
2123                 }
2124                 sctrl->epub->sdio_state = sif_sdio_state;
2125                 if(sif_sdio_state != ESP_SDIO_STATE_FIRST_NORMAL_EXIT){
2126                         if (sctrl->epub->sip) {
2127                                 sip_detach(sctrl->epub->sip);
2128                                 sctrl->epub->sip = NULL;
2129                                 esp_dbg(ESP_DBG_TRACE, "%s sip detached \n", __func__);
2130                         }
2131 #ifdef USE_EXT_GPIO
2132                         if (sif_get_ate_config() == 0)
2133                                 ext_gpio_deinit();
2134 #endif
2135                 } else {
2136                         //sif_disable_target_interrupt(sctrl->epub);
2137                         atomic_set(&sctrl->epub->sip->state, SIP_STOP);
2138                         sif_disable_irq(sctrl->epub);
2139                 }
2140
2141 #ifdef TEST_MODE
2142                 test_exit_netlink();
2143 #endif /* TEST_MODE */
2144                 if(sif_sdio_state != ESP_SDIO_STATE_FIRST_NORMAL_EXIT){
2145                         esp_pub_dealloc_mac80211(sctrl->epub);
2146                         esp_dbg(ESP_DBG_TRACE, "%s dealloc mac80211 \n", __func__);
2147
2148                         if (sctrl->dma_buffer) {
2149                                 kfree(sctrl->dma_buffer);
2150                                 sctrl->dma_buffer = NULL;
2151                                 esp_dbg(ESP_DBG_TRACE, "%s free dma_buffer \n", __func__);
2152                         }
2153
2154                         kfree(sctrl);
2155
2156                         if (buf_addr) {
2157 #ifdef ESP_PREALLOC
2158                                 esp_put_lspi_buf(&buf_addr);
2159 #else
2160                                 kfree(buf_addr);
2161 #endif
2162                                 buf_addr = NULL;
2163                                 rx_cmd = NULL;
2164                                 tx_cmd = NULL;
2165                         }
2166
2167                         if (check_buf) {
2168                                 kfree(check_buf);
2169                                 check_buf = NULL;
2170                         }
2171
2172                         if (ff_buf) {
2173                                 kfree(ff_buf);
2174                                 ff_buf = NULL;
2175                         }
2176
2177                 }
2178
2179         } while (0);
2180
2181         spi_set_drvdata(spi,NULL);
2182
2183         esp_dbg(ESP_DBG_TRACE, "eagle spi remove complete\n");
2184
2185         return 0;
2186 }
2187
2188 static int esp_spi_suspend(struct device *dev)
2189 {
2190         struct spi_device *spi = to_spi_device(dev);
2191         struct esp_spi_ctrl *sctrl = spi_get_drvdata(spi);
2192         struct esp_pub *epub = sctrl->epub;
2193
2194         printk("%s", __func__);
2195 #if 0
2196         sip_send_suspend_config(epub, 1);
2197 #endif
2198         atomic_set(&epub->ps.state, ESP_PM_ON);
2199         return 0;
2200 }
2201
2202 static int esp_spi_resume(struct device *dev)
2203 {
2204         esp_dbg(ESP_DBG_ERROR, "%s", __func__);
2205
2206         return 0;
2207 }
2208
2209 static const struct dev_pm_ops esp_spi_pm_ops = {
2210         .suspend= esp_spi_suspend,
2211         .resume= esp_spi_resume,
2212 };
2213
2214 extern struct spi_device_id esp_spi_id[];
2215
2216 struct spi_driver esp_spi_driver = {
2217         .id_table = esp_spi_id,
2218         .driver = {
2219                 .name   = "eagle",
2220                 .bus    = &spi_bus_type,
2221                 .owner  = THIS_MODULE,
2222                 .pm = &esp_spi_pm_ops,
2223         },
2224         .probe  = esp_spi_probe,
2225         .remove = esp_spi_remove,
2226 };
2227
2228 static int esp_spi_dummy_probe(struct spi_device *spi)
2229 {
2230         esp_dbg(ESP_DBG_ERROR, "%s enter\n", __func__);
2231
2232         up(&esp_powerup_sem);
2233
2234         return 0;
2235 }
2236
2237 static int esp_spi_dummy_remove(struct spi_device *spi)
2238 {
2239         return 0;
2240 }
2241
2242 struct spi_driver esp_spi_dummy_driver = {
2243         .id_table = esp_spi_id,
2244         .driver = {
2245                 .name   = "eagle_dummy",
2246                 .bus    = &spi_bus_type,
2247                 .owner  = THIS_MODULE,
2248         },
2249         .probe  = esp_spi_dummy_probe,
2250         .remove = esp_spi_dummy_remove,
2251 };
2252
2253 int esp_spi_init(void)
2254 {
2255 #define ESP_WAIT_UP_TIME_MS 11000
2256         int err;
2257         int retry = 3;
2258         bool powerup = false;
2259
2260         esp_dbg(ESP_DBG_TRACE, "%s \n", __func__);
2261
2262 #ifdef REGISTER_SPI_BOARD_INFO
2263         sif_platform_register_board_info();
2264 #endif
2265
2266         esp_wakelock_init();
2267         esp_wake_lock();
2268
2269         do {
2270                 sema_init(&esp_powerup_sem, 0);
2271
2272                 sif_platform_target_poweron();
2273
2274                 err = spi_register_driver(&esp_spi_dummy_driver);
2275                 if (err) {
2276                         esp_dbg(ESP_DBG_ERROR, "eagle spi driver registration failed, error code: %d\n", err);
2277                         goto _fail;
2278                 }
2279
2280                 if (down_timeout(&esp_powerup_sem,
2281                                  msecs_to_jiffies(ESP_WAIT_UP_TIME_MS)) == 0)
2282                 {
2283
2284                         powerup = true;
2285                         msleep(200);
2286                         break;
2287                 }
2288
2289                 esp_dbg(ESP_SHOW, "%s ------ RETRY ------ \n", __func__);
2290
2291                 sif_record_retry_config();
2292
2293                 spi_unregister_driver(&esp_spi_dummy_driver);
2294
2295                 sif_platform_target_poweroff();
2296
2297         } while (retry--);
2298
2299         if (!powerup) {
2300                 esp_dbg(ESP_DBG_ERROR, "eagle spi can not power up!\n");
2301
2302                 err = -ENODEV;
2303                 goto _fail;
2304         }
2305
2306         esp_dbg(ESP_SHOW, "%s power up OK\n", __func__);
2307
2308         spi_unregister_driver(&esp_spi_dummy_driver);
2309
2310         sif_sdio_state = ESP_SDIO_STATE_FIRST_INIT;
2311         sema_init(&esp_powerup_sem, 0);
2312
2313         spi_register_driver(&esp_spi_driver);
2314
2315         if (down_timeout(&esp_powerup_sem,
2316                                  msecs_to_jiffies(ESP_WAIT_UP_TIME_MS)) == 0 && sif_get_ate_config() == 0) {
2317                 if(sif_sdio_state == ESP_SDIO_STATE_FIRST_NORMAL_EXIT){
2318                         spi_unregister_driver(&esp_spi_driver);
2319
2320                         msleep(100);
2321
2322                         sif_sdio_state = ESP_SDIO_STATE_SECOND_INIT;
2323
2324                         spi_register_driver(&esp_spi_driver);
2325                 }
2326
2327         }
2328
2329         esp_register_early_suspend();
2330         esp_wake_unlock();
2331 #ifdef REQUEST_RTC_IRQ
2332         request_rtc_irq();
2333 #endif
2334         return err;
2335
2336 _fail:
2337         esp_wake_unlock();
2338         esp_wakelock_destroy();
2339
2340         return err;
2341 }
2342
2343 void esp_spi_exit(void)
2344 {
2345         esp_dbg(ESP_SHOW, "%s \n", __func__);
2346
2347         esp_unregister_early_suspend();
2348
2349         spi_unregister_driver(&esp_spi_driver);
2350
2351 #ifndef FPGA_DEBUG
2352         sif_platform_target_poweroff();
2353 #endif /* !FPGA_DEBUG */
2354
2355         esp_wakelock_destroy();
2356 }
2357
2358 MODULE_AUTHOR("Espressif System");
2359 MODULE_DESCRIPTION("Driver for SPI interconnected eagle low-power WLAN devices");
2360 MODULE_LICENSE("GPL");
2361 #endif /* ESP_USE_SPI */