drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
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   4  * redistributing this file, you may do so under either license.
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   6  * GPL LICENSE SUMMARY
   7  *
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  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
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  20  * along with this program; if not, write to the Free Software
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  44  *    the documentation and/or other materials provided with the
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  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
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  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/pci.h>
  64 #include <linux/pci-aspm.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/sched.h>
  68 #include <linux/bitops.h>
  69 #include <linux/gfp.h>
  70
  71 #include "iwl-drv.h"
  72 #include "iwl-trans.h"
  73 #include "iwl-csr.h"
  74 #include "iwl-prph.h"
  75 #include "iwl-agn-hw.h"
  76 #include "internal.h"
  77
  78 static void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans,
  79                                                   u32 reg, u32 mask, u32 value)
  80 {
  81         u32 v;
  82
  83 #ifdef CONFIG_IWLWIFI_DEBUG
  84         WARN_ON_ONCE(value & ~mask);
  85 #endif
  86
  87         v = iwl_read32(trans, reg);
  88         v &= ~mask;
  89         v |= value;
  90         iwl_write32(trans, reg, v);
  91 }
  92
  93 static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans,
  94                                               u32 reg, u32 mask)
  95 {
  96         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0);
  97 }
  98
  99 static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
 100                                             u32 reg, u32 mask)
 101 {
 102         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
 103 }
 104
 105 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 106 {
 107         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 108                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 109                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 110                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 111         else
 112                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 113                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 114                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 115 }
 116
 117 /* PCI registers */
 118 #define PCI_CFG_RETRY_TIMEOUT   0x041
 119
 120 static void iwl_pcie_apm_config(struct iwl_trans *trans)
 121 {
 122         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 123         u16 lctl;
 124
 125         /*
 126          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 127          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 128          * If so (likely), disable L0S, so device moves directly L0->L1;
 129          *    costs negligible amount of power savings.
 130          * If not (unlikely), enable L0S, so there is at least some
 131          *    power savings, even without L1.
 132          */
 133         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 134         if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
 135                 /* L1-ASPM enabled; disable(!) L0S */
 136                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 137                 dev_info(trans->dev, "L1 Enabled; Disabling L0S\n");
 138         } else {
 139                 /* L1-ASPM disabled; enable(!) L0S */
 140                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 141                 dev_info(trans->dev, "L1 Disabled; Enabling L0S\n");
 142         }
 143         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 144 }
 145
 146 /*
 147  * Start up NIC's basic functionality after it has been reset
 148  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 149  * NOTE:  This does not load uCode nor start the embedded processor
 150  */
 151 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 152 {
 153         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 154         int ret = 0;
 155         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 156
 157         /*
 158          * Use "set_bit" below rather than "write", to preserve any hardware
 159          * bits already set by default after reset.
 160          */
 161
 162         /* Disable L0S exit timer (platform NMI Work/Around) */
 163         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 164                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 165
 166         /*
 167          * Disable L0s without affecting L1;
 168          *  don't wait for ICH L0s (ICH bug W/A)
 169          */
 170         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 171                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 172
 173         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 174         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 175
 176         /*
 177          * Enable HAP INTA (interrupt from management bus) to
 178          * wake device's PCI Express link L1a -> L0s
 179          */
 180         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 181                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 182
 183         iwl_pcie_apm_config(trans);
 184
 185         /* Configure analog phase-lock-loop before activating to D0A */
 186         if (trans->cfg->base_params->pll_cfg_val)
 187                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 188                             trans->cfg->base_params->pll_cfg_val);
 189
 190         /*
 191          * Set "initialization complete" bit to move adapter from
 192          * D0U* --> D0A* (powered-up active) state.
 193          */
 194         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 195
 196         /*
 197          * Wait for clock stabilization; once stabilized, access to
 198          * device-internal resources is supported, e.g. iwl_write_prph()
 199          * and accesses to uCode SRAM.
 200          */
 201         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 202                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 203                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 204         if (ret < 0) {
 205                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 206                 goto out;
 207         }
 208
 209         /*
 210          * Enable the oscillator to count wake up time for L1 exit. This
 211          * consumes slightly more power (100uA) - but allows to be sure
 212          * that we wake up from L1 on time.
 213          *
 214          * This looks weird: read twice the same register, discard the
 215          * value, set a bit, and yet again, read that same register
 216          * just to discard the value. But that's the way the hardware
 217          * seems to like it.
 218          */
 219         iwl_read_prph(trans, OSC_CLK);
 220         iwl_read_prph(trans, OSC_CLK);
 221         iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 222         iwl_read_prph(trans, OSC_CLK);
 223         iwl_read_prph(trans, OSC_CLK);
 224
 225         /*
 226          * Enable DMA clock and wait for it to stabilize.
 227          *
 228          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
 229          * do not disable clocks.  This preserves any hardware bits already
 230          * set by default in "CLK_CTRL_REG" after reset.
 231          */
 232         iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 233         udelay(20);
 234
 235         /* Disable L1-Active */
 236         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 237                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 238
 239         set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 240
 241 out:
 242         return ret;
 243 }
 244
 245 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 246 {
 247         int ret = 0;
 248
 249         /* stop device's busmaster DMA activity */
 250         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 251
 252         ret = iwl_poll_bit(trans, CSR_RESET,
 253                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 254                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 255         if (ret)
 256                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 257
 258         IWL_DEBUG_INFO(trans, "stop master\n");
 259
 260         return ret;
 261 }
 262
 263 static void iwl_pcie_apm_stop(struct iwl_trans *trans)
 264 {
 265         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 266         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 267
 268         clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 269
 270         /* Stop device's DMA activity */
 271         iwl_pcie_apm_stop_master(trans);
 272
 273         /* Reset the entire device */
 274         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 275
 276         udelay(10);
 277
 278         /*
 279          * Clear "initialization complete" bit to move adapter from
 280          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 281          */
 282         iwl_clear_bit(trans, CSR_GP_CNTRL,
 283                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 284 }
 285
 286 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 287 {
 288         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 289         unsigned long flags;
 290
 291         /* nic_init */
 292         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 293         iwl_pcie_apm_init(trans);
 294
 295         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 296
 297         iwl_pcie_set_pwr(trans, false);
 298
 299         iwl_op_mode_nic_config(trans->op_mode);
 300
 301         /* Allocate the RX queue, or reset if it is already allocated */
 302         iwl_pcie_rx_init(trans);
 303
 304         /* Allocate or reset and init all Tx and Command queues */
 305         if (iwl_pcie_tx_init(trans))
 306                 return -ENOMEM;
 307
 308         if (trans->cfg->base_params->shadow_reg_enable) {
 309                 /* enable shadow regs in HW */
 310                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 311                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 312         }
 313
 314         return 0;
 315 }
 316
 317 #define HW_READY_TIMEOUT (50)
 318
 319 /* Note: returns poll_bit return value, which is >= 0 if success */
 320 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 321 {
 322         int ret;
 323
 324         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 325                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 326
 327         /* See if we got it */
 328         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 329                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 330                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 331                            HW_READY_TIMEOUT);
 332
 333         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 334         return ret;
 335 }
 336
 337 /* Note: returns standard 0/-ERROR code */
 338 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 339 {
 340         int ret;
 341         int t = 0;
 342         int iter;
 343
 344         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 345
 346         ret = iwl_pcie_set_hw_ready(trans);
 347         /* If the card is ready, exit 0 */
 348         if (ret >= 0)
 349                 return 0;
 350
 351         for (iter = 0; iter < 10; iter++) {
 352                 /* If HW is not ready, prepare the conditions to check again */
 353                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 354                             CSR_HW_IF_CONFIG_REG_PREPARE);
 355
 356                 do {
 357                         ret = iwl_pcie_set_hw_ready(trans);
 358                         if (ret >= 0)
 359                                 return 0;
 360
 361                         usleep_range(200, 1000);
 362                         t += 200;
 363                 } while (t < 150000);
 364                 msleep(25);
 365         }
 366
 367         IWL_DEBUG_INFO(trans, "got NIC after %d iterations\n", iter);
 368
 369         return ret;
 370 }
 371
 372 /*
 373  * ucode
 374  */
 375 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 376                                    dma_addr_t phy_addr, u32 byte_cnt)
 377 {
 378         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 379         int ret;
 380
 381         trans_pcie->ucode_write_complete = false;
 382
 383         iwl_write_direct32(trans,
 384                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 385                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 386
 387         iwl_write_direct32(trans,
 388                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 389                            dst_addr);
 390
 391         iwl_write_direct32(trans,
 392                            FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 393                            phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 394
 395         iwl_write_direct32(trans,
 396                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 397                            (iwl_get_dma_hi_addr(phy_addr)
 398                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 399
 400         iwl_write_direct32(trans,
 401                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 402                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 403                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 404                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 405
 406         iwl_write_direct32(trans,
 407                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 408                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 409                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 410                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 411
 412         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 413                                  trans_pcie->ucode_write_complete, 5 * HZ);
 414         if (!ret) {
 415                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 416                 return -ETIMEDOUT;
 417         }
 418
 419         return 0;
 420 }
 421
 422 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 423                             const struct fw_desc *section)
 424 {
 425         u8 *v_addr;
 426         dma_addr_t p_addr;
 427         u32 offset;
 428         int ret = 0;
 429
 430         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 431                      section_num);
 432
 433         v_addr = dma_alloc_coherent(trans->dev, PAGE_SIZE, &p_addr, GFP_KERNEL);
 434         if (!v_addr)
 435                 return -ENOMEM;
 436
 437         for (offset = 0; offset < section->len; offset += PAGE_SIZE) {
 438                 u32 copy_size;
 439
 440                 copy_size = min_t(u32, PAGE_SIZE, section->len - offset);
 441
 442                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 443                 ret = iwl_pcie_load_firmware_chunk(trans,
 444                                                    section->offset + offset,
 445                                                    p_addr, copy_size);
 446                 if (ret) {
 447                         IWL_ERR(trans,
 448                                 "Could not load the [%d] uCode section\n",
 449                                 section_num);
 450                         break;
 451                 }
 452         }
 453
 454         dma_free_coherent(trans->dev, PAGE_SIZE, v_addr, p_addr);
 455         return ret;
 456 }
 457
 458 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 459                                 const struct fw_img *image)
 460 {
 461         int i, ret = 0;
 462
 463         for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
 464                 if (!image->sec[i].data)
 465                         break;
 466
 467                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 468                 if (ret)
 469                         return ret;
 470         }
 471
 472         /* Remove all resets to allow NIC to operate */
 473         iwl_write32(trans, CSR_RESET, 0);
 474
 475         return 0;
 476 }
 477
 478 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 479                                    const struct fw_img *fw, bool run_in_rfkill)
 480 {
 481         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 482         int ret;
 483         bool hw_rfkill;
 484
 485         /* This may fail if AMT took ownership of the device */
 486         if (iwl_pcie_prepare_card_hw(trans)) {
 487                 IWL_WARN(trans, "Exit HW not ready\n");
 488                 return -EIO;
 489         }
 490
 491         clear_bit(STATUS_FW_ERROR, &trans_pcie->status);
 492
 493         iwl_enable_rfkill_int(trans);
 494
 495         /* If platform's RF_KILL switch is NOT set to KILL */
 496         hw_rfkill = iwl_is_rfkill_set(trans);
 497         if (hw_rfkill)
 498                 set_bit(STATUS_RFKILL, &trans_pcie->status);
 499         else
 500                 clear_bit(STATUS_RFKILL, &trans_pcie->status);
 501         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 502         if (hw_rfkill && !run_in_rfkill)
 503                 return -ERFKILL;
 504
 505         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 506
 507         ret = iwl_pcie_nic_init(trans);
 508         if (ret) {
 509                 IWL_ERR(trans, "Unable to init nic\n");
 510                 return ret;
 511         }
 512
 513         /* make sure rfkill handshake bits are cleared */
 514         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 515         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
 516                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 517
 518         /* clear (again), then enable host interrupts */
 519         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 520         iwl_enable_interrupts(trans);
 521
 522         /* really make sure rfkill handshake bits are cleared */
 523         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 524         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 525
 526         /* Load the given image to the HW */
 527         return iwl_pcie_load_given_ucode(trans, fw);
 528 }
 529
 530 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
 531 {
 532         iwl_pcie_reset_ict(trans);
 533         iwl_pcie_tx_start(trans, scd_addr);
 534 }
 535
 536 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
 537 {
 538         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 539         unsigned long flags;
 540
 541         /* tell the device to stop sending interrupts */
 542         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 543         iwl_disable_interrupts(trans);
 544         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 545
 546         /* device going down, Stop using ICT table */
 547         iwl_pcie_disable_ict(trans);
 548
 549         /*
 550          * If a HW restart happens during firmware loading,
 551          * then the firmware loading might call this function
 552          * and later it might be called again due to the
 553          * restart. So don't process again if the device is
 554          * already dead.
 555          */
 556         if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
 557                 iwl_pcie_tx_stop(trans);
 558                 iwl_pcie_rx_stop(trans);
 559
 560                 /* Power-down device's busmaster DMA clocks */
 561                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
 562                                APMG_CLK_VAL_DMA_CLK_RQT);
 563                 udelay(5);
 564         }
 565
 566         /* Make sure (redundant) we've released our request to stay awake */
 567         iwl_clear_bit(trans, CSR_GP_CNTRL,
 568                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 569
 570         /* Stop the device, and put it in low power state */
 571         iwl_pcie_apm_stop(trans);
 572
 573         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
 574          * Clean again the interrupt here
 575          */
 576         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 577         iwl_disable_interrupts(trans);
 578         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 579
 580         iwl_enable_rfkill_int(trans);
 581
 582         /* stop and reset the on-board processor */
 583         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
 584
 585         /* clear all status bits */
 586         clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
 587         clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
 588         clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 589         clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
 590         clear_bit(STATUS_RFKILL, &trans_pcie->status);
 591 }
 592
 593 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans)
 594 {
 595         /* let the ucode operate on its own */
 596         iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
 597                     CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
 598
 599         iwl_disable_interrupts(trans);
 600         iwl_pcie_disable_ict(trans);
 601
 602         iwl_clear_bit(trans, CSR_GP_CNTRL,
 603                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 604         iwl_clear_bit(trans, CSR_GP_CNTRL,
 605                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 606
 607         /*
 608          * reset TX queues -- some of their registers reset during S3
 609          * so if we don't reset everything here the D3 image would try
 610          * to execute some invalid memory upon resume
 611          */
 612         iwl_trans_pcie_tx_reset(trans);
 613
 614         iwl_pcie_set_pwr(trans, true);
 615 }
 616
 617 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
 618                                     enum iwl_d3_status *status)
 619 {
 620         u32 val;
 621         int ret;
 622
 623         iwl_pcie_set_pwr(trans, false);
 624
 625         val = iwl_read32(trans, CSR_RESET);
 626         if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
 627                 *status = IWL_D3_STATUS_RESET;
 628                 return 0;
 629         }
 630
 631         /*
 632          * Also enables interrupts - none will happen as the device doesn't
 633          * know we're waking it up, only when the opmode actually tells it
 634          * after this call.
 635          */
 636         iwl_pcie_reset_ict(trans);
 637
 638         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 639         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 640
 641         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 642                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 643                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 644                            25000);
 645         if (ret) {
 646                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
 647                 return ret;
 648         }
 649
 650         iwl_trans_pcie_tx_reset(trans);
 651
 652         ret = iwl_pcie_rx_init(trans);
 653         if (ret) {
 654                 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
 655                 return ret;
 656         }
 657
 658         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
 659                     CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
 660
 661         *status = IWL_D3_STATUS_ALIVE;
 662         return 0;
 663 }
 664
 665 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
 666 {
 667         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 668         bool hw_rfkill;
 669         int err;
 670
 671         err = iwl_pcie_prepare_card_hw(trans);
 672         if (err) {
 673                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
 674                 return err;
 675         }
 676
 677         iwl_pcie_apm_init(trans);
 678
 679         /* From now on, the op_mode will be kept updated about RF kill state */
 680         iwl_enable_rfkill_int(trans);
 681
 682         hw_rfkill = iwl_is_rfkill_set(trans);
 683         if (hw_rfkill)
 684                 set_bit(STATUS_RFKILL, &trans_pcie->status);
 685         else
 686                 clear_bit(STATUS_RFKILL, &trans_pcie->status);
 687         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 688
 689         return 0;
 690 }
 691
 692 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
 693                                    bool op_mode_leaving)
 694 {
 695         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 696         bool hw_rfkill;
 697         unsigned long flags;
 698
 699         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 700         iwl_disable_interrupts(trans);
 701         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 702
 703         iwl_pcie_apm_stop(trans);
 704
 705         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 706         iwl_disable_interrupts(trans);
 707         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 708
 709         iwl_pcie_disable_ict(trans);
 710
 711         if (!op_mode_leaving) {
 712                 /*
 713                  * Even if we stop the HW, we still want the RF kill
 714                  * interrupt
 715                  */
 716                 iwl_enable_rfkill_int(trans);
 717
 718                 /*
 719                  * Check again since the RF kill state may have changed while
 720                  * all the interrupts were disabled, in this case we couldn't
 721                  * receive the RF kill interrupt and update the state in the
 722                  * op_mode.
 723                  */
 724                 hw_rfkill = iwl_is_rfkill_set(trans);
 725                 if (hw_rfkill)
 726                         set_bit(STATUS_RFKILL, &trans_pcie->status);
 727                 else
 728                         clear_bit(STATUS_RFKILL, &trans_pcie->status);
 729                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 730         }
 731 }
 732
 733 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
 734 {
 735         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 736 }
 737
 738 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
 739 {
 740         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 741 }
 742
 743 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
 744 {
 745         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 746 }
 747
 748 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
 749 {
 750         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
 751                                ((reg & 0x000FFFFF) | (3 << 24)));
 752         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
 753 }
 754
 755 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
 756                                       u32 val)
 757 {
 758         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
 759                                ((addr & 0x000FFFFF) | (3 << 24)));
 760         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
 761 }
 762
 763 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
 764                                      const struct iwl_trans_config *trans_cfg)
 765 {
 766         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 767
 768         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
 769         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
 770         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
 771                 trans_pcie->n_no_reclaim_cmds = 0;
 772         else
 773                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
 774         if (trans_pcie->n_no_reclaim_cmds)
 775                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
 776                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
 777
 778         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
 779         if (trans_pcie->rx_buf_size_8k)
 780                 trans_pcie->rx_page_order = get_order(8 * 1024);
 781         else
 782                 trans_pcie->rx_page_order = get_order(4 * 1024);
 783
 784         trans_pcie->wd_timeout =
 785                 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
 786
 787         trans_pcie->command_names = trans_cfg->command_names;
 788         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
 789 }
 790
 791 void iwl_trans_pcie_free(struct iwl_trans *trans)
 792 {
 793         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 794
 795         synchronize_irq(trans_pcie->pci_dev->irq);
 796
 797         iwl_pcie_tx_free(trans);
 798         iwl_pcie_rx_free(trans);
 799
 800         free_irq(trans_pcie->pci_dev->irq, trans);
 801         iwl_pcie_free_ict(trans);
 802
 803         pci_disable_msi(trans_pcie->pci_dev);
 804         iounmap(trans_pcie->hw_base);
 805         pci_release_regions(trans_pcie->pci_dev);
 806         pci_disable_device(trans_pcie->pci_dev);
 807         kmem_cache_destroy(trans->dev_cmd_pool);
 808
 809         kfree(trans);
 810 }
 811
 812 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
 813 {
 814         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 815
 816         if (state)
 817                 set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
 818         else
 819                 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
 820 }
 821
 822 #ifdef CONFIG_PM_SLEEP
 823 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
 824 {
 825         return 0;
 826 }
 827
 828 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
 829 {
 830         bool hw_rfkill;
 831
 832         iwl_enable_rfkill_int(trans);
 833
 834         hw_rfkill = iwl_is_rfkill_set(trans);
 835         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 836
 837         return 0;
 838 }
 839 #endif /* CONFIG_PM_SLEEP */
 840
 841 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
 842                                                 unsigned long *flags)
 843 {
 844         int ret;
 845         struct iwl_trans_pcie *pcie_trans = IWL_TRANS_GET_PCIE_TRANS(trans);
 846         spin_lock_irqsave(&pcie_trans->reg_lock, *flags);
 847
 848         /* this bit wakes up the NIC */
 849         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 850                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 851
 852         /*
 853          * These bits say the device is running, and should keep running for
 854          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
 855          * but they do not indicate that embedded SRAM is restored yet;
 856          * 3945 and 4965 have volatile SRAM, and must save/restore contents
 857          * to/from host DRAM when sleeping/waking for power-saving.
 858          * Each direction takes approximately 1/4 millisecond; with this
 859          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
 860          * series of register accesses are expected (e.g. reading Event Log),
 861          * to keep device from sleeping.
 862          *
 863          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
 864          * SRAM is okay/restored.  We don't check that here because this call
 865          * is just for hardware register access; but GP1 MAC_SLEEP check is a
 866          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
 867          *
 868          * 5000 series and later (including 1000 series) have non-volatile SRAM,
 869          * and do not save/restore SRAM when power cycling.
 870          */
 871         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 872                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
 873                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
 874                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
 875         if (unlikely(ret < 0)) {
 876                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
 877                 if (!silent) {
 878                         u32 val = iwl_read32(trans, CSR_GP_CNTRL);
 879                         WARN_ONCE(1,
 880                                   "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
 881                                   val);
 882                         spin_unlock_irqrestore(&pcie_trans->reg_lock, *flags);
 883                         return false;
 884                 }
 885         }
 886
 887         /*
 888          * Fool sparse by faking we release the lock - sparse will
 889          * track nic_access anyway.
 890          */
 891         __release(&pcie_trans->reg_lock);
 892         return true;
 893 }
 894
 895 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
 896                                               unsigned long *flags)
 897 {
 898         struct iwl_trans_pcie *pcie_trans = IWL_TRANS_GET_PCIE_TRANS(trans);
 899
 900         lockdep_assert_held(&pcie_trans->reg_lock);
 901
 902         /*
 903          * Fool sparse by faking we acquiring the lock - sparse will
 904          * track nic_access anyway.
 905          */
 906         __acquire(&pcie_trans->reg_lock);
 907
 908         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 909                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 910         /*
 911          * Above we read the CSR_GP_CNTRL register, which will flush
 912          * any previous writes, but we need the write that clears the
 913          * MAC_ACCESS_REQ bit to be performed before any other writes
 914          * scheduled on different CPUs (after we drop reg_lock).
 915          */
 916         mmiowb();
 917         spin_unlock_irqrestore(&pcie_trans->reg_lock, *flags);
 918 }
 919
 920 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
 921                                    void *buf, int dwords)
 922 {
 923         unsigned long flags;
 924         int offs, ret = 0;
 925         u32 *vals = buf;
 926
 927         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
 928                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
 929                 for (offs = 0; offs < dwords; offs++)
 930                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
 931                 iwl_trans_release_nic_access(trans, &flags);
 932         } else {
 933                 ret = -EBUSY;
 934         }
 935         return ret;
 936 }
 937
 938 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
 939                                     void *buf, int dwords)
 940 {
 941         unsigned long flags;
 942         int offs, ret = 0;
 943         u32 *vals = buf;
 944
 945         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
 946                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
 947                 for (offs = 0; offs < dwords; offs++)
 948                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
 949                                     vals ? vals[offs] : 0);
 950                 iwl_trans_release_nic_access(trans, &flags);
 951         } else {
 952                 ret = -EBUSY;
 953         }
 954         return ret;
 955 }
 956
 957 #define IWL_FLUSH_WAIT_MS       2000
 958
 959 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
 960 {
 961         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 962         struct iwl_txq *txq;
 963         struct iwl_queue *q;
 964         int cnt;
 965         unsigned long now = jiffies;
 966         u32 scd_sram_addr;
 967         u8 buf[16];
 968         int ret = 0;
 969
 970         /* waiting for all the tx frames complete might take a while */
 971         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
 972                 if (cnt == trans_pcie->cmd_queue)
 973                         continue;
 974                 txq = &trans_pcie->txq[cnt];
 975                 q = &txq->q;
 976                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
 977                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
 978                         msleep(1);
 979
 980                 if (q->read_ptr != q->write_ptr) {
 981                         IWL_ERR(trans,
 982                                 "fail to flush all tx fifo queues Q %d\n", cnt);
 983                         ret = -ETIMEDOUT;
 984                         break;
 985                 }
 986         }
 987
 988         if (!ret)
 989                 return 0;
 990
 991         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
 992                 txq->q.read_ptr, txq->q.write_ptr);
 993
 994         scd_sram_addr = trans_pcie->scd_base_addr +
 995                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
 996         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
 997
 998         iwl_print_hex_error(trans, buf, sizeof(buf));
 999
1000         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1001                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1002                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1003
1004         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1005                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1006                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1007                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1008                 u32 tbl_dw =
1009                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1010                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1011
1012                 if (cnt & 0x1)
1013                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1014                 else
1015                         tbl_dw = tbl_dw & 0x0000FFFF;
1016
1017                 IWL_ERR(trans,
1018                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1019                         cnt, active ? "" : "in", fifo, tbl_dw,
1020                         iwl_read_prph(trans,
1021                                       SCD_QUEUE_RDPTR(cnt)) & (txq->q.n_bd - 1),
1022                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1023         }
1024
1025         return ret;
1026 }
1027
1028 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1029                                          u32 mask, u32 value)
1030 {
1031         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1032         unsigned long flags;
1033
1034         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1035         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1036         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1037 }
1038
1039 static const char *get_fh_string(int cmd)
1040 {
1041 #define IWL_CMD(x) case x: return #x
1042         switch (cmd) {
1043         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1044         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1045         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1046         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1047         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1048         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1049         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1050         IWL_CMD(FH_TSSR_TX_STATUS_REG);
1051         IWL_CMD(FH_TSSR_TX_ERROR_REG);
1052         default:
1053                 return "UNKNOWN";
1054         }
1055 #undef IWL_CMD
1056 }
1057
1058 int iwl_pcie_dump_fh(struct iwl_trans *trans, char **buf)
1059 {
1060         int i;
1061         static const u32 fh_tbl[] = {
1062                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1063                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1064                 FH_RSCSR_CHNL0_WPTR,
1065                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1066                 FH_MEM_RSSR_SHARED_CTRL_REG,
1067                 FH_MEM_RSSR_RX_STATUS_REG,
1068                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1069                 FH_TSSR_TX_STATUS_REG,
1070                 FH_TSSR_TX_ERROR_REG
1071         };
1072
1073 #ifdef CONFIG_IWLWIFI_DEBUGFS
1074         if (buf) {
1075                 int pos = 0;
1076                 size_t bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1077
1078                 *buf = kmalloc(bufsz, GFP_KERNEL);
1079                 if (!*buf)
1080                         return -ENOMEM;
1081
1082                 pos += scnprintf(*buf + pos, bufsz - pos,
1083                                 "FH register values:\n");
1084
1085                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
1086                         pos += scnprintf(*buf + pos, bufsz - pos,
1087                                 "  %34s: 0X%08x\n",
1088                                 get_fh_string(fh_tbl[i]),
1089                                 iwl_read_direct32(trans, fh_tbl[i]));
1090
1091                 return pos;
1092         }
1093 #endif
1094
1095         IWL_ERR(trans, "FH register values:\n");
1096         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++)
1097                 IWL_ERR(trans, "  %34s: 0X%08x\n",
1098                         get_fh_string(fh_tbl[i]),
1099                         iwl_read_direct32(trans, fh_tbl[i]));
1100
1101         return 0;
1102 }
1103
1104 static const char *get_csr_string(int cmd)
1105 {
1106 #define IWL_CMD(x) case x: return #x
1107         switch (cmd) {
1108         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1109         IWL_CMD(CSR_INT_COALESCING);
1110         IWL_CMD(CSR_INT);
1111         IWL_CMD(CSR_INT_MASK);
1112         IWL_CMD(CSR_FH_INT_STATUS);
1113         IWL_CMD(CSR_GPIO_IN);
1114         IWL_CMD(CSR_RESET);
1115         IWL_CMD(CSR_GP_CNTRL);
1116         IWL_CMD(CSR_HW_REV);
1117         IWL_CMD(CSR_EEPROM_REG);
1118         IWL_CMD(CSR_EEPROM_GP);
1119         IWL_CMD(CSR_OTP_GP_REG);
1120         IWL_CMD(CSR_GIO_REG);
1121         IWL_CMD(CSR_GP_UCODE_REG);
1122         IWL_CMD(CSR_GP_DRIVER_REG);
1123         IWL_CMD(CSR_UCODE_DRV_GP1);
1124         IWL_CMD(CSR_UCODE_DRV_GP2);
1125         IWL_CMD(CSR_LED_REG);
1126         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1127         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1128         IWL_CMD(CSR_ANA_PLL_CFG);
1129         IWL_CMD(CSR_HW_REV_WA_REG);
1130         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1131         default:
1132                 return "UNKNOWN";
1133         }
1134 #undef IWL_CMD
1135 }
1136
1137 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1138 {
1139         int i;
1140         static const u32 csr_tbl[] = {
1141                 CSR_HW_IF_CONFIG_REG,
1142                 CSR_INT_COALESCING,
1143                 CSR_INT,
1144                 CSR_INT_MASK,
1145                 CSR_FH_INT_STATUS,
1146                 CSR_GPIO_IN,
1147                 CSR_RESET,
1148                 CSR_GP_CNTRL,
1149                 CSR_HW_REV,
1150                 CSR_EEPROM_REG,
1151                 CSR_EEPROM_GP,
1152                 CSR_OTP_GP_REG,
1153                 CSR_GIO_REG,
1154                 CSR_GP_UCODE_REG,
1155                 CSR_GP_DRIVER_REG,
1156                 CSR_UCODE_DRV_GP1,
1157                 CSR_UCODE_DRV_GP2,
1158                 CSR_LED_REG,
1159                 CSR_DRAM_INT_TBL_REG,
1160                 CSR_GIO_CHICKEN_BITS,
1161                 CSR_ANA_PLL_CFG,
1162                 CSR_HW_REV_WA_REG,
1163                 CSR_DBG_HPET_MEM_REG
1164         };
1165         IWL_ERR(trans, "CSR values:\n");
1166         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1167                 "CSR_INT_PERIODIC_REG)\n");
1168         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1169                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1170                         get_csr_string(csr_tbl[i]),
1171                         iwl_read32(trans, csr_tbl[i]));
1172         }
1173 }
1174
1175 #ifdef CONFIG_IWLWIFI_DEBUGFS
1176 /* create and remove of files */
1177 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1178         if (!debugfs_create_file(#name, mode, parent, trans,            \
1179                                  &iwl_dbgfs_##name##_ops))              \
1180                 goto err;                                               \
1181 } while (0)
1182
1183 /* file operation */
1184 #define DEBUGFS_READ_FUNC(name)                                         \
1185 static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
1186                                         char __user *user_buf,          \
1187                                         size_t count, loff_t *ppos);
1188
1189 #define DEBUGFS_WRITE_FUNC(name)                                        \
1190 static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
1191                                         const char __user *user_buf,    \
1192                                         size_t count, loff_t *ppos);
1193
1194 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1195         DEBUGFS_READ_FUNC(name);                                        \
1196 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1197         .read = iwl_dbgfs_##name##_read,                                \
1198         .open = simple_open,                                            \
1199         .llseek = generic_file_llseek,                                  \
1200 };
1201
1202 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1203         DEBUGFS_WRITE_FUNC(name);                                       \
1204 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1205         .write = iwl_dbgfs_##name##_write,                              \
1206         .open = simple_open,                                            \
1207         .llseek = generic_file_llseek,                                  \
1208 };
1209
1210 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1211         DEBUGFS_READ_FUNC(name);                                        \
1212         DEBUGFS_WRITE_FUNC(name);                                       \
1213 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1214         .write = iwl_dbgfs_##name##_write,                              \
1215         .read = iwl_dbgfs_##name##_read,                                \
1216         .open = simple_open,                                            \
1217         .llseek = generic_file_llseek,                                  \
1218 };
1219
1220 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1221                                        char __user *user_buf,
1222                                        size_t count, loff_t *ppos)
1223 {
1224         struct iwl_trans *trans = file->private_data;
1225         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1226         struct iwl_txq *txq;
1227         struct iwl_queue *q;
1228         char *buf;
1229         int pos = 0;
1230         int cnt;
1231         int ret;
1232         size_t bufsz;
1233
1234         bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1235
1236         if (!trans_pcie->txq)
1237                 return -EAGAIN;
1238
1239         buf = kzalloc(bufsz, GFP_KERNEL);
1240         if (!buf)
1241                 return -ENOMEM;
1242
1243         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1244                 txq = &trans_pcie->txq[cnt];
1245                 q = &txq->q;
1246                 pos += scnprintf(buf + pos, bufsz - pos,
1247                                 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1248                                 cnt, q->read_ptr, q->write_ptr,
1249                                 !!test_bit(cnt, trans_pcie->queue_used),
1250                                 !!test_bit(cnt, trans_pcie->queue_stopped));
1251         }
1252         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1253         kfree(buf);
1254         return ret;
1255 }
1256
1257 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1258                                        char __user *user_buf,
1259                                        size_t count, loff_t *ppos)
1260 {
1261         struct iwl_trans *trans = file->private_data;
1262         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1263         struct iwl_rxq *rxq = &trans_pcie->rxq;
1264         char buf[256];
1265         int pos = 0;
1266         const size_t bufsz = sizeof(buf);
1267
1268         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1269                                                 rxq->read);
1270         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1271                                                 rxq->write);
1272         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1273                                                 rxq->free_count);
1274         if (rxq->rb_stts) {
1275                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1276                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1277         } else {
1278                 pos += scnprintf(buf + pos, bufsz - pos,
1279                                         "closed_rb_num: Not Allocated\n");
1280         }
1281         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1282 }
1283
1284 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1285                                         char __user *user_buf,
1286                                         size_t count, loff_t *ppos)
1287 {
1288         struct iwl_trans *trans = file->private_data;
1289         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1290         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1291
1292         int pos = 0;
1293         char *buf;
1294         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1295         ssize_t ret;
1296
1297         buf = kzalloc(bufsz, GFP_KERNEL);
1298         if (!buf)
1299                 return -ENOMEM;
1300
1301         pos += scnprintf(buf + pos, bufsz - pos,
1302                         "Interrupt Statistics Report:\n");
1303
1304         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1305                 isr_stats->hw);
1306         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1307                 isr_stats->sw);
1308         if (isr_stats->sw || isr_stats->hw) {
1309                 pos += scnprintf(buf + pos, bufsz - pos,
1310                         "\tLast Restarting Code:  0x%X\n",
1311                         isr_stats->err_code);
1312         }
1313 #ifdef CONFIG_IWLWIFI_DEBUG
1314         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1315                 isr_stats->sch);
1316         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1317                 isr_stats->alive);
1318 #endif
1319         pos += scnprintf(buf + pos, bufsz - pos,
1320                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1321
1322         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1323                 isr_stats->ctkill);
1324
1325         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1326                 isr_stats->wakeup);
1327
1328         pos += scnprintf(buf + pos, bufsz - pos,
1329                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1330
1331         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1332                 isr_stats->tx);
1333
1334         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1335                 isr_stats->unhandled);
1336
1337         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1338         kfree(buf);
1339         return ret;
1340 }
1341
1342 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1343                                          const char __user *user_buf,
1344                                          size_t count, loff_t *ppos)
1345 {
1346         struct iwl_trans *trans = file->private_data;
1347         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1348         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1349
1350         char buf[8];
1351         int buf_size;
1352         u32 reset_flag;
1353
1354         memset(buf, 0, sizeof(buf));
1355         buf_size = min(count, sizeof(buf) -  1);
1356         if (copy_from_user(buf, user_buf, buf_size))
1357                 return -EFAULT;
1358         if (sscanf(buf, "%x", &reset_flag) != 1)
1359                 return -EFAULT;
1360         if (reset_flag == 0)
1361                 memset(isr_stats, 0, sizeof(*isr_stats));
1362
1363         return count;
1364 }
1365
1366 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1367                                    const char __user *user_buf,
1368                                    size_t count, loff_t *ppos)
1369 {
1370         struct iwl_trans *trans = file->private_data;
1371         char buf[8];
1372         int buf_size;
1373         int csr;
1374
1375         memset(buf, 0, sizeof(buf));
1376         buf_size = min(count, sizeof(buf) -  1);
1377         if (copy_from_user(buf, user_buf, buf_size))
1378                 return -EFAULT;
1379         if (sscanf(buf, "%d", &csr) != 1)
1380                 return -EFAULT;
1381
1382         iwl_pcie_dump_csr(trans);
1383
1384         return count;
1385 }
1386
1387 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1388                                      char __user *user_buf,
1389                                      size_t count, loff_t *ppos)
1390 {
1391         struct iwl_trans *trans = file->private_data;
1392         char *buf = NULL;
1393         int pos = 0;
1394         ssize_t ret = -EFAULT;
1395
1396         ret = pos = iwl_pcie_dump_fh(trans, &buf);
1397         if (buf) {
1398                 ret = simple_read_from_buffer(user_buf,
1399                                               count, ppos, buf, pos);
1400                 kfree(buf);
1401         }
1402
1403         return ret;
1404 }
1405
1406 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1407 DEBUGFS_READ_FILE_OPS(fh_reg);
1408 DEBUGFS_READ_FILE_OPS(rx_queue);
1409 DEBUGFS_READ_FILE_OPS(tx_queue);
1410 DEBUGFS_WRITE_FILE_OPS(csr);
1411
1412 /*
1413  * Create the debugfs files and directories
1414  *
1415  */
1416 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1417                                          struct dentry *dir)
1418 {
1419         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1420         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1421         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1422         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1423         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1424         return 0;
1425
1426 err:
1427         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1428         return -ENOMEM;
1429 }
1430 #else
1431 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1432                                          struct dentry *dir)
1433 {
1434         return 0;
1435 }
1436 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1437
1438 static const struct iwl_trans_ops trans_ops_pcie = {
1439         .start_hw = iwl_trans_pcie_start_hw,
1440         .stop_hw = iwl_trans_pcie_stop_hw,
1441         .fw_alive = iwl_trans_pcie_fw_alive,
1442         .start_fw = iwl_trans_pcie_start_fw,
1443         .stop_device = iwl_trans_pcie_stop_device,
1444
1445         .d3_suspend = iwl_trans_pcie_d3_suspend,
1446         .d3_resume = iwl_trans_pcie_d3_resume,
1447
1448         .send_cmd = iwl_trans_pcie_send_hcmd,
1449
1450         .tx = iwl_trans_pcie_tx,
1451         .reclaim = iwl_trans_pcie_reclaim,
1452
1453         .txq_disable = iwl_trans_pcie_txq_disable,
1454         .txq_enable = iwl_trans_pcie_txq_enable,
1455
1456         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1457
1458         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
1459
1460 #ifdef CONFIG_PM_SLEEP
1461         .suspend = iwl_trans_pcie_suspend,
1462         .resume = iwl_trans_pcie_resume,
1463 #endif
1464         .write8 = iwl_trans_pcie_write8,
1465         .write32 = iwl_trans_pcie_write32,
1466         .read32 = iwl_trans_pcie_read32,
1467         .read_prph = iwl_trans_pcie_read_prph,
1468         .write_prph = iwl_trans_pcie_write_prph,
1469         .read_mem = iwl_trans_pcie_read_mem,
1470         .write_mem = iwl_trans_pcie_write_mem,
1471         .configure = iwl_trans_pcie_configure,
1472         .set_pmi = iwl_trans_pcie_set_pmi,
1473         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
1474         .release_nic_access = iwl_trans_pcie_release_nic_access,
1475         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
1476 };
1477
1478 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
1479                                        const struct pci_device_id *ent,
1480                                        const struct iwl_cfg *cfg)
1481 {
1482         struct iwl_trans_pcie *trans_pcie;
1483         struct iwl_trans *trans;
1484         u16 pci_cmd;
1485         int err;
1486
1487         trans = kzalloc(sizeof(struct iwl_trans) +
1488                         sizeof(struct iwl_trans_pcie), GFP_KERNEL);
1489
1490         if (!trans)
1491                 return NULL;
1492
1493         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1494
1495         trans->ops = &trans_ops_pcie;
1496         trans->cfg = cfg;
1497         trans_lockdep_init(trans);
1498         trans_pcie->trans = trans;
1499         spin_lock_init(&trans_pcie->irq_lock);
1500         spin_lock_init(&trans_pcie->reg_lock);
1501         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
1502
1503         if (pci_enable_device(pdev)) {
1504                 err = -ENODEV;
1505                 goto out_no_pci;
1506         }
1507
1508         /* W/A - seems to solve weird behavior. We need to remove this if we
1509          * don't want to stay in L1 all the time. This wastes a lot of power */
1510         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
1511                                PCIE_LINK_STATE_CLKPM);
1512
1513         pci_set_master(pdev);
1514
1515         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
1516         if (!err)
1517                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
1518         if (err) {
1519                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1520                 if (!err)
1521                         err = pci_set_consistent_dma_mask(pdev,
1522                                                           DMA_BIT_MASK(32));
1523                 /* both attempts failed: */
1524                 if (err) {
1525                         dev_err(&pdev->dev, "No suitable DMA available\n");
1526                         goto out_pci_disable_device;
1527                 }
1528         }
1529
1530         err = pci_request_regions(pdev, DRV_NAME);
1531         if (err) {
1532                 dev_err(&pdev->dev, "pci_request_regions failed\n");
1533                 goto out_pci_disable_device;
1534         }
1535
1536         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
1537         if (!trans_pcie->hw_base) {
1538                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
1539                 err = -ENODEV;
1540                 goto out_pci_release_regions;
1541         }
1542
1543         /* We disable the RETRY_TIMEOUT register (0x41) to keep
1544          * PCI Tx retries from interfering with C3 CPU state */
1545         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
1546
1547         err = pci_enable_msi(pdev);
1548         if (err) {
1549                 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
1550                 /* enable rfkill interrupt: hw bug w/a */
1551                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1552                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1553                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1554                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1555                 }
1556         }
1557
1558         trans->dev = &pdev->dev;
1559         trans_pcie->pci_dev = pdev;
1560         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
1561         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
1562         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
1563                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
1564
1565         /* Initialize the wait queue for commands */
1566         init_waitqueue_head(&trans_pcie->wait_command_queue);
1567
1568         snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
1569                  "iwl_cmd_pool:%s", dev_name(trans->dev));
1570
1571         trans->dev_cmd_headroom = 0;
1572         trans->dev_cmd_pool =
1573                 kmem_cache_create(trans->dev_cmd_pool_name,
1574                                   sizeof(struct iwl_device_cmd)
1575                                   + trans->dev_cmd_headroom,
1576                                   sizeof(void *),
1577                                   SLAB_HWCACHE_ALIGN,
1578                                   NULL);
1579
1580         if (!trans->dev_cmd_pool)
1581                 goto out_pci_disable_msi;
1582
1583         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1584
1585         if (iwl_pcie_alloc_ict(trans))
1586                 goto out_free_cmd_pool;
1587
1588         if (request_threaded_irq(pdev->irq, iwl_pcie_isr_ict,
1589                                  iwl_pcie_irq_handler,
1590                                  IRQF_SHARED, DRV_NAME, trans)) {
1591                 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
1592                 goto out_free_ict;
1593         }
1594
1595         return trans;
1596
1597 out_free_ict:
1598         iwl_pcie_free_ict(trans);
1599 out_free_cmd_pool:
1600         kmem_cache_destroy(trans->dev_cmd_pool);
1601 out_pci_disable_msi:
1602         pci_disable_msi(pdev);
1603 out_pci_release_regions:
1604         pci_release_regions(pdev);
1605 out_pci_disable_device:
1606         pci_disable_device(pdev);
1607 out_no_pci:
1608         kfree(trans);
1609         return NULL;
1610 }