2 * Copyright (c) 2010-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/export.h>
19 #include "ar9003_phy.h"
21 static const int firstep_table[] =
22 /* level: 0 1 2 3 4 5 6 7 8 */
23 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
25 static const int cycpwrThr1_table[] =
26 /* level: 0 1 2 3 4 5 6 7 8 */
27 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
30 * register values to turn OFDM weak signal detection OFF
32 static const int m1ThreshLow_off = 127;
33 static const int m2ThreshLow_off = 127;
34 static const int m1Thresh_off = 127;
35 static const int m2Thresh_off = 127;
36 static const int m2CountThr_off = 31;
37 static const int m2CountThrLow_off = 63;
38 static const int m1ThreshLowExt_off = 127;
39 static const int m2ThreshLowExt_off = 127;
40 static const int m1ThreshExt_off = 127;
41 static const int m2ThreshExt_off = 127;
44 * ar9003_hw_set_channel - set channel on single-chip device
45 * @ah: atheros hardware structure
48 * This is the function to change channel on single-chip devices, that is
49 * for AR9300 family of chipsets.
51 * This function takes the channel value in MHz and sets
52 * hardware channel value. Assumes writes have been enabled to analog bus.
57 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
61 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
62 * (freq_ref = 40MHz/(24>>amodeRefSel))
64 * For 5GHz channels which are 5MHz spaced,
65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
68 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
70 u16 bMode, fracMode = 0, aModeRefSel = 0;
71 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0;
72 struct chan_centers centers;
75 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
76 freq = centers.synth_center;
78 if (freq < 4800) { /* 2 GHz, fractional mode */
79 if (AR_SREV_9330(ah)) {
85 channelSel = (freq * 4) / div;
86 chan_frac = (((freq * 4) % div) * 0x20000) / div;
87 channelSel = (channelSel << 17) | chan_frac;
88 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
90 * freq_ref = 40 / (refdiva >> amoderefsel);
91 * where refdiva=1 and amoderefsel=0
92 * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
93 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
95 channelSel = (freq * 4) / 120;
96 chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
97 channelSel = (channelSel << 17) | chan_frac;
98 } else if (AR_SREV_9340(ah)) {
99 if (ah->is_clk_25mhz) {
100 channelSel = (freq * 2) / 75;
101 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
102 channelSel = (channelSel << 17) | chan_frac;
104 channelSel = CHANSEL_2G(freq) >> 1;
106 } else if (AR_SREV_9550(ah)) {
107 if (ah->is_clk_25mhz)
112 channelSel = (freq * 4) / div;
113 chan_frac = (((freq * 4) % div) * 0x20000) / div;
114 channelSel = (channelSel << 17) | chan_frac;
116 channelSel = CHANSEL_2G(freq);
121 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) &&
123 channelSel = freq / 75;
124 chan_frac = ((freq % 75) * 0x20000) / 75;
125 channelSel = (channelSel << 17) | chan_frac;
127 channelSel = CHANSEL_5G(freq);
128 /* Doubler is ON, so, divide channelSel by 2. */
135 /* Enable fractional mode for all channels */
138 loadSynthChannel = 0;
140 reg32 = (bMode << 29);
141 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
143 /* Enable Long shift Select for Synthesizer */
144 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
145 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
147 /* Program Synth. setting */
148 reg32 = (channelSel << 2) | (fracMode << 30) |
149 (aModeRefSel << 28) | (loadSynthChannel << 31);
150 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
152 /* Toggle Load Synth channel bit */
153 loadSynthChannel = 1;
154 reg32 = (channelSel << 2) | (fracMode << 30) |
155 (aModeRefSel << 28) | (loadSynthChannel << 31);
156 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
164 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
165 * @ah: atheros hardware structure
168 * For single-chip solutions. Converts to baseband spur frequency given the
169 * input channel frequency and compute register settings below.
171 * Spur mitigation for MRC CCK
173 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
174 struct ath9k_channel *chan)
176 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
177 int cur_bb_spur, negative = 0, cck_spur_freq;
179 int range, max_spur_cnts, synth_freq;
180 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
183 * Need to verify range +/- 10 MHz in control channel, otherwise spur
184 * is out-of-band and can be ignored.
187 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
189 if (spur_fbin_ptr[0] == 0) /* No spur */
192 if (IS_CHAN_HT40(chan)) {
194 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
195 AR_PHY_GC_DYN2040_PRI_CH) == 0)
196 synth_freq = chan->channel + 10;
198 synth_freq = chan->channel - 10;
201 synth_freq = chan->channel;
204 range = AR_SREV_9462(ah) ? 5 : 10;
206 synth_freq = chan->channel;
209 for (i = 0; i < max_spur_cnts; i++) {
210 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
214 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
216 cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
219 cur_bb_spur = spur_freq[i];
221 cur_bb_spur -= synth_freq;
222 if (cur_bb_spur < 0) {
224 cur_bb_spur = -cur_bb_spur;
226 if (cur_bb_spur < range) {
227 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
230 cck_spur_freq = -cck_spur_freq;
232 cck_spur_freq = cck_spur_freq & 0xfffff;
234 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
235 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
236 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
237 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
238 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
239 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
241 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
242 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
244 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
245 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
252 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
253 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
254 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
255 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
256 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
257 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
260 /* Clean all spur register fields */
261 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
263 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
264 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
265 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
266 AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
267 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
268 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
269 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
270 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
271 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
272 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
273 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
274 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
275 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
276 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
277 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
278 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
279 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
280 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
282 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
283 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
284 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
285 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
286 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
287 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
288 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
289 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
290 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
291 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
292 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
293 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
294 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
295 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
296 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
297 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
298 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
299 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
300 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
301 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
304 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
307 int spur_delta_phase,
308 int spur_subchannel_sd,
314 /* OFDM Spur mitigation */
315 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
316 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
317 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
318 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
319 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
320 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
321 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
322 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
323 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
324 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
326 if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437))
327 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
328 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
330 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
331 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
332 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
333 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
334 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
335 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
337 if (!AR_SREV_9340(ah) &&
338 REG_READ_FIELD(ah, AR_PHY_MODE,
339 AR_PHY_MODE_DYNAMIC) == 0x1)
340 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
341 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
343 mask_index = (freq_offset << 4) / 5;
345 mask_index = mask_index - 1;
347 mask_index = mask_index & 0x7f;
349 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
350 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
351 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
352 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
353 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
354 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
355 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
356 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
357 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
358 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
359 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
360 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
361 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
362 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
363 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
364 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
365 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
366 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
367 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
368 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
371 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah,
376 mask_index = (freq_offset << 4) / 5;
378 mask_index = mask_index - 1;
380 mask_index = mask_index & 0x7f;
382 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
383 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B,
387 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
388 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A,
391 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
392 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B,
394 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
395 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe);
396 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
397 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe);
400 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
401 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
404 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
405 struct ath9k_channel *chan,
410 int spur_freq_sd = 0;
411 int spur_subchannel_sd = 0;
412 int spur_delta_phase = 0;
414 if (IS_CHAN_HT40(chan)) {
415 if (freq_offset < 0) {
416 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
417 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
418 spur_subchannel_sd = 1;
420 spur_subchannel_sd = 0;
422 spur_freq_sd = ((freq_offset + 10) << 9) / 11;
425 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
426 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
427 spur_subchannel_sd = 0;
429 spur_subchannel_sd = 1;
431 spur_freq_sd = ((freq_offset - 10) << 9) / 11;
435 spur_delta_phase = (freq_offset << 17) / 5;
438 spur_subchannel_sd = 0;
439 spur_freq_sd = (freq_offset << 9) /11;
440 spur_delta_phase = (freq_offset << 18) / 5;
443 spur_freq_sd = spur_freq_sd & 0x3ff;
444 spur_delta_phase = spur_delta_phase & 0xfffff;
446 ar9003_hw_spur_ofdm(ah,
454 /* Spur mitigation for OFDM */
455 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
456 struct ath9k_channel *chan)
464 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
466 if (IS_CHAN_5GHZ(chan)) {
467 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
471 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
475 if (spurChansPtr[0] == 0)
476 return; /* No spur in the mode */
478 if (IS_CHAN_HT40(chan)) {
480 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
481 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
482 synth_freq = chan->channel - 10;
484 synth_freq = chan->channel + 10;
487 synth_freq = chan->channel;
490 ar9003_hw_spur_ofdm_clear(ah);
492 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
493 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode);
494 freq_offset -= synth_freq;
495 if (abs(freq_offset) < range) {
496 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset,
499 if (AR_SREV_9565(ah) && (i < 4)) {
500 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1],
502 freq_offset -= synth_freq;
503 if (abs(freq_offset) < range)
504 ar9003_hw_spur_ofdm_9565(ah, freq_offset);
512 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
513 struct ath9k_channel *chan)
515 if (!AR_SREV_9565(ah))
516 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
517 ar9003_hw_spur_mitigate_ofdm(ah, chan);
520 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
521 struct ath9k_channel *chan)
525 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
527 if (chan && IS_CHAN_HALF_RATE(chan))
528 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
529 else if (chan && IS_CHAN_QUARTER_RATE(chan))
530 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
532 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
537 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
538 struct ath9k_channel *chan)
541 u32 enableDacFifo = 0;
544 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
546 /* Enable 11n HT, 20 MHz */
547 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 |
548 AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
550 /* Configure baseband for dynamic 20/40 operation */
551 if (IS_CHAN_HT40(chan)) {
552 phymode |= AR_PHY_GC_DYN2040_EN;
553 /* Configure control (primary) channel at +-10MHz */
554 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
555 (chan->chanmode == CHANNEL_G_HT40PLUS))
556 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
560 /* make sure we preserve INI settings */
561 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
562 /* turn off Green Field detection for STA for now */
563 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
565 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
567 /* Configure MAC for 20/40 operation */
568 ath9k_hw_set11nmac2040(ah);
570 /* global transmit timeout (25 TUs default)*/
571 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
572 /* carrier sense timeout */
573 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
576 static void ar9003_hw_init_bb(struct ath_hw *ah,
577 struct ath9k_channel *chan)
582 * Wait for the frequency synth to settle (synth goes on
583 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
584 * Value is in 100ns increments.
586 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
588 /* Activate the PHY (includes baseband activate + synthesizer on) */
589 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
590 ath9k_hw_synth_delay(ah, chan, synthDelay);
593 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
595 if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
596 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
597 AR_PHY_SWAP_ALT_CHAIN);
599 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
600 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
602 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
605 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
609 * Override INI values with chip specific configuration.
611 static void ar9003_hw_override_ini(struct ath_hw *ah)
616 * Set the RX_ABORT and RX_DIS and clear it only after
617 * RXE is set for MAC. This prevents frames with
618 * corrupted descriptor status.
620 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
623 * For AR9280 and above, there is a new feature that allows
624 * Multicast search based on both MAC Address and Key ID. By default,
625 * this feature is enabled. But since the driver is not using this
626 * feature, we switch it off; otherwise multicast search based on
627 * MAC addr only will fail.
629 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
630 REG_WRITE(ah, AR_PCU_MISC_MODE2,
631 val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
633 REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
634 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
637 static void ar9003_hw_prog_ini(struct ath_hw *ah,
638 struct ar5416IniArray *iniArr,
641 unsigned int i, regWrites = 0;
643 /* New INI format: Array may be undefined (pre, core, post arrays) */
644 if (!iniArr->ia_array)
648 * New INI format: Pre, core, and post arrays for a given subsystem
649 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
650 * the array is non-modal and force the column to 1.
652 if (column >= iniArr->ia_columns)
655 for (i = 0; i < iniArr->ia_rows; i++) {
656 u32 reg = INI_RA(iniArr, i, 0);
657 u32 val = INI_RA(iniArr, i, column);
659 REG_WRITE(ah, reg, val);
665 static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
666 struct ath9k_channel *chan)
670 switch (chan->chanmode) {
673 if (chan->channel <= 5350)
675 else if ((chan->channel > 5350) && (chan->channel <= 5600))
681 case CHANNEL_A_HT40PLUS:
682 case CHANNEL_A_HT40MINUS:
683 if (chan->channel <= 5350)
685 else if ((chan->channel > 5350) && (chan->channel <= 5600))
697 case CHANNEL_G_HT40PLUS:
698 case CHANNEL_G_HT40MINUS:
709 static int ar9003_hw_process_ini(struct ath_hw *ah,
710 struct ath9k_channel *chan)
712 unsigned int regWrites = 0, i;
715 switch (chan->chanmode) {
720 case CHANNEL_A_HT40PLUS:
721 case CHANNEL_A_HT40MINUS:
729 case CHANNEL_G_HT40PLUS:
730 case CHANNEL_G_HT40MINUS:
738 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
739 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
740 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
741 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
742 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
743 if (i == ATH_INI_POST && AR_SREV_9462_20(ah))
744 ar9003_hw_prog_ini(ah,
745 &ah->ini_radio_post_sys2ant,
749 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
750 if (AR_SREV_9550(ah))
751 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
754 if (AR_SREV_9550(ah)) {
755 int modes_txgain_index;
757 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
758 if (modes_txgain_index < 0)
761 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
764 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
768 * For 5GHz channels requiring Fast Clock, apply
769 * different modal values.
771 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
772 REG_WRITE_ARRAY(&ah->iniModesFastClock,
773 modesIndex, regWrites);
775 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
777 if (chan->channel == 2484)
778 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
780 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
781 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
782 AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
784 ah->modes_index = modesIndex;
785 ar9003_hw_override_ini(ah);
786 ar9003_hw_set_channel_regs(ah, chan);
787 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
788 ath9k_hw_apply_txpower(ah, chan, false);
790 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
791 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
792 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
793 ah->enabled_cals |= TX_IQ_CAL;
795 ah->enabled_cals &= ~TX_IQ_CAL;
797 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
798 ah->enabled_cals |= TX_CL_CAL;
800 ah->enabled_cals &= ~TX_CL_CAL;
806 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
807 struct ath9k_channel *chan)
814 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
815 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
817 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
818 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
819 if (IS_CHAN_QUARTER_RATE(chan))
820 rfMode |= AR_PHY_MODE_QUARTER;
821 if (IS_CHAN_HALF_RATE(chan))
822 rfMode |= AR_PHY_MODE_HALF;
824 if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
825 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
826 AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
828 REG_WRITE(ah, AR_PHY_MODE, rfMode);
831 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
833 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
836 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
837 struct ath9k_channel *chan)
839 u32 coef_scaled, ds_coef_exp, ds_coef_man;
840 u32 clockMhzScaled = 0x64000000;
841 struct chan_centers centers;
844 * half and quarter rate can divide the scaled clock by 2 or 4
845 * scale for selected channel bandwidth
847 if (IS_CHAN_HALF_RATE(chan))
848 clockMhzScaled = clockMhzScaled >> 1;
849 else if (IS_CHAN_QUARTER_RATE(chan))
850 clockMhzScaled = clockMhzScaled >> 2;
853 * ALGO -> coef = 1e8/fcarrier*fclock/40;
854 * scaled coef to provide precision for this floating calculation
856 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
857 coef_scaled = clockMhzScaled / centers.synth_center;
859 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
862 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
863 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
864 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
865 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
869 * scaled coeff is 9/10 that of normal coeff
871 coef_scaled = (9 * coef_scaled) / 10;
873 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
877 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
878 AR_PHY_SGI_DSC_MAN, ds_coef_man);
879 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
880 AR_PHY_SGI_DSC_EXP, ds_coef_exp);
883 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
885 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
886 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
887 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
891 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
892 * Read the phy active delay register. Value is in 100ns increments.
894 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
896 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
898 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
900 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
903 static bool ar9003_hw_ani_control(struct ath_hw *ah,
904 enum ath9k_ani_cmd cmd, int param)
906 struct ath_common *common = ath9k_hw_common(ah);
907 struct ath9k_channel *chan = ah->curchan;
908 struct ar5416AniState *aniState = &chan->ani;
911 switch (cmd & ah->ani_function) {
912 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
914 * on == 1 means ofdm weak signal detection is ON
915 * on == 1 is the default, for less noise immunity
917 * on == 0 means ofdm weak signal detection is OFF
918 * on == 0 means more noise imm
920 u32 on = param ? 1 : 0;
923 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
924 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
926 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
927 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
929 if (on != aniState->ofdmWeakSigDetect) {
931 "** ch %d: ofdm weak signal: %s=>%s\n",
933 aniState->ofdmWeakSigDetect ?
937 ah->stats.ast_ani_ofdmon++;
939 ah->stats.ast_ani_ofdmoff++;
940 aniState->ofdmWeakSigDetect = on;
944 case ATH9K_ANI_FIRSTEP_LEVEL:{
947 if (level >= ARRAY_SIZE(firstep_table)) {
949 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
950 level, ARRAY_SIZE(firstep_table));
955 * make register setting relative to default
956 * from INI file & cap value
958 value = firstep_table[level] -
959 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
960 aniState->iniDef.firstep;
961 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
962 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
963 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
964 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
965 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
966 AR_PHY_FIND_SIG_FIRSTEP,
969 * we need to set first step low register too
970 * make register setting relative to default
971 * from INI file & cap value
973 value2 = firstep_table[level] -
974 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
975 aniState->iniDef.firstepLow;
976 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
977 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
978 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
979 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
981 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
982 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
984 if (level != aniState->firstepLevel) {
986 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
988 aniState->firstepLevel,
990 ATH9K_ANI_FIRSTEP_LVL,
992 aniState->iniDef.firstep);
994 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
996 aniState->firstepLevel,
998 ATH9K_ANI_FIRSTEP_LVL,
1000 aniState->iniDef.firstepLow);
1001 if (level > aniState->firstepLevel)
1002 ah->stats.ast_ani_stepup++;
1003 else if (level < aniState->firstepLevel)
1004 ah->stats.ast_ani_stepdown++;
1005 aniState->firstepLevel = level;
1009 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1012 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1013 ath_dbg(common, ANI,
1014 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1015 level, ARRAY_SIZE(cycpwrThr1_table));
1019 * make register setting relative to default
1020 * from INI file & cap value
1022 value = cycpwrThr1_table[level] -
1023 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1024 aniState->iniDef.cycpwrThr1;
1025 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1026 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1027 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1028 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1029 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1030 AR_PHY_TIMING5_CYCPWR_THR1,
1034 * set AR_PHY_EXT_CCA for extension channel
1035 * make register setting relative to default
1036 * from INI file & cap value
1038 value2 = cycpwrThr1_table[level] -
1039 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1040 aniState->iniDef.cycpwrThr1Ext;
1041 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1042 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1043 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1044 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1045 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1046 AR_PHY_EXT_CYCPWR_THR1, value2);
1048 if (level != aniState->spurImmunityLevel) {
1049 ath_dbg(common, ANI,
1050 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1052 aniState->spurImmunityLevel,
1054 ATH9K_ANI_SPUR_IMMUNE_LVL,
1056 aniState->iniDef.cycpwrThr1);
1057 ath_dbg(common, ANI,
1058 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1060 aniState->spurImmunityLevel,
1062 ATH9K_ANI_SPUR_IMMUNE_LVL,
1064 aniState->iniDef.cycpwrThr1Ext);
1065 if (level > aniState->spurImmunityLevel)
1066 ah->stats.ast_ani_spurup++;
1067 else if (level < aniState->spurImmunityLevel)
1068 ah->stats.ast_ani_spurdown++;
1069 aniState->spurImmunityLevel = level;
1073 case ATH9K_ANI_MRC_CCK:{
1075 * is_on == 1 means MRC CCK ON (default, less noise imm)
1076 * is_on == 0 means MRC CCK is OFF (more noise imm)
1078 bool is_on = param ? 1 : 0;
1080 if (ah->caps.rx_chainmask == 1)
1083 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1084 AR_PHY_MRC_CCK_ENABLE, is_on);
1085 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1086 AR_PHY_MRC_CCK_MUX_REG, is_on);
1087 if (is_on != aniState->mrcCCK) {
1088 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
1090 aniState->mrcCCK ? "on" : "off",
1091 is_on ? "on" : "off");
1093 ah->stats.ast_ani_ccklow++;
1095 ah->stats.ast_ani_cckhigh++;
1096 aniState->mrcCCK = is_on;
1100 case ATH9K_ANI_PRESENT:
1103 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1107 ath_dbg(common, ANI,
1108 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1109 aniState->spurImmunityLevel,
1110 aniState->ofdmWeakSigDetect ? "on" : "off",
1111 aniState->firstepLevel,
1112 aniState->mrcCCK ? "on" : "off",
1113 aniState->listenTime,
1114 aniState->ofdmPhyErrCount,
1115 aniState->cckPhyErrCount);
1119 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1120 int16_t nfarray[NUM_NF_READINGS])
1122 #define AR_PHY_CH_MINCCA_PWR 0x1FF00000
1123 #define AR_PHY_CH_MINCCA_PWR_S 20
1124 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1125 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1130 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1131 if (ah->rxchainmask & BIT(i)) {
1132 nf = MS(REG_READ(ah, ah->nf_regs[i]),
1133 AR_PHY_CH_MINCCA_PWR);
1134 nfarray[i] = sign_extend32(nf, 8);
1136 if (IS_CHAN_HT40(ah->curchan)) {
1137 u8 ext_idx = AR9300_MAX_CHAINS + i;
1139 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1140 AR_PHY_CH_EXT_MINCCA_PWR);
1141 nfarray[ext_idx] = sign_extend32(nf, 8);
1147 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1149 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1150 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1151 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1152 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1153 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1154 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1156 if (AR_SREV_9330(ah))
1157 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1159 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
1160 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1161 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1162 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1163 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1168 * Initialize the ANI register values with default (ini) values.
1169 * This routine is called during a (full) hardware reset after
1170 * all the registers are initialised from the INI.
1172 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1174 struct ar5416AniState *aniState;
1175 struct ath_common *common = ath9k_hw_common(ah);
1176 struct ath9k_channel *chan = ah->curchan;
1177 struct ath9k_ani_default *iniDef;
1180 aniState = &ah->curchan->ani;
1181 iniDef = &aniState->iniDef;
1183 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1184 ah->hw_version.macVersion,
1185 ah->hw_version.macRev,
1188 chan->channelFlags);
1190 val = REG_READ(ah, AR_PHY_SFCORR);
1191 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1192 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1193 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1195 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1196 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1197 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1198 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1200 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1201 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1202 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1203 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1204 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1205 iniDef->firstep = REG_READ_FIELD(ah,
1207 AR_PHY_FIND_SIG_FIRSTEP);
1208 iniDef->firstepLow = REG_READ_FIELD(ah,
1209 AR_PHY_FIND_SIG_LOW,
1210 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1211 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1213 AR_PHY_TIMING5_CYCPWR_THR1);
1214 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1216 AR_PHY_EXT_CYCPWR_THR1);
1218 /* these levels just got reset to defaults by the INI */
1219 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1220 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
1221 aniState->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG;
1222 aniState->mrcCCK = true;
1225 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1226 struct ath_hw_radar_conf *conf)
1228 u32 radar_0 = 0, radar_1 = 0;
1231 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1235 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1236 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1237 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1238 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1239 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1240 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1242 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1243 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1244 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1245 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1246 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1248 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1249 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1250 if (conf->ext_channel)
1251 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1253 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1256 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1258 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1260 conf->fir_power = -28;
1261 conf->radar_rssi = 0;
1262 conf->pulse_height = 10;
1263 conf->pulse_rssi = 24;
1264 conf->pulse_inband = 8;
1265 conf->pulse_maxlen = 255;
1266 conf->pulse_inband_step = 12;
1267 conf->radar_inband = 8;
1270 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1271 struct ath_hw_antcomb_conf *antconf)
1275 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1276 antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1277 AR_PHY_ANT_DIV_MAIN_LNACONF_S;
1278 antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1279 AR_PHY_ANT_DIV_ALT_LNACONF_S;
1280 antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1281 AR_PHY_ANT_FAST_DIV_BIAS_S;
1283 if (AR_SREV_9330_11(ah)) {
1284 antconf->lna1_lna2_delta = -9;
1285 antconf->div_group = 1;
1286 } else if (AR_SREV_9485(ah)) {
1287 antconf->lna1_lna2_delta = -9;
1288 antconf->div_group = 2;
1289 } else if (AR_SREV_9565(ah)) {
1290 antconf->lna1_lna2_delta = -3;
1291 antconf->div_group = 3;
1293 antconf->lna1_lna2_delta = -3;
1294 antconf->div_group = 0;
1298 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1299 struct ath_hw_antcomb_conf *antconf)
1303 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1304 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1305 AR_PHY_ANT_DIV_ALT_LNACONF |
1306 AR_PHY_ANT_FAST_DIV_BIAS |
1307 AR_PHY_ANT_DIV_MAIN_GAINTB |
1308 AR_PHY_ANT_DIV_ALT_GAINTB);
1309 regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1310 & AR_PHY_ANT_DIV_MAIN_LNACONF);
1311 regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
1312 & AR_PHY_ANT_DIV_ALT_LNACONF);
1313 regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
1314 & AR_PHY_ANT_FAST_DIV_BIAS);
1315 regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
1316 & AR_PHY_ANT_DIV_MAIN_GAINTB);
1317 regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
1318 & AR_PHY_ANT_DIV_ALT_GAINTB);
1320 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1323 static void ar9003_hw_antctrl_shared_chain_lnadiv(struct ath_hw *ah,
1329 if (!AR_SREV_9565(ah))
1332 ah->shared_chain_lnadiv = enable;
1333 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1335 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1336 regval &= (~AR_ANT_DIV_CTRL_ALL);
1337 regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
1338 regval &= ~AR_PHY_ANT_DIV_LNADIV;
1339 regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
1342 regval |= AR_ANT_DIV_ENABLE;
1344 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1346 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
1347 regval &= ~AR_FAST_DIV_ENABLE;
1348 regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
1351 regval |= AR_FAST_DIV_ENABLE;
1353 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
1356 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1357 (1 << AR_PHY_ANT_SW_RX_PROT_S));
1358 if (ah->curchan && IS_CHAN_2GHZ(ah->curchan))
1359 REG_SET_BIT(ah, AR_PHY_RESTART,
1360 AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1361 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
1362 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1364 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE);
1365 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1366 (1 << AR_PHY_ANT_SW_RX_PROT_S));
1367 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE);
1368 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
1369 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1371 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1372 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1373 AR_PHY_ANT_DIV_ALT_LNACONF |
1374 AR_PHY_ANT_DIV_MAIN_GAINTB |
1375 AR_PHY_ANT_DIV_ALT_GAINTB);
1376 regval |= (AR_PHY_ANT_DIV_LNA1 << AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1377 regval |= (AR_PHY_ANT_DIV_LNA2 << AR_PHY_ANT_DIV_ALT_LNACONF_S);
1378 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1382 static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1383 struct ath9k_channel *chan,
1386 unsigned int regWrites = 0;
1389 switch (chan->chanmode) {
1391 case CHANNEL_A_HT20:
1394 case CHANNEL_A_HT40PLUS:
1395 case CHANNEL_A_HT40MINUS:
1399 case CHANNEL_G_HT20:
1403 case CHANNEL_G_HT40PLUS:
1404 case CHANNEL_G_HT40MINUS:
1412 if (modesIndex == ah->modes_index) {
1413 *ini_reloaded = false;
1417 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1418 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1419 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1420 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1422 if (AR_SREV_9462_20(ah))
1423 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1426 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1429 * For 5GHz channels requiring Fast Clock, apply
1430 * different modal values.
1432 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1433 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
1435 if (AR_SREV_9565(ah))
1436 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1438 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
1440 ah->modes_index = modesIndex;
1441 *ini_reloaded = true;
1444 ar9003_hw_set_rfmode(ah, chan);
1448 static void ar9003_hw_spectral_scan_config(struct ath_hw *ah,
1449 struct ath_spec_scan *param)
1453 if (!param->enabled) {
1454 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1455 AR_PHY_SPECTRAL_SCAN_ENABLE);
1459 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
1460 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
1462 /* on AR93xx and newer, count = 0 will make the the chip send
1463 * spectral samples endlessly. Check if this really was intended,
1464 * and fix otherwise.
1466 count = param->count;
1469 else if (param->count == 0)
1472 if (param->short_repeat)
1473 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1474 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1476 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1477 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1479 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1480 AR_PHY_SPECTRAL_SCAN_COUNT, count);
1481 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1482 AR_PHY_SPECTRAL_SCAN_PERIOD, param->period);
1483 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1484 AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period);
1489 static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah)
1491 /* Activate spectral scan */
1492 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1493 AR_PHY_SPECTRAL_SCAN_ACTIVE);
1496 static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah)
1498 struct ath_common *common = ath9k_hw_common(ah);
1500 /* Poll for spectral scan complete */
1501 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN,
1502 AR_PHY_SPECTRAL_SCAN_ACTIVE,
1503 0, AH_WAIT_TIMEOUT)) {
1504 ath_err(common, "spectral scan wait failed\n");
1509 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1511 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1512 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1513 static const u32 ar9300_cca_regs[6] = {
1522 priv_ops->rf_set_freq = ar9003_hw_set_channel;
1523 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1524 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1525 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1526 priv_ops->init_bb = ar9003_hw_init_bb;
1527 priv_ops->process_ini = ar9003_hw_process_ini;
1528 priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1529 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1530 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1531 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1532 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1533 priv_ops->ani_control = ar9003_hw_ani_control;
1534 priv_ops->do_getnf = ar9003_hw_do_getnf;
1535 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1536 priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1537 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
1539 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1540 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1541 ops->antctrl_shared_chain_lnadiv = ar9003_hw_antctrl_shared_chain_lnadiv;
1542 ops->spectral_scan_config = ar9003_hw_spectral_scan_config;
1543 ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger;
1544 ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait;
1546 ar9003_hw_set_nf_limits(ah);
1547 ar9003_hw_set_radar_conf(ah);
1548 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1551 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1553 struct ath_common *common = ath9k_hw_common(ah);
1554 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1555 u32 val, idle_count;
1558 /* disable IRQ, disable chip-reset for BB panic */
1559 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1560 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1561 ~(AR_PHY_WATCHDOG_RST_ENABLE |
1562 AR_PHY_WATCHDOG_IRQ_ENABLE));
1564 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1565 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1566 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1567 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1568 AR_PHY_WATCHDOG_IDLE_ENABLE));
1570 ath_dbg(common, RESET, "Disabled BB Watchdog\n");
1574 /* enable IRQ, disable chip-reset for BB watchdog */
1575 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1576 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1577 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1578 ~AR_PHY_WATCHDOG_RST_ENABLE);
1580 /* bound limit to 10 secs */
1581 if (idle_tmo_ms > 10000)
1582 idle_tmo_ms = 10000;
1585 * The time unit for watchdog event is 2^15 44/88MHz cycles.
1587 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1588 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1590 * Given we use fast clock now in 5 GHz, these time units should
1591 * be common for both 2 GHz and 5 GHz.
1593 idle_count = (100 * idle_tmo_ms) / 74;
1594 if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1595 idle_count = (100 * idle_tmo_ms) / 37;
1598 * enable watchdog in non-IDLE mode, disable in IDLE mode,
1599 * set idle time-out.
1601 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1602 AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1603 AR_PHY_WATCHDOG_IDLE_MASK |
1604 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1606 ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
1610 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1613 * we want to avoid printing in ISR context so we save the
1614 * watchdog status to be printed later in bottom half context.
1616 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1619 * the watchdog timer should reset on status read but to be sure
1620 * sure we write 0 to the watchdog status bit.
1622 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1623 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1626 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1628 struct ath_common *common = ath9k_hw_common(ah);
1631 if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1634 status = ah->bb_watchdog_last_status;
1635 ath_dbg(common, RESET,
1636 "\n==== BB update: BB status=0x%08x ====\n", status);
1637 ath_dbg(common, RESET,
1638 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1639 MS(status, AR_PHY_WATCHDOG_INFO),
1640 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1641 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1642 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1643 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1644 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1645 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1646 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1647 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1649 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1650 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1651 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1652 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
1653 REG_READ(ah, AR_PHY_GEN_CTRL));
1655 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1656 if (common->cc_survey.cycles)
1657 ath_dbg(common, RESET,
1658 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1659 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
1661 ath_dbg(common, RESET, "==== BB update: done ====\n\n");
1663 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
1665 void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1669 /* While receiving unsupported rate frame rx state machine
1670 * gets into a state 0xb and if phy_restart happens in that
1671 * state, BB would go hang. If RXSM is in 0xb state after
1672 * first bb panic, ensure to disable the phy_restart.
1674 if (!((MS(ah->bb_watchdog_last_status,
1675 AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
1676 ah->bb_hang_rx_ofdm))
1679 ah->bb_hang_rx_ofdm = true;
1680 val = REG_READ(ah, AR_PHY_RESTART);
1681 val &= ~AR_PHY_RESTART_ENA;
1683 REG_WRITE(ah, AR_PHY_RESTART, val);
1685 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);