2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "ar9002_phy.h"
22 /* All code below is for AR5008, AR9001, AR9002 */
24 static const int firstep_table[] =
25 /* level: 0 1 2 3 4 5 6 7 8 */
26 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
28 static const int cycpwrThr1_table[] =
29 /* level: 0 1 2 3 4 5 6 7 8 */
30 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
33 * register values to turn OFDM weak signal detection OFF
35 static const int m1ThreshLow_off = 127;
36 static const int m2ThreshLow_off = 127;
37 static const int m1Thresh_off = 127;
38 static const int m2Thresh_off = 127;
39 static const int m2CountThr_off = 31;
40 static const int m2CountThrLow_off = 63;
41 static const int m1ThreshLowExt_off = 127;
42 static const int m2ThreshLowExt_off = 127;
43 static const int m1ThreshExt_off = 127;
44 static const int m2ThreshExt_off = 127;
47 static void ar5008_rf_bank_setup(u32 *bank, struct ar5416IniArray *array,
52 for (i = 0; i < array->ia_rows; i++)
53 bank[i] = INI_RA(array, i, col);
57 #define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) \
58 ar5008_write_rf_array(ah, iniarray, regData, &(regWr))
60 static void ar5008_write_rf_array(struct ath_hw *ah, struct ar5416IniArray *array,
61 u32 *data, unsigned int *writecnt)
65 ENABLE_REGWRITE_BUFFER(ah);
67 for (r = 0; r < array->ia_rows; r++) {
68 REG_WRITE(ah, INI_RA(array, r, 0), data[r]);
72 REGWRITE_BUFFER_FLUSH(ah);
76 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
83 * Performs analog "swizzling" of parameters into their location.
84 * Used on external AR2133/AR5133 radios.
86 static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
87 u32 numBits, u32 firstBit,
90 u32 tmp32, mask, arrayEntry, lastBit;
91 int32_t bitPosition, bitsLeft;
93 tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
94 arrayEntry = (firstBit - 1) / 8;
95 bitPosition = (firstBit - 1) % 8;
97 while (bitsLeft > 0) {
98 lastBit = (bitPosition + bitsLeft > 8) ?
99 8 : bitPosition + bitsLeft;
100 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
102 rfBuf[arrayEntry] &= ~mask;
103 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
104 (column * 8)) & mask;
105 bitsLeft -= 8 - bitPosition;
106 tmp32 = tmp32 >> (8 - bitPosition);
113 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
119 * if synth_freq < 2412
121 * else if 2412 <= synth_freq <= 2422
123 * else // synth_freq > 2422
125 * else if forceBias > 0
126 * bias = forceBias & 7
128 * no change, use value from ini file
130 * no change, invalid band
133 * 2422 also uses value of 2
137 * Less than 2412 uses value of 0, 2412 and above uses value of 2
139 static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
141 struct ath_common *common = ath9k_hw_common(ah);
146 if (!AR_SREV_5416(ah) || synth_freq >= 3000)
149 BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
151 if (synth_freq < 2412)
153 else if (synth_freq < 2422)
158 /* pre-reverse this field */
159 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
161 ath_dbg(common, ATH_DBG_CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n",
162 new_bias, synth_freq);
164 /* swizzle rf_pwd_icsyndiv */
165 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
167 /* write Bank 6 with new params */
168 REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
172 * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
173 * @ah: atheros hardware structure
176 * For the external AR2133/AR5133 radios, takes the MHz channel value and set
177 * the channel value. Assumes writes enabled to analog bus and bank6 register
178 * cache in ah->analogBank6Data.
180 static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
182 struct ath_common *common = ath9k_hw_common(ah);
188 struct chan_centers centers;
190 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
191 freq = centers.synth_center;
196 if (((freq - 2192) % 5) == 0) {
197 channelSel = ((freq - 672) * 2 - 3040) / 10;
199 } else if (((freq - 2224) % 5) == 0) {
200 channelSel = ((freq - 704) * 2 - 3040) / 10;
203 ath_err(common, "Invalid channel %u MHz\n", freq);
207 channelSel = (channelSel << 2) & 0xff;
208 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
210 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
213 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
214 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
216 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
217 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
220 } else if ((freq % 20) == 0 && freq >= 5120) {
222 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
223 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
224 } else if ((freq % 10) == 0) {
226 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
227 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
228 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
230 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
231 } else if ((freq % 5) == 0) {
232 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
233 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
235 ath_err(common, "Invalid channel %u MHz\n", freq);
239 ar5008_hw_force_bias(ah, freq);
242 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
245 REG_WRITE(ah, AR_PHY(0x37), reg32);
248 ah->curchan_rad_index = -1;
254 * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
255 * @ah: atheros hardware structure
258 * For non single-chip solutions. Converts to baseband spur frequency given the
259 * input channel frequency and compute register settings below.
261 static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
262 struct ath9k_channel *chan)
264 int bb_spur = AR_NO_SPUR;
267 int spur_delta_phase;
269 int upper, lower, cur_vit_mask;
272 static int pilot_mask_reg[4] = {
273 AR_PHY_TIMING7, AR_PHY_TIMING8,
274 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
276 static int chan_mask_reg[4] = {
277 AR_PHY_TIMING9, AR_PHY_TIMING10,
278 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
280 static int inc[4] = { 0, 100, 0, 0 };
287 bool is2GHz = IS_CHAN_2GHZ(chan);
289 memset(&mask_m, 0, sizeof(int8_t) * 123);
290 memset(&mask_p, 0, sizeof(int8_t) * 123);
292 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
293 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
294 if (AR_NO_SPUR == cur_bb_spur)
296 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
297 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
298 bb_spur = cur_bb_spur;
303 if (AR_NO_SPUR == bb_spur)
308 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
309 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
310 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
311 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
312 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
314 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
316 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
317 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
318 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
319 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
320 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
321 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
323 spur_delta_phase = ((bb_spur * 524288) / 100) &
324 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
326 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
327 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
329 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
330 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
331 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
332 REG_WRITE(ah, AR_PHY_TIMING11, new);
338 for (i = 0; i < 4; i++) {
342 for (bp = 0; bp < 30; bp++) {
343 if ((cur_bin > lower) && (cur_bin < upper)) {
344 pilot_mask = pilot_mask | 0x1 << bp;
345 chan_mask = chan_mask | 0x1 << bp;
350 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
351 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
358 for (i = 0; i < 123; i++) {
359 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
361 /* workaround for gcc bug #37014 */
362 volatile int tmp_v = abs(cur_vit_mask - bin);
368 if (cur_vit_mask < 0)
369 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
371 mask_p[cur_vit_mask / 100] = mask_amt;
376 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
377 | (mask_m[48] << 26) | (mask_m[49] << 24)
378 | (mask_m[50] << 22) | (mask_m[51] << 20)
379 | (mask_m[52] << 18) | (mask_m[53] << 16)
380 | (mask_m[54] << 14) | (mask_m[55] << 12)
381 | (mask_m[56] << 10) | (mask_m[57] << 8)
382 | (mask_m[58] << 6) | (mask_m[59] << 4)
383 | (mask_m[60] << 2) | (mask_m[61] << 0);
384 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
385 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
387 tmp_mask = (mask_m[31] << 28)
388 | (mask_m[32] << 26) | (mask_m[33] << 24)
389 | (mask_m[34] << 22) | (mask_m[35] << 20)
390 | (mask_m[36] << 18) | (mask_m[37] << 16)
391 | (mask_m[48] << 14) | (mask_m[39] << 12)
392 | (mask_m[40] << 10) | (mask_m[41] << 8)
393 | (mask_m[42] << 6) | (mask_m[43] << 4)
394 | (mask_m[44] << 2) | (mask_m[45] << 0);
395 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
396 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
398 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
399 | (mask_m[18] << 26) | (mask_m[18] << 24)
400 | (mask_m[20] << 22) | (mask_m[20] << 20)
401 | (mask_m[22] << 18) | (mask_m[22] << 16)
402 | (mask_m[24] << 14) | (mask_m[24] << 12)
403 | (mask_m[25] << 10) | (mask_m[26] << 8)
404 | (mask_m[27] << 6) | (mask_m[28] << 4)
405 | (mask_m[29] << 2) | (mask_m[30] << 0);
406 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
407 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
409 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
410 | (mask_m[2] << 26) | (mask_m[3] << 24)
411 | (mask_m[4] << 22) | (mask_m[5] << 20)
412 | (mask_m[6] << 18) | (mask_m[7] << 16)
413 | (mask_m[8] << 14) | (mask_m[9] << 12)
414 | (mask_m[10] << 10) | (mask_m[11] << 8)
415 | (mask_m[12] << 6) | (mask_m[13] << 4)
416 | (mask_m[14] << 2) | (mask_m[15] << 0);
417 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
418 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
420 tmp_mask = (mask_p[15] << 28)
421 | (mask_p[14] << 26) | (mask_p[13] << 24)
422 | (mask_p[12] << 22) | (mask_p[11] << 20)
423 | (mask_p[10] << 18) | (mask_p[9] << 16)
424 | (mask_p[8] << 14) | (mask_p[7] << 12)
425 | (mask_p[6] << 10) | (mask_p[5] << 8)
426 | (mask_p[4] << 6) | (mask_p[3] << 4)
427 | (mask_p[2] << 2) | (mask_p[1] << 0);
428 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
429 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
431 tmp_mask = (mask_p[30] << 28)
432 | (mask_p[29] << 26) | (mask_p[28] << 24)
433 | (mask_p[27] << 22) | (mask_p[26] << 20)
434 | (mask_p[25] << 18) | (mask_p[24] << 16)
435 | (mask_p[23] << 14) | (mask_p[22] << 12)
436 | (mask_p[21] << 10) | (mask_p[20] << 8)
437 | (mask_p[19] << 6) | (mask_p[18] << 4)
438 | (mask_p[17] << 2) | (mask_p[16] << 0);
439 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
440 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
442 tmp_mask = (mask_p[45] << 28)
443 | (mask_p[44] << 26) | (mask_p[43] << 24)
444 | (mask_p[42] << 22) | (mask_p[41] << 20)
445 | (mask_p[40] << 18) | (mask_p[39] << 16)
446 | (mask_p[38] << 14) | (mask_p[37] << 12)
447 | (mask_p[36] << 10) | (mask_p[35] << 8)
448 | (mask_p[34] << 6) | (mask_p[33] << 4)
449 | (mask_p[32] << 2) | (mask_p[31] << 0);
450 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
451 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
453 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
454 | (mask_p[59] << 26) | (mask_p[58] << 24)
455 | (mask_p[57] << 22) | (mask_p[56] << 20)
456 | (mask_p[55] << 18) | (mask_p[54] << 16)
457 | (mask_p[53] << 14) | (mask_p[52] << 12)
458 | (mask_p[51] << 10) | (mask_p[50] << 8)
459 | (mask_p[49] << 6) | (mask_p[48] << 4)
460 | (mask_p[47] << 2) | (mask_p[46] << 0);
461 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
462 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
466 * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
467 * @ah: atheros hardware structure
469 * Only required for older devices with external AR2133/AR5133 radios.
471 static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
473 #define ATH_ALLOC_BANK(bank, size) do { \
474 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
476 ath_err(common, "Cannot allocate RF banks\n"); \
481 struct ath_common *common = ath9k_hw_common(ah);
483 BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
485 ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
486 ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
487 ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
488 ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
489 ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
490 ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
491 ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
492 ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
495 #undef ATH_ALLOC_BANK
500 * ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
501 * @ah: atheros hardware struture
502 * For the external AR2133/AR5133 radios banks.
504 static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
506 #define ATH_FREE_BANK(bank) do { \
511 BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
513 ATH_FREE_BANK(ah->analogBank0Data);
514 ATH_FREE_BANK(ah->analogBank1Data);
515 ATH_FREE_BANK(ah->analogBank2Data);
516 ATH_FREE_BANK(ah->analogBank3Data);
517 ATH_FREE_BANK(ah->analogBank6Data);
518 ATH_FREE_BANK(ah->analogBank6TPCData);
519 ATH_FREE_BANK(ah->analogBank7Data);
520 ATH_FREE_BANK(ah->bank6Temp);
526 * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
527 * @ah: atheros hardware structure
531 * Used for the external AR2133/AR5133 radios.
533 * Reads the EEPROM header info from the device structure and programs
534 * all rf registers. This routine requires access to the analog
535 * rf device. This is not required for single-chip devices.
537 static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
538 struct ath9k_channel *chan,
542 u32 ob5GHz = 0, db5GHz = 0;
543 u32 ob2GHz = 0, db2GHz = 0;
547 * Software does not need to program bank data
548 * for single chip devices, that is AR9280 or anything
551 if (AR_SREV_9280_20_OR_LATER(ah))
554 /* Setup rf parameters */
555 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
557 /* Setup Bank 0 Write */
558 ar5008_rf_bank_setup(ah->analogBank0Data, &ah->iniBank0, 1);
560 /* Setup Bank 1 Write */
561 ar5008_rf_bank_setup(ah->analogBank1Data, &ah->iniBank1, 1);
563 /* Setup Bank 2 Write */
564 ar5008_rf_bank_setup(ah->analogBank2Data, &ah->iniBank2, 1);
566 /* Setup Bank 6 Write */
567 ar5008_rf_bank_setup(ah->analogBank3Data, &ah->iniBank3,
571 for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
572 ah->analogBank6Data[i] =
573 INI_RA(&ah->iniBank6TPC, i, modesIndex);
577 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
578 if (eepMinorRev >= 2) {
579 if (IS_CHAN_2GHZ(chan)) {
580 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
581 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
582 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
584 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
587 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
588 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
589 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
591 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
596 /* Setup Bank 7 Setup */
597 ar5008_rf_bank_setup(ah->analogBank7Data, &ah->iniBank7, 1);
599 /* Write Analog registers */
600 REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
602 REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
604 REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
606 REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
608 REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
610 REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
616 static void ar5008_hw_init_bb(struct ath_hw *ah,
617 struct ath9k_channel *chan)
621 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
623 synthDelay = (4 * synthDelay) / 22;
627 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
629 udelay(synthDelay + BASE_ACTIVATE_DELAY);
632 static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
634 int rx_chainmask, tx_chainmask;
636 rx_chainmask = ah->rxchainmask;
637 tx_chainmask = ah->txchainmask;
640 switch (rx_chainmask) {
642 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
643 AR_PHY_SWAP_ALT_CHAIN);
645 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
646 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
647 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
653 ENABLE_REGWRITE_BUFFER(ah);
654 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
655 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
658 ENABLE_REGWRITE_BUFFER(ah);
662 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
664 REGWRITE_BUFFER_FLUSH(ah);
666 if (tx_chainmask == 0x5) {
667 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
668 AR_PHY_SWAP_ALT_CHAIN);
670 if (AR_SREV_9100(ah))
671 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
672 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
675 static void ar5008_hw_override_ini(struct ath_hw *ah,
676 struct ath9k_channel *chan)
681 * Set the RX_ABORT and RX_DIS and clear if off only after
682 * RXE is set for MAC. This prevents frames with corrupted
685 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
687 if (AR_SREV_9280_20_OR_LATER(ah)) {
688 val = REG_READ(ah, AR_PCU_MISC_MODE2);
690 if (!AR_SREV_9271(ah))
691 val &= ~AR_PCU_MISC_MODE2_HWWAR1;
693 if (AR_SREV_9287_11_OR_LATER(ah))
694 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
696 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
699 if (!AR_SREV_5416_20_OR_LATER(ah) ||
700 AR_SREV_9280_20_OR_LATER(ah))
703 * Disable BB clock gating
704 * Necessary to avoid issues on AR5416 2.0
706 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
709 * Disable RIFS search on some chips to avoid baseband
712 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
713 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
714 val &= ~AR_PHY_RIFS_INIT_DELAY;
715 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
719 static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
720 struct ath9k_channel *chan)
723 u32 enableDacFifo = 0;
725 if (AR_SREV_9285_12_OR_LATER(ah))
726 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
727 AR_PHY_FC_ENABLE_DAC_FIFO);
729 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
730 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
732 if (IS_CHAN_HT40(chan)) {
733 phymode |= AR_PHY_FC_DYN2040_EN;
735 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
736 (chan->chanmode == CHANNEL_G_HT40PLUS))
737 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
740 REG_WRITE(ah, AR_PHY_TURBO, phymode);
742 ath9k_hw_set11nmac2040(ah);
744 ENABLE_REGWRITE_BUFFER(ah);
746 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
747 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
749 REGWRITE_BUFFER_FLUSH(ah);
753 static int ar5008_hw_process_ini(struct ath_hw *ah,
754 struct ath9k_channel *chan)
756 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
757 struct ath_common *common = ath9k_hw_common(ah);
758 int i, regWrites = 0;
759 struct ieee80211_channel *channel = chan->chan;
760 u32 modesIndex, freqIndex;
762 switch (chan->chanmode) {
768 case CHANNEL_A_HT40PLUS:
769 case CHANNEL_A_HT40MINUS:
779 case CHANNEL_G_HT40PLUS:
780 case CHANNEL_G_HT40MINUS:
790 * Set correct baseband to analog shift setting to
791 * access analog chips.
793 REG_WRITE(ah, AR_PHY(0), 0x00000007);
795 /* Write ADDAC shifts */
796 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
797 ah->eep_ops->set_addac(ah, chan);
799 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
800 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
802 ENABLE_REGWRITE_BUFFER(ah);
804 for (i = 0; i < ah->iniModes.ia_rows; i++) {
805 u32 reg = INI_RA(&ah->iniModes, i, 0);
806 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
808 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
809 val &= ~AR_AN_TOP2_PWDCLKIND;
811 REG_WRITE(ah, reg, val);
813 if (reg >= 0x7800 && reg < 0x78a0
814 && ah->config.analog_shiftreg
815 && (common->bus_ops->ath_bus_type != ATH_USB)) {
822 REGWRITE_BUFFER_FLUSH(ah);
824 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah))
825 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
827 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
828 AR_SREV_9287_11_OR_LATER(ah))
829 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
831 if (AR_SREV_9271_10(ah))
832 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
833 modesIndex, regWrites);
835 ENABLE_REGWRITE_BUFFER(ah);
837 /* Write common array parameters */
838 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
839 u32 reg = INI_RA(&ah->iniCommon, i, 0);
840 u32 val = INI_RA(&ah->iniCommon, i, 1);
842 REG_WRITE(ah, reg, val);
844 if (reg >= 0x7800 && reg < 0x78a0
845 && ah->config.analog_shiftreg
846 && (common->bus_ops->ath_bus_type != ATH_USB)) {
853 REGWRITE_BUFFER_FLUSH(ah);
855 if (AR_SREV_9271(ah)) {
856 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
857 REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
858 modesIndex, regWrites);
860 REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
861 modesIndex, regWrites);
864 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
866 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) {
867 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
871 ar5008_hw_override_ini(ah, chan);
872 ar5008_hw_set_channel_regs(ah, chan);
873 ar5008_hw_init_chain_masks(ah);
877 ah->eep_ops->set_txpower(ah, chan,
878 ath9k_regd_get_ctl(regulatory, chan),
879 channel->max_antenna_gain * 2,
880 channel->max_power * 2,
881 min((u32) MAX_RATE_POWER,
882 (u32) regulatory->power_limit), false);
884 /* Write analog registers */
885 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
886 ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n");
893 static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
900 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
901 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
903 if (!AR_SREV_9280_20_OR_LATER(ah))
904 rfMode |= (IS_CHAN_5GHZ(chan)) ?
905 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
907 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
908 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
910 REG_WRITE(ah, AR_PHY_MODE, rfMode);
913 static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
915 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
918 static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
919 struct ath9k_channel *chan)
921 u32 coef_scaled, ds_coef_exp, ds_coef_man;
922 u32 clockMhzScaled = 0x64000000;
923 struct chan_centers centers;
925 if (IS_CHAN_HALF_RATE(chan))
926 clockMhzScaled = clockMhzScaled >> 1;
927 else if (IS_CHAN_QUARTER_RATE(chan))
928 clockMhzScaled = clockMhzScaled >> 2;
930 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
931 coef_scaled = clockMhzScaled / centers.synth_center;
933 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
936 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
937 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
938 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
939 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
941 coef_scaled = (9 * coef_scaled) / 10;
943 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
946 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
947 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
948 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
949 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
952 static bool ar5008_hw_rfbus_req(struct ath_hw *ah)
954 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
955 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
956 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
959 static void ar5008_hw_rfbus_done(struct ath_hw *ah)
961 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
962 if (IS_CHAN_B(ah->curchan))
963 synthDelay = (4 * synthDelay) / 22;
967 udelay(synthDelay + BASE_ACTIVATE_DELAY);
969 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
972 static void ar5008_restore_chainmask(struct ath_hw *ah)
974 int rx_chainmask = ah->rxchainmask;
976 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
977 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
978 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
982 static void ar5008_set_diversity(struct ath_hw *ah, bool value)
984 u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
986 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
988 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
989 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
992 static u32 ar9100_hw_compute_pll_control(struct ath_hw *ah,
993 struct ath9k_channel *chan)
995 if (chan && IS_CHAN_5GHZ(chan))
1000 static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah,
1001 struct ath9k_channel *chan)
1005 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1007 if (chan && IS_CHAN_HALF_RATE(chan))
1008 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1009 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1010 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1012 if (chan && IS_CHAN_5GHZ(chan))
1013 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1015 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1020 static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah,
1021 struct ath9k_channel *chan)
1025 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1027 if (chan && IS_CHAN_HALF_RATE(chan))
1028 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1029 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1030 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1032 if (chan && IS_CHAN_5GHZ(chan))
1033 pll |= SM(0xa, AR_RTC_PLL_DIV);
1035 pll |= SM(0xb, AR_RTC_PLL_DIV);
1040 static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
1041 enum ath9k_ani_cmd cmd,
1044 struct ar5416AniState *aniState = &ah->curchan->ani;
1045 struct ath_common *common = ath9k_hw_common(ah);
1047 switch (cmd & ah->ani_function) {
1048 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
1051 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
1052 ath_dbg(common, ATH_DBG_ANI,
1053 "level out of range (%u > %zu)\n",
1054 level, ARRAY_SIZE(ah->totalSizeDesired));
1058 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
1059 AR_PHY_DESIRED_SZ_TOT_DES,
1060 ah->totalSizeDesired[level]);
1061 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1062 AR_PHY_AGC_CTL1_COARSE_LOW,
1063 ah->coarse_low[level]);
1064 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1065 AR_PHY_AGC_CTL1_COARSE_HIGH,
1066 ah->coarse_high[level]);
1067 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1068 AR_PHY_FIND_SIG_FIRPWR,
1071 if (level > aniState->noiseImmunityLevel)
1072 ah->stats.ast_ani_niup++;
1073 else if (level < aniState->noiseImmunityLevel)
1074 ah->stats.ast_ani_nidown++;
1075 aniState->noiseImmunityLevel = level;
1078 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1079 static const int m1ThreshLow[] = { 127, 50 };
1080 static const int m2ThreshLow[] = { 127, 40 };
1081 static const int m1Thresh[] = { 127, 0x4d };
1082 static const int m2Thresh[] = { 127, 0x40 };
1083 static const int m2CountThr[] = { 31, 16 };
1084 static const int m2CountThrLow[] = { 63, 48 };
1085 u32 on = param ? 1 : 0;
1087 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1088 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1090 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1091 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1093 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1094 AR_PHY_SFCORR_M1_THRESH,
1096 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1097 AR_PHY_SFCORR_M2_THRESH,
1099 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1100 AR_PHY_SFCORR_M2COUNT_THR,
1102 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1103 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1106 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1107 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
1109 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1110 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
1112 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1113 AR_PHY_SFCORR_EXT_M1_THRESH,
1115 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1116 AR_PHY_SFCORR_EXT_M2_THRESH,
1120 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1121 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1123 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1124 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1126 if (!on != aniState->ofdmWeakSigDetectOff) {
1128 ah->stats.ast_ani_ofdmon++;
1130 ah->stats.ast_ani_ofdmoff++;
1131 aniState->ofdmWeakSigDetectOff = !on;
1135 case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
1136 static const int weakSigThrCck[] = { 8, 6 };
1137 u32 high = param ? 1 : 0;
1139 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
1140 AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
1141 weakSigThrCck[high]);
1142 if (high != aniState->cckWeakSigThreshold) {
1144 ah->stats.ast_ani_cckhigh++;
1146 ah->stats.ast_ani_ccklow++;
1147 aniState->cckWeakSigThreshold = high;
1151 case ATH9K_ANI_FIRSTEP_LEVEL:{
1152 static const int firstep[] = { 0, 4, 8 };
1155 if (level >= ARRAY_SIZE(firstep)) {
1156 ath_dbg(common, ATH_DBG_ANI,
1157 "level out of range (%u > %zu)\n",
1158 level, ARRAY_SIZE(firstep));
1161 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1162 AR_PHY_FIND_SIG_FIRSTEP,
1164 if (level > aniState->firstepLevel)
1165 ah->stats.ast_ani_stepup++;
1166 else if (level < aniState->firstepLevel)
1167 ah->stats.ast_ani_stepdown++;
1168 aniState->firstepLevel = level;
1171 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1172 static const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
1175 if (level >= ARRAY_SIZE(cycpwrThr1)) {
1176 ath_dbg(common, ATH_DBG_ANI,
1177 "level out of range (%u > %zu)\n",
1178 level, ARRAY_SIZE(cycpwrThr1));
1181 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1182 AR_PHY_TIMING5_CYCPWR_THR1,
1184 if (level > aniState->spurImmunityLevel)
1185 ah->stats.ast_ani_spurup++;
1186 else if (level < aniState->spurImmunityLevel)
1187 ah->stats.ast_ani_spurdown++;
1188 aniState->spurImmunityLevel = level;
1191 case ATH9K_ANI_PRESENT:
1194 ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
1198 ath_dbg(common, ATH_DBG_ANI, "ANI parameters:\n");
1199 ath_dbg(common, ATH_DBG_ANI,
1200 "noiseImmunityLevel=%d, spurImmunityLevel=%d, ofdmWeakSigDetectOff=%d\n",
1201 aniState->noiseImmunityLevel,
1202 aniState->spurImmunityLevel,
1203 !aniState->ofdmWeakSigDetectOff);
1204 ath_dbg(common, ATH_DBG_ANI,
1205 "cckWeakSigThreshold=%d, firstepLevel=%d, listenTime=%d\n",
1206 aniState->cckWeakSigThreshold,
1207 aniState->firstepLevel,
1208 aniState->listenTime);
1209 ath_dbg(common, ATH_DBG_ANI,
1210 "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
1211 aniState->ofdmPhyErrCount,
1212 aniState->cckPhyErrCount);
1217 static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1218 enum ath9k_ani_cmd cmd,
1221 struct ath_common *common = ath9k_hw_common(ah);
1222 struct ath9k_channel *chan = ah->curchan;
1223 struct ar5416AniState *aniState = &chan->ani;
1226 switch (cmd & ah->ani_function) {
1227 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1229 * on == 1 means ofdm weak signal detection is ON
1230 * on == 1 is the default, for less noise immunity
1232 * on == 0 means ofdm weak signal detection is OFF
1233 * on == 0 means more noise imm
1235 u32 on = param ? 1 : 0;
1237 * make register setting for default
1238 * (weak sig detect ON) come from INI file
1240 int m1ThreshLow = on ?
1241 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
1242 int m2ThreshLow = on ?
1243 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
1245 aniState->iniDef.m1Thresh : m1Thresh_off;
1247 aniState->iniDef.m2Thresh : m2Thresh_off;
1248 int m2CountThr = on ?
1249 aniState->iniDef.m2CountThr : m2CountThr_off;
1250 int m2CountThrLow = on ?
1251 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
1252 int m1ThreshLowExt = on ?
1253 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
1254 int m2ThreshLowExt = on ?
1255 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
1256 int m1ThreshExt = on ?
1257 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
1258 int m2ThreshExt = on ?
1259 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
1261 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1262 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1264 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1265 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1267 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1268 AR_PHY_SFCORR_M1_THRESH, m1Thresh);
1269 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1270 AR_PHY_SFCORR_M2_THRESH, m2Thresh);
1271 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1272 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
1273 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1274 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1277 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1278 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
1279 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1280 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
1281 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1282 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
1283 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1284 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
1287 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1288 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1290 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1291 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1293 if (!on != aniState->ofdmWeakSigDetectOff) {
1294 ath_dbg(common, ATH_DBG_ANI,
1295 "** ch %d: ofdm weak signal: %s=>%s\n",
1297 !aniState->ofdmWeakSigDetectOff ?
1301 ah->stats.ast_ani_ofdmon++;
1303 ah->stats.ast_ani_ofdmoff++;
1304 aniState->ofdmWeakSigDetectOff = !on;
1308 case ATH9K_ANI_FIRSTEP_LEVEL:{
1311 if (level >= ARRAY_SIZE(firstep_table)) {
1312 ath_dbg(common, ATH_DBG_ANI,
1313 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1314 level, ARRAY_SIZE(firstep_table));
1319 * make register setting relative to default
1320 * from INI file & cap value
1322 value = firstep_table[level] -
1323 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
1324 aniState->iniDef.firstep;
1325 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1326 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1327 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1328 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1329 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1330 AR_PHY_FIND_SIG_FIRSTEP,
1333 * we need to set first step low register too
1334 * make register setting relative to default
1335 * from INI file & cap value
1337 value2 = firstep_table[level] -
1338 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
1339 aniState->iniDef.firstepLow;
1340 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1341 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1342 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1343 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1345 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1346 AR_PHY_FIND_SIG_FIRSTEP_LOW, value2);
1348 if (level != aniState->firstepLevel) {
1349 ath_dbg(common, ATH_DBG_ANI,
1350 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1352 aniState->firstepLevel,
1354 ATH9K_ANI_FIRSTEP_LVL_NEW,
1356 aniState->iniDef.firstep);
1357 ath_dbg(common, ATH_DBG_ANI,
1358 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1360 aniState->firstepLevel,
1362 ATH9K_ANI_FIRSTEP_LVL_NEW,
1364 aniState->iniDef.firstepLow);
1365 if (level > aniState->firstepLevel)
1366 ah->stats.ast_ani_stepup++;
1367 else if (level < aniState->firstepLevel)
1368 ah->stats.ast_ani_stepdown++;
1369 aniState->firstepLevel = level;
1373 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1376 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1377 ath_dbg(common, ATH_DBG_ANI,
1378 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1379 level, ARRAY_SIZE(cycpwrThr1_table));
1383 * make register setting relative to default
1384 * from INI file & cap value
1386 value = cycpwrThr1_table[level] -
1387 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
1388 aniState->iniDef.cycpwrThr1;
1389 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1390 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1391 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1392 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1393 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1394 AR_PHY_TIMING5_CYCPWR_THR1,
1398 * set AR_PHY_EXT_CCA for extension channel
1399 * make register setting relative to default
1400 * from INI file & cap value
1402 value2 = cycpwrThr1_table[level] -
1403 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
1404 aniState->iniDef.cycpwrThr1Ext;
1405 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1406 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1407 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1408 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1409 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1410 AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2);
1412 if (level != aniState->spurImmunityLevel) {
1413 ath_dbg(common, ATH_DBG_ANI,
1414 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1416 aniState->spurImmunityLevel,
1418 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1420 aniState->iniDef.cycpwrThr1);
1421 ath_dbg(common, ATH_DBG_ANI,
1422 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1424 aniState->spurImmunityLevel,
1426 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1428 aniState->iniDef.cycpwrThr1Ext);
1429 if (level > aniState->spurImmunityLevel)
1430 ah->stats.ast_ani_spurup++;
1431 else if (level < aniState->spurImmunityLevel)
1432 ah->stats.ast_ani_spurdown++;
1433 aniState->spurImmunityLevel = level;
1437 case ATH9K_ANI_MRC_CCK:
1439 * You should not see this as AR5008, AR9001, AR9002
1440 * does not have hardware support for MRC CCK.
1444 case ATH9K_ANI_PRESENT:
1447 ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
1451 ath_dbg(common, ATH_DBG_ANI,
1452 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1453 aniState->spurImmunityLevel,
1454 !aniState->ofdmWeakSigDetectOff ? "on" : "off",
1455 aniState->firstepLevel,
1456 !aniState->mrcCCKOff ? "on" : "off",
1457 aniState->listenTime,
1458 aniState->ofdmPhyErrCount,
1459 aniState->cckPhyErrCount);
1463 static void ar5008_hw_do_getnf(struct ath_hw *ah,
1464 int16_t nfarray[NUM_NF_READINGS])
1468 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
1469 nfarray[0] = sign_extend32(nf, 8);
1471 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
1472 nfarray[1] = sign_extend32(nf, 8);
1474 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
1475 nfarray[2] = sign_extend32(nf, 8);
1477 if (!IS_CHAN_HT40(ah->curchan))
1480 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
1481 nfarray[3] = sign_extend32(nf, 8);
1483 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
1484 nfarray[4] = sign_extend32(nf, 8);
1486 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
1487 nfarray[5] = sign_extend32(nf, 8);
1491 * Initialize the ANI register values with default (ini) values.
1492 * This routine is called during a (full) hardware reset after
1493 * all the registers are initialised from the INI.
1495 static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
1497 struct ath_common *common = ath9k_hw_common(ah);
1498 struct ath9k_channel *chan = ah->curchan;
1499 struct ar5416AniState *aniState = &chan->ani;
1500 struct ath9k_ani_default *iniDef;
1503 iniDef = &aniState->iniDef;
1505 ath_dbg(common, ATH_DBG_ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1506 ah->hw_version.macVersion,
1507 ah->hw_version.macRev,
1510 chan->channelFlags);
1512 val = REG_READ(ah, AR_PHY_SFCORR);
1513 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1514 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1515 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1517 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1518 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1519 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1520 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1522 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1523 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1524 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1525 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1526 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1527 iniDef->firstep = REG_READ_FIELD(ah,
1529 AR_PHY_FIND_SIG_FIRSTEP);
1530 iniDef->firstepLow = REG_READ_FIELD(ah,
1531 AR_PHY_FIND_SIG_LOW,
1532 AR_PHY_FIND_SIG_FIRSTEP_LOW);
1533 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1535 AR_PHY_TIMING5_CYCPWR_THR1);
1536 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1538 AR_PHY_EXT_TIMING5_CYCPWR_THR1);
1540 /* these levels just got reset to defaults by the INI */
1541 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1542 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1543 aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
1544 aniState->mrcCCKOff = true; /* not available on pre AR9003 */
1547 static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
1549 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;
1550 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;
1551 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;
1552 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;
1553 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;
1554 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
1557 static void ar5008_hw_set_radar_params(struct ath_hw *ah,
1558 struct ath_hw_radar_conf *conf)
1560 u32 radar_0 = 0, radar_1 = 0;
1563 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1567 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1568 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1569 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1570 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1571 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1572 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1574 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1575 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1576 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1577 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1578 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1580 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1581 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1582 if (conf->ext_channel)
1583 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1585 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1588 static void ar5008_hw_set_radar_conf(struct ath_hw *ah)
1590 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1592 conf->fir_power = -33;
1593 conf->radar_rssi = 20;
1594 conf->pulse_height = 10;
1595 conf->pulse_rssi = 24;
1596 conf->pulse_inband = 15;
1597 conf->pulse_maxlen = 255;
1598 conf->pulse_inband_step = 12;
1599 conf->radar_inband = 8;
1602 void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
1604 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1605 static const u32 ar5416_cca_regs[6] = {
1614 priv_ops->rf_set_freq = ar5008_hw_set_channel;
1615 priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
1617 priv_ops->rf_alloc_ext_banks = ar5008_hw_rf_alloc_ext_banks;
1618 priv_ops->rf_free_ext_banks = ar5008_hw_rf_free_ext_banks;
1619 priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
1620 priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
1621 priv_ops->init_bb = ar5008_hw_init_bb;
1622 priv_ops->process_ini = ar5008_hw_process_ini;
1623 priv_ops->set_rfmode = ar5008_hw_set_rfmode;
1624 priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;
1625 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
1626 priv_ops->rfbus_req = ar5008_hw_rfbus_req;
1627 priv_ops->rfbus_done = ar5008_hw_rfbus_done;
1628 priv_ops->restore_chainmask = ar5008_restore_chainmask;
1629 priv_ops->set_diversity = ar5008_set_diversity;
1630 priv_ops->do_getnf = ar5008_hw_do_getnf;
1631 priv_ops->set_radar_params = ar5008_hw_set_radar_params;
1633 if (modparam_force_new_ani) {
1634 priv_ops->ani_control = ar5008_hw_ani_control_new;
1635 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs;
1637 priv_ops->ani_control = ar5008_hw_ani_control_old;
1639 if (AR_SREV_9100(ah))
1640 priv_ops->compute_pll_control = ar9100_hw_compute_pll_control;
1641 else if (AR_SREV_9160_10_OR_LATER(ah))
1642 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
1644 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
1646 ar5008_hw_set_nf_limits(ah);
1647 ar5008_hw_set_radar_conf(ah);
1648 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));