drivers/net/ethernet/rockchip/gmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5         Copyright(C) 2007-2011 STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/clk.h>
  32 #include <linux/kernel.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ip.h>
  35 #include <linux/tcp.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/if_ether.h>
  39 #include <linux/crc32.h>
  40 #include <linux/mii.h>
  41 #include <linux/if.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/slab.h>
  45 #include <linux/prefetch.h>
  46 #ifdef CONFIG_GMAC_DEBUG_FS
  47 #include <linux/debugfs.h>
  48 #include <linux/seq_file.h>
  49 #endif /* CONFIG_GMAC_DEBUG_FS */
  50 #include <linux/net_tstamp.h>
  51 #include "stmmac_ptp.h"
  52 #include "stmmac.h"
  53 #include "../eth_mac.h"
  54
  55 #undef STMMAC_DEBUG
  56 /*#define STMMAC_DEBUG*/
  57 #ifdef STMMAC_DEBUG
  58 #define DBG(nlevel, klevel, fmt, args...) \
  59                 ((void)(netif_msg_##nlevel(priv) && \
  60                 printk(KERN_##klevel fmt, ## args)))
  61 #else
  62 #define DBG(nlevel, klevel, fmt, args...) do { } while (0)
  63 #endif
  64
  65 #undef STMMAC_RX_DEBUG
  66 /*#define STMMAC_RX_DEBUG*/
  67 #ifdef STMMAC_RX_DEBUG
  68 #define RX_DBG(fmt, args...)  printk(fmt, ## args)
  69 #else
  70 #define RX_DBG(fmt, args...)  do { } while (0)
  71 #endif
  72
  73 #undef STMMAC_XMIT_DEBUG
  74 /*#define STMMAC_XMIT_DEBUG*/
  75 #ifdef STMMAC_XMIT_DEBUG
  76 #define TX_DBG(fmt, args...)  printk(fmt, ## args)
  77 #else
  78 #define TX_DBG(fmt, args...)  do { } while (0)
  79 #endif
  80
  81 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
  82 #define JUMBO_LEN       9000
  83
  84 /* Module parameters */
  85 #define TX_TIMEO        5000
  86 static int watchdog = TX_TIMEO;
  87 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  88 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  89
  90 static int debug = -1;
  91 module_param(debug, int, S_IRUGO | S_IWUSR);
  92 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  93
  94 int phyaddr = -1;
  95 module_param(phyaddr, int, S_IRUGO);
  96 MODULE_PARM_DESC(phyaddr, "Physical device address");
  97
  98 #define DMA_TX_SIZE 256
  99 static int dma_txsize = DMA_TX_SIZE;
 100 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
 101 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
 102
 103 #define DMA_RX_SIZE 256
 104 static int dma_rxsize = DMA_RX_SIZE;
 105 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
 106 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
 107
 108 static int flow_ctrl = FLOW_OFF;
 109 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
 110 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
 111
 112 static int pause = PAUSE_TIME;
 113 module_param(pause, int, S_IRUGO | S_IWUSR);
 114 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
 115
 116 #define TC_DEFAULT 64
 117 static int tc = TC_DEFAULT;
 118 module_param(tc, int, S_IRUGO | S_IWUSR);
 119 MODULE_PARM_DESC(tc, "DMA threshold control value");
 120
 121 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
 122 static int buf_sz = DMA_BUFFER_SIZE;
 123 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
 124 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 125
 126 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 127                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 128                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 129
 130 #define STMMAC_DEFAULT_LPI_TIMER        1000
 131 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 132 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 133 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 134 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
 135
 136 /* By default the driver will use the ring mode to manage tx and rx descriptors
 137  * but passing this value so user can force to use the chain instead of the ring
 138  */
 139 static unsigned int chain_mode;
 140 module_param(chain_mode, int, S_IRUGO);
 141 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 142
 143 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 144
 145 #ifdef CONFIG_GMAC_DEBUG_FS
 146 static int stmmac_init_fs(struct net_device *dev);
 147 static void stmmac_exit_fs(void);
 148 #endif
 149
 150 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 151
 152 /**
 153  * stmmac_verify_args - verify the driver parameters.
 154  * Description: it verifies if some wrong parameter is passed to the driver.
 155  * Note that wrong parameters are replaced with the default values.
 156  */
 157 static void stmmac_verify_args(void)
 158 {
 159         if (unlikely(watchdog < 0))
 160                 watchdog = TX_TIMEO;
 161         if (unlikely(dma_rxsize < 0))
 162                 dma_rxsize = DMA_RX_SIZE;
 163         if (unlikely(dma_txsize < 0))
 164                 dma_txsize = DMA_TX_SIZE;
 165         if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
 166                 buf_sz = DMA_BUFFER_SIZE;
 167         if (unlikely(flow_ctrl > 1))
 168                 flow_ctrl = FLOW_AUTO;
 169         else if (likely(flow_ctrl < 0))
 170                 flow_ctrl = FLOW_OFF;
 171         if (unlikely((pause < 0) || (pause > 0xffff)))
 172                 pause = PAUSE_TIME;
 173         if (eee_timer < 0)
 174                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 175 }
 176
 177 /**
 178  * stmmac_clk_csr_set - dynamically set the MDC clock
 179  * @priv: driver private structure
 180  * Description: this is to dynamically set the MDC clock according to the csr
 181  * clock input.
 182  * Note:
 183  *      If a specific clk_csr value is passed from the platform
 184  *      this means that the CSR Clock Range selection cannot be
 185  *      changed at run-time and it is fixed (as reported in the driver
 186  *      documentation). Viceversa the driver will try to set the MDC
 187  *      clock dynamically according to the actual clock input.
 188  */
 189 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 190 {
 191         u32 clk_rate;
 192
 193         clk_rate = clk_get_rate(priv->stmmac_clk);
 194
 195         /* Platform provided default clk_csr would be assumed valid
 196          * for all other cases except for the below mentioned ones.
 197          * For values higher than the IEEE 802.3 specified frequency
 198          * we can not estimate the proper divider as it is not known
 199          * the frequency of clk_csr_i. So we do not change the default
 200          * divider.
 201          */
 202         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 203                 if (clk_rate < CSR_F_35M)
 204                         priv->clk_csr = STMMAC_CSR_20_35M;
 205                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 206                         priv->clk_csr = STMMAC_CSR_35_60M;
 207                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 208                         priv->clk_csr = STMMAC_CSR_60_100M;
 209                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 210                         priv->clk_csr = STMMAC_CSR_100_150M;
 211                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 212                         priv->clk_csr = STMMAC_CSR_150_250M;
 213                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 214                         priv->clk_csr = STMMAC_CSR_250_300M;
 215         }
 216 }
 217
 218 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
 219 static void print_pkt(unsigned char *buf, int len)
 220 {
 221         int j;
 222         pr_info("len = %d byte, buf addr: 0x%p", len, buf);
 223         for (j = 0; j < len; j++) {
 224                 if ((j % 16) == 0)
 225                         pr_info("\n %03x:", j);
 226                 pr_info(" %02x", buf[j]);
 227         }
 228         pr_info("\n");
 229 }
 230 #endif
 231
 232 /* minimum number of free TX descriptors required to wake up TX process */
 233 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
 234
 235 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 236 {
 237         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
 238 }
 239
 240 /**
 241  * stmmac_hw_fix_mac_speed: callback for speed selection
 242  * @priv: driver private structure
 243  * Description: on some platforms (e.g. ST), some HW system configuraton
 244  * registers have to be set according to the link speed negotiated.
 245  */
 246 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
 247 {
 248         struct phy_device *phydev = priv->phydev;
 249
 250         if (likely(priv->plat->fix_mac_speed))
 251                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
 252 }
 253
 254 /**
 255  * stmmac_enable_eee_mode: Check and enter in LPI mode
 256  * @priv: driver private structure
 257  * Description: this function is to verify and enter in LPI mode for EEE.
 258  */
 259 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 260 {
 261         /* Check and enter in LPI mode */
 262         if ((priv->dirty_tx == priv->cur_tx) &&
 263             (priv->tx_path_in_lpi_mode == false))
 264                 priv->hw->mac->set_eee_mode(priv->ioaddr);
 265 }
 266
 267 /**
 268  * stmmac_disable_eee_mode: disable/exit from EEE
 269  * @priv: driver private structure
 270  * Description: this function is to exit and disable EEE in case of
 271  * LPI state is true. This is called by the xmit.
 272  */
 273 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 274 {
 275         priv->hw->mac->reset_eee_mode(priv->ioaddr);
 276         del_timer_sync(&priv->eee_ctrl_timer);
 277         priv->tx_path_in_lpi_mode = false;
 278 }
 279
 280 /**
 281  * stmmac_eee_ctrl_timer: EEE TX SW timer.
 282  * @arg : data hook
 283  * Description:
 284  *  if there is no data transfer and if we are not in LPI state,
 285  *  then MAC Transmitter can be moved to LPI state.
 286  */
 287 static void stmmac_eee_ctrl_timer(unsigned long arg)
 288 {
 289         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 290
 291         stmmac_enable_eee_mode(priv);
 292         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 293 }
 294
 295 /**
 296  * stmmac_eee_init: init EEE
 297  * @priv: driver private structure
 298  * Description:
 299  *  If the EEE support has been enabled while configuring the driver,
 300  *  if the GMAC actually supports the EEE (from the HW cap reg) and the
 301  *  phy can also manage EEE, so enable the LPI state and start the timer
 302  *  to verify if the tx path can enter in LPI state.
 303  */
 304 bool stmmac_eee_init(struct stmmac_priv *priv)
 305 {
 306         bool ret = false;
 307
 308         /* Using PCS we cannot dial with the phy registers at this stage
 309          * so we do not support extra feature like EEE.
 310          */
 311         if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
 312             (priv->pcs == STMMAC_PCS_RTBI))
 313                 goto out;
 314
 315         /* MAC core supports the EEE feature. */
 316         if (priv->dma_cap.eee) {
 317                 /* Check if the PHY supports EEE */
 318                 if (phy_init_eee(priv->phydev, 1))
 319                         goto out;
 320
 321                 if (!priv->eee_active) {
 322                         priv->eee_active = 1;
 323                         init_timer(&priv->eee_ctrl_timer);
 324                         priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
 325                         priv->eee_ctrl_timer.data = (unsigned long)priv;
 326                         priv->eee_ctrl_timer.expires = STMMAC_LPI_T(eee_timer);
 327                         add_timer(&priv->eee_ctrl_timer);
 328
 329                         priv->hw->mac->set_eee_timer(priv->ioaddr,
 330                                                      STMMAC_DEFAULT_LIT_LS,
 331                                                      priv->tx_lpi_timer);
 332                 } else
 333                         /* Set HW EEE according to the speed */
 334                         priv->hw->mac->set_eee_pls(priv->ioaddr,
 335                                                    priv->phydev->link);
 336
 337                 pr_info("stmmac: Energy-Efficient Ethernet initialized\n");
 338
 339                 ret = true;
 340         }
 341 out:
 342         return ret;
 343 }
 344
 345 /* stmmac_get_tx_hwtstamp: get HW TX timestamps
 346  * @priv: driver private structure
 347  * @entry : descriptor index to be used.
 348  * @skb : the socket buffer
 349  * Description :
 350  * This function will read timestamp from the descriptor & pass it to stack.
 351  * and also perform some sanity checks.
 352  */
 353 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 354                                    unsigned int entry, struct sk_buff *skb)
 355 {
 356         struct skb_shared_hwtstamps shhwtstamp;
 357         u64 ns;
 358         void *desc = NULL;
 359
 360         if (!priv->hwts_tx_en)
 361                 return;
 362
 363         /* exit if skb doesn't support hw tstamp */
 364         if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 365                 return;
 366
 367         if (priv->adv_ts)
 368                 desc = (priv->dma_etx + entry);
 369         else
 370                 desc = (priv->dma_tx + entry);
 371
 372         /* check tx tstamp status */
 373         if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
 374                 return;
 375
 376         /* get the valid tstamp */
 377         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 378
 379         memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 380         shhwtstamp.hwtstamp = ns_to_ktime(ns);
 381         /* pass tstamp to stack */
 382         skb_tstamp_tx(skb, &shhwtstamp);
 383
 384         return;
 385 }
 386
 387 /* stmmac_get_rx_hwtstamp: get HW RX timestamps
 388  * @priv: driver private structure
 389  * @entry : descriptor index to be used.
 390  * @skb : the socket buffer
 391  * Description :
 392  * This function will read received packet's timestamp from the descriptor
 393  * and pass it to stack. It also perform some sanity checks.
 394  */
 395 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
 396                                    unsigned int entry, struct sk_buff *skb)
 397 {
 398         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 399         u64 ns;
 400         void *desc = NULL;
 401
 402         if (!priv->hwts_rx_en)
 403                 return;
 404
 405         if (priv->adv_ts)
 406                 desc = (priv->dma_erx + entry);
 407         else
 408                 desc = (priv->dma_rx + entry);
 409
 410         /* exit if rx tstamp is not valid */
 411         if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
 412                 return;
 413
 414         /* get valid tstamp */
 415         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 416         shhwtstamp = skb_hwtstamps(skb);
 417         memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 418         shhwtstamp->hwtstamp = ns_to_ktime(ns);
 419 }
 420
 421 /**
 422  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
 423  *  @dev: device pointer.
 424  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
 425  *  a proprietary structure used to pass information to the driver.
 426  *  Description:
 427  *  This function configures the MAC to enable/disable both outgoing(TX)
 428  *  and incoming(RX) packets time stamping based on user input.
 429  *  Return Value:
 430  *  0 on success and an appropriate -ve integer on failure.
 431  */
 432 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
 433 {
 434         struct stmmac_priv *priv = netdev_priv(dev);
 435         struct hwtstamp_config config;
 436         struct timespec now;
 437         u64 temp = 0;
 438         u32 ptp_v2 = 0;
 439         u32 tstamp_all = 0;
 440         u32 ptp_over_ipv4_udp = 0;
 441         u32 ptp_over_ipv6_udp = 0;
 442         u32 ptp_over_ethernet = 0;
 443         u32 snap_type_sel = 0;
 444         u32 ts_master_en = 0;
 445         u32 ts_event_en = 0;
 446         u32 value = 0;
 447
 448         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 449                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 450                 priv->hwts_tx_en = 0;
 451                 priv->hwts_rx_en = 0;
 452
 453                 return -EOPNOTSUPP;
 454         }
 455
 456         if (copy_from_user(&config, ifr->ifr_data,
 457                            sizeof(struct hwtstamp_config)))
 458                 return -EFAULT;
 459
 460         pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 461                  __func__, config.flags, config.tx_type, config.rx_filter);
 462
 463         /* reserved for future extensions */
 464         if (config.flags)
 465                 return -EINVAL;
 466
 467         switch (config.tx_type) {
 468         case HWTSTAMP_TX_OFF:
 469                 priv->hwts_tx_en = 0;
 470                 break;
 471         case HWTSTAMP_TX_ON:
 472                 priv->hwts_tx_en = 1;
 473                 break;
 474         default:
 475                 return -ERANGE;
 476         }
 477
 478         if (priv->adv_ts) {
 479                 switch (config.rx_filter) {
 480                 case HWTSTAMP_FILTER_NONE:
 481                         /* time stamp no incoming packet at all */
 482                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 483                         break;
 484
 485                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 486                         /* PTP v1, UDP, any kind of event packet */
 487                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 488                         /* take time stamp for all event messages */
 489                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 490
 491                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 492                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 493                         break;
 494
 495                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 496                         /* PTP v1, UDP, Sync packet */
 497                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 498                         /* take time stamp for SYNC messages only */
 499                         ts_event_en = PTP_TCR_TSEVNTENA;
 500
 501                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 502                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 503                         break;
 504
 505                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 506                         /* PTP v1, UDP, Delay_req packet */
 507                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 508                         /* take time stamp for Delay_Req messages only */
 509                         ts_master_en = PTP_TCR_TSMSTRENA;
 510                         ts_event_en = PTP_TCR_TSEVNTENA;
 511
 512                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 513                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 514                         break;
 515
 516                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 517                         /* PTP v2, UDP, any kind of event packet */
 518                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 519                         ptp_v2 = PTP_TCR_TSVER2ENA;
 520                         /* take time stamp for all event messages */
 521                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 522
 523                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 524                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 525                         break;
 526
 527                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 528                         /* PTP v2, UDP, Sync packet */
 529                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 530                         ptp_v2 = PTP_TCR_TSVER2ENA;
 531                         /* take time stamp for SYNC messages only */
 532                         ts_event_en = PTP_TCR_TSEVNTENA;
 533
 534                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 535                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 536                         break;
 537
 538                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 539                         /* PTP v2, UDP, Delay_req packet */
 540                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 541                         ptp_v2 = PTP_TCR_TSVER2ENA;
 542                         /* take time stamp for Delay_Req messages only */
 543                         ts_master_en = PTP_TCR_TSMSTRENA;
 544                         ts_event_en = PTP_TCR_TSEVNTENA;
 545
 546                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 547                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 548                         break;
 549
 550                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 551                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 552                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 553                         ptp_v2 = PTP_TCR_TSVER2ENA;
 554                         /* take time stamp for all event messages */
 555                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 556
 557                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 558                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 559                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 560                         break;
 561
 562                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 563                         /* PTP v2/802.AS1, any layer, Sync packet */
 564                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 565                         ptp_v2 = PTP_TCR_TSVER2ENA;
 566                         /* take time stamp for SYNC messages only */
 567                         ts_event_en = PTP_TCR_TSEVNTENA;
 568
 569                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 570                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 571                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 572                         break;
 573
 574                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 575                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 576                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 577                         ptp_v2 = PTP_TCR_TSVER2ENA;
 578                         /* take time stamp for Delay_Req messages only */
 579                         ts_master_en = PTP_TCR_TSMSTRENA;
 580                         ts_event_en = PTP_TCR_TSEVNTENA;
 581
 582                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 583                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 584                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 585                         break;
 586
 587                 case HWTSTAMP_FILTER_ALL:
 588                         /* time stamp any incoming packet */
 589                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 590                         tstamp_all = PTP_TCR_TSENALL;
 591                         break;
 592
 593                 default:
 594                         return -ERANGE;
 595                 }
 596         } else {
 597                 switch (config.rx_filter) {
 598                 case HWTSTAMP_FILTER_NONE:
 599                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 600                         break;
 601                 default:
 602                         /* PTP v1, UDP, any kind of event packet */
 603                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 604                         break;
 605                 }
 606         }
 607         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 608
 609         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 610                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
 611         else {
 612                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 613                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 614                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 615                          ts_master_en | snap_type_sel);
 616
 617                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
 618
 619                 /* program Sub Second Increment reg */
 620                 priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
 621
 622                 /* calculate default added value:
 623                  * formula is :
 624                  * addend = (2^32)/freq_div_ratio;
 625                  * where, freq_div_ratio = STMMAC_SYSCLOCK/50MHz
 626                  * hence, addend = ((2^32) * 50MHz)/STMMAC_SYSCLOCK;
 627                  * NOTE: STMMAC_SYSCLOCK should be >= 50MHz to
 628                  *       achive 20ns accuracy.
 629                  *
 630                  * 2^x * y == (y << x), hence
 631                  * 2^32 * 50000000 ==> (50000000 << 32)
 632                  */
 633                 temp = (u64) (50000000ULL << 32);
 634                 priv->default_addend = div_u64(temp, STMMAC_SYSCLOCK);
 635                 priv->hw->ptp->config_addend(priv->ioaddr,
 636                                              priv->default_addend);
 637
 638                 /* initialize system time */
 639                 getnstimeofday(&now);
 640                 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec,
 641                                             now.tv_nsec);
 642         }
 643
 644         return copy_to_user(ifr->ifr_data, &config,
 645                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
 646 }
 647
 648 /**
 649  * stmmac_init_ptp: init PTP
 650  * @priv: driver private structure
 651  * Description: this is to verify if the HW supports the PTPv1 or v2.
 652  * This is done by looking at the HW cap. register.
 653  * Also it registers the ptp driver.
 654  */
 655 /*
 656 static int stmmac_init_ptp(struct stmmac_priv *priv)
 657 {
 658         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 659                 return -EOPNOTSUPP;
 660
 661         if (netif_msg_hw(priv)) {
 662                 if (priv->dma_cap.time_stamp) {
 663                         pr_debug("IEEE 1588-2002 Time Stamp supported\n");
 664                         priv->adv_ts = 0;
 665                 }
 666                 if (priv->dma_cap.atime_stamp && priv->extend_desc) {
 667                         pr_debug
 668                             ("IEEE 1588-2008 Advanced Time Stamp supported\n");
 669                         priv->adv_ts = 1;
 670                 }
 671         }
 672
 673         priv->hw->ptp = &stmmac_ptp;
 674         priv->hwts_tx_en = 0;
 675         priv->hwts_rx_en = 0;
 676
 677         return stmmac_ptp_register(priv);
 678 }
 679 */
 680 static void stmmac_release_ptp(struct stmmac_priv *priv)
 681 {
 682         stmmac_ptp_unregister(priv);
 683 }
 684
 685 /**
 686  * stmmac_adjust_link
 687  * @dev: net device structure
 688  * Description: it adjusts the link parameters.
 689  */
 690 static void stmmac_adjust_link(struct net_device *dev)
 691 {
 692         struct stmmac_priv *priv = netdev_priv(dev);
 693         struct phy_device *phydev = priv->phydev;
 694         unsigned long flags;
 695         int new_state = 0;
 696         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 697
 698         if (phydev == NULL)
 699                 return;
 700
 701         DBG(probe, DEBUG, "stmmac_adjust_link: called.  address %d link %d\n",
 702             phydev->addr, phydev->link);
 703
 704         spin_lock_irqsave(&priv->lock, flags);
 705
 706         if (phydev->link) {
 707                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 708
 709                 /* Now we make sure that we can be in full duplex mode.
 710                  * If not, we operate in half-duplex mode. */
 711                 if (phydev->duplex != priv->oldduplex) {
 712                         new_state = 1;
 713                         if (!(phydev->duplex))
 714                                 ctrl &= ~priv->hw->link.duplex;
 715                         else
 716                                 ctrl |= priv->hw->link.duplex;
 717                         priv->oldduplex = phydev->duplex;
 718                 }
 719                 /* Flow Control operation */
 720                 if (phydev->pause)
 721                         priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
 722                                                  fc, pause_time);
 723
 724                 if (phydev->speed != priv->speed) {
 725                         new_state = 1;
 726                         switch (phydev->speed) {
 727                         case 1000:
 728                                 if (likely(priv->plat->has_gmac))
 729                                         ctrl &= ~priv->hw->link.port;
 730                                 stmmac_hw_fix_mac_speed(priv);
 731                                 break;
 732                         case 100:
 733                         case 10:
 734                                 if (priv->plat->has_gmac) {
 735                                         ctrl |= priv->hw->link.port;
 736                                         if (phydev->speed == SPEED_100) {
 737                                                 ctrl |= priv->hw->link.speed;
 738                                         } else {
 739                                                 ctrl &= ~(priv->hw->link.speed);
 740                                         }
 741                                 } else {
 742                                         ctrl &= ~priv->hw->link.port;
 743                                 }
 744                                 stmmac_hw_fix_mac_speed(priv);
 745                                 break;
 746                         default:
 747                                 if (netif_msg_link(priv))
 748                                         pr_warn("%s: Speed (%d) not 10/100\n",
 749                                                 dev->name, phydev->speed);
 750                                 break;
 751                         }
 752
 753                         priv->speed = phydev->speed;
 754                 }
 755
 756                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 757
 758                 if (!priv->oldlink) {
 759                         new_state = 1;
 760                         priv->oldlink = 1;
 761                 }
 762         } else if (priv->oldlink) {
 763                 new_state = 1;
 764                 priv->oldlink = 0;
 765                 priv->speed = 0;
 766                 priv->oldduplex = -1;
 767         }
 768
 769         if (new_state && netif_msg_link(priv))
 770                 phy_print_status(phydev);
 771
 772         /* At this stage, it could be needed to setup the EEE or adjust some
 773          * MAC related HW registers.
 774          */
 775         priv->eee_enabled = stmmac_eee_init(priv);
 776
 777         spin_unlock_irqrestore(&priv->lock, flags);
 778
 779         DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
 780 }
 781
 782 /**
 783  * stmmac_check_pcs_mode: verify if RGMII/SGMII is supported
 784  * @priv: driver private structure
 785  * Description: this is to verify if the HW supports the PCS.
 786  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 787  * configured for the TBI, RTBI, or SGMII PHY interface.
 788  */
 789 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 790 {
 791         int interface = priv->plat->interface;
 792
 793         if (priv->dma_cap.pcs) {
 794                 if ((interface & PHY_INTERFACE_MODE_RGMII) ||
 795                     (interface & PHY_INTERFACE_MODE_RGMII_ID) ||
 796                     (interface & PHY_INTERFACE_MODE_RGMII_RXID) ||
 797                     (interface & PHY_INTERFACE_MODE_RGMII_TXID)) {
 798                         pr_debug("STMMAC: PCS RGMII support enable\n");
 799                         priv->pcs = STMMAC_PCS_RGMII;
 800                 } else if (interface & PHY_INTERFACE_MODE_SGMII) {
 801                         pr_debug("STMMAC: PCS SGMII support enable\n");
 802                         priv->pcs = STMMAC_PCS_SGMII;
 803                 }
 804         }
 805 }
 806
 807 static int gPhyReg;
 808
 809 static ssize_t show_phy_reg(struct device *dev,
 810                                 struct device_attribute *attr, char *buf) {
 811         int ret = snprintf(buf, PAGE_SIZE, "current phy reg = 0x%x\n", gPhyReg);
 812         return ret;
 813 }
 814
 815 static ssize_t set_phy_reg(struct device *dev,struct device_attribute *attr,
 816                                 const char *buf, size_t count) {
 817         int ovl;
 818         int r = kstrtoint(buf, 0, &ovl);
 819         if (r) printk("kstrtoint failed\n");
 820         gPhyReg = ovl;
 821         printk("%s----ovl=0x%x\n", __FUNCTION__, ovl);
 822         return count;
 823 }
 824
 825 static ssize_t show_phy_regValue(struct device *dev,
 826                                         struct device_attribute *attr, char *buf) {
 827         struct phy_device *phy_dev = dev_get_drvdata(dev);
 828         int ret = 0;
 829         int val;
 830 #if 0
 831         val = phy_read(phy_dev, gPhyReg);
 832         ret = snprintf(buf, PAGE_SIZE, "phy reg 0x%x = 0x%x\n", gPhyReg, val);
 833 #else
 834         int i=0;
 835
 836         for (i=0; i<32; i++) {
 837                 printk("%d: 0x%x\n", i, phy_read(phy_dev, i));
 838         }
 839
 840         val = phy_read(phy_dev, gPhyReg);
 841         ret = snprintf(buf, PAGE_SIZE, "phy reg 0x%x = 0x%x\n", gPhyReg, val);
 842 #endif
 843         return ret;
 844 }
 845
 846 static ssize_t set_phy_regValue(struct device *dev,
 847                                         struct device_attribute *attr,
 848                                         const char *buf, size_t count) {
 849         int ovl;
 850         int ret;
 851
 852         struct phy_device *phy_dev = dev_get_drvdata(dev);
 853         ret = kstrtoint(buf, 0, &ovl);
 854         printk("%s----reg 0x%x: ovl=0x%x\n", __FUNCTION__, gPhyReg, ovl);
 855         phy_write(phy_dev, gPhyReg, ovl);
 856         return count;
 857 }
 858
 859 static struct device_attribute phy_reg_attrs[] = {
 860         __ATTR(phy_reg, S_IRUGO | S_IWUSR, show_phy_reg, set_phy_reg),
 861         __ATTR(phy_regValue, S_IRUGO | S_IWUSR, show_phy_regValue, set_phy_regValue)
 862 };
 863
 864 int gmac_create_sysfs(struct phy_device * phy_dev) {
 865         int r;
 866         int t;
 867
 868         dev_set_drvdata(&phy_dev->dev, phy_dev);
 869         for (t = 0; t < ARRAY_SIZE(phy_reg_attrs); t++) {
 870                 r = device_create_file(&phy_dev->dev,&phy_reg_attrs[t]);
 871                 if (r) {
 872                         dev_err(&phy_dev->dev, "failed to create sysfs file\n");
 873                         return r;
 874                 }
 875         }
 876
 877         return 0;
 878 }
 879
 880 int gmac_remove_sysfs(struct phy_device * phy_dev) {
 881         int t;
 882
 883         for (t = 0; t < ARRAY_SIZE(phy_reg_attrs); t++) {
 884                 device_remove_file(&phy_dev->dev,&phy_reg_attrs[t]);
 885         }
 886
 887         return 0;
 888 }
 889
 890 /**
 891  * stmmac_init_phy - PHY initialization
 892  * @dev: net device structure
 893  * Description: it initializes the driver's PHY state, and attaches the PHY
 894  * to the mac driver.
 895  *  Return value:
 896  *  0 on success
 897  */
 898 static int stmmac_init_phy(struct net_device *dev)
 899 {
 900         struct stmmac_priv *priv = netdev_priv(dev);
 901         struct phy_device *phydev;
 902         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 903         char bus_id[MII_BUS_ID_SIZE];
 904         int interface = priv->plat->interface;
 905         priv->oldlink = 0;
 906         priv->speed = 0;
 907         priv->oldduplex = -1;
 908
 909         if (priv->plat->phy_bus_name)
 910                 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
 911                          priv->plat->phy_bus_name, priv->plat->bus_id);
 912         else
 913                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
 914                          priv->plat->bus_id);
 915
 916         snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 917                  priv->plat->phy_addr);
 918         pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id_fmt);
 919
 920         phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
 921
 922         if (IS_ERR(phydev)) {
 923                 pr_err("%s: Could not attach to PHY\n", dev->name);
 924                 return PTR_ERR(phydev);
 925         }
 926
 927         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 928         if ((interface == PHY_INTERFACE_MODE_MII) ||
 929             (interface == PHY_INTERFACE_MODE_RMII))
 930                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 931                                          SUPPORTED_1000baseT_Full);
 932
 933         /*
 934          * Broken HW is sometimes missing the pull-up resistor on the
 935          * MDIO line, which results in reads to non-existent devices returning
 936          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 937          * device as well.
 938          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 939          */
 940         if (phydev->phy_id == 0) {
 941                 phy_disconnect(phydev);
 942                 return -ENODEV;
 943         }
 944         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 945                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 946
 947         priv->phydev = phydev;
 948
 949         gmac_create_sysfs(phydev);
 950
 951         return 0;
 952 }
 953
 954 /**
 955  * stmmac_display_ring: display ring
 956  * @head: pointer to the head of the ring passed.
 957  * @size: size of the ring.
 958  * @extend_desc: to verify if extended descriptors are used.
 959  * Description: display the control/status and buffer descriptors.
 960  */
 961 static void stmmac_display_ring(void *head, int size, int extend_desc)
 962 {
 963         int i;
 964         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
 965         struct dma_desc *p = (struct dma_desc *)head;
 966
 967         for (i = 0; i < size; i++) {
 968                 u64 x;
 969                 if (extend_desc) {
 970                         x = *(u64 *) ep;
 971                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
 972                                 i, (unsigned int)virt_to_phys(ep),
 973                                 (unsigned int)x, (unsigned int)(x >> 32),
 974                                 ep->basic.des2, ep->basic.des3);
 975                         ep++;
 976                 } else {
 977                         x = *(u64 *) p;
 978                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
 979                                 i, (unsigned int)virt_to_phys(p),
 980                                 (unsigned int)x, (unsigned int)(x >> 32),
 981                                 p->des2, p->des3);
 982                         p++;
 983                 }
 984                 pr_info("\n");
 985         }
 986 }
 987
 988 static void stmmac_display_rings(struct stmmac_priv *priv)
 989 {
 990         unsigned int txsize = priv->dma_tx_size;
 991         unsigned int rxsize = priv->dma_rx_size;
 992
 993         if (priv->extend_desc) {
 994                 pr_info("Extended RX descriptor ring:\n");
 995                 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
 996                 pr_info("Extended TX descriptor ring:\n");
 997                 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
 998         } else {
 999                 pr_info("RX descriptor ring:\n");
1000                 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
1001                 pr_info("TX descriptor ring:\n");
1002                 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
1003         }
1004 }
1005
1006 static int stmmac_set_bfsize(int mtu, int bufsize)
1007 {
1008         int ret = bufsize;
1009
1010         if (mtu >= BUF_SIZE_4KiB)
1011                 ret = BUF_SIZE_8KiB;
1012         else if (mtu >= BUF_SIZE_2KiB)
1013                 ret = BUF_SIZE_4KiB;
1014         else if (mtu >= DMA_BUFFER_SIZE)
1015                 ret = BUF_SIZE_2KiB;
1016         else
1017                 ret = DMA_BUFFER_SIZE;
1018
1019         return ret;
1020 }
1021
1022 /**
1023  * stmmac_clear_descriptors: clear descriptors
1024  * @priv: driver private structure
1025  * Description: this function is called to clear the tx and rx descriptors
1026  * in case of both basic and extended descriptors are used.
1027  */
1028 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1029 {
1030         int i;
1031         unsigned int txsize = priv->dma_tx_size;
1032         unsigned int rxsize = priv->dma_rx_size;
1033
1034         /* Clear the Rx/Tx descriptors */
1035         for (i = 0; i < rxsize; i++)
1036                 if (priv->extend_desc)
1037                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
1038                                                      priv->use_riwt, priv->mode,
1039                                                      (i == rxsize - 1));
1040                 else
1041                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
1042                                                      priv->use_riwt, priv->mode,
1043                                                      (i == rxsize - 1));
1044         for (i = 0; i < txsize; i++)
1045                 if (priv->extend_desc)
1046                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1047                                                      priv->mode,
1048                                                      (i == txsize - 1));
1049                 else
1050                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1051                                                      priv->mode,
1052                                                      (i == txsize - 1));
1053 }
1054
1055 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1056                                   int i)
1057 {
1058         struct sk_buff *skb;
1059
1060         skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN,
1061                                  GFP_KERNEL);
1062         if (unlikely(skb == NULL)) {
1063                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
1064                 return 1;
1065         }
1066         skb_reserve(skb, NET_IP_ALIGN);
1067         priv->rx_skbuff[i] = skb;
1068         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
1069                                                 priv->dma_buf_sz,
1070                                                 DMA_FROM_DEVICE);
1071
1072         p->des2 = priv->rx_skbuff_dma[i];
1073
1074         if ((priv->mode == STMMAC_RING_MODE) &&
1075             (priv->dma_buf_sz == BUF_SIZE_16KiB))
1076                 priv->hw->ring->init_desc3(p);
1077
1078         return 0;
1079 }
1080
1081 /**
1082  * init_dma_desc_rings - init the RX/TX descriptor rings
1083  * @dev: net device structure
1084  * Description:  this function initializes the DMA RX/TX descriptors
1085  * and allocates the socket buffers. It suppors the chained and ring
1086  * modes.
1087  */
1088 static void init_dma_desc_rings(struct net_device *dev)
1089 {
1090         int i;
1091         struct stmmac_priv *priv = netdev_priv(dev);
1092         unsigned int txsize = priv->dma_tx_size;
1093         unsigned int rxsize = priv->dma_rx_size;
1094         unsigned int bfsize = 0;
1095
1096         /* Set the max buffer size according to the DESC mode
1097          * and the MTU. Note that RING mode allows 16KiB bsize.
1098          */
1099         if (priv->mode == STMMAC_RING_MODE)
1100                 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
1101
1102         if (bfsize < BUF_SIZE_16KiB)
1103                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1104
1105         DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
1106             txsize, rxsize, bfsize);
1107
1108         if (priv->extend_desc) {
1109                 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
1110                                                    sizeof(struct
1111                                                           dma_extended_desc),
1112                                                    &priv->dma_rx_phy,
1113                                                    GFP_KERNEL);
1114                 priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
1115                                                    sizeof(struct
1116                                                           dma_extended_desc),
1117                                                    &priv->dma_tx_phy,
1118                                                    GFP_KERNEL);
1119                 if ((!priv->dma_erx) || (!priv->dma_etx))
1120                         return;
1121         } else {
1122                 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
1123                                                   sizeof(struct dma_desc),
1124                                                   &priv->dma_rx_phy,
1125                                                   GFP_KERNEL);
1126                 priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
1127                                                   sizeof(struct dma_desc),
1128                                                   &priv->dma_tx_phy,
1129                                                   GFP_KERNEL);
1130                 if ((!priv->dma_rx) || (!priv->dma_tx))
1131                         return;
1132
1133                 memset(priv->dma_rx, 0, rxsize * sizeof(struct dma_desc));
1134                 memset(priv->dma_tx, 0, txsize * sizeof(struct dma_desc));
1135         }
1136
1137         priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
1138                                             GFP_KERNEL);
1139         priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
1140                                         GFP_KERNEL);
1141         priv->tx_skbuff_dma = kmalloc_array(txsize, sizeof(dma_addr_t),
1142                                             GFP_KERNEL);
1143         priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
1144                                         GFP_KERNEL);
1145         if (netif_msg_drv(priv))
1146                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1147                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1148
1149         /* RX INITIALIZATION */
1150         DBG(probe, INFO, "stmmac: SKB addresses:\nskb\t\tskb data\tdma data\n");
1151         for (i = 0; i < rxsize; i++) {
1152                 struct dma_desc *p;
1153                 if (priv->extend_desc)
1154                         p = &((priv->dma_erx + i)->basic);
1155                 else
1156                         p = priv->dma_rx + i;
1157
1158                 if (stmmac_init_rx_buffers(priv, p, i))
1159                         break;
1160
1161                 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1162                     priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
1163         }
1164         priv->cur_rx = 0;
1165         priv->dirty_rx = (unsigned int)(i - rxsize);
1166         priv->dma_buf_sz = bfsize;
1167         buf_sz = bfsize;
1168
1169         /* Setup the chained descriptor addresses */
1170         if (priv->mode == STMMAC_CHAIN_MODE) {
1171                 if (priv->extend_desc) {
1172                         priv->hw->chain->init(priv->dma_erx, priv->dma_rx_phy,
1173                                               rxsize, 1);
1174                         priv->hw->chain->init(priv->dma_etx, priv->dma_tx_phy,
1175                                               txsize, 1);
1176                 } else {
1177                         priv->hw->chain->init(priv->dma_rx, priv->dma_rx_phy,
1178                                               rxsize, 0);
1179                         priv->hw->chain->init(priv->dma_tx, priv->dma_tx_phy,
1180                                               txsize, 0);
1181                 }
1182         }
1183
1184         /* TX INITIALIZATION */
1185         for (i = 0; i < txsize; i++) {
1186                 struct dma_desc *p;
1187                 if (priv->extend_desc)
1188                         p = &((priv->dma_etx + i)->basic);
1189                 else
1190                         p = priv->dma_tx + i;
1191                 p->des2 = 0;
1192                 priv->tx_skbuff_dma[i] = 0;
1193                 priv->tx_skbuff[i] = NULL;
1194         }
1195
1196         priv->dirty_tx = 0;
1197         priv->cur_tx = 0;
1198
1199         stmmac_clear_descriptors(priv);
1200
1201         if (netif_msg_hw(priv))
1202                 stmmac_display_rings(priv);
1203 }
1204
1205 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1206 {
1207         int i;
1208
1209         for (i = 0; i < priv->dma_rx_size; i++) {
1210                 if (priv->rx_skbuff[i]) {
1211                         dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1212                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
1213                         dev_kfree_skb_any(priv->rx_skbuff[i]);
1214                 }
1215                 priv->rx_skbuff[i] = NULL;
1216         }
1217 }
1218
1219 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1220 {
1221         int i;
1222
1223         for (i = 0; i < priv->dma_tx_size; i++) {
1224                 if (priv->tx_skbuff[i] != NULL) {
1225                         struct dma_desc *p;
1226                         if (priv->extend_desc)
1227                                 p = &((priv->dma_etx + i)->basic);
1228                         else
1229                                 p = priv->dma_tx + i;
1230
1231                         if (priv->tx_skbuff_dma[i])
1232                                 dma_unmap_single(priv->device,
1233                                                  priv->tx_skbuff_dma[i],
1234                                                  priv->hw->desc->get_tx_len(p),
1235                                                  DMA_TO_DEVICE);
1236                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1237                         priv->tx_skbuff[i] = NULL;
1238                         priv->tx_skbuff_dma[i] = 0;
1239                 }
1240         }
1241 }
1242
1243 static void free_dma_desc_resources(struct stmmac_priv *priv)
1244 {
1245         /* Release the DMA TX/RX socket buffers */
1246         dma_free_rx_skbufs(priv);
1247         dma_free_tx_skbufs(priv);
1248
1249         /* Free DMA regions of consistent memory previously allocated */
1250         if (!priv->extend_desc) {
1251                 dma_free_coherent(priv->device,
1252                                   priv->dma_tx_size * sizeof(struct dma_desc),
1253                                   priv->dma_tx, priv->dma_tx_phy);
1254                 dma_free_coherent(priv->device,
1255                                   priv->dma_rx_size * sizeof(struct dma_desc),
1256                                   priv->dma_rx, priv->dma_rx_phy);
1257         } else {
1258                 dma_free_coherent(priv->device, priv->dma_tx_size *
1259                                   sizeof(struct dma_extended_desc),
1260                                   priv->dma_etx, priv->dma_tx_phy);
1261                 dma_free_coherent(priv->device, priv->dma_rx_size *
1262                                   sizeof(struct dma_extended_desc),
1263                                   priv->dma_erx, priv->dma_rx_phy);
1264         }
1265         kfree(priv->rx_skbuff_dma);
1266         kfree(priv->rx_skbuff);
1267         kfree(priv->tx_skbuff_dma);
1268         kfree(priv->tx_skbuff);
1269 }
1270
1271 /**
1272  *  stmmac_dma_operation_mode - HW DMA operation mode
1273  *  @priv: driver private structure
1274  *  Description: it sets the DMA operation mode: tx/rx DMA thresholds
1275  *  or Store-And-Forward capability.
1276  */
1277 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1278 {
1279         if (likely(priv->plat->force_sf_dma_mode ||
1280                    ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
1281                 /*
1282                  * In case of GMAC, SF mode can be enabled
1283                  * to perform the TX COE in HW. This depends on:
1284                  * 1) TX COE if actually supported
1285                  * 2) There is no bugged Jumbo frame support
1286                  *    that needs to not insert csum in the TDES.
1287                  */
1288                 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE);
1289                 tc = SF_DMA_MODE;
1290         } else
1291                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1292 }
1293
1294 /**
1295  * stmmac_tx_clean:
1296  * @priv: driver private structure
1297  * Description: it reclaims resources after transmission completes.
1298  */
1299 static void stmmac_tx_clean(struct stmmac_priv *priv)
1300 {
1301         unsigned int txsize = priv->dma_tx_size;
1302
1303         spin_lock(&priv->tx_lock);
1304
1305         priv->xstats.tx_clean++;
1306
1307         while (priv->dirty_tx != priv->cur_tx) {
1308                 int last;
1309                 unsigned int entry = priv->dirty_tx % txsize;
1310                 struct sk_buff *skb = priv->tx_skbuff[entry];
1311                 struct dma_desc *p;
1312
1313                 if (priv->extend_desc)
1314                         p = (struct dma_desc *)(priv->dma_etx + entry);
1315                 else
1316                         p = priv->dma_tx + entry;
1317
1318                 /* Check if the descriptor is owned by the DMA. */
1319                 if (priv->hw->desc->get_tx_owner(p))
1320                         break;
1321
1322                 /* Verify tx error by looking at the last segment. */
1323                 last = priv->hw->desc->get_tx_ls(p);
1324                 if (likely(last)) {
1325                         int tx_error =
1326                             priv->hw->desc->tx_status(&priv->dev->stats,
1327                                                       &priv->xstats, p,
1328                                                       priv->ioaddr);
1329                         if (likely(tx_error == 0)) {
1330                                 priv->dev->stats.tx_packets++;
1331                                 priv->xstats.tx_pkt_n++;
1332                         } else
1333                                 priv->dev->stats.tx_errors++;
1334
1335                         stmmac_get_tx_hwtstamp(priv, entry, skb);
1336                 }
1337                 TX_DBG("%s: curr %d, dirty %d\n", __func__,
1338                        priv->cur_tx, priv->dirty_tx);
1339
1340                 if (likely(priv->tx_skbuff_dma[entry])) {
1341                         dma_unmap_single(priv->device,
1342                                          priv->tx_skbuff_dma[entry],
1343                                          priv->hw->desc->get_tx_len(p),
1344                                          DMA_TO_DEVICE);
1345                         priv->tx_skbuff_dma[entry] = 0;
1346                 }
1347                 priv->hw->ring->clean_desc3(priv, p);
1348
1349                 if (likely(skb != NULL)) {
1350                         dev_kfree_skb(skb);
1351                         priv->tx_skbuff[entry] = NULL;
1352                 }
1353
1354                 priv->hw->desc->release_tx_desc(p, priv->mode);
1355
1356                 priv->dirty_tx++;
1357         }
1358         if (unlikely(netif_queue_stopped(priv->dev) &&
1359                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1360                 netif_tx_lock(priv->dev);
1361                 if (netif_queue_stopped(priv->dev) &&
1362                     stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
1363                         TX_DBG("%s: restart transmit\n", __func__);
1364                         netif_wake_queue(priv->dev);
1365                 }
1366                 netif_tx_unlock(priv->dev);
1367         }
1368
1369         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1370                 stmmac_enable_eee_mode(priv);
1371                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1372         }
1373         spin_unlock(&priv->tx_lock);
1374 }
1375
1376 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1377 {
1378         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1379 }
1380
1381 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1382 {
1383         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1384 }
1385
1386 /**
1387  * stmmac_tx_err: irq tx error mng function
1388  * @priv: driver private structure
1389  * Description: it cleans the descriptors and restarts the transmission
1390  * in case of errors.
1391  */
1392 static void stmmac_tx_err(struct stmmac_priv *priv)
1393 {
1394         int i;
1395         int txsize = priv->dma_tx_size;
1396         netif_stop_queue(priv->dev);
1397
1398         priv->hw->dma->stop_tx(priv->ioaddr);
1399         dma_free_tx_skbufs(priv);
1400         for (i = 0; i < txsize; i++)
1401                 if (priv->extend_desc)
1402                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1403                                                      priv->mode,
1404                                                      (i == txsize - 1));
1405                 else
1406                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1407                                                      priv->mode,
1408                                                      (i == txsize - 1));
1409         priv->dirty_tx = 0;
1410         priv->cur_tx = 0;
1411         priv->hw->dma->start_tx(priv->ioaddr);
1412
1413         priv->dev->stats.tx_errors++;
1414         netif_wake_queue(priv->dev);
1415 }
1416
1417 /**
1418  * stmmac_dma_interrupt: DMA ISR
1419  * @priv: driver private structure
1420  * Description: this is the DMA ISR. It is called by the main ISR.
1421  * It calls the dwmac dma routine to understand which type of interrupt
1422  * happened. In case of there is a Normal interrupt and either TX or RX
1423  * interrupt happened so the NAPI is scheduled.
1424  */
1425 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1426 {
1427         int status;
1428
1429         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1430         if (likely((status & handle_rx)) || (status & handle_tx)) {
1431                 if (likely(napi_schedule_prep(&priv->napi))) {
1432                         stmmac_disable_dma_irq(priv);
1433                         __napi_schedule(&priv->napi);
1434                 }
1435         }
1436         if (unlikely(status & tx_hard_error_bump_tc)) {
1437                 /* Try to bump up the dma threshold on this failure */
1438                 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
1439                         tc += 64;
1440                         priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1441                         priv->xstats.threshold = tc;
1442                 }
1443         } else if (unlikely(status == tx_hard_error))
1444                 stmmac_tx_err(priv);
1445 }
1446
1447 /**
1448  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1449  * @priv: driver private structure
1450  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1451  */
1452 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1453 {
1454         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1455             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1456
1457         dwmac_mmc_intr_all_mask(priv->ioaddr);
1458
1459         if (priv->dma_cap.rmon) {
1460                 dwmac_mmc_ctrl(priv->ioaddr, mode);
1461                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1462         } else
1463                 pr_info(" No MAC Management Counters available\n");
1464 }
1465
1466 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1467 {
1468         u32 hwid = priv->hw->synopsys_uid;
1469
1470         /* Check Synopsys Id (not available on old chips) */
1471         if (likely(hwid)) {
1472                 u32 uid = ((hwid & 0x0000ff00) >> 8);
1473                 u32 synid = (hwid & 0x000000ff);
1474
1475                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1476                         uid, synid);
1477
1478                 return synid;
1479         }
1480         return 0;
1481 }
1482
1483 /**
1484  * stmmac_selec_desc_mode: to select among: normal/alternate/extend descriptors
1485  * @priv: driver private structure
1486  * Description: select the Enhanced/Alternate or Normal descriptors.
1487  * In case of Enhanced/Alternate, it looks at the extended descriptors are
1488  * supported by the HW cap. register.
1489  */
1490 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1491 {
1492         if (priv->plat->enh_desc) {
1493                 pr_info(" Enhanced/Alternate descriptors\n");
1494
1495                 /* GMAC older than 3.50 has no extended descriptors */
1496                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1497                         pr_info("\tEnabled extended descriptors\n");
1498                         priv->extend_desc = 1;
1499                 } else
1500                         pr_warn("Extended descriptors not supported\n");
1501
1502                 priv->hw->desc = &enh_desc_ops;
1503         } else {
1504                 pr_info(" Normal descriptors\n");
1505                 priv->hw->desc = &ndesc_ops;
1506         }
1507 }
1508
1509 /**
1510  * stmmac_get_hw_features: get MAC capabilities from the HW cap. register.
1511  * @priv: driver private structure
1512  * Description:
1513  *  new GMAC chip generations have a new register to indicate the
1514  *  presence of the optional feature/functions.
1515  *  This can be also used to override the value passed through the
1516  *  platform and necessary for old MAC10/100 and GMAC chips.
1517  */
1518 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1519 {
1520         u32 hw_cap = 0;
1521
1522         if (priv->hw->dma->get_hw_feature) {
1523                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1524
1525                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1526                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1527                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1528                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1529                 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1530                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1531                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1532                 priv->dma_cap.pmt_remote_wake_up =
1533                     (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1534                 priv->dma_cap.pmt_magic_frame =
1535                     (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1536                 /* MMC */
1537                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1538                 /* IEEE 1588-2002 */
1539                 priv->dma_cap.time_stamp =
1540                     (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1541                 /* IEEE 1588-2008 */
1542                 priv->dma_cap.atime_stamp =
1543                     (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1544                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1545                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1546                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1547                 /* TX and RX csum */
1548                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1549                 priv->dma_cap.rx_coe_type1 =
1550                     (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1551                 priv->dma_cap.rx_coe_type2 =
1552                     (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1553                 priv->dma_cap.rxfifo_over_2048 =
1554                     (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1555                 /* TX and RX number of channels */
1556                 priv->dma_cap.number_rx_channel =
1557                     (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1558                 priv->dma_cap.number_tx_channel =
1559                     (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1560                 /* Alternate (enhanced) DESC mode */
1561                 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1562         }
1563
1564         return hw_cap;
1565 }
1566
1567 /**
1568  * stmmac_check_ether_addr: check if the MAC addr is valid
1569  * @priv: driver private structure
1570  * Description:
1571  * it is to verify if the MAC address is valid, in case of failures it
1572  * generates a random MAC address
1573  */
1574 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1575 {
1576         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1577                 priv->hw->mac->get_umac_addr((void __iomem *)
1578                                              priv->dev->base_addr,
1579                                              priv->dev->dev_addr, 0);
1580                 if (!is_valid_ether_addr(priv->dev->dev_addr))
1581                         eth_mac_idb(priv->dev->dev_addr);
1582                 if (!is_valid_ether_addr(priv->dev->dev_addr))
1583                         eth_hw_addr_random(priv->dev);
1584         }
1585         pr_warn("%s: device MAC address %pM\n", priv->dev->name,
1586                 priv->dev->dev_addr);
1587 }
1588
1589 /**
1590  * stmmac_init_dma_engine: DMA init.
1591  * @priv: driver private structure
1592  * Description:
1593  * It inits the DMA invoking the specific MAC/GMAC callback.
1594  * Some DMA parameters can be passed from the platform;
1595  * in case of these are not passed a default is kept for the MAC or GMAC.
1596  */
1597 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1598 {
1599         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1600         int mixed_burst = 0;
1601         int atds = 0;
1602
1603         if (priv->plat->dma_cfg) {
1604                 pbl = priv->plat->dma_cfg->pbl;
1605                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1606                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1607                 burst_len = priv->plat->dma_cfg->burst_len;
1608         }
1609
1610         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1611                 atds = 1;
1612
1613         return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1614                                    burst_len, priv->dma_tx_phy,
1615                                    priv->dma_rx_phy, atds);
1616 }
1617
1618 /**
1619  * stmmac_tx_timer: mitigation sw timer for tx.
1620  * @data: data pointer
1621  * Description:
1622  * This is the timer handler to directly invoke the stmmac_tx_clean.
1623  */
1624 static void stmmac_tx_timer(unsigned long data)
1625 {
1626         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1627
1628         stmmac_tx_clean(priv);
1629 }
1630
1631 /**
1632  * stmmac_init_tx_coalesce: init tx mitigation options.
1633  * @priv: driver private structure
1634  * Description:
1635  * This inits the transmit coalesce parameters: i.e. timer rate,
1636  * timer handler and default threshold used for enabling the
1637  * interrupt on completion bit.
1638  */
1639 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1640 {
1641         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1642         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1643         init_timer(&priv->txtimer);
1644         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1645         priv->txtimer.data = (unsigned long)priv;
1646         priv->txtimer.function = stmmac_tx_timer;
1647         add_timer(&priv->txtimer);
1648 }
1649
1650 /**
1651  *  stmmac_open - open entry point of the driver
1652  *  @dev : pointer to the device structure.
1653  *  Description:
1654  *  This function is the open entry point of the driver.
1655  *  Return value:
1656  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1657  *  file on failure.
1658  */
1659 static int stmmac_open(struct net_device *dev)
1660 {
1661         struct stmmac_priv *priv = netdev_priv(dev);
1662         int ret;
1663
1664         if ((priv->plat) && (priv->plat->bsp_priv)) {
1665                 struct bsp_priv * bsp_priv = priv->plat->bsp_priv;
1666                 if (bsp_priv) {
1667                         if (bsp_priv->phy_power_on) {
1668                                 bsp_priv->phy_power_on(true);
1669                         }
1670                         if (bsp_priv->gmac_clk_enable) {
1671                                 bsp_priv->gmac_clk_enable(true);
1672                         }
1673                 }
1674         }
1675
1676         stmmac_check_ether_addr(priv);
1677
1678
1679         if (priv->pcs != STMMAC_PCS_SGMII && priv->pcs != STMMAC_PCS_TBI &&
1680             priv->pcs != STMMAC_PCS_RTBI) {
1681                 if(!priv->mdio_registered) {
1682                         /* MDIO bus Registration */
1683                         ret = stmmac_mdio_register(priv->dev);
1684                         if (ret < 0) {
1685                                 pr_debug("%s: MDIO bus (id: %d) registration failed",
1686                                         __func__, priv->plat->bus_id);
1687                                 goto open_error;
1688                         }
1689                         priv->mdio_registered = true;
1690                 }
1691                 ret = stmmac_init_phy(dev);
1692                 if (ret) {
1693                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1694                                __func__, ret);
1695                         goto open_error;
1696                 }
1697         }
1698
1699         /* Create and initialize the TX/RX descriptors chains. */
1700         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1701         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1702         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1703         init_dma_desc_rings(dev);
1704
1705         /* DMA initialization and SW reset */
1706         ret = stmmac_init_dma_engine(priv);
1707         if (ret < 0) {
1708                 pr_err("%s: DMA initialization failed\n", __func__);
1709                 goto open_error;
1710         }
1711
1712         /* Copy the MAC addr into the HW  */
1713         priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1714
1715         /* If required, perform hw setup of the bus. */
1716         if (priv->plat->bus_setup)
1717                 priv->plat->bus_setup(priv->ioaddr);
1718
1719         /* Initialize the MAC Core */
1720         priv->hw->mac->core_init(priv->ioaddr);
1721
1722         /* Request the IRQ lines */
1723         ret = request_irq(dev->irq, stmmac_interrupt,
1724                           IRQF_SHARED, dev->name, dev);
1725         if (unlikely(ret < 0)) {
1726                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1727                        __func__, dev->irq, ret);
1728                 goto open_error;
1729         }
1730
1731         /* Request the Wake IRQ in case of another line is used for WoL */
1732         if (priv->wol_irq != dev->irq) {
1733                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1734                                   IRQF_SHARED, dev->name, dev);
1735                 if (unlikely(ret < 0)) {
1736                         pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1737                                __func__, priv->wol_irq, ret);
1738                         goto open_error_wolirq;
1739                 }
1740         }
1741
1742         /* Request the IRQ lines */
1743         if (priv->lpi_irq != -ENXIO) {
1744                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1745                                   dev->name, dev);
1746                 if (unlikely(ret < 0)) {
1747                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1748                                __func__, priv->lpi_irq, ret);
1749                         goto open_error_lpiirq;
1750                 }
1751         }
1752
1753         /* Enable the MAC Rx/Tx */
1754         stmmac_set_mac(priv->ioaddr, true);
1755
1756         /* Set the HW DMA mode and the COE */
1757         stmmac_dma_operation_mode(priv);
1758
1759         /* Extra statistics */
1760         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1761         priv->xstats.threshold = tc;
1762
1763         stmmac_mmc_setup(priv);
1764 /*
1765         ret = stmmac_init_ptp(priv);
1766         if (ret)
1767                 pr_warn("%s: failed PTP initialisation\n", __func__);
1768 */
1769 #ifdef CONFIG_GMAC_DEBUG_FS
1770         ret = stmmac_init_fs(dev);
1771         if (ret < 0)
1772                 pr_warn("%s: failed debugFS registration\n", __func__);
1773 #endif
1774         /* Start the ball rolling... */
1775         DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
1776         priv->hw->dma->start_tx(priv->ioaddr);
1777         priv->hw->dma->start_rx(priv->ioaddr);
1778
1779         /* Dump DMA/MAC registers */
1780         if (netif_msg_hw(priv)) {
1781                 priv->hw->mac->dump_regs(priv->ioaddr);
1782                 priv->hw->dma->dump_regs(priv->ioaddr);
1783         }
1784
1785         if (priv->phydev)
1786                 phy_start(priv->phydev);
1787
1788         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1789
1790         priv->eee_enabled = stmmac_eee_init(priv);
1791
1792         stmmac_init_tx_coalesce(priv);
1793
1794         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1795                 priv->rx_riwt = MAX_DMA_RIWT;
1796                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1797         }
1798
1799         if (priv->pcs && priv->hw->mac->ctrl_ane)
1800                 priv->hw->mac->ctrl_ane(priv->ioaddr, 0);
1801
1802         napi_enable(&priv->napi);
1803         netif_start_queue(dev);
1804
1805         return 0;
1806
1807 open_error_lpiirq:
1808         if (priv->wol_irq != dev->irq)
1809                 free_irq(priv->wol_irq, dev);
1810
1811 open_error_wolirq:
1812         free_irq(dev->irq, dev);
1813
1814 open_error:
1815         if (priv->phydev)
1816                 phy_disconnect(priv->phydev);
1817
1818         if ((priv->plat) && (priv->plat->bsp_priv)) {
1819                 struct bsp_priv * bsp_priv = priv->plat->bsp_priv;
1820                 if ((bsp_priv) && (bsp_priv->gmac_clk_enable)) {
1821                         bsp_priv->gmac_clk_enable(false);
1822                 }
1823         }
1824
1825         return ret;
1826 }
1827
1828 /**
1829  *  stmmac_release - close entry point of the driver
1830  *  @dev : device pointer.
1831  *  Description:
1832  *  This is the stop entry point of the driver.
1833  */
1834 static int stmmac_release(struct net_device *dev)
1835 {
1836         struct stmmac_priv *priv = netdev_priv(dev);
1837
1838         if (priv->eee_enabled)
1839                 del_timer_sync(&priv->eee_ctrl_timer);
1840
1841         /* Stop and disconnect the PHY */
1842         if (priv->phydev) {
1843
1844                 gmac_remove_sysfs(priv->phydev);
1845
1846                 phy_stop(priv->phydev);
1847                 phy_disconnect(priv->phydev);
1848                 priv->phydev = NULL;
1849         }
1850
1851         netif_stop_queue(dev);
1852
1853         napi_disable(&priv->napi);
1854
1855         del_timer_sync(&priv->txtimer);
1856
1857         /* Free the IRQ lines */
1858         free_irq(dev->irq, dev);
1859         if (priv->wol_irq != dev->irq)
1860                 free_irq(priv->wol_irq, dev);
1861         if (priv->lpi_irq != -ENXIO)
1862                 free_irq(priv->lpi_irq, dev);
1863
1864         /* Stop TX/RX DMA and clear the descriptors */
1865         priv->hw->dma->stop_tx(priv->ioaddr);
1866         priv->hw->dma->stop_rx(priv->ioaddr);
1867
1868         /* Release and free the Rx/Tx resources */
1869         free_dma_desc_resources(priv);
1870
1871         /* Disable the MAC Rx/Tx */
1872         stmmac_set_mac(priv->ioaddr, false);
1873
1874         netif_carrier_off(dev);
1875
1876 #ifdef CONFIG_GMAC_DEBUG_FS
1877         stmmac_exit_fs();
1878 #endif
1879
1880         stmmac_release_ptp(priv);
1881
1882         if ((priv->plat) && (priv->plat->bsp_priv)) {
1883                 struct bsp_priv * bsp_priv = priv->plat->bsp_priv;
1884                 if (bsp_priv) {
1885                         if (bsp_priv->phy_power_on) {
1886                                 bsp_priv->phy_power_on(false);
1887                         }
1888                         if (bsp_priv->gmac_clk_enable) {
1889                                 bsp_priv->gmac_clk_enable(false);
1890                         }
1891                 }
1892         }
1893
1894         return 0;
1895 }
1896
1897 /**
1898  *  stmmac_xmit: Tx entry point of the driver
1899  *  @skb : the socket buffer
1900  *  @dev : device pointer
1901  *  Description : this is the tx entry point of the driver.
1902  *  It programs the chain or the ring and supports oversized frames
1903  *  and SG feature.
1904  */
1905 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1906 {
1907         struct stmmac_priv *priv = netdev_priv(dev);
1908         unsigned int txsize = priv->dma_tx_size;
1909         unsigned int entry;
1910         int i, csum_insertion = 0, is_jumbo = 0;
1911         int nfrags = skb_shinfo(skb)->nr_frags;
1912         struct dma_desc *desc, *first;
1913         unsigned int nopaged_len = skb_headlen(skb);
1914
1915         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1916                 if (!netif_queue_stopped(dev)) {
1917                         netif_stop_queue(dev);
1918                         /* This is a hard error, log it. */
1919                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
1920                 }
1921                 return NETDEV_TX_BUSY;
1922         }
1923
1924         spin_lock(&priv->tx_lock);
1925
1926         if (priv->tx_path_in_lpi_mode)
1927                 stmmac_disable_eee_mode(priv);
1928
1929         entry = priv->cur_tx % txsize;
1930
1931 #ifdef STMMAC_XMIT_DEBUG
1932         if ((skb->len > ETH_FRAME_LEN) || nfrags)
1933                 pr_debug("%s: [entry %d]: skb addr %p len: %d nopagedlen: %d\n"
1934                          "\tn_frags: %d - ip_summed: %d - %s gso\n"
1935                          "\ttx_count_frames %d\n", __func__, entry,
1936                          skb, skb->len, nopaged_len, nfrags, skb->ip_summed,
1937                          !skb_is_gso(skb) ? "isn't" : "is",
1938                          priv->tx_count_frames);
1939 #endif
1940
1941         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1942
1943         if (priv->extend_desc)
1944                 desc = (struct dma_desc *)(priv->dma_etx + entry);
1945         else
1946                 desc = priv->dma_tx + entry;
1947
1948         first = desc;
1949
1950 #ifdef STMMAC_XMIT_DEBUG
1951         if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1952                 pr_debug("\tskb len: %d, nopaged_len: %d,\n"
1953                          "\t\tn_frags: %d, ip_summed: %d\n",
1954                          skb->len, nopaged_len, nfrags, skb->ip_summed);
1955 #endif
1956         priv->tx_skbuff[entry] = skb;
1957
1958         /* To program the descriptors according to the size of the frame */
1959         if (priv->mode == STMMAC_RING_MODE) {
1960                 is_jumbo = priv->hw->ring->is_jumbo_frm(skb->len,
1961                                                         priv->plat->enh_desc);
1962                 if (unlikely(is_jumbo))
1963                         entry = priv->hw->ring->jumbo_frm(priv, skb,
1964                                                           csum_insertion);
1965         } else {
1966                 is_jumbo = priv->hw->chain->is_jumbo_frm(skb->len,
1967                                                          priv->plat->enh_desc);
1968                 if (unlikely(is_jumbo))
1969                         entry = priv->hw->chain->jumbo_frm(priv, skb,
1970                                                            csum_insertion);
1971         }
1972         if (likely(!is_jumbo)) {
1973                 desc->des2 = dma_map_single(priv->device, skb->data,
1974                                             nopaged_len, DMA_TO_DEVICE);
1975                 priv->tx_skbuff_dma[entry] = desc->des2;
1976                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1977                                                 csum_insertion, priv->mode);
1978         } else
1979                 desc = first;
1980
1981         for (i = 0; i < nfrags; i++) {
1982                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1983                 int len = skb_frag_size(frag);
1984
1985                 entry = (++priv->cur_tx) % txsize;
1986                 if (priv->extend_desc)
1987                         desc = (struct dma_desc *)(priv->dma_etx + entry);
1988                 else
1989                         desc = priv->dma_tx + entry;
1990
1991                 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1992                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1993                                               DMA_TO_DEVICE);
1994                 priv->tx_skbuff_dma[entry] = desc->des2;
1995                 priv->tx_skbuff[entry] = NULL;
1996                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
1997                                                 priv->mode);
1998                 wmb();
1999                 priv->hw->desc->set_tx_owner(desc);
2000                 wmb();
2001         }
2002
2003         /* Finalize the latest segment. */
2004         priv->hw->desc->close_tx_desc(desc);
2005
2006         wmb();
2007         /* According to the coalesce parameter the IC bit for the latest
2008          * segment could be reset and the timer re-started to invoke the
2009          * stmmac_tx function. This approach takes care about the fragments.
2010          */
2011         priv->tx_count_frames += nfrags + 1;
2012         if (priv->tx_coal_frames > priv->tx_count_frames) {
2013                 priv->hw->desc->clear_tx_ic(desc);
2014                 priv->xstats.tx_reset_ic_bit++;
2015                 TX_DBG("\t[entry %d]: tx_count_frames %d\n", entry,
2016                        priv->tx_count_frames);
2017                 mod_timer(&priv->txtimer,
2018                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
2019         } else
2020                 priv->tx_count_frames = 0;
2021
2022         /* To avoid raise condition */
2023         priv->hw->desc->set_tx_owner(first);
2024         wmb();
2025
2026         priv->cur_tx++;
2027
2028 #ifdef STMMAC_XMIT_DEBUG
2029         if (netif_msg_pktdata(priv)) {
2030                 pr_info("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
2031                         __func__, (priv->cur_tx % txsize),
2032                         (priv->dirty_tx % txsize), entry, first, nfrags);
2033                 if (priv->extend_desc)
2034                         stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
2035                 else
2036                         stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
2037
2038                 pr_info(">>> frame to be transmitted: ");
2039                 print_pkt(skb->data, skb->len);
2040         }
2041 #endif
2042         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2043                 TX_DBG("%s: stop transmitted packets\n", __func__);
2044                 netif_stop_queue(dev);
2045         }
2046
2047         dev->stats.tx_bytes += skb->len;
2048
2049         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2050                      priv->hwts_tx_en)) {
2051                 /* declare that device is doing timestamping */
2052                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2053                 priv->hw->desc->enable_tx_timestamp(first);
2054         }
2055
2056         if (!priv->hwts_tx_en)
2057                 skb_tx_timestamp(skb);
2058
2059         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2060
2061         spin_unlock(&priv->tx_lock);
2062
2063         return NETDEV_TX_OK;
2064 }
2065
2066 /**
2067  * stmmac_rx_refill: refill used skb preallocated buffers
2068  * @priv: driver private structure
2069  * Description : this is to reallocate the skb for the reception process
2070  * that is based on zero-copy.
2071  */
2072 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2073 {
2074         unsigned int rxsize = priv->dma_rx_size;
2075         int bfsize = priv->dma_buf_sz;
2076
2077         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
2078                 unsigned int entry = priv->dirty_rx % rxsize;
2079                 struct dma_desc *p;
2080
2081                 if (priv->extend_desc)
2082                         p = (struct dma_desc *)(priv->dma_erx + entry);
2083                 else
2084                         p = priv->dma_rx + entry;
2085
2086                 if (likely(priv->rx_skbuff[entry] == NULL)) {
2087                         struct sk_buff *skb;
2088
2089                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2090
2091                         if (unlikely(skb == NULL))
2092                                 break;
2093
2094                         priv->rx_skbuff[entry] = skb;
2095                         priv->rx_skbuff_dma[entry] =
2096                             dma_map_single(priv->device, skb->data, bfsize,
2097                                            DMA_FROM_DEVICE);
2098
2099                         p->des2 = priv->rx_skbuff_dma[entry];
2100
2101                         priv->hw->ring->refill_desc3(priv, p);
2102
2103                         RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
2104                 }
2105                 wmb();
2106                 priv->hw->desc->set_rx_owner(p);
2107                 wmb();
2108         }
2109 }
2110
2111 /**
2112  * stmmac_rx_refill: refill used skb preallocated buffers
2113  * @priv: driver private structure
2114  * @limit: napi bugget.
2115  * Description :  this the function called by the napi poll method.
2116  * It gets all the frames inside the ring.
2117  */
2118 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2119 {
2120         unsigned int rxsize = priv->dma_rx_size;
2121         unsigned int entry = priv->cur_rx % rxsize;
2122         unsigned int next_entry;
2123         unsigned int count = 0;
2124         int coe = priv->plat->rx_coe;
2125
2126 #ifdef STMMAC_RX_DEBUG
2127         if (netif_msg_hw(priv)) {
2128                 pr_debug(">>> stmmac_rx: descriptor ring:\n");
2129                 if (priv->extend_desc)
2130                         stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
2131                 else
2132                         stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
2133         }
2134 #endif
2135         while (count < limit) {
2136                 int status;
2137                 struct dma_desc *p;
2138
2139                 if (priv->extend_desc)
2140                         p = (struct dma_desc *)(priv->dma_erx + entry);
2141                 else
2142                         p = priv->dma_rx + entry;
2143
2144                 if (priv->hw->desc->get_rx_owner(p))
2145                         break;
2146
2147                 count++;
2148
2149                 next_entry = (++priv->cur_rx) % rxsize;
2150                 if (priv->extend_desc)
2151                         prefetch(priv->dma_erx + next_entry);
2152                 else
2153                         prefetch(priv->dma_rx + next_entry);
2154
2155                 /* read the status of the incoming frame */
2156                 status = priv->hw->desc->rx_status(&priv->dev->stats,
2157                                                    &priv->xstats, p);
2158                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2159                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
2160                                                            &priv->xstats,
2161                                                            priv->dma_erx +
2162                                                            entry);
2163                 if (unlikely(status == discard_frame)) {
2164                         priv->dev->stats.rx_errors++;
2165                         if (priv->hwts_rx_en && !priv->extend_desc) {
2166                                 /* DESC2 & DESC3 will be overwitten by device
2167                                  * with timestamp value, hence reinitialize
2168                                  * them in stmmac_rx_refill() function so that
2169                                  * device can reuse it.
2170                                  */
2171                                 priv->rx_skbuff[entry] = NULL;
2172                                 dma_unmap_single(priv->device,
2173                                                  priv->rx_skbuff_dma[entry],
2174                                                  priv->dma_buf_sz,
2175                                                  DMA_FROM_DEVICE);
2176                         }
2177                 } else {
2178                         struct sk_buff *skb;
2179                         int frame_len;
2180
2181                         frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2182
2183                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2184                          * Type frames (LLC/LLC-SNAP)
2185                          */
2186                         if (unlikely(status != llc_snap))
2187                                 frame_len -= ETH_FCS_LEN;
2188 #ifdef STMMAC_RX_DEBUG
2189                         if (frame_len > ETH_FRAME_LEN)
2190                                 pr_debug("\tRX frame size %d, COE status: %d\n",
2191                                          frame_len, status);
2192
2193                         if (netif_msg_hw(priv))
2194                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2195                                          p, entry, p->des2);
2196 #endif
2197                         skb = priv->rx_skbuff[entry];
2198                         if (unlikely(!skb)) {
2199                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
2200                                        priv->dev->name);
2201                                 priv->dev->stats.rx_dropped++;
2202                                 break;
2203                         }
2204                         prefetch(skb->data - NET_IP_ALIGN);
2205                         priv->rx_skbuff[entry] = NULL;
2206
2207                         stmmac_get_rx_hwtstamp(priv, entry, skb);
2208
2209                         skb_put(skb, frame_len);
2210                         dma_unmap_single(priv->device,
2211                                          priv->rx_skbuff_dma[entry],
2212                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
2213 #ifdef STMMAC_RX_DEBUG
2214                         if (netif_msg_pktdata(priv)) {
2215                                 pr_info(" frame received (%dbytes)", frame_len);
2216                                 print_pkt(skb->data, frame_len);
2217                         }
2218 #endif
2219                         skb->protocol = eth_type_trans(skb, priv->dev);
2220
2221                         if (unlikely(!coe))
2222                                 skb_checksum_none_assert(skb);
2223                         else
2224                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2225
2226                         napi_gro_receive(&priv->napi, skb);
2227
2228                         priv->dev->stats.rx_packets++;
2229                         priv->dev->stats.rx_bytes += frame_len;
2230                 }
2231                 entry = next_entry;
2232         }
2233
2234         stmmac_rx_refill(priv);
2235
2236         priv->xstats.rx_pkt_n += count;
2237
2238         return count;
2239 }
2240
2241 /**
2242  *  stmmac_poll - stmmac poll method (NAPI)
2243  *  @napi : pointer to the napi structure.
2244  *  @budget : maximum number of packets that the current CPU can receive from
2245  *            all interfaces.
2246  *  Description :
2247  *  To look at the incoming frames and clear the tx resources.
2248  */
2249 static int stmmac_poll(struct napi_struct *napi, int budget)
2250 {
2251         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2252         int work_done = 0;
2253
2254         priv->xstats.napi_poll++;
2255         stmmac_tx_clean(priv);
2256
2257         work_done = stmmac_rx(priv, budget);
2258         if (work_done < budget) {
2259                 napi_complete(napi);
2260                 stmmac_enable_dma_irq(priv);
2261         }
2262         return work_done;
2263 }
2264
2265 /**
2266  *  stmmac_tx_timeout
2267  *  @dev : Pointer to net device structure
2268  *  Description: this function is called when a packet transmission fails to
2269  *   complete within a reasonable time. The driver will mark the error in the
2270  *   netdev structure and arrange for the device to be reset to a sane state
2271  *   in order to transmit a new packet.
2272  */
2273 static void stmmac_tx_timeout(struct net_device *dev)
2274 {
2275         struct stmmac_priv *priv = netdev_priv(dev);
2276
2277         /* Clear Tx resources and restart transmitting again */
2278         stmmac_tx_err(priv);
2279 }
2280
2281 /* Configuration changes (passed on by ifconfig) */
2282 static int stmmac_config(struct net_device *dev, struct ifmap *map)
2283 {
2284         if (dev->flags & IFF_UP)        /* can't act on a running interface */
2285                 return -EBUSY;
2286
2287         /* Don't allow changing the I/O address */
2288         if (map->base_addr != dev->base_addr) {
2289                 pr_warn("%s: can't change I/O address\n", dev->name);
2290                 return -EOPNOTSUPP;
2291         }
2292
2293         /* Don't allow changing the IRQ */
2294         if (map->irq != dev->irq) {
2295                 pr_warn("%s: not change IRQ number %d\n", dev->name, dev->irq);
2296                 return -EOPNOTSUPP;
2297         }
2298
2299         return 0;
2300 }
2301
2302 /**
2303  *  stmmac_set_rx_mode - entry point for multicast addressing
2304  *  @dev : pointer to the device structure
2305  *  Description:
2306  *  This function is a driver entry point which gets called by the kernel
2307  *  whenever multicast addresses must be enabled/disabled.
2308  *  Return value:
2309  *  void.
2310  */
2311 static void stmmac_set_rx_mode(struct net_device *dev)
2312 {
2313         struct stmmac_priv *priv = netdev_priv(dev);
2314
2315         spin_lock(&priv->lock);
2316         priv->hw->mac->set_filter(dev, priv->synopsys_id);
2317         spin_unlock(&priv->lock);
2318 }
2319
2320 /**
2321  *  stmmac_change_mtu - entry point to change MTU size for the device.
2322  *  @dev : device pointer.
2323  *  @new_mtu : the new MTU size for the device.
2324  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2325  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2326  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2327  *  Return value:
2328  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2329  *  file on failure.
2330  */
2331 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2332 {
2333         struct stmmac_priv *priv = netdev_priv(dev);
2334         int max_mtu;
2335
2336         if (netif_running(dev)) {
2337                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2338                 return -EBUSY;
2339         }
2340
2341         if (priv->plat->enh_desc)
2342                 max_mtu = JUMBO_LEN;
2343         else
2344                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2345
2346         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2347                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2348                 return -EINVAL;
2349         }
2350
2351         dev->mtu = new_mtu;
2352         netdev_update_features(dev);
2353
2354         return 0;
2355 }
2356
2357 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2358                                              netdev_features_t features)
2359 {
2360         struct stmmac_priv *priv = netdev_priv(dev);
2361
2362         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2363                 features &= ~NETIF_F_RXCSUM;
2364         else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1)
2365                 features &= ~NETIF_F_IPV6_CSUM;
2366         if (!priv->plat->tx_coe)
2367                 features &= ~NETIF_F_ALL_CSUM;
2368
2369         /* Some GMAC devices have a bugged Jumbo frame support that
2370          * needs to have the Tx COE disabled for oversized frames
2371          * (due to limited buffer sizes). In this case we disable
2372          * the TX csum insertionin the TDES and not use SF.
2373          */
2374         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2375                 features &= ~NETIF_F_ALL_CSUM;
2376
2377         return features;
2378 }
2379
2380 /**
2381  *  stmmac_interrupt - main ISR
2382  *  @irq: interrupt number.
2383  *  @dev_id: to pass the net device pointer.
2384  *  Description: this is the main driver interrupt service routine.
2385  *  It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI
2386  *  interrupts.
2387  */
2388 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2389 {
2390         struct net_device *dev = (struct net_device *)dev_id;
2391         struct stmmac_priv *priv = netdev_priv(dev);
2392
2393         if (unlikely(!dev)) {
2394                 pr_err("%s: invalid dev pointer\n", __func__);
2395                 return IRQ_NONE;
2396         }
2397
2398         /* To handle GMAC own interrupts */
2399         if (priv->plat->has_gmac) {
2400                 int status = priv->hw->mac->host_irq_status((void __iomem *)
2401                                                             dev->base_addr,
2402                                                             &priv->xstats);
2403                 if (unlikely(status)) {
2404                         /* For LPI we need to save the tx status */
2405                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2406                                 priv->tx_path_in_lpi_mode = true;
2407                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2408                                 priv->tx_path_in_lpi_mode = false;
2409                 }
2410         }
2411
2412         /* To handle DMA interrupts */
2413         stmmac_dma_interrupt(priv);
2414
2415         return IRQ_HANDLED;
2416 }
2417
2418 #ifdef CONFIG_NET_POLL_CONTROLLER
2419 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2420  * to allow network I/O with interrupts disabled.
2421  */
2422 static void stmmac_poll_controller(struct net_device *dev)
2423 {
2424         disable_irq(dev->irq);
2425         stmmac_interrupt(dev->irq, dev);
2426         enable_irq(dev->irq);
2427 }
2428 #endif
2429
2430 /**
2431  *  stmmac_ioctl - Entry point for the Ioctl
2432  *  @dev: Device pointer.
2433  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2434  *  a proprietary structure used to pass information to the driver.
2435  *  @cmd: IOCTL command
2436  *  Description:
2437  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2438  */
2439 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2440 {
2441         struct stmmac_priv *priv = netdev_priv(dev);
2442         int ret = -EOPNOTSUPP;
2443
2444         if (!netif_running(dev))
2445                 return -EINVAL;
2446
2447         switch (cmd) {
2448         case SIOCGMIIPHY:
2449         case SIOCGMIIREG:
2450         case SIOCSMIIREG:
2451                 if (!priv->phydev)
2452                         return -EINVAL;
2453                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2454                 break;
2455         case SIOCSHWTSTAMP:
2456                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2457                 break;
2458         default:
2459                 break;
2460         }
2461
2462         return ret;
2463 }
2464
2465 #ifdef CONFIG_GMAC_DEBUG_FS
2466 static struct dentry *stmmac_fs_dir;
2467 static struct dentry *stmmac_rings_status;
2468 static struct dentry *stmmac_dma_cap;
2469
2470 static void sysfs_display_ring(void *head, int size, int extend_desc,
2471                                struct seq_file *seq)
2472 {
2473         int i;
2474         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2475         struct dma_desc *p = (struct dma_desc *)head;
2476
2477         for (i = 0; i < size; i++) {
2478                 u64 x;
2479                 if (extend_desc) {
2480                         x = *(u64 *) ep;
2481                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2482                                    i, (unsigned int)virt_to_phys(ep),
2483                                    (unsigned int)x, (unsigned int)(x >> 32),
2484                                    ep->basic.des2, ep->basic.des3);
2485                         ep++;
2486                 } else {
2487                         x = *(u64 *) p;
2488                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2489                                    i, (unsigned int)virt_to_phys(ep),
2490                                    (unsigned int)x, (unsigned int)(x >> 32),
2491                                    p->des2, p->des3);
2492                         p++;
2493                 }
2494                 seq_printf(seq, "\n");
2495         }
2496 }
2497
2498 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2499 {
2500         struct net_device *dev = seq->private;
2501         struct stmmac_priv *priv = netdev_priv(dev);
2502         unsigned int txsize = priv->dma_tx_size;
2503         unsigned int rxsize = priv->dma_rx_size;
2504
2505         if (priv->extend_desc) {
2506                 seq_printf(seq, "Extended RX descriptor ring:\n");
2507                 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq);
2508                 seq_printf(seq, "Extended TX descriptor ring:\n");
2509                 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq);
2510         } else {
2511                 seq_printf(seq, "RX descriptor ring:\n");
2512                 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2513                 seq_printf(seq, "TX descriptor ring:\n");
2514                 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
2515         }
2516
2517         return 0;
2518 }
2519
2520 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2521 {
2522         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2523 }
2524
2525 static const struct file_operations stmmac_rings_status_fops = {
2526         .owner = THIS_MODULE,
2527         .open = stmmac_sysfs_ring_open,
2528         .read = seq_read,
2529         .llseek = seq_lseek,
2530         .release = single_release,
2531 };
2532
2533 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2534 {
2535         struct net_device *dev = seq->private;
2536         struct stmmac_priv *priv = netdev_priv(dev);
2537
2538         if (!priv->hw_cap_support) {
2539                 seq_printf(seq, "DMA HW features not supported\n");
2540                 return 0;
2541         }
2542
2543         seq_printf(seq, "==============================\n");
2544         seq_printf(seq, "\tDMA HW features\n");
2545         seq_printf(seq, "==============================\n");
2546
2547         seq_printf(seq, "\t10/100 Mbps %s\n",
2548                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2549         seq_printf(seq, "\t1000 Mbps %s\n",
2550                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
2551         seq_printf(seq, "\tHalf duple %s\n",
2552                    (priv->dma_cap.half_duplex) ? "Y" : "N");
2553         seq_printf(seq, "\tHash Filter: %s\n",
2554                    (priv->dma_cap.hash_filter) ? "Y" : "N");
2555         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2556                    (priv->dma_cap.multi_addr) ? "Y" : "N");
2557         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2558                    (priv->dma_cap.pcs) ? "Y" : "N");
2559         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2560                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
2561         seq_printf(seq, "\tPMT Remote wake up: %s\n",
2562                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2563         seq_printf(seq, "\tPMT Magic Frame: %s\n",
2564                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2565         seq_printf(seq, "\tRMON module: %s\n",
2566                    (priv->dma_cap.rmon) ? "Y" : "N");
2567         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2568                    (priv->dma_cap.time_stamp) ? "Y" : "N");
2569         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2570                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
2571         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2572                    (priv->dma_cap.eee) ? "Y" : "N");
2573         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2574         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2575                    (priv->dma_cap.tx_coe) ? "Y" : "N");
2576         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2577                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2578         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2579                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2580         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2581                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2582         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2583                    priv->dma_cap.number_rx_channel);
2584         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2585                    priv->dma_cap.number_tx_channel);
2586         seq_printf(seq, "\tEnhanced descriptors: %s\n",
2587                    (priv->dma_cap.enh_desc) ? "Y" : "N");
2588
2589         return 0;
2590 }
2591
2592 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2593 {
2594         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2595 }
2596
2597 static const struct file_operations stmmac_dma_cap_fops = {
2598         .owner = THIS_MODULE,
2599         .open = stmmac_sysfs_dma_cap_open,
2600         .read = seq_read,
2601         .llseek = seq_lseek,
2602         .release = single_release,
2603 };
2604
2605 static int stmmac_init_fs(struct net_device *dev)
2606 {
2607         /* Create debugfs entries */
2608         stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
2609
2610         if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
2611                 pr_err("ERROR %s, debugfs create directory failed\n",
2612                        STMMAC_RESOURCE_NAME);
2613
2614                 return -ENOMEM;
2615         }
2616
2617         /* Entry to report DMA RX/TX rings */
2618         stmmac_rings_status = debugfs_create_file("descriptors_status",
2619                                                   S_IRUGO, stmmac_fs_dir, dev,
2620                                                   &stmmac_rings_status_fops);
2621
2622         if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
2623                 pr_info("ERROR creating stmmac ring debugfs file\n");
2624                 debugfs_remove(stmmac_fs_dir);
2625
2626                 return -ENOMEM;
2627         }
2628
2629         /* Entry to report the DMA HW features */
2630         stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
2631                                              dev, &stmmac_dma_cap_fops);
2632
2633         if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
2634                 pr_info("ERROR creating stmmac MMC debugfs file\n");
2635                 debugfs_remove(stmmac_rings_status);
2636                 debugfs_remove(stmmac_fs_dir);
2637
2638                 return -ENOMEM;
2639         }
2640
2641         return 0;
2642 }
2643
2644 static void stmmac_exit_fs(void)
2645 {
2646         debugfs_remove(stmmac_rings_status);
2647         debugfs_remove(stmmac_dma_cap);
2648         debugfs_remove(stmmac_fs_dir);
2649 }
2650 #endif /* CONFIG_GMAC_DEBUG_FS */
2651
2652 static const struct net_device_ops stmmac_netdev_ops = {
2653         .ndo_open = stmmac_open,
2654         .ndo_start_xmit = stmmac_xmit,
2655         .ndo_stop = stmmac_release,
2656         .ndo_change_mtu = stmmac_change_mtu,
2657         .ndo_fix_features = stmmac_fix_features,
2658         .ndo_set_rx_mode = stmmac_set_rx_mode,
2659         .ndo_tx_timeout = stmmac_tx_timeout,
2660         .ndo_do_ioctl = stmmac_ioctl,
2661         .ndo_set_config = stmmac_config,
2662 #ifdef CONFIG_NET_POLL_CONTROLLER
2663         .ndo_poll_controller = stmmac_poll_controller,
2664 #endif
2665         .ndo_set_mac_address = eth_mac_addr,
2666 };
2667
2668 /**
2669  *  stmmac_hw_init - Init the MAC device
2670  *  @priv: driver private structure
2671  *  Description: this function detects which MAC device
2672  *  (GMAC/MAC10-100) has to attached, checks the HW capability
2673  *  (if supported) and sets the driver's features (for example
2674  *  to use the ring or chaine mode or support the normal/enh
2675  *  descriptor structure).
2676  */
2677 static int stmmac_hw_init(struct stmmac_priv *priv)
2678 {
2679         int ret;
2680         struct mac_device_info *mac;
2681
2682         /* Identify the MAC HW device */
2683         if (priv->plat->has_gmac) {
2684                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2685                 mac = dwmac1000_setup(priv->ioaddr);
2686         } else {
2687                 mac = dwmac100_setup(priv->ioaddr);
2688         }
2689         if (!mac)
2690                 return -ENOMEM;
2691
2692         priv->hw = mac;
2693
2694         /* Get and dump the chip ID */
2695         priv->synopsys_id = stmmac_get_synopsys_id(priv);
2696
2697         /* To use alternate (extended) or normal descriptor structures */
2698         stmmac_selec_desc_mode(priv);
2699
2700         /* To use the chained or ring mode */
2701         if (chain_mode) {
2702                 priv->hw->chain = &chain_mode_ops;
2703                 pr_info(" Chain mode enabled\n");
2704                 priv->mode = STMMAC_CHAIN_MODE;
2705         } else {
2706                 priv->hw->ring = &ring_mode_ops;
2707                 pr_info(" Ring mode enabled\n");
2708                 priv->mode = STMMAC_RING_MODE;
2709         }
2710
2711         /* Get the HW capability (new GMAC newer than 3.50a) */
2712         priv->hw_cap_support = stmmac_get_hw_features(priv);
2713         if (priv->hw_cap_support) {
2714                 pr_info(" DMA HW capability register supported");
2715
2716                 /* We can override some gmac/dma configuration fields: e.g.
2717                  * enh_desc, tx_coe (e.g. that are passed through the
2718                  * platform) with the values from the HW capability
2719                  * register (if supported).
2720                  */
2721                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2722                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2723
2724                 priv->plat->tx_coe = priv->dma_cap.tx_coe;
2725
2726                 if (priv->dma_cap.rx_coe_type2)
2727                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2728                 else if (priv->dma_cap.rx_coe_type1)
2729                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2730
2731         } else
2732                 pr_info(" No HW DMA feature register supported");
2733
2734         ret = priv->hw->mac->rx_ipc(priv->ioaddr);
2735         if (!ret) {
2736                 pr_warn(" RX IPC Checksum Offload not configured.\n");
2737                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2738         }
2739
2740         if (priv->plat->rx_coe)
2741                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2742                         priv->plat->rx_coe);
2743         if (priv->plat->tx_coe)
2744                 pr_info(" TX Checksum insertion supported\n");
2745
2746         if (priv->plat->pmt) {
2747                 pr_info(" Wake-Up On Lan supported\n");
2748                 device_set_wakeup_capable(priv->device, 1);
2749         }
2750
2751         return 0;
2752 }
2753
2754 /**
2755  * stmmac_dvr_probe
2756  * @device: device pointer
2757  * @plat_dat: platform data pointer
2758  * @addr: iobase memory address
2759  * Description: this is the main probe function used to
2760  * call the alloc_etherdev, allocate the priv structure.
2761  */
2762 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
2763                                      struct plat_stmmacenet_data *plat_dat,
2764                                      void __iomem *addr)
2765 {
2766         int ret = 0;
2767         struct net_device *ndev = NULL;
2768         struct stmmac_priv *priv;
2769
2770         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2771         if (!ndev)
2772                 return NULL;
2773
2774         SET_NETDEV_DEV(ndev, device);
2775
2776         priv = netdev_priv(ndev);
2777         priv->device = device;
2778         priv->dev = ndev;
2779
2780         ether_setup(ndev);
2781
2782         stmmac_set_ethtool_ops(ndev);
2783         priv->pause = pause;
2784         priv->plat = plat_dat;
2785         priv->ioaddr = addr;
2786         priv->dev->base_addr = (unsigned long)addr;
2787
2788         /* Verify driver arguments */
2789         stmmac_verify_args();
2790
2791         priv->plat->phy_addr = -1;
2792
2793         /* Override with kernel parameters if supplied XXX CRS XXX
2794          * this needs to have multiple instances
2795          */
2796         if ((phyaddr >= 0) && (phyaddr <= 31))
2797                 priv->plat->phy_addr = phyaddr;
2798
2799         /* Init MAC and get the capabilities */
2800         ret = stmmac_hw_init(priv);
2801         if (ret)
2802                 goto error_free_netdev;
2803
2804         ndev->netdev_ops = &stmmac_netdev_ops;
2805
2806         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2807                             NETIF_F_RXCSUM;
2808         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2809         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2810 #ifdef STMMAC_VLAN_TAG_USED
2811         /* Both mac100 and gmac support receive VLAN tag detection */
2812         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2813 #endif
2814         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2815
2816         if (flow_ctrl)
2817                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2818
2819         /* Rx Watchdog is available in the COREs newer than the 3.40.
2820          * In some case, for example on bugged HW this feature
2821          * has to be disable and this can be done by passing the
2822          * riwt_off field from the platform.
2823          */
2824         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2825                 priv->use_riwt = 1;
2826                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2827         }
2828
2829         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2830
2831         spin_lock_init(&priv->lock);
2832         spin_lock_init(&priv->tx_lock);
2833
2834         ret = register_netdev(ndev);
2835         if (ret) {
2836                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2837                 goto error_netdev_register;
2838         }
2839
2840         priv->mdio_registered = false;
2841
2842         priv->stmmac_clk = ((struct bsp_priv *)(priv->plat->bsp_priv))->clk_mac;
2843         if (IS_ERR(priv->stmmac_clk)) {
2844                 pr_warn("%s: warning: cannot get CSR clock\n", __func__);
2845                 goto error_clk_get;
2846         }
2847
2848         /* If a specific clk_csr value is passed from the platform
2849          * this means that the CSR Clock Range selection cannot be
2850          * changed at run-time and it is fixed. Viceversa the driver'll try to
2851          * set the MDC clock dynamically according to the csr actual
2852          * clock input.
2853          */
2854         if (!priv->plat->clk_csr)
2855                 stmmac_clk_csr_set(priv);
2856         else
2857                 priv->clk_csr = priv->plat->clk_csr;
2858
2859         stmmac_check_pcs_mode(priv);
2860 #if 0
2861         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2862             priv->pcs != STMMAC_PCS_RTBI) {
2863                 /* MDIO bus Registration */
2864                 ret = stmmac_mdio_register(ndev);
2865                 if (ret < 0) {
2866                         pr_debug("%s: MDIO bus (id: %d) registration failed",
2867                                  __func__, priv->plat->bus_id);
2868                         goto error_mdio_register;
2869                 }
2870         }
2871 #endif
2872         return priv;
2873 #if 0
2874 error_mdio_register:
2875         clk_put(priv->stmmac_clk);
2876 #endif
2877 error_clk_get:
2878         unregister_netdev(ndev);
2879 error_netdev_register:
2880         netif_napi_del(&priv->napi);
2881 error_free_netdev:
2882         free_netdev(ndev);
2883
2884         return NULL;
2885 }
2886
2887 /**
2888  * stmmac_dvr_remove
2889  * @ndev: net device pointer
2890  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2891  * changes the link status, releases the DMA descriptor rings.
2892  */
2893 int stmmac_dvr_remove(struct net_device *ndev)
2894 {
2895         struct stmmac_priv *priv = netdev_priv(ndev);
2896
2897         pr_info("%s:\n\tremoving driver", __func__);
2898
2899         priv->hw->dma->stop_rx(priv->ioaddr);
2900         priv->hw->dma->stop_tx(priv->ioaddr);
2901
2902         stmmac_set_mac(priv->ioaddr, false);
2903         if (priv->pcs != STMMAC_PCS_SGMII && priv->pcs != STMMAC_PCS_TBI &&
2904             priv->pcs != STMMAC_PCS_RTBI)
2905                 stmmac_mdio_unregister(ndev);
2906         netif_carrier_off(ndev);
2907         unregister_netdev(ndev);
2908         free_netdev(ndev);
2909
2910         return 0;
2911 }
2912
2913 #ifdef CONFIG_PM
2914 int stmmac_suspend(struct net_device *ndev)
2915 {
2916         struct stmmac_priv *priv = netdev_priv(ndev);
2917         unsigned long flags;
2918         bool pwr_off_phy = false;
2919         struct bsp_priv * bsp_priv = NULL;
2920
2921         if (!ndev || !netif_running(ndev))
2922                 return 0;
2923
2924         if (priv->phydev)
2925                 phy_stop(priv->phydev);
2926
2927         spin_lock_irqsave(&priv->lock, flags);
2928
2929         netif_device_detach(ndev);
2930         netif_stop_queue(ndev);
2931
2932         napi_disable(&priv->napi);
2933
2934         /* Stop TX/RX DMA */
2935         priv->hw->dma->stop_tx(priv->ioaddr);
2936         priv->hw->dma->stop_rx(priv->ioaddr);
2937
2938         stmmac_clear_descriptors(priv);
2939
2940         /* Enable Power down mode by programming the PMT regs */
2941         if (device_may_wakeup(priv->device))
2942                 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
2943         else {
2944                 stmmac_set_mac(priv->ioaddr, false);
2945                 /* Disable clock in case of PWM is off */
2946                 if ((priv->plat) && (priv->plat->bsp_priv)) {
2947                         bsp_priv = priv->plat->bsp_priv;
2948                         pwr_off_phy = true;
2949                         if (bsp_priv && bsp_priv->gmac_clk_enable) {
2950                                 bsp_priv->gmac_clk_enable(false);
2951                         }
2952                 }
2953         }
2954         spin_unlock_irqrestore(&priv->lock, flags);
2955
2956         if (pwr_off_phy && bsp_priv) {
2957                 if (bsp_priv->phy_power_on) {
2958                         bsp_priv->phy_power_on(false);
2959                 }
2960         }
2961
2962         return 0;
2963 }
2964
2965 int stmmac_resume(struct net_device *ndev)
2966 {
2967         struct stmmac_priv *priv = netdev_priv(ndev);
2968         unsigned long flags;
2969         bool pwr_on_phy = false;
2970         struct bsp_priv * bsp_priv = NULL;
2971
2972         if (!netif_running(ndev))
2973                 return 0;
2974
2975         spin_lock_irqsave(&priv->lock, flags);
2976
2977         /* Power Down bit, into the PM register, is cleared
2978          * automatically as soon as a magic packet or a Wake-up frame
2979          * is received. Anyway, it's better to manually clear
2980          * this bit because it can generate problems while resuming
2981          * from another devices (e.g. serial console).
2982          */
2983         if (device_may_wakeup(priv->device))
2984                 priv->hw->mac->pmt(priv->ioaddr, 0);
2985         else {
2986                 /* enable the clk prevously disabled */
2987                 if (priv->plat && (priv->plat->bsp_priv)) {
2988                         bsp_priv = priv->plat->bsp_priv;
2989                         if (bsp_priv && bsp_priv->gmac_clk_enable) {
2990                                 bsp_priv->gmac_clk_enable(true);
2991                         }
2992
2993                         pwr_on_phy = true;
2994                 }
2995         }
2996
2997         netif_device_attach(ndev);
2998
2999         /* Enable the MAC and DMA */
3000         stmmac_set_mac(priv->ioaddr, true);
3001         priv->hw->dma->start_tx(priv->ioaddr);
3002         priv->hw->dma->start_rx(priv->ioaddr);
3003
3004         napi_enable(&priv->napi);
3005
3006         netif_start_queue(ndev);
3007
3008         spin_unlock_irqrestore(&priv->lock, flags);
3009
3010         if (pwr_on_phy && bsp_priv) {
3011                 if (bsp_priv->phy_power_on) {
3012                         bsp_priv->phy_power_on(true);
3013                 }
3014         }
3015
3016         if (priv->phydev)
3017                 phy_start(priv->phydev);
3018
3019         return 0;
3020 }
3021
3022 int stmmac_freeze(struct net_device *ndev)
3023 {
3024         if (!ndev || !netif_running(ndev))
3025                 return 0;
3026
3027         return stmmac_release(ndev);
3028 }
3029
3030 int stmmac_restore(struct net_device *ndev)
3031 {
3032         if (!ndev || !netif_running(ndev))
3033                 return 0;
3034
3035         return stmmac_open(ndev);
3036 }
3037 #endif /* CONFIG_PM */
3038
3039 /* Driver can be configured w/ and w/ both PCI and Platf drivers
3040  * depending on the configuration selected.
3041  */
3042 static int __init stmmac_init(void)
3043 {
3044         int ret;
3045
3046         ret = stmmac_register_platform();
3047         if (ret)
3048                 goto err;
3049         ret = stmmac_register_pci();
3050         if (ret)
3051                 goto err_pci;
3052         return 0;
3053 err_pci:
3054         stmmac_unregister_platform();
3055 err:
3056         pr_err("stmmac: driver registration failed\n");
3057         return ret;
3058 }
3059
3060 static void __exit stmmac_exit(void)
3061 {
3062         stmmac_unregister_platform();
3063         stmmac_unregister_pci();
3064 }
3065
3066 module_init(stmmac_init);
3067 module_exit(stmmac_exit);
3068
3069 #ifndef MODULE
3070 static int __init stmmac_cmdline_opt(char *str)
3071 {
3072         char *opt;
3073
3074         if (!str || !*str)
3075                 return -EINVAL;
3076         while ((opt = strsep(&str, ",")) != NULL) {
3077                 if (!strncmp(opt, "debug:", 6)) {
3078                         if (kstrtoint(opt + 6, 0, &debug))
3079                                 goto err;
3080                 } else if (!strncmp(opt, "phyaddr:", 8)) {
3081                         if (kstrtoint(opt + 8, 0, &phyaddr))
3082                                 goto err;
3083                 } else if (!strncmp(opt, "dma_txsize:", 11)) {
3084                         if (kstrtoint(opt + 11, 0, &dma_txsize))
3085                                 goto err;
3086                 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
3087                         if (kstrtoint(opt + 11, 0, &dma_rxsize))
3088                                 goto err;
3089                 } else if (!strncmp(opt, "buf_sz:", 7)) {
3090                         if (kstrtoint(opt + 7, 0, &buf_sz))
3091                                 goto err;
3092                 } else if (!strncmp(opt, "tc:", 3)) {
3093                         if (kstrtoint(opt + 3, 0, &tc))
3094                                 goto err;
3095                 } else if (!strncmp(opt, "watchdog:", 9)) {
3096                         if (kstrtoint(opt + 9, 0, &watchdog))
3097                                 goto err;
3098                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3099                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
3100                                 goto err;
3101                 } else if (!strncmp(opt, "pause:", 6)) {
3102                         if (kstrtoint(opt + 6, 0, &pause))
3103                                 goto err;
3104                 } else if (!strncmp(opt, "eee_timer:", 10)) {
3105                         if (kstrtoint(opt + 10, 0, &eee_timer))
3106                                 goto err;
3107                 } else if (!strncmp(opt, "chain_mode:", 11)) {
3108                         if (kstrtoint(opt + 11, 0, &chain_mode))
3109                                 goto err;
3110                 }
3111         }
3112         return 0;
3113
3114 err:
3115         pr_err("%s: ERROR broken module parameter conversion", __func__);
3116         return -EINVAL;
3117 }
3118
3119 __setup("stmmaceth=", stmmac_cmdline_opt);
3120 #endif /* MODULE */
3121
3122 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3123 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3124 MODULE_LICENSE("GPL");