drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34
  35 #define RTL8169_VERSION "2.3LK-NAPI"
  36 #define MODULENAME "r8169"
  37 #define PFX MODULENAME ": "
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  44 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  45 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  46 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  47 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  48 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  51 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  52 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  53
  54 #ifdef RTL8169_DEBUG
  55 #define assert(expr) \
  56         if (!(expr)) {                                  \
  57                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  58                 #expr,__FILE__,__func__,__LINE__);              \
  59         }
  60 #define dprintk(fmt, args...) \
  61         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  62 #else
  63 #define assert(expr) do {} while (0)
  64 #define dprintk(fmt, args...)   do {} while (0)
  65 #endif /* RTL8169_DEBUG */
  66
  67 #define R8169_MSG_DEFAULT \
  68         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  69
  70 #define TX_SLOTS_AVAIL(tp) \
  71         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  72
  73 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  74 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  75         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  76
  77 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  78    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  79 static const int multicast_filter_limit = 32;
  80
  81 #define MAX_READ_REQUEST_SHIFT  12
  82 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  83 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  84
  85 #define R8169_REGS_SIZE         256
  86 #define R8169_NAPI_WEIGHT       64
  87 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  88 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  89 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  90 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  91
  92 #define RTL8169_TX_TIMEOUT      (6*HZ)
  93 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  94
  95 /* write/read MMIO register */
  96 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  97 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  98 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  99 #define RTL_R8(reg)             readb (ioaddr + (reg))
 100 #define RTL_R16(reg)            readw (ioaddr + (reg))
 101 #define RTL_R32(reg)            readl (ioaddr + (reg))
 102
 103 enum mac_version {
 104         RTL_GIGA_MAC_VER_01 = 0,
 105         RTL_GIGA_MAC_VER_02,
 106         RTL_GIGA_MAC_VER_03,
 107         RTL_GIGA_MAC_VER_04,
 108         RTL_GIGA_MAC_VER_05,
 109         RTL_GIGA_MAC_VER_06,
 110         RTL_GIGA_MAC_VER_07,
 111         RTL_GIGA_MAC_VER_08,
 112         RTL_GIGA_MAC_VER_09,
 113         RTL_GIGA_MAC_VER_10,
 114         RTL_GIGA_MAC_VER_11,
 115         RTL_GIGA_MAC_VER_12,
 116         RTL_GIGA_MAC_VER_13,
 117         RTL_GIGA_MAC_VER_14,
 118         RTL_GIGA_MAC_VER_15,
 119         RTL_GIGA_MAC_VER_16,
 120         RTL_GIGA_MAC_VER_17,
 121         RTL_GIGA_MAC_VER_18,
 122         RTL_GIGA_MAC_VER_19,
 123         RTL_GIGA_MAC_VER_20,
 124         RTL_GIGA_MAC_VER_21,
 125         RTL_GIGA_MAC_VER_22,
 126         RTL_GIGA_MAC_VER_23,
 127         RTL_GIGA_MAC_VER_24,
 128         RTL_GIGA_MAC_VER_25,
 129         RTL_GIGA_MAC_VER_26,
 130         RTL_GIGA_MAC_VER_27,
 131         RTL_GIGA_MAC_VER_28,
 132         RTL_GIGA_MAC_VER_29,
 133         RTL_GIGA_MAC_VER_30,
 134         RTL_GIGA_MAC_VER_31,
 135         RTL_GIGA_MAC_VER_32,
 136         RTL_GIGA_MAC_VER_33,
 137         RTL_GIGA_MAC_VER_34,
 138         RTL_GIGA_MAC_VER_35,
 139         RTL_GIGA_MAC_VER_36,
 140         RTL_GIGA_MAC_VER_37,
 141         RTL_GIGA_MAC_VER_38,
 142         RTL_GIGA_MAC_VER_39,
 143         RTL_GIGA_MAC_VER_40,
 144         RTL_GIGA_MAC_VER_41,
 145         RTL_GIGA_MAC_VER_42,
 146         RTL_GIGA_MAC_VER_43,
 147         RTL_GIGA_MAC_NONE   = 0xff,
 148 };
 149
 150 enum rtl_tx_desc_version {
 151         RTL_TD_0        = 0,
 152         RTL_TD_1        = 1,
 153 };
 154
 155 #define JUMBO_1K        ETH_DATA_LEN
 156 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 157 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 158 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 159 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 160
 161 #define _R(NAME,TD,FW,SZ,B) {   \
 162         .name = NAME,           \
 163         .txd_version = TD,      \
 164         .fw_name = FW,          \
 165         .jumbo_max = SZ,        \
 166         .jumbo_tx_csum = B      \
 167 }
 168
 169 static const struct {
 170         const char *name;
 171         enum rtl_tx_desc_version txd_version;
 172         const char *fw_name;
 173         u16 jumbo_max;
 174         bool jumbo_tx_csum;
 175 } rtl_chip_infos[] = {
 176         /* PCI devices. */
 177         [RTL_GIGA_MAC_VER_01] =
 178                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 179         [RTL_GIGA_MAC_VER_02] =
 180                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 181         [RTL_GIGA_MAC_VER_03] =
 182                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 183         [RTL_GIGA_MAC_VER_04] =
 184                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 185         [RTL_GIGA_MAC_VER_05] =
 186                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 187         [RTL_GIGA_MAC_VER_06] =
 188                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 189         /* PCI-E devices. */
 190         [RTL_GIGA_MAC_VER_07] =
 191                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 192         [RTL_GIGA_MAC_VER_08] =
 193                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 194         [RTL_GIGA_MAC_VER_09] =
 195                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 196         [RTL_GIGA_MAC_VER_10] =
 197                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 198         [RTL_GIGA_MAC_VER_11] =
 199                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 200         [RTL_GIGA_MAC_VER_12] =
 201                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 202         [RTL_GIGA_MAC_VER_13] =
 203                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 204         [RTL_GIGA_MAC_VER_14] =
 205                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 206         [RTL_GIGA_MAC_VER_15] =
 207                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 208         [RTL_GIGA_MAC_VER_16] =
 209                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 210         [RTL_GIGA_MAC_VER_17] =
 211                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
 212         [RTL_GIGA_MAC_VER_18] =
 213                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 214         [RTL_GIGA_MAC_VER_19] =
 215                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 216         [RTL_GIGA_MAC_VER_20] =
 217                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 218         [RTL_GIGA_MAC_VER_21] =
 219                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 220         [RTL_GIGA_MAC_VER_22] =
 221                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 222         [RTL_GIGA_MAC_VER_23] =
 223                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 224         [RTL_GIGA_MAC_VER_24] =
 225                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 226         [RTL_GIGA_MAC_VER_25] =
 227                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 228                                                         JUMBO_9K, false),
 229         [RTL_GIGA_MAC_VER_26] =
 230                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 231                                                         JUMBO_9K, false),
 232         [RTL_GIGA_MAC_VER_27] =
 233                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 234         [RTL_GIGA_MAC_VER_28] =
 235                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 236         [RTL_GIGA_MAC_VER_29] =
 237                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 238                                                         JUMBO_1K, true),
 239         [RTL_GIGA_MAC_VER_30] =
 240                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 241                                                         JUMBO_1K, true),
 242         [RTL_GIGA_MAC_VER_31] =
 243                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 244         [RTL_GIGA_MAC_VER_32] =
 245                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 246                                                         JUMBO_9K, false),
 247         [RTL_GIGA_MAC_VER_33] =
 248                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 249                                                         JUMBO_9K, false),
 250         [RTL_GIGA_MAC_VER_34] =
 251                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 252                                                         JUMBO_9K, false),
 253         [RTL_GIGA_MAC_VER_35] =
 254                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 255                                                         JUMBO_9K, false),
 256         [RTL_GIGA_MAC_VER_36] =
 257                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 258                                                         JUMBO_9K, false),
 259         [RTL_GIGA_MAC_VER_37] =
 260                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
 261                                                         JUMBO_1K, true),
 262         [RTL_GIGA_MAC_VER_38] =
 263                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
 264                                                         JUMBO_9K, false),
 265         [RTL_GIGA_MAC_VER_39] =
 266                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
 267                                                         JUMBO_1K, true),
 268         [RTL_GIGA_MAC_VER_40] =
 269                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_2,
 270                                                         JUMBO_9K, false),
 271         [RTL_GIGA_MAC_VER_41] =
 272                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K, false),
 273         [RTL_GIGA_MAC_VER_42] =
 274                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_3,
 275                                                         JUMBO_9K, false),
 276         [RTL_GIGA_MAC_VER_43] =
 277                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_2,
 278                                                         JUMBO_1K, true),
 279 };
 280 #undef _R
 281
 282 enum cfg_version {
 283         RTL_CFG_0 = 0x00,
 284         RTL_CFG_1,
 285         RTL_CFG_2
 286 };
 287
 288 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 289         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 290         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 291         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 292         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 293         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 294         { PCI_VENDOR_ID_DLINK,                  0x4300,
 295                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 296         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 297         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 298         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 299         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 300         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 301                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 302         { 0x0001,                               0x8168,
 303                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 304         {0,},
 305 };
 306
 307 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 308
 309 static int rx_buf_sz = 16383;
 310 static int use_dac;
 311 static struct {
 312         u32 msg_enable;
 313 } debug = { -1 };
 314
 315 enum rtl_registers {
 316         MAC0            = 0,    /* Ethernet hardware address. */
 317         MAC4            = 4,
 318         MAR0            = 8,    /* Multicast filter. */
 319         CounterAddrLow          = 0x10,
 320         CounterAddrHigh         = 0x14,
 321         TxDescStartAddrLow      = 0x20,
 322         TxDescStartAddrHigh     = 0x24,
 323         TxHDescStartAddrLow     = 0x28,
 324         TxHDescStartAddrHigh    = 0x2c,
 325         FLASH           = 0x30,
 326         ERSR            = 0x36,
 327         ChipCmd         = 0x37,
 328         TxPoll          = 0x38,
 329         IntrMask        = 0x3c,
 330         IntrStatus      = 0x3e,
 331
 332         TxConfig        = 0x40,
 333 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 334 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 335
 336         RxConfig        = 0x44,
 337 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 338 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 339 #define RXCFG_FIFO_SHIFT                13
 340                                         /* No threshold before first PCI xfer */
 341 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 342 #define RX_EARLY_OFF                    (1 << 11)
 343 #define RXCFG_DMA_SHIFT                 8
 344                                         /* Unlimited maximum PCI burst. */
 345 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 346
 347         RxMissed        = 0x4c,
 348         Cfg9346         = 0x50,
 349         Config0         = 0x51,
 350         Config1         = 0x52,
 351         Config2         = 0x53,
 352 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 353
 354         Config3         = 0x54,
 355         Config4         = 0x55,
 356         Config5         = 0x56,
 357         MultiIntr       = 0x5c,
 358         PHYAR           = 0x60,
 359         PHYstatus       = 0x6c,
 360         RxMaxSize       = 0xda,
 361         CPlusCmd        = 0xe0,
 362         IntrMitigate    = 0xe2,
 363         RxDescAddrLow   = 0xe4,
 364         RxDescAddrHigh  = 0xe8,
 365         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 366
 367 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 368
 369         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 370
 371 #define TxPacketMax     (8064 >> 7)
 372 #define EarlySize       0x27
 373
 374         FuncEvent       = 0xf0,
 375         FuncEventMask   = 0xf4,
 376         FuncPresetState = 0xf8,
 377         FuncForceEvent  = 0xfc,
 378 };
 379
 380 enum rtl8110_registers {
 381         TBICSR                  = 0x64,
 382         TBI_ANAR                = 0x68,
 383         TBI_LPAR                = 0x6a,
 384 };
 385
 386 enum rtl8168_8101_registers {
 387         CSIDR                   = 0x64,
 388         CSIAR                   = 0x68,
 389 #define CSIAR_FLAG                      0x80000000
 390 #define CSIAR_WRITE_CMD                 0x80000000
 391 #define CSIAR_BYTE_ENABLE               0x0f
 392 #define CSIAR_BYTE_ENABLE_SHIFT         12
 393 #define CSIAR_ADDR_MASK                 0x0fff
 394 #define CSIAR_FUNC_CARD                 0x00000000
 395 #define CSIAR_FUNC_SDIO                 0x00010000
 396 #define CSIAR_FUNC_NIC                  0x00020000
 397         PMCH                    = 0x6f,
 398         EPHYAR                  = 0x80,
 399 #define EPHYAR_FLAG                     0x80000000
 400 #define EPHYAR_WRITE_CMD                0x80000000
 401 #define EPHYAR_REG_MASK                 0x1f
 402 #define EPHYAR_REG_SHIFT                16
 403 #define EPHYAR_DATA_MASK                0xffff
 404         DLLPR                   = 0xd0,
 405 #define PFM_EN                          (1 << 6)
 406         DBG_REG                 = 0xd1,
 407 #define FIX_NAK_1                       (1 << 4)
 408 #define FIX_NAK_2                       (1 << 3)
 409         TWSI                    = 0xd2,
 410         MCU                     = 0xd3,
 411 #define NOW_IS_OOB                      (1 << 7)
 412 #define TX_EMPTY                        (1 << 5)
 413 #define RX_EMPTY                        (1 << 4)
 414 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 415 #define EN_NDP                          (1 << 3)
 416 #define EN_OOB_RESET                    (1 << 2)
 417 #define LINK_LIST_RDY                   (1 << 1)
 418         EFUSEAR                 = 0xdc,
 419 #define EFUSEAR_FLAG                    0x80000000
 420 #define EFUSEAR_WRITE_CMD               0x80000000
 421 #define EFUSEAR_READ_CMD                0x00000000
 422 #define EFUSEAR_REG_MASK                0x03ff
 423 #define EFUSEAR_REG_SHIFT               8
 424 #define EFUSEAR_DATA_MASK               0xff
 425 };
 426
 427 enum rtl8168_registers {
 428         LED_FREQ                = 0x1a,
 429         EEE_LED                 = 0x1b,
 430         ERIDR                   = 0x70,
 431         ERIAR                   = 0x74,
 432 #define ERIAR_FLAG                      0x80000000
 433 #define ERIAR_WRITE_CMD                 0x80000000
 434 #define ERIAR_READ_CMD                  0x00000000
 435 #define ERIAR_ADDR_BYTE_ALIGN           4
 436 #define ERIAR_TYPE_SHIFT                16
 437 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 438 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 439 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 440 #define ERIAR_MASK_SHIFT                12
 441 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 442 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 443 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 444 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 445         EPHY_RXER_NUM           = 0x7c,
 446         OCPDR                   = 0xb0, /* OCP GPHY access */
 447 #define OCPDR_WRITE_CMD                 0x80000000
 448 #define OCPDR_READ_CMD                  0x00000000
 449 #define OCPDR_REG_MASK                  0x7f
 450 #define OCPDR_GPHY_REG_SHIFT            16
 451 #define OCPDR_DATA_MASK                 0xffff
 452         OCPAR                   = 0xb4,
 453 #define OCPAR_FLAG                      0x80000000
 454 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 455 #define OCPAR_GPHY_READ_CMD             0x0000f060
 456         GPHY_OCP                = 0xb8,
 457         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 458         MISC                    = 0xf0, /* 8168e only. */
 459 #define TXPLA_RST                       (1 << 29)
 460 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 461 #define PWM_EN                          (1 << 22)
 462 #define RXDV_GATED_EN                   (1 << 19)
 463 #define EARLY_TALLY_EN                  (1 << 16)
 464 };
 465
 466 enum rtl_register_content {
 467         /* InterruptStatusBits */
 468         SYSErr          = 0x8000,
 469         PCSTimeout      = 0x4000,
 470         SWInt           = 0x0100,
 471         TxDescUnavail   = 0x0080,
 472         RxFIFOOver      = 0x0040,
 473         LinkChg         = 0x0020,
 474         RxOverflow      = 0x0010,
 475         TxErr           = 0x0008,
 476         TxOK            = 0x0004,
 477         RxErr           = 0x0002,
 478         RxOK            = 0x0001,
 479
 480         /* RxStatusDesc */
 481         RxBOVF  = (1 << 24),
 482         RxFOVF  = (1 << 23),
 483         RxRWT   = (1 << 22),
 484         RxRES   = (1 << 21),
 485         RxRUNT  = (1 << 20),
 486         RxCRC   = (1 << 19),
 487
 488         /* ChipCmdBits */
 489         StopReq         = 0x80,
 490         CmdReset        = 0x10,
 491         CmdRxEnb        = 0x08,
 492         CmdTxEnb        = 0x04,
 493         RxBufEmpty      = 0x01,
 494
 495         /* TXPoll register p.5 */
 496         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 497         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 498         FSWInt          = 0x01,         /* Forced software interrupt */
 499
 500         /* Cfg9346Bits */
 501         Cfg9346_Lock    = 0x00,
 502         Cfg9346_Unlock  = 0xc0,
 503
 504         /* rx_mode_bits */
 505         AcceptErr       = 0x20,
 506         AcceptRunt      = 0x10,
 507         AcceptBroadcast = 0x08,
 508         AcceptMulticast = 0x04,
 509         AcceptMyPhys    = 0x02,
 510         AcceptAllPhys   = 0x01,
 511 #define RX_CONFIG_ACCEPT_MASK           0x3f
 512
 513         /* TxConfigBits */
 514         TxInterFrameGapShift = 24,
 515         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 516
 517         /* Config1 register p.24 */
 518         LEDS1           = (1 << 7),
 519         LEDS0           = (1 << 6),
 520         Speed_down      = (1 << 4),
 521         MEMMAP          = (1 << 3),
 522         IOMAP           = (1 << 2),
 523         VPD             = (1 << 1),
 524         PMEnable        = (1 << 0),     /* Power Management Enable */
 525
 526         /* Config2 register p. 25 */
 527         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 528         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 529         PCI_Clock_66MHz = 0x01,
 530         PCI_Clock_33MHz = 0x00,
 531
 532         /* Config3 register p.25 */
 533         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 534         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 535         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 536         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 537
 538         /* Config4 register */
 539         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 540
 541         /* Config5 register p.27 */
 542         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 543         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 544         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 545         Spi_en          = (1 << 3),
 546         LanWake         = (1 << 1),     /* LanWake enable/disable */
 547         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 548         ASPM_en         = (1 << 0),     /* ASPM enable */
 549
 550         /* TBICSR p.28 */
 551         TBIReset        = 0x80000000,
 552         TBILoopback     = 0x40000000,
 553         TBINwEnable     = 0x20000000,
 554         TBINwRestart    = 0x10000000,
 555         TBILinkOk       = 0x02000000,
 556         TBINwComplete   = 0x01000000,
 557
 558         /* CPlusCmd p.31 */
 559         EnableBist      = (1 << 15),    // 8168 8101
 560         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 561         Normal_mode     = (1 << 13),    // unused
 562         Force_half_dup  = (1 << 12),    // 8168 8101
 563         Force_rxflow_en = (1 << 11),    // 8168 8101
 564         Force_txflow_en = (1 << 10),    // 8168 8101
 565         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 566         ASF             = (1 << 8),     // 8168 8101
 567         PktCntrDisable  = (1 << 7),     // 8168 8101
 568         Mac_dbgo_sel    = 0x001c,       // 8168
 569         RxVlan          = (1 << 6),
 570         RxChkSum        = (1 << 5),
 571         PCIDAC          = (1 << 4),
 572         PCIMulRW        = (1 << 3),
 573         INTT_0          = 0x0000,       // 8168
 574         INTT_1          = 0x0001,       // 8168
 575         INTT_2          = 0x0002,       // 8168
 576         INTT_3          = 0x0003,       // 8168
 577
 578         /* rtl8169_PHYstatus */
 579         TBI_Enable      = 0x80,
 580         TxFlowCtrl      = 0x40,
 581         RxFlowCtrl      = 0x20,
 582         _1000bpsF       = 0x10,
 583         _100bps         = 0x08,
 584         _10bps          = 0x04,
 585         LinkStatus      = 0x02,
 586         FullDup         = 0x01,
 587
 588         /* _TBICSRBit */
 589         TBILinkOK       = 0x02000000,
 590
 591         /* DumpCounterCommand */
 592         CounterDump     = 0x8,
 593 };
 594
 595 enum rtl_desc_bit {
 596         /* First doubleword. */
 597         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 598         RingEnd         = (1 << 30), /* End of descriptor ring */
 599         FirstFrag       = (1 << 29), /* First segment of a packet */
 600         LastFrag        = (1 << 28), /* Final segment of a packet */
 601 };
 602
 603 /* Generic case. */
 604 enum rtl_tx_desc_bit {
 605         /* First doubleword. */
 606         TD_LSO          = (1 << 27),            /* Large Send Offload */
 607 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 608
 609         /* Second doubleword. */
 610         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 611 };
 612
 613 /* 8169, 8168b and 810x except 8102e. */
 614 enum rtl_tx_desc_bit_0 {
 615         /* First doubleword. */
 616 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 617         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 618         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 619         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 620 };
 621
 622 /* 8102e, 8168c and beyond. */
 623 enum rtl_tx_desc_bit_1 {
 624         /* Second doubleword. */
 625 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 626         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 627         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 628         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 629 };
 630
 631 static const struct rtl_tx_desc_info {
 632         struct {
 633                 u32 udp;
 634                 u32 tcp;
 635         } checksum;
 636         u16 mss_shift;
 637         u16 opts_offset;
 638 } tx_desc_info [] = {
 639         [RTL_TD_0] = {
 640                 .checksum = {
 641                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 642                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 643                 },
 644                 .mss_shift      = TD0_MSS_SHIFT,
 645                 .opts_offset    = 0
 646         },
 647         [RTL_TD_1] = {
 648                 .checksum = {
 649                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 650                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 651                 },
 652                 .mss_shift      = TD1_MSS_SHIFT,
 653                 .opts_offset    = 1
 654         }
 655 };
 656
 657 enum rtl_rx_desc_bit {
 658         /* Rx private */
 659         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 660         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 661
 662 #define RxProtoUDP      (PID1)
 663 #define RxProtoTCP      (PID0)
 664 #define RxProtoIP       (PID1 | PID0)
 665 #define RxProtoMask     RxProtoIP
 666
 667         IPFail          = (1 << 16), /* IP checksum failed */
 668         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 669         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 670         RxVlanTag       = (1 << 16), /* VLAN tag available */
 671 };
 672
 673 #define RsvdMask        0x3fffc000
 674
 675 struct TxDesc {
 676         __le32 opts1;
 677         __le32 opts2;
 678         __le64 addr;
 679 };
 680
 681 struct RxDesc {
 682         __le32 opts1;
 683         __le32 opts2;
 684         __le64 addr;
 685 };
 686
 687 struct ring_info {
 688         struct sk_buff  *skb;
 689         u32             len;
 690         u8              __pad[sizeof(void *) - sizeof(u32)];
 691 };
 692
 693 enum features {
 694         RTL_FEATURE_WOL         = (1 << 0),
 695         RTL_FEATURE_MSI         = (1 << 1),
 696         RTL_FEATURE_GMII        = (1 << 2),
 697 };
 698
 699 struct rtl8169_counters {
 700         __le64  tx_packets;
 701         __le64  rx_packets;
 702         __le64  tx_errors;
 703         __le32  rx_errors;
 704         __le16  rx_missed;
 705         __le16  align_errors;
 706         __le32  tx_one_collision;
 707         __le32  tx_multi_collision;
 708         __le64  rx_unicast;
 709         __le64  rx_broadcast;
 710         __le32  rx_multicast;
 711         __le16  tx_aborted;
 712         __le16  tx_underun;
 713 };
 714
 715 enum rtl_flag {
 716         RTL_FLAG_TASK_ENABLED,
 717         RTL_FLAG_TASK_SLOW_PENDING,
 718         RTL_FLAG_TASK_RESET_PENDING,
 719         RTL_FLAG_TASK_PHY_PENDING,
 720         RTL_FLAG_MAX
 721 };
 722
 723 struct rtl8169_stats {
 724         u64                     packets;
 725         u64                     bytes;
 726         struct u64_stats_sync   syncp;
 727 };
 728
 729 struct rtl8169_private {
 730         void __iomem *mmio_addr;        /* memory map physical address */
 731         struct pci_dev *pci_dev;
 732         struct net_device *dev;
 733         struct napi_struct napi;
 734         u32 msg_enable;
 735         u16 txd_version;
 736         u16 mac_version;
 737         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 738         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 739         u32 dirty_tx;
 740         struct rtl8169_stats rx_stats;
 741         struct rtl8169_stats tx_stats;
 742         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 743         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 744         dma_addr_t TxPhyAddr;
 745         dma_addr_t RxPhyAddr;
 746         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 747         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 748         struct timer_list timer;
 749         u16 cp_cmd;
 750
 751         u16 event_slow;
 752
 753         struct mdio_ops {
 754                 void (*write)(struct rtl8169_private *, int, int);
 755                 int (*read)(struct rtl8169_private *, int);
 756         } mdio_ops;
 757
 758         struct pll_power_ops {
 759                 void (*down)(struct rtl8169_private *);
 760                 void (*up)(struct rtl8169_private *);
 761         } pll_power_ops;
 762
 763         struct jumbo_ops {
 764                 void (*enable)(struct rtl8169_private *);
 765                 void (*disable)(struct rtl8169_private *);
 766         } jumbo_ops;
 767
 768         struct csi_ops {
 769                 void (*write)(struct rtl8169_private *, int, int);
 770                 u32 (*read)(struct rtl8169_private *, int);
 771         } csi_ops;
 772
 773         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 774         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 775         void (*phy_reset_enable)(struct rtl8169_private *tp);
 776         void (*hw_start)(struct net_device *);
 777         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 778         unsigned int (*link_ok)(void __iomem *);
 779         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 780
 781         struct {
 782                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 783                 struct mutex mutex;
 784                 struct work_struct work;
 785         } wk;
 786
 787         unsigned features;
 788
 789         struct mii_if_info mii;
 790         struct rtl8169_counters counters;
 791         u32 saved_wolopts;
 792         u32 opts1_mask;
 793
 794         struct rtl_fw {
 795                 const struct firmware *fw;
 796
 797 #define RTL_VER_SIZE            32
 798
 799                 char version[RTL_VER_SIZE];
 800
 801                 struct rtl_fw_phy_action {
 802                         __le32 *code;
 803                         size_t size;
 804                 } phy_action;
 805         } *rtl_fw;
 806 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 807
 808         u32 ocp_base;
 809 };
 810
 811 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 812 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 813 module_param(use_dac, int, 0);
 814 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 815 module_param_named(debug, debug.msg_enable, int, 0);
 816 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 817 MODULE_LICENSE("GPL");
 818 MODULE_VERSION(RTL8169_VERSION);
 819 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 820 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 821 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 822 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 823 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 824 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 825 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 826 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 827 MODULE_FIRMWARE(FIRMWARE_8402_1);
 828 MODULE_FIRMWARE(FIRMWARE_8411_1);
 829 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 830 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 831 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 832 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 833
 834 static void rtl_lock_work(struct rtl8169_private *tp)
 835 {
 836         mutex_lock(&tp->wk.mutex);
 837 }
 838
 839 static void rtl_unlock_work(struct rtl8169_private *tp)
 840 {
 841         mutex_unlock(&tp->wk.mutex);
 842 }
 843
 844 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 845 {
 846         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
 847                                            PCI_EXP_DEVCTL_READRQ, force);
 848 }
 849
 850 struct rtl_cond {
 851         bool (*check)(struct rtl8169_private *);
 852         const char *msg;
 853 };
 854
 855 static void rtl_udelay(unsigned int d)
 856 {
 857         udelay(d);
 858 }
 859
 860 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 861                           void (*delay)(unsigned int), unsigned int d, int n,
 862                           bool high)
 863 {
 864         int i;
 865
 866         for (i = 0; i < n; i++) {
 867                 delay(d);
 868                 if (c->check(tp) == high)
 869                         return true;
 870         }
 871         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 872                   c->msg, !high, n, d);
 873         return false;
 874 }
 875
 876 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 877                                       const struct rtl_cond *c,
 878                                       unsigned int d, int n)
 879 {
 880         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 881 }
 882
 883 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 884                                      const struct rtl_cond *c,
 885                                      unsigned int d, int n)
 886 {
 887         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 888 }
 889
 890 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 891                                       const struct rtl_cond *c,
 892                                       unsigned int d, int n)
 893 {
 894         return rtl_loop_wait(tp, c, msleep, d, n, true);
 895 }
 896
 897 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 898                                      const struct rtl_cond *c,
 899                                      unsigned int d, int n)
 900 {
 901         return rtl_loop_wait(tp, c, msleep, d, n, false);
 902 }
 903
 904 #define DECLARE_RTL_COND(name)                          \
 905 static bool name ## _check(struct rtl8169_private *);   \
 906                                                         \
 907 static const struct rtl_cond name = {                   \
 908         .check  = name ## _check,                       \
 909         .msg    = #name                                 \
 910 };                                                      \
 911                                                         \
 912 static bool name ## _check(struct rtl8169_private *tp)
 913
 914 DECLARE_RTL_COND(rtl_ocpar_cond)
 915 {
 916         void __iomem *ioaddr = tp->mmio_addr;
 917
 918         return RTL_R32(OCPAR) & OCPAR_FLAG;
 919 }
 920
 921 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 922 {
 923         void __iomem *ioaddr = tp->mmio_addr;
 924
 925         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 926
 927         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
 928                 RTL_R32(OCPDR) : ~0;
 929 }
 930
 931 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 932 {
 933         void __iomem *ioaddr = tp->mmio_addr;
 934
 935         RTL_W32(OCPDR, data);
 936         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 937
 938         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
 939 }
 940
 941 DECLARE_RTL_COND(rtl_eriar_cond)
 942 {
 943         void __iomem *ioaddr = tp->mmio_addr;
 944
 945         return RTL_R32(ERIAR) & ERIAR_FLAG;
 946 }
 947
 948 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 949 {
 950         void __iomem *ioaddr = tp->mmio_addr;
 951
 952         RTL_W8(ERIDR, cmd);
 953         RTL_W32(ERIAR, 0x800010e8);
 954         msleep(2);
 955
 956         if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
 957                 return;
 958
 959         ocp_write(tp, 0x1, 0x30, 0x00000001);
 960 }
 961
 962 #define OOB_CMD_RESET           0x00
 963 #define OOB_CMD_DRIVER_START    0x05
 964 #define OOB_CMD_DRIVER_STOP     0x06
 965
 966 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 967 {
 968         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 969 }
 970
 971 DECLARE_RTL_COND(rtl_ocp_read_cond)
 972 {
 973         u16 reg;
 974
 975         reg = rtl8168_get_ocp_reg(tp);
 976
 977         return ocp_read(tp, 0x0f, reg) & 0x00000800;
 978 }
 979
 980 static void rtl8168_driver_start(struct rtl8169_private *tp)
 981 {
 982         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 983
 984         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
 985 }
 986
 987 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 988 {
 989         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 990
 991         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
 992 }
 993
 994 static int r8168dp_check_dash(struct rtl8169_private *tp)
 995 {
 996         u16 reg = rtl8168_get_ocp_reg(tp);
 997
 998         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 999 }
1000
1001 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
1002 {
1003         if (reg & 0xffff0001) {
1004                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
1005                 return true;
1006         }
1007         return false;
1008 }
1009
1010 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1011 {
1012         void __iomem *ioaddr = tp->mmio_addr;
1013
1014         return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1015 }
1016
1017 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1018 {
1019         void __iomem *ioaddr = tp->mmio_addr;
1020
1021         if (rtl_ocp_reg_failure(tp, reg))
1022                 return;
1023
1024         RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1025
1026         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1027 }
1028
1029 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1030 {
1031         void __iomem *ioaddr = tp->mmio_addr;
1032
1033         if (rtl_ocp_reg_failure(tp, reg))
1034                 return 0;
1035
1036         RTL_W32(GPHY_OCP, reg << 15);
1037
1038         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1039                 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1040 }
1041
1042 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1043 {
1044         void __iomem *ioaddr = tp->mmio_addr;
1045
1046         if (rtl_ocp_reg_failure(tp, reg))
1047                 return;
1048
1049         RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1050 }
1051
1052 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1053 {
1054         void __iomem *ioaddr = tp->mmio_addr;
1055
1056         if (rtl_ocp_reg_failure(tp, reg))
1057                 return 0;
1058
1059         RTL_W32(OCPDR, reg << 15);
1060
1061         return RTL_R32(OCPDR);
1062 }
1063
1064 #define OCP_STD_PHY_BASE        0xa400
1065
1066 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1067 {
1068         if (reg == 0x1f) {
1069                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1070                 return;
1071         }
1072
1073         if (tp->ocp_base != OCP_STD_PHY_BASE)
1074                 reg -= 0x10;
1075
1076         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1077 }
1078
1079 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1080 {
1081         if (tp->ocp_base != OCP_STD_PHY_BASE)
1082                 reg -= 0x10;
1083
1084         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1085 }
1086
1087 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1088 {
1089         if (reg == 0x1f) {
1090                 tp->ocp_base = value << 4;
1091                 return;
1092         }
1093
1094         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1095 }
1096
1097 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1098 {
1099         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1100 }
1101
1102 DECLARE_RTL_COND(rtl_phyar_cond)
1103 {
1104         void __iomem *ioaddr = tp->mmio_addr;
1105
1106         return RTL_R32(PHYAR) & 0x80000000;
1107 }
1108
1109 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1110 {
1111         void __iomem *ioaddr = tp->mmio_addr;
1112
1113         RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1114
1115         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1116         /*
1117          * According to hardware specs a 20us delay is required after write
1118          * complete indication, but before sending next command.
1119          */
1120         udelay(20);
1121 }
1122
1123 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1124 {
1125         void __iomem *ioaddr = tp->mmio_addr;
1126         int value;
1127
1128         RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1129
1130         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1131                 RTL_R32(PHYAR) & 0xffff : ~0;
1132
1133         /*
1134          * According to hardware specs a 20us delay is required after read
1135          * complete indication, but before sending next command.
1136          */
1137         udelay(20);
1138
1139         return value;
1140 }
1141
1142 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1143 {
1144         void __iomem *ioaddr = tp->mmio_addr;
1145
1146         RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1147         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1148         RTL_W32(EPHY_RXER_NUM, 0);
1149
1150         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1151 }
1152
1153 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1154 {
1155         r8168dp_1_mdio_access(tp, reg,
1156                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1157 }
1158
1159 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1160 {
1161         void __iomem *ioaddr = tp->mmio_addr;
1162
1163         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1164
1165         mdelay(1);
1166         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1167         RTL_W32(EPHY_RXER_NUM, 0);
1168
1169         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1170                 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1171 }
1172
1173 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1174
1175 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1176 {
1177         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1178 }
1179
1180 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1181 {
1182         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1183 }
1184
1185 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1186 {
1187         void __iomem *ioaddr = tp->mmio_addr;
1188
1189         r8168dp_2_mdio_start(ioaddr);
1190
1191         r8169_mdio_write(tp, reg, value);
1192
1193         r8168dp_2_mdio_stop(ioaddr);
1194 }
1195
1196 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1197 {
1198         void __iomem *ioaddr = tp->mmio_addr;
1199         int value;
1200
1201         r8168dp_2_mdio_start(ioaddr);
1202
1203         value = r8169_mdio_read(tp, reg);
1204
1205         r8168dp_2_mdio_stop(ioaddr);
1206
1207         return value;
1208 }
1209
1210 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1211 {
1212         tp->mdio_ops.write(tp, location, val);
1213 }
1214
1215 static int rtl_readphy(struct rtl8169_private *tp, int location)
1216 {
1217         return tp->mdio_ops.read(tp, location);
1218 }
1219
1220 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1221 {
1222         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1223 }
1224
1225 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1226 {
1227         int val;
1228
1229         val = rtl_readphy(tp, reg_addr);
1230         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1231 }
1232
1233 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1234                            int val)
1235 {
1236         struct rtl8169_private *tp = netdev_priv(dev);
1237
1238         rtl_writephy(tp, location, val);
1239 }
1240
1241 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1242 {
1243         struct rtl8169_private *tp = netdev_priv(dev);
1244
1245         return rtl_readphy(tp, location);
1246 }
1247
1248 DECLARE_RTL_COND(rtl_ephyar_cond)
1249 {
1250         void __iomem *ioaddr = tp->mmio_addr;
1251
1252         return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1253 }
1254
1255 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1256 {
1257         void __iomem *ioaddr = tp->mmio_addr;
1258
1259         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1260                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1261
1262         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1263
1264         udelay(10);
1265 }
1266
1267 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1268 {
1269         void __iomem *ioaddr = tp->mmio_addr;
1270
1271         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1272
1273         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1274                 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1275 }
1276
1277 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1278                           u32 val, int type)
1279 {
1280         void __iomem *ioaddr = tp->mmio_addr;
1281
1282         BUG_ON((addr & 3) || (mask == 0));
1283         RTL_W32(ERIDR, val);
1284         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1285
1286         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1287 }
1288
1289 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1290 {
1291         void __iomem *ioaddr = tp->mmio_addr;
1292
1293         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1294
1295         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1296                 RTL_R32(ERIDR) : ~0;
1297 }
1298
1299 static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1300                          u32 m, int type)
1301 {
1302         u32 val;
1303
1304         val = rtl_eri_read(tp, addr, type);
1305         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1306 }
1307
1308 struct exgmac_reg {
1309         u16 addr;
1310         u16 mask;
1311         u32 val;
1312 };
1313
1314 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1315                                    const struct exgmac_reg *r, int len)
1316 {
1317         while (len-- > 0) {
1318                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1319                 r++;
1320         }
1321 }
1322
1323 DECLARE_RTL_COND(rtl_efusear_cond)
1324 {
1325         void __iomem *ioaddr = tp->mmio_addr;
1326
1327         return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1328 }
1329
1330 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1331 {
1332         void __iomem *ioaddr = tp->mmio_addr;
1333
1334         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1335
1336         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1337                 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1338 }
1339
1340 static u16 rtl_get_events(struct rtl8169_private *tp)
1341 {
1342         void __iomem *ioaddr = tp->mmio_addr;
1343
1344         return RTL_R16(IntrStatus);
1345 }
1346
1347 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1348 {
1349         void __iomem *ioaddr = tp->mmio_addr;
1350
1351         RTL_W16(IntrStatus, bits);
1352         mmiowb();
1353 }
1354
1355 static void rtl_irq_disable(struct rtl8169_private *tp)
1356 {
1357         void __iomem *ioaddr = tp->mmio_addr;
1358
1359         RTL_W16(IntrMask, 0);
1360         mmiowb();
1361 }
1362
1363 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1364 {
1365         void __iomem *ioaddr = tp->mmio_addr;
1366
1367         RTL_W16(IntrMask, bits);
1368 }
1369
1370 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1371 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1372 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1373
1374 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1375 {
1376         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1377 }
1378
1379 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1380 {
1381         void __iomem *ioaddr = tp->mmio_addr;
1382
1383         rtl_irq_disable(tp);
1384         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1385         RTL_R8(ChipCmd);
1386 }
1387
1388 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1389 {
1390         void __iomem *ioaddr = tp->mmio_addr;
1391
1392         return RTL_R32(TBICSR) & TBIReset;
1393 }
1394
1395 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1396 {
1397         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1398 }
1399
1400 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1401 {
1402         return RTL_R32(TBICSR) & TBILinkOk;
1403 }
1404
1405 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1406 {
1407         return RTL_R8(PHYstatus) & LinkStatus;
1408 }
1409
1410 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1411 {
1412         void __iomem *ioaddr = tp->mmio_addr;
1413
1414         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1415 }
1416
1417 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1418 {
1419         unsigned int val;
1420
1421         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1422         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1423 }
1424
1425 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1426 {
1427         void __iomem *ioaddr = tp->mmio_addr;
1428         struct net_device *dev = tp->dev;
1429
1430         if (!netif_running(dev))
1431                 return;
1432
1433         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1434             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1435                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1436                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1437                                       ERIAR_EXGMAC);
1438                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1439                                       ERIAR_EXGMAC);
1440                 } else if (RTL_R8(PHYstatus) & _100bps) {
1441                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1442                                       ERIAR_EXGMAC);
1443                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1444                                       ERIAR_EXGMAC);
1445                 } else {
1446                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1447                                       ERIAR_EXGMAC);
1448                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1449                                       ERIAR_EXGMAC);
1450                 }
1451                 /* Reset packet filter */
1452                 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1453                              ERIAR_EXGMAC);
1454                 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1455                              ERIAR_EXGMAC);
1456         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1457                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1458                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1459                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1460                                       ERIAR_EXGMAC);
1461                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1462                                       ERIAR_EXGMAC);
1463                 } else {
1464                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1465                                       ERIAR_EXGMAC);
1466                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1467                                       ERIAR_EXGMAC);
1468                 }
1469         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1470                 if (RTL_R8(PHYstatus) & _10bps) {
1471                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1472                                       ERIAR_EXGMAC);
1473                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1474                                       ERIAR_EXGMAC);
1475                 } else {
1476                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1477                                       ERIAR_EXGMAC);
1478                 }
1479         }
1480 }
1481
1482 static void __rtl8169_check_link_status(struct net_device *dev,
1483                                         struct rtl8169_private *tp,
1484                                         void __iomem *ioaddr, bool pm)
1485 {
1486         if (tp->link_ok(ioaddr)) {
1487                 rtl_link_chg_patch(tp);
1488                 /* This is to cancel a scheduled suspend if there's one. */
1489                 if (pm)
1490                         pm_request_resume(&tp->pci_dev->dev);
1491                 netif_carrier_on(dev);
1492                 if (net_ratelimit())
1493                         netif_info(tp, ifup, dev, "link up\n");
1494         } else {
1495                 netif_carrier_off(dev);
1496                 netif_info(tp, ifdown, dev, "link down\n");
1497                 if (pm)
1498                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1499         }
1500 }
1501
1502 static void rtl8169_check_link_status(struct net_device *dev,
1503                                       struct rtl8169_private *tp,
1504                                       void __iomem *ioaddr)
1505 {
1506         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1507 }
1508
1509 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1510
1511 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1512 {
1513         void __iomem *ioaddr = tp->mmio_addr;
1514         u8 options;
1515         u32 wolopts = 0;
1516
1517         options = RTL_R8(Config1);
1518         if (!(options & PMEnable))
1519                 return 0;
1520
1521         options = RTL_R8(Config3);
1522         if (options & LinkUp)
1523                 wolopts |= WAKE_PHY;
1524         if (options & MagicPacket)
1525                 wolopts |= WAKE_MAGIC;
1526
1527         options = RTL_R8(Config5);
1528         if (options & UWF)
1529                 wolopts |= WAKE_UCAST;
1530         if (options & BWF)
1531                 wolopts |= WAKE_BCAST;
1532         if (options & MWF)
1533                 wolopts |= WAKE_MCAST;
1534
1535         return wolopts;
1536 }
1537
1538 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1539 {
1540         struct rtl8169_private *tp = netdev_priv(dev);
1541
1542         rtl_lock_work(tp);
1543
1544         wol->supported = WAKE_ANY;
1545         wol->wolopts = __rtl8169_get_wol(tp);
1546
1547         rtl_unlock_work(tp);
1548 }
1549
1550 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1551 {
1552         void __iomem *ioaddr = tp->mmio_addr;
1553         unsigned int i;
1554         static const struct {
1555                 u32 opt;
1556                 u16 reg;
1557                 u8  mask;
1558         } cfg[] = {
1559                 { WAKE_PHY,   Config3, LinkUp },
1560                 { WAKE_MAGIC, Config3, MagicPacket },
1561                 { WAKE_UCAST, Config5, UWF },
1562                 { WAKE_BCAST, Config5, BWF },
1563                 { WAKE_MCAST, Config5, MWF },
1564                 { WAKE_ANY,   Config5, LanWake }
1565         };
1566         u8 options;
1567
1568         RTL_W8(Cfg9346, Cfg9346_Unlock);
1569
1570         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1571                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1572                 if (wolopts & cfg[i].opt)
1573                         options |= cfg[i].mask;
1574                 RTL_W8(cfg[i].reg, options);
1575         }
1576
1577         switch (tp->mac_version) {
1578         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1579                 options = RTL_R8(Config1) & ~PMEnable;
1580                 if (wolopts)
1581                         options |= PMEnable;
1582                 RTL_W8(Config1, options);
1583                 break;
1584         default:
1585                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1586                 if (wolopts)
1587                         options |= PME_SIGNAL;
1588                 RTL_W8(Config2, options);
1589                 break;
1590         }
1591
1592         RTL_W8(Cfg9346, Cfg9346_Lock);
1593 }
1594
1595 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1596 {
1597         struct rtl8169_private *tp = netdev_priv(dev);
1598
1599         rtl_lock_work(tp);
1600
1601         if (wol->wolopts)
1602                 tp->features |= RTL_FEATURE_WOL;
1603         else
1604                 tp->features &= ~RTL_FEATURE_WOL;
1605         __rtl8169_set_wol(tp, wol->wolopts);
1606
1607         rtl_unlock_work(tp);
1608
1609         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1610
1611         return 0;
1612 }
1613
1614 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1615 {
1616         return rtl_chip_infos[tp->mac_version].fw_name;
1617 }
1618
1619 static void rtl8169_get_drvinfo(struct net_device *dev,
1620                                 struct ethtool_drvinfo *info)
1621 {
1622         struct rtl8169_private *tp = netdev_priv(dev);
1623         struct rtl_fw *rtl_fw = tp->rtl_fw;
1624
1625         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1626         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1627         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1628         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1629         if (!IS_ERR_OR_NULL(rtl_fw))
1630                 strlcpy(info->fw_version, rtl_fw->version,
1631                         sizeof(info->fw_version));
1632 }
1633
1634 static int rtl8169_get_regs_len(struct net_device *dev)
1635 {
1636         return R8169_REGS_SIZE;
1637 }
1638
1639 static int rtl8169_set_speed_tbi(struct net_device *dev,
1640                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1641 {
1642         struct rtl8169_private *tp = netdev_priv(dev);
1643         void __iomem *ioaddr = tp->mmio_addr;
1644         int ret = 0;
1645         u32 reg;
1646
1647         reg = RTL_R32(TBICSR);
1648         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1649             (duplex == DUPLEX_FULL)) {
1650                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1651         } else if (autoneg == AUTONEG_ENABLE)
1652                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1653         else {
1654                 netif_warn(tp, link, dev,
1655                            "incorrect speed setting refused in TBI mode\n");
1656                 ret = -EOPNOTSUPP;
1657         }
1658
1659         return ret;
1660 }
1661
1662 static int rtl8169_set_speed_xmii(struct net_device *dev,
1663                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1664 {
1665         struct rtl8169_private *tp = netdev_priv(dev);
1666         int giga_ctrl, bmcr;
1667         int rc = -EINVAL;
1668
1669         rtl_writephy(tp, 0x1f, 0x0000);
1670
1671         if (autoneg == AUTONEG_ENABLE) {
1672                 int auto_nego;
1673
1674                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1675                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1676                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1677
1678                 if (adv & ADVERTISED_10baseT_Half)
1679                         auto_nego |= ADVERTISE_10HALF;
1680                 if (adv & ADVERTISED_10baseT_Full)
1681                         auto_nego |= ADVERTISE_10FULL;
1682                 if (adv & ADVERTISED_100baseT_Half)
1683                         auto_nego |= ADVERTISE_100HALF;
1684                 if (adv & ADVERTISED_100baseT_Full)
1685                         auto_nego |= ADVERTISE_100FULL;
1686
1687                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1688
1689                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1690                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1691
1692                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1693                 if (tp->mii.supports_gmii) {
1694                         if (adv & ADVERTISED_1000baseT_Half)
1695                                 giga_ctrl |= ADVERTISE_1000HALF;
1696                         if (adv & ADVERTISED_1000baseT_Full)
1697                                 giga_ctrl |= ADVERTISE_1000FULL;
1698                 } else if (adv & (ADVERTISED_1000baseT_Half |
1699                                   ADVERTISED_1000baseT_Full)) {
1700                         netif_info(tp, link, dev,
1701                                    "PHY does not support 1000Mbps\n");
1702                         goto out;
1703                 }
1704
1705                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1706
1707                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1708                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1709         } else {
1710                 giga_ctrl = 0;
1711
1712                 if (speed == SPEED_10)
1713                         bmcr = 0;
1714                 else if (speed == SPEED_100)
1715                         bmcr = BMCR_SPEED100;
1716                 else
1717                         goto out;
1718
1719                 if (duplex == DUPLEX_FULL)
1720                         bmcr |= BMCR_FULLDPLX;
1721         }
1722
1723         rtl_writephy(tp, MII_BMCR, bmcr);
1724
1725         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1726             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1727                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1728                         rtl_writephy(tp, 0x17, 0x2138);
1729                         rtl_writephy(tp, 0x0e, 0x0260);
1730                 } else {
1731                         rtl_writephy(tp, 0x17, 0x2108);
1732                         rtl_writephy(tp, 0x0e, 0x0000);
1733                 }
1734         }
1735
1736         rc = 0;
1737 out:
1738         return rc;
1739 }
1740
1741 static int rtl8169_set_speed(struct net_device *dev,
1742                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1743 {
1744         struct rtl8169_private *tp = netdev_priv(dev);
1745         int ret;
1746
1747         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1748         if (ret < 0)
1749                 goto out;
1750
1751         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1752             (advertising & ADVERTISED_1000baseT_Full)) {
1753                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1754         }
1755 out:
1756         return ret;
1757 }
1758
1759 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1760 {
1761         struct rtl8169_private *tp = netdev_priv(dev);
1762         int ret;
1763
1764         del_timer_sync(&tp->timer);
1765
1766         rtl_lock_work(tp);
1767         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1768                                 cmd->duplex, cmd->advertising);
1769         rtl_unlock_work(tp);
1770
1771         return ret;
1772 }
1773
1774 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1775         netdev_features_t features)
1776 {
1777         struct rtl8169_private *tp = netdev_priv(dev);
1778
1779         if (dev->mtu > TD_MSS_MAX)
1780                 features &= ~NETIF_F_ALL_TSO;
1781
1782         if (dev->mtu > JUMBO_1K &&
1783             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1784                 features &= ~NETIF_F_IP_CSUM;
1785
1786         return features;
1787 }
1788
1789 static void __rtl8169_set_features(struct net_device *dev,
1790                                    netdev_features_t features)
1791 {
1792         struct rtl8169_private *tp = netdev_priv(dev);
1793         netdev_features_t changed = features ^ dev->features;
1794         void __iomem *ioaddr = tp->mmio_addr;
1795
1796         if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM |
1797                          NETIF_F_HW_VLAN_CTAG_RX)))
1798                 return;
1799
1800         if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX)) {
1801                 if (features & NETIF_F_RXCSUM)
1802                         tp->cp_cmd |= RxChkSum;
1803                 else
1804                         tp->cp_cmd &= ~RxChkSum;
1805
1806                 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
1807                         tp->cp_cmd |= RxVlan;
1808                 else
1809                         tp->cp_cmd &= ~RxVlan;
1810
1811                 RTL_W16(CPlusCmd, tp->cp_cmd);
1812                 RTL_R16(CPlusCmd);
1813         }
1814         if (changed & NETIF_F_RXALL) {
1815                 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1816                 if (features & NETIF_F_RXALL)
1817                         tmp |= (AcceptErr | AcceptRunt);
1818                 RTL_W32(RxConfig, tmp);
1819         }
1820 }
1821
1822 static int rtl8169_set_features(struct net_device *dev,
1823                                 netdev_features_t features)
1824 {
1825         struct rtl8169_private *tp = netdev_priv(dev);
1826
1827         rtl_lock_work(tp);
1828         __rtl8169_set_features(dev, features);
1829         rtl_unlock_work(tp);
1830
1831         return 0;
1832 }
1833
1834
1835 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1836 {
1837         return (vlan_tx_tag_present(skb)) ?
1838                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1839 }
1840
1841 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1842 {
1843         u32 opts2 = le32_to_cpu(desc->opts2);
1844
1845         if (opts2 & RxVlanTag)
1846                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1847 }
1848
1849 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1850 {
1851         struct rtl8169_private *tp = netdev_priv(dev);
1852         void __iomem *ioaddr = tp->mmio_addr;
1853         u32 status;
1854
1855         cmd->supported =
1856                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1857         cmd->port = PORT_FIBRE;
1858         cmd->transceiver = XCVR_INTERNAL;
1859
1860         status = RTL_R32(TBICSR);
1861         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1862         cmd->autoneg = !!(status & TBINwEnable);
1863
1864         ethtool_cmd_speed_set(cmd, SPEED_1000);
1865         cmd->duplex = DUPLEX_FULL; /* Always set */
1866
1867         return 0;
1868 }
1869
1870 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1871 {
1872         struct rtl8169_private *tp = netdev_priv(dev);
1873
1874         return mii_ethtool_gset(&tp->mii, cmd);
1875 }
1876
1877 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1878 {
1879         struct rtl8169_private *tp = netdev_priv(dev);
1880         int rc;
1881
1882         rtl_lock_work(tp);
1883         rc = tp->get_settings(dev, cmd);
1884         rtl_unlock_work(tp);
1885
1886         return rc;
1887 }
1888
1889 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1890                              void *p)
1891 {
1892         struct rtl8169_private *tp = netdev_priv(dev);
1893
1894         if (regs->len > R8169_REGS_SIZE)
1895                 regs->len = R8169_REGS_SIZE;
1896
1897         rtl_lock_work(tp);
1898         memcpy_fromio(p, tp->mmio_addr, regs->len);
1899         rtl_unlock_work(tp);
1900 }
1901
1902 static u32 rtl8169_get_msglevel(struct net_device *dev)
1903 {
1904         struct rtl8169_private *tp = netdev_priv(dev);
1905
1906         return tp->msg_enable;
1907 }
1908
1909 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1910 {
1911         struct rtl8169_private *tp = netdev_priv(dev);
1912
1913         tp->msg_enable = value;
1914 }
1915
1916 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1917         "tx_packets",
1918         "rx_packets",
1919         "tx_errors",
1920         "rx_errors",
1921         "rx_missed",
1922         "align_errors",
1923         "tx_single_collisions",
1924         "tx_multi_collisions",
1925         "unicast",
1926         "broadcast",
1927         "multicast",
1928         "tx_aborted",
1929         "tx_underrun",
1930 };
1931
1932 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1933 {
1934         switch (sset) {
1935         case ETH_SS_STATS:
1936                 return ARRAY_SIZE(rtl8169_gstrings);
1937         default:
1938                 return -EOPNOTSUPP;
1939         }
1940 }
1941
1942 DECLARE_RTL_COND(rtl_counters_cond)
1943 {
1944         void __iomem *ioaddr = tp->mmio_addr;
1945
1946         return RTL_R32(CounterAddrLow) & CounterDump;
1947 }
1948
1949 static void rtl8169_update_counters(struct net_device *dev)
1950 {
1951         struct rtl8169_private *tp = netdev_priv(dev);
1952         void __iomem *ioaddr = tp->mmio_addr;
1953         struct device *d = &tp->pci_dev->dev;
1954         struct rtl8169_counters *counters;
1955         dma_addr_t paddr;
1956         u32 cmd;
1957
1958         /*
1959          * Some chips are unable to dump tally counters when the receiver
1960          * is disabled.
1961          */
1962         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1963                 return;
1964
1965         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1966         if (!counters)
1967                 return;
1968
1969         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1970         cmd = (u64)paddr & DMA_BIT_MASK(32);
1971         RTL_W32(CounterAddrLow, cmd);
1972         RTL_W32(CounterAddrLow, cmd | CounterDump);
1973
1974         if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1975                 memcpy(&tp->counters, counters, sizeof(*counters));
1976
1977         RTL_W32(CounterAddrLow, 0);
1978         RTL_W32(CounterAddrHigh, 0);
1979
1980         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1981 }
1982
1983 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1984                                       struct ethtool_stats *stats, u64 *data)
1985 {
1986         struct rtl8169_private *tp = netdev_priv(dev);
1987
1988         ASSERT_RTNL();
1989
1990         rtl8169_update_counters(dev);
1991
1992         data[0] = le64_to_cpu(tp->counters.tx_packets);
1993         data[1] = le64_to_cpu(tp->counters.rx_packets);
1994         data[2] = le64_to_cpu(tp->counters.tx_errors);
1995         data[3] = le32_to_cpu(tp->counters.rx_errors);
1996         data[4] = le16_to_cpu(tp->counters.rx_missed);
1997         data[5] = le16_to_cpu(tp->counters.align_errors);
1998         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1999         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
2000         data[8] = le64_to_cpu(tp->counters.rx_unicast);
2001         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
2002         data[10] = le32_to_cpu(tp->counters.rx_multicast);
2003         data[11] = le16_to_cpu(tp->counters.tx_aborted);
2004         data[12] = le16_to_cpu(tp->counters.tx_underun);
2005 }
2006
2007 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2008 {
2009         switch(stringset) {
2010         case ETH_SS_STATS:
2011                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2012                 break;
2013         }
2014 }
2015
2016 static const struct ethtool_ops rtl8169_ethtool_ops = {
2017         .get_drvinfo            = rtl8169_get_drvinfo,
2018         .get_regs_len           = rtl8169_get_regs_len,
2019         .get_link               = ethtool_op_get_link,
2020         .get_settings           = rtl8169_get_settings,
2021         .set_settings           = rtl8169_set_settings,
2022         .get_msglevel           = rtl8169_get_msglevel,
2023         .set_msglevel           = rtl8169_set_msglevel,
2024         .get_regs               = rtl8169_get_regs,
2025         .get_wol                = rtl8169_get_wol,
2026         .set_wol                = rtl8169_set_wol,
2027         .get_strings            = rtl8169_get_strings,
2028         .get_sset_count         = rtl8169_get_sset_count,
2029         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2030         .get_ts_info            = ethtool_op_get_ts_info,
2031 };
2032
2033 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2034                                     struct net_device *dev, u8 default_version)
2035 {
2036         void __iomem *ioaddr = tp->mmio_addr;
2037         /*
2038          * The driver currently handles the 8168Bf and the 8168Be identically
2039          * but they can be identified more specifically through the test below
2040          * if needed:
2041          *
2042          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2043          *
2044          * Same thing for the 8101Eb and the 8101Ec:
2045          *
2046          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2047          */
2048         static const struct rtl_mac_info {
2049                 u32 mask;
2050                 u32 val;
2051                 int mac_version;
2052         } mac_info[] = {
2053                 /* 8168G family. */
2054                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2055                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2056                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2057
2058                 /* 8168F family. */
2059                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2060                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2061                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2062
2063                 /* 8168E family. */
2064                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2065                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
2066                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2067                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2068
2069                 /* 8168D family. */
2070                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
2071                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2072                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2073
2074                 /* 8168DP family. */
2075                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2076                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2077                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2078
2079                 /* 8168C family. */
2080                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
2081                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2082                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2083                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2084                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2085                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2086                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2087                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
2088                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2089
2090                 /* 8168B family. */
2091                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2092                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
2093                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2094                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2095
2096                 /* 8101 family. */
2097                 { 0x7cf00000, 0x44900000,       RTL_GIGA_MAC_VER_39 },
2098                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2099                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2100                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
2101                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
2102                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2103                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2104                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
2105                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
2106                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2107                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2108                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2109                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2110                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2111                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2112                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2113                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2114                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2115                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2116                 /* FIXME: where did these entries come from ? -- FR */
2117                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2118                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2119
2120                 /* 8110 family. */
2121                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2122                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2123                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2124                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2125                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2126                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2127
2128                 /* Catch-all */
2129                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2130         };
2131         const struct rtl_mac_info *p = mac_info;
2132         u32 reg;
2133
2134         reg = RTL_R32(TxConfig);
2135         while ((reg & p->mask) != p->val)
2136                 p++;
2137         tp->mac_version = p->mac_version;
2138
2139         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2140                 netif_notice(tp, probe, dev,
2141                              "unknown MAC, using family default\n");
2142                 tp->mac_version = default_version;
2143         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2144                 tp->mac_version = tp->mii.supports_gmii ?
2145                                   RTL_GIGA_MAC_VER_42 :
2146                                   RTL_GIGA_MAC_VER_43;
2147         }
2148 }
2149
2150 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2151 {
2152         dprintk("mac_version = 0x%02x\n", tp->mac_version);
2153 }
2154
2155 struct phy_reg {
2156         u16 reg;
2157         u16 val;
2158 };
2159
2160 static void rtl_writephy_batch(struct rtl8169_private *tp,
2161                                const struct phy_reg *regs, int len)
2162 {
2163         while (len-- > 0) {
2164                 rtl_writephy(tp, regs->reg, regs->val);
2165                 regs++;
2166         }
2167 }
2168
2169 #define PHY_READ                0x00000000
2170 #define PHY_DATA_OR             0x10000000
2171 #define PHY_DATA_AND            0x20000000
2172 #define PHY_BJMPN               0x30000000
2173 #define PHY_MDIO_CHG            0x40000000
2174 #define PHY_CLEAR_READCOUNT     0x70000000
2175 #define PHY_WRITE               0x80000000
2176 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2177 #define PHY_COMP_EQ_SKIPN       0xa0000000
2178 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2179 #define PHY_WRITE_PREVIOUS      0xc0000000
2180 #define PHY_SKIPN               0xd0000000
2181 #define PHY_DELAY_MS            0xe0000000
2182
2183 struct fw_info {
2184         u32     magic;
2185         char    version[RTL_VER_SIZE];
2186         __le32  fw_start;
2187         __le32  fw_len;
2188         u8      chksum;
2189 } __packed;
2190
2191 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2192
2193 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2194 {
2195         const struct firmware *fw = rtl_fw->fw;
2196         struct fw_info *fw_info = (struct fw_info *)fw->data;
2197         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2198         char *version = rtl_fw->version;
2199         bool rc = false;
2200
2201         if (fw->size < FW_OPCODE_SIZE)
2202                 goto out;
2203
2204         if (!fw_info->magic) {
2205                 size_t i, size, start;
2206                 u8 checksum = 0;
2207
2208                 if (fw->size < sizeof(*fw_info))
2209                         goto out;
2210
2211                 for (i = 0; i < fw->size; i++)
2212                         checksum += fw->data[i];
2213                 if (checksum != 0)
2214                         goto out;
2215
2216                 start = le32_to_cpu(fw_info->fw_start);
2217                 if (start > fw->size)
2218                         goto out;
2219
2220                 size = le32_to_cpu(fw_info->fw_len);
2221                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2222                         goto out;
2223
2224                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2225
2226                 pa->code = (__le32 *)(fw->data + start);
2227                 pa->size = size;
2228         } else {
2229                 if (fw->size % FW_OPCODE_SIZE)
2230                         goto out;
2231
2232                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2233
2234                 pa->code = (__le32 *)fw->data;
2235                 pa->size = fw->size / FW_OPCODE_SIZE;
2236         }
2237         version[RTL_VER_SIZE - 1] = 0;
2238
2239         rc = true;
2240 out:
2241         return rc;
2242 }
2243
2244 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2245                            struct rtl_fw_phy_action *pa)
2246 {
2247         bool rc = false;
2248         size_t index;
2249
2250         for (index = 0; index < pa->size; index++) {
2251                 u32 action = le32_to_cpu(pa->code[index]);
2252                 u32 regno = (action & 0x0fff0000) >> 16;
2253
2254                 switch(action & 0xf0000000) {
2255                 case PHY_READ:
2256                 case PHY_DATA_OR:
2257                 case PHY_DATA_AND:
2258                 case PHY_MDIO_CHG:
2259                 case PHY_CLEAR_READCOUNT:
2260                 case PHY_WRITE:
2261                 case PHY_WRITE_PREVIOUS:
2262                 case PHY_DELAY_MS:
2263                         break;
2264
2265                 case PHY_BJMPN:
2266                         if (regno > index) {
2267                                 netif_err(tp, ifup, tp->dev,
2268                                           "Out of range of firmware\n");
2269                                 goto out;
2270                         }
2271                         break;
2272                 case PHY_READCOUNT_EQ_SKIP:
2273                         if (index + 2 >= pa->size) {
2274                                 netif_err(tp, ifup, tp->dev,
2275                                           "Out of range of firmware\n");
2276                                 goto out;
2277                         }
2278                         break;
2279                 case PHY_COMP_EQ_SKIPN:
2280                 case PHY_COMP_NEQ_SKIPN:
2281                 case PHY_SKIPN:
2282                         if (index + 1 + regno >= pa->size) {
2283                                 netif_err(tp, ifup, tp->dev,
2284                                           "Out of range of firmware\n");
2285                                 goto out;
2286                         }
2287                         break;
2288
2289                 default:
2290                         netif_err(tp, ifup, tp->dev,
2291                                   "Invalid action 0x%08x\n", action);
2292                         goto out;
2293                 }
2294         }
2295         rc = true;
2296 out:
2297         return rc;
2298 }
2299
2300 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2301 {
2302         struct net_device *dev = tp->dev;
2303         int rc = -EINVAL;
2304
2305         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2306                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2307                 goto out;
2308         }
2309
2310         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2311                 rc = 0;
2312 out:
2313         return rc;
2314 }
2315
2316 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2317 {
2318         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2319         struct mdio_ops org, *ops = &tp->mdio_ops;
2320         u32 predata, count;
2321         size_t index;
2322
2323         predata = count = 0;
2324         org.write = ops->write;
2325         org.read = ops->read;
2326
2327         for (index = 0; index < pa->size; ) {
2328                 u32 action = le32_to_cpu(pa->code[index]);
2329                 u32 data = action & 0x0000ffff;
2330                 u32 regno = (action & 0x0fff0000) >> 16;
2331
2332                 if (!action)
2333                         break;
2334
2335                 switch(action & 0xf0000000) {
2336                 case PHY_READ:
2337                         predata = rtl_readphy(tp, regno);
2338                         count++;
2339                         index++;
2340                         break;
2341                 case PHY_DATA_OR:
2342                         predata |= data;
2343                         index++;
2344                         break;
2345                 case PHY_DATA_AND:
2346                         predata &= data;
2347                         index++;
2348                         break;
2349                 case PHY_BJMPN:
2350                         index -= regno;
2351                         break;
2352                 case PHY_MDIO_CHG:
2353                         if (data == 0) {
2354                                 ops->write = org.write;
2355                                 ops->read = org.read;
2356                         } else if (data == 1) {
2357                                 ops->write = mac_mcu_write;
2358                                 ops->read = mac_mcu_read;
2359                         }
2360
2361                         index++;
2362                         break;
2363                 case PHY_CLEAR_READCOUNT:
2364                         count = 0;
2365                         index++;
2366                         break;
2367                 case PHY_WRITE:
2368                         rtl_writephy(tp, regno, data);
2369                         index++;
2370                         break;
2371                 case PHY_READCOUNT_EQ_SKIP:
2372                         index += (count == data) ? 2 : 1;
2373                         break;
2374                 case PHY_COMP_EQ_SKIPN:
2375                         if (predata == data)
2376                                 index += regno;
2377                         index++;
2378                         break;
2379                 case PHY_COMP_NEQ_SKIPN:
2380                         if (predata != data)
2381                                 index += regno;
2382                         index++;
2383                         break;
2384                 case PHY_WRITE_PREVIOUS:
2385                         rtl_writephy(tp, regno, predata);
2386                         index++;
2387                         break;
2388                 case PHY_SKIPN:
2389                         index += regno + 1;
2390                         break;
2391                 case PHY_DELAY_MS:
2392                         mdelay(data);
2393                         index++;
2394                         break;
2395
2396                 default:
2397                         BUG();
2398                 }
2399         }
2400
2401         ops->write = org.write;
2402         ops->read = org.read;
2403 }
2404
2405 static void rtl_release_firmware(struct rtl8169_private *tp)
2406 {
2407         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2408                 release_firmware(tp->rtl_fw->fw);
2409                 kfree(tp->rtl_fw);
2410         }
2411         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2412 }
2413
2414 static void rtl_apply_firmware(struct rtl8169_private *tp)
2415 {
2416         struct rtl_fw *rtl_fw = tp->rtl_fw;
2417
2418         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2419         if (!IS_ERR_OR_NULL(rtl_fw))
2420                 rtl_phy_write_fw(tp, rtl_fw);
2421 }
2422
2423 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2424 {
2425         if (rtl_readphy(tp, reg) != val)
2426                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2427         else
2428                 rtl_apply_firmware(tp);
2429 }
2430
2431 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2432 {
2433         static const struct phy_reg phy_reg_init[] = {
2434                 { 0x1f, 0x0001 },
2435                 { 0x06, 0x006e },
2436                 { 0x08, 0x0708 },
2437                 { 0x15, 0x4000 },
2438                 { 0x18, 0x65c7 },
2439
2440                 { 0x1f, 0x0001 },
2441                 { 0x03, 0x00a1 },
2442                 { 0x02, 0x0008 },
2443                 { 0x01, 0x0120 },
2444                 { 0x00, 0x1000 },
2445                 { 0x04, 0x0800 },
2446                 { 0x04, 0x0000 },
2447
2448                 { 0x03, 0xff41 },
2449                 { 0x02, 0xdf60 },
2450                 { 0x01, 0x0140 },
2451                 { 0x00, 0x0077 },
2452                 { 0x04, 0x7800 },
2453                 { 0x04, 0x7000 },
2454
2455                 { 0x03, 0x802f },
2456                 { 0x02, 0x4f02 },
2457                 { 0x01, 0x0409 },
2458                 { 0x00, 0xf0f9 },
2459                 { 0x04, 0x9800 },
2460                 { 0x04, 0x9000 },
2461
2462                 { 0x03, 0xdf01 },
2463                 { 0x02, 0xdf20 },
2464                 { 0x01, 0xff95 },
2465                 { 0x00, 0xba00 },
2466                 { 0x04, 0xa800 },
2467                 { 0x04, 0xa000 },
2468
2469                 { 0x03, 0xff41 },
2470                 { 0x02, 0xdf20 },
2471                 { 0x01, 0x0140 },
2472                 { 0x00, 0x00bb },
2473                 { 0x04, 0xb800 },
2474                 { 0x04, 0xb000 },
2475
2476                 { 0x03, 0xdf41 },
2477                 { 0x02, 0xdc60 },
2478                 { 0x01, 0x6340 },
2479                 { 0x00, 0x007d },
2480                 { 0x04, 0xd800 },
2481                 { 0x04, 0xd000 },
2482
2483                 { 0x03, 0xdf01 },
2484                 { 0x02, 0xdf20 },
2485                 { 0x01, 0x100a },
2486                 { 0x00, 0xa0ff },
2487                 { 0x04, 0xf800 },
2488                 { 0x04, 0xf000 },
2489
2490                 { 0x1f, 0x0000 },
2491                 { 0x0b, 0x0000 },
2492                 { 0x00, 0x9200 }
2493         };
2494
2495         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2496 }
2497
2498 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2499 {
2500         static const struct phy_reg phy_reg_init[] = {
2501                 { 0x1f, 0x0002 },
2502                 { 0x01, 0x90d0 },
2503                 { 0x1f, 0x0000 }
2504         };
2505
2506         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2507 }
2508
2509 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2510 {
2511         struct pci_dev *pdev = tp->pci_dev;
2512
2513         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2514             (pdev->subsystem_device != 0xe000))
2515                 return;
2516
2517         rtl_writephy(tp, 0x1f, 0x0001);
2518         rtl_writephy(tp, 0x10, 0xf01b);
2519         rtl_writephy(tp, 0x1f, 0x0000);
2520 }
2521
2522 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2523 {
2524         static const struct phy_reg phy_reg_init[] = {
2525                 { 0x1f, 0x0001 },
2526                 { 0x04, 0x0000 },
2527                 { 0x03, 0x00a1 },
2528                 { 0x02, 0x0008 },
2529                 { 0x01, 0x0120 },
2530                 { 0x00, 0x1000 },
2531                 { 0x04, 0x0800 },
2532                 { 0x04, 0x9000 },
2533                 { 0x03, 0x802f },
2534                 { 0x02, 0x4f02 },
2535                 { 0x01, 0x0409 },
2536                 { 0x00, 0xf099 },
2537                 { 0x04, 0x9800 },
2538                 { 0x04, 0xa000 },
2539                 { 0x03, 0xdf01 },
2540                 { 0x02, 0xdf20 },
2541                 { 0x01, 0xff95 },
2542                 { 0x00, 0xba00 },
2543                 { 0x04, 0xa800 },
2544                 { 0x04, 0xf000 },
2545                 { 0x03, 0xdf01 },
2546                 { 0x02, 0xdf20 },
2547                 { 0x01, 0x101a },
2548                 { 0x00, 0xa0ff },
2549                 { 0x04, 0xf800 },
2550                 { 0x04, 0x0000 },
2551                 { 0x1f, 0x0000 },
2552
2553                 { 0x1f, 0x0001 },
2554                 { 0x10, 0xf41b },
2555                 { 0x14, 0xfb54 },
2556                 { 0x18, 0xf5c7 },
2557                 { 0x1f, 0x0000 },
2558
2559                 { 0x1f, 0x0001 },
2560                 { 0x17, 0x0cc0 },
2561                 { 0x1f, 0x0000 }
2562         };
2563
2564         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2565
2566         rtl8169scd_hw_phy_config_quirk(tp);
2567 }
2568
2569 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2570 {
2571         static const struct phy_reg phy_reg_init[] = {
2572                 { 0x1f, 0x0001 },
2573                 { 0x04, 0x0000 },
2574                 { 0x03, 0x00a1 },
2575                 { 0x02, 0x0008 },
2576                 { 0x01, 0x0120 },
2577                 { 0x00, 0x1000 },
2578                 { 0x04, 0x0800 },
2579                 { 0x04, 0x9000 },
2580                 { 0x03, 0x802f },
2581                 { 0x02, 0x4f02 },
2582                 { 0x01, 0x0409 },
2583                 { 0x00, 0xf099 },
2584                 { 0x04, 0x9800 },
2585                 { 0x04, 0xa000 },
2586                 { 0x03, 0xdf01 },
2587                 { 0x02, 0xdf20 },
2588                 { 0x01, 0xff95 },
2589                 { 0x00, 0xba00 },
2590                 { 0x04, 0xa800 },
2591                 { 0x04, 0xf000 },
2592                 { 0x03, 0xdf01 },
2593                 { 0x02, 0xdf20 },
2594                 { 0x01, 0x101a },
2595                 { 0x00, 0xa0ff },
2596                 { 0x04, 0xf800 },
2597                 { 0x04, 0x0000 },
2598                 { 0x1f, 0x0000 },
2599
2600                 { 0x1f, 0x0001 },
2601                 { 0x0b, 0x8480 },
2602                 { 0x1f, 0x0000 },
2603
2604                 { 0x1f, 0x0001 },
2605                 { 0x18, 0x67c7 },
2606                 { 0x04, 0x2000 },
2607                 { 0x03, 0x002f },
2608                 { 0x02, 0x4360 },
2609                 { 0x01, 0x0109 },
2610                 { 0x00, 0x3022 },
2611                 { 0x04, 0x2800 },
2612                 { 0x1f, 0x0000 },
2613
2614                 { 0x1f, 0x0001 },
2615                 { 0x17, 0x0cc0 },
2616                 { 0x1f, 0x0000 }
2617         };
2618
2619         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2620 }
2621
2622 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2623 {
2624         static const struct phy_reg phy_reg_init[] = {
2625                 { 0x10, 0xf41b },
2626                 { 0x1f, 0x0000 }
2627         };
2628
2629         rtl_writephy(tp, 0x1f, 0x0001);
2630         rtl_patchphy(tp, 0x16, 1 << 0);
2631
2632         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2633 }
2634
2635 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2636 {
2637         static const struct phy_reg phy_reg_init[] = {
2638                 { 0x1f, 0x0001 },
2639                 { 0x10, 0xf41b },
2640                 { 0x1f, 0x0000 }
2641         };
2642
2643         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2644 }
2645
2646 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2647 {
2648         static const struct phy_reg phy_reg_init[] = {
2649                 { 0x1f, 0x0000 },
2650                 { 0x1d, 0x0f00 },
2651                 { 0x1f, 0x0002 },
2652                 { 0x0c, 0x1ec8 },
2653                 { 0x1f, 0x0000 }
2654         };
2655
2656         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2657 }
2658
2659 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2660 {
2661         static const struct phy_reg phy_reg_init[] = {
2662                 { 0x1f, 0x0001 },
2663                 { 0x1d, 0x3d98 },
2664                 { 0x1f, 0x0000 }
2665         };
2666
2667         rtl_writephy(tp, 0x1f, 0x0000);
2668         rtl_patchphy(tp, 0x14, 1 << 5);
2669         rtl_patchphy(tp, 0x0d, 1 << 5);
2670
2671         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2672 }
2673
2674 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2675 {
2676         static const struct phy_reg phy_reg_init[] = {
2677                 { 0x1f, 0x0001 },
2678                 { 0x12, 0x2300 },
2679                 { 0x1f, 0x0002 },
2680                 { 0x00, 0x88d4 },
2681                 { 0x01, 0x82b1 },
2682                 { 0x03, 0x7002 },
2683                 { 0x08, 0x9e30 },
2684                 { 0x09, 0x01f0 },
2685                 { 0x0a, 0x5500 },
2686                 { 0x0c, 0x00c8 },
2687                 { 0x1f, 0x0003 },
2688                 { 0x12, 0xc096 },
2689                 { 0x16, 0x000a },
2690                 { 0x1f, 0x0000 },
2691                 { 0x1f, 0x0000 },
2692                 { 0x09, 0x2000 },
2693                 { 0x09, 0x0000 }
2694         };
2695
2696         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2697
2698         rtl_patchphy(tp, 0x14, 1 << 5);
2699         rtl_patchphy(tp, 0x0d, 1 << 5);
2700         rtl_writephy(tp, 0x1f, 0x0000);
2701 }
2702
2703 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2704 {
2705         static const struct phy_reg phy_reg_init[] = {
2706                 { 0x1f, 0x0001 },
2707                 { 0x12, 0x2300 },
2708                 { 0x03, 0x802f },
2709                 { 0x02, 0x4f02 },
2710                 { 0x01, 0x0409 },
2711                 { 0x00, 0xf099 },
2712                 { 0x04, 0x9800 },
2713                 { 0x04, 0x9000 },
2714                 { 0x1d, 0x3d98 },
2715                 { 0x1f, 0x0002 },
2716                 { 0x0c, 0x7eb8 },
2717                 { 0x06, 0x0761 },
2718                 { 0x1f, 0x0003 },
2719                 { 0x16, 0x0f0a },
2720                 { 0x1f, 0x0000 }
2721         };
2722
2723         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2724
2725         rtl_patchphy(tp, 0x16, 1 << 0);
2726         rtl_patchphy(tp, 0x14, 1 << 5);
2727         rtl_patchphy(tp, 0x0d, 1 << 5);
2728         rtl_writephy(tp, 0x1f, 0x0000);
2729 }
2730
2731 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2732 {
2733         static const struct phy_reg phy_reg_init[] = {
2734                 { 0x1f, 0x0001 },
2735                 { 0x12, 0x2300 },
2736                 { 0x1d, 0x3d98 },
2737                 { 0x1f, 0x0002 },
2738                 { 0x0c, 0x7eb8 },
2739                 { 0x06, 0x5461 },
2740                 { 0x1f, 0x0003 },
2741                 { 0x16, 0x0f0a },
2742                 { 0x1f, 0x0000 }
2743         };
2744
2745         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2746
2747         rtl_patchphy(tp, 0x16, 1 << 0);
2748         rtl_patchphy(tp, 0x14, 1 << 5);
2749         rtl_patchphy(tp, 0x0d, 1 << 5);
2750         rtl_writephy(tp, 0x1f, 0x0000);
2751 }
2752
2753 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2754 {
2755         rtl8168c_3_hw_phy_config(tp);
2756 }
2757
2758 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2759 {
2760         static const struct phy_reg phy_reg_init_0[] = {
2761                 /* Channel Estimation */
2762                 { 0x1f, 0x0001 },
2763                 { 0x06, 0x4064 },
2764                 { 0x07, 0x2863 },
2765                 { 0x08, 0x059c },
2766                 { 0x09, 0x26b4 },
2767                 { 0x0a, 0x6a19 },
2768                 { 0x0b, 0xdcc8 },
2769                 { 0x10, 0xf06d },
2770                 { 0x14, 0x7f68 },
2771                 { 0x18, 0x7fd9 },
2772                 { 0x1c, 0xf0ff },
2773                 { 0x1d, 0x3d9c },
2774                 { 0x1f, 0x0003 },
2775                 { 0x12, 0xf49f },
2776                 { 0x13, 0x070b },
2777                 { 0x1a, 0x05ad },
2778                 { 0x14, 0x94c0 },
2779
2780                 /*
2781                  * Tx Error Issue
2782                  * Enhance line driver power
2783                  */
2784                 { 0x1f, 0x0002 },
2785                 { 0x06, 0x5561 },
2786                 { 0x1f, 0x0005 },
2787                 { 0x05, 0x8332 },
2788                 { 0x06, 0x5561 },
2789
2790                 /*
2791                  * Can not link to 1Gbps with bad cable
2792                  * Decrease SNR threshold form 21.07dB to 19.04dB
2793                  */
2794                 { 0x1f, 0x0001 },
2795                 { 0x17, 0x0cc0 },
2796
2797                 { 0x1f, 0x0000 },
2798                 { 0x0d, 0xf880 }
2799         };
2800
2801         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2802
2803         /*
2804          * Rx Error Issue
2805          * Fine Tune Switching regulator parameter
2806          */
2807         rtl_writephy(tp, 0x1f, 0x0002);
2808         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2809         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2810
2811         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2812                 static const struct phy_reg phy_reg_init[] = {
2813                         { 0x1f, 0x0002 },
2814                         { 0x05, 0x669a },
2815                         { 0x1f, 0x0005 },
2816                         { 0x05, 0x8330 },
2817                         { 0x06, 0x669a },
2818                         { 0x1f, 0x0002 }
2819                 };
2820                 int val;
2821
2822                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2823
2824                 val = rtl_readphy(tp, 0x0d);
2825
2826                 if ((val & 0x00ff) != 0x006c) {
2827                         static const u32 set[] = {
2828                                 0x0065, 0x0066, 0x0067, 0x0068,
2829                                 0x0069, 0x006a, 0x006b, 0x006c
2830                         };
2831                         int i;
2832
2833                         rtl_writephy(tp, 0x1f, 0x0002);
2834
2835                         val &= 0xff00;
2836                         for (i = 0; i < ARRAY_SIZE(set); i++)
2837                                 rtl_writephy(tp, 0x0d, val | set[i]);
2838                 }
2839         } else {
2840                 static const struct phy_reg phy_reg_init[] = {
2841                         { 0x1f, 0x0002 },
2842                         { 0x05, 0x6662 },
2843                         { 0x1f, 0x0005 },
2844                         { 0x05, 0x8330 },
2845                         { 0x06, 0x6662 }
2846                 };
2847
2848                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2849         }
2850
2851         /* RSET couple improve */
2852         rtl_writephy(tp, 0x1f, 0x0002);
2853         rtl_patchphy(tp, 0x0d, 0x0300);
2854         rtl_patchphy(tp, 0x0f, 0x0010);
2855
2856         /* Fine tune PLL performance */
2857         rtl_writephy(tp, 0x1f, 0x0002);
2858         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2859         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2860
2861         rtl_writephy(tp, 0x1f, 0x0005);
2862         rtl_writephy(tp, 0x05, 0x001b);
2863
2864         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2865
2866         rtl_writephy(tp, 0x1f, 0x0000);
2867 }
2868
2869 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2870 {
2871         static const struct phy_reg phy_reg_init_0[] = {
2872                 /* Channel Estimation */
2873                 { 0x1f, 0x0001 },
2874                 { 0x06, 0x4064 },
2875                 { 0x07, 0x2863 },
2876                 { 0x08, 0x059c },
2877                 { 0x09, 0x26b4 },
2878                 { 0x0a, 0x6a19 },
2879                 { 0x0b, 0xdcc8 },
2880                 { 0x10, 0xf06d },
2881                 { 0x14, 0x7f68 },
2882                 { 0x18, 0x7fd9 },
2883                 { 0x1c, 0xf0ff },
2884                 { 0x1d, 0x3d9c },
2885                 { 0x1f, 0x0003 },
2886                 { 0x12, 0xf49f },
2887                 { 0x13, 0x070b },
2888                 { 0x1a, 0x05ad },
2889                 { 0x14, 0x94c0 },
2890
2891                 /*
2892                  * Tx Error Issue
2893                  * Enhance line driver power
2894                  */
2895                 { 0x1f, 0x0002 },
2896                 { 0x06, 0x5561 },
2897                 { 0x1f, 0x0005 },
2898                 { 0x05, 0x8332 },
2899                 { 0x06, 0x5561 },
2900
2901                 /*
2902                  * Can not link to 1Gbps with bad cable
2903                  * Decrease SNR threshold form 21.07dB to 19.04dB
2904                  */
2905                 { 0x1f, 0x0001 },
2906                 { 0x17, 0x0cc0 },
2907
2908                 { 0x1f, 0x0000 },
2909                 { 0x0d, 0xf880 }
2910         };
2911
2912         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2913
2914         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2915                 static const struct phy_reg phy_reg_init[] = {
2916                         { 0x1f, 0x0002 },
2917                         { 0x05, 0x669a },
2918                         { 0x1f, 0x0005 },
2919                         { 0x05, 0x8330 },
2920                         { 0x06, 0x669a },
2921
2922                         { 0x1f, 0x0002 }
2923                 };
2924                 int val;
2925
2926                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2927
2928                 val = rtl_readphy(tp, 0x0d);
2929                 if ((val & 0x00ff) != 0x006c) {
2930                         static const u32 set[] = {
2931                                 0x0065, 0x0066, 0x0067, 0x0068,
2932                                 0x0069, 0x006a, 0x006b, 0x006c
2933                         };
2934                         int i;
2935
2936                         rtl_writephy(tp, 0x1f, 0x0002);
2937
2938                         val &= 0xff00;
2939                         for (i = 0; i < ARRAY_SIZE(set); i++)
2940                                 rtl_writephy(tp, 0x0d, val | set[i]);
2941                 }
2942         } else {
2943                 static const struct phy_reg phy_reg_init[] = {
2944                         { 0x1f, 0x0002 },
2945                         { 0x05, 0x2642 },
2946                         { 0x1f, 0x0005 },
2947                         { 0x05, 0x8330 },
2948                         { 0x06, 0x2642 }
2949                 };
2950
2951                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2952         }
2953
2954         /* Fine tune PLL performance */
2955         rtl_writephy(tp, 0x1f, 0x0002);
2956         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2957         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2958
2959         /* Switching regulator Slew rate */
2960         rtl_writephy(tp, 0x1f, 0x0002);
2961         rtl_patchphy(tp, 0x0f, 0x0017);
2962
2963         rtl_writephy(tp, 0x1f, 0x0005);
2964         rtl_writephy(tp, 0x05, 0x001b);
2965
2966         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2967
2968         rtl_writephy(tp, 0x1f, 0x0000);
2969 }
2970
2971 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2972 {
2973         static const struct phy_reg phy_reg_init[] = {
2974                 { 0x1f, 0x0002 },
2975                 { 0x10, 0x0008 },
2976                 { 0x0d, 0x006c },
2977
2978                 { 0x1f, 0x0000 },
2979                 { 0x0d, 0xf880 },
2980
2981                 { 0x1f, 0x0001 },
2982                 { 0x17, 0x0cc0 },
2983
2984                 { 0x1f, 0x0001 },
2985                 { 0x0b, 0xa4d8 },
2986                 { 0x09, 0x281c },
2987                 { 0x07, 0x2883 },
2988                 { 0x0a, 0x6b35 },
2989                 { 0x1d, 0x3da4 },
2990                 { 0x1c, 0xeffd },
2991                 { 0x14, 0x7f52 },
2992                 { 0x18, 0x7fc6 },
2993                 { 0x08, 0x0601 },
2994                 { 0x06, 0x4063 },
2995                 { 0x10, 0xf074 },
2996                 { 0x1f, 0x0003 },
2997                 { 0x13, 0x0789 },
2998                 { 0x12, 0xf4bd },
2999                 { 0x1a, 0x04fd },
3000                 { 0x14, 0x84b0 },
3001                 { 0x1f, 0x0000 },
3002                 { 0x00, 0x9200 },
3003
3004                 { 0x1f, 0x0005 },
3005                 { 0x01, 0x0340 },
3006                 { 0x1f, 0x0001 },
3007                 { 0x04, 0x4000 },
3008                 { 0x03, 0x1d21 },
3009                 { 0x02, 0x0c32 },
3010                 { 0x01, 0x0200 },
3011                 { 0x00, 0x5554 },
3012                 { 0x04, 0x4800 },
3013                 { 0x04, 0x4000 },
3014                 { 0x04, 0xf000 },
3015                 { 0x03, 0xdf01 },
3016                 { 0x02, 0xdf20 },
3017                 { 0x01, 0x101a },
3018                 { 0x00, 0xa0ff },
3019                 { 0x04, 0xf800 },
3020                 { 0x04, 0xf000 },
3021                 { 0x1f, 0x0000 },
3022
3023                 { 0x1f, 0x0007 },
3024                 { 0x1e, 0x0023 },
3025                 { 0x16, 0x0000 },
3026                 { 0x1f, 0x0000 }
3027         };
3028
3029         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3030 }
3031
3032 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3033 {
3034         static const struct phy_reg phy_reg_init[] = {
3035                 { 0x1f, 0x0001 },
3036                 { 0x17, 0x0cc0 },
3037
3038                 { 0x1f, 0x0007 },
3039                 { 0x1e, 0x002d },
3040                 { 0x18, 0x0040 },
3041                 { 0x1f, 0x0000 }
3042         };
3043
3044         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3045         rtl_patchphy(tp, 0x0d, 1 << 5);
3046 }
3047
3048 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3049 {
3050         static const struct phy_reg phy_reg_init[] = {
3051                 /* Enable Delay cap */
3052                 { 0x1f, 0x0005 },
3053                 { 0x05, 0x8b80 },
3054                 { 0x06, 0xc896 },
3055                 { 0x1f, 0x0000 },
3056
3057                 /* Channel estimation fine tune */
3058                 { 0x1f, 0x0001 },
3059                 { 0x0b, 0x6c20 },
3060                 { 0x07, 0x2872 },
3061                 { 0x1c, 0xefff },
3062                 { 0x1f, 0x0003 },
3063                 { 0x14, 0x6420 },
3064                 { 0x1f, 0x0000 },
3065
3066                 /* Update PFM & 10M TX idle timer */
3067                 { 0x1f, 0x0007 },
3068                 { 0x1e, 0x002f },
3069                 { 0x15, 0x1919 },
3070                 { 0x1f, 0x0000 },
3071
3072                 { 0x1f, 0x0007 },
3073                 { 0x1e, 0x00ac },
3074                 { 0x18, 0x0006 },
3075                 { 0x1f, 0x0000 }
3076         };
3077
3078         rtl_apply_firmware(tp);
3079
3080         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3081
3082         /* DCO enable for 10M IDLE Power */
3083         rtl_writephy(tp, 0x1f, 0x0007);
3084         rtl_writephy(tp, 0x1e, 0x0023);
3085         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3086         rtl_writephy(tp, 0x1f, 0x0000);
3087
3088         /* For impedance matching */
3089         rtl_writephy(tp, 0x1f, 0x0002);
3090         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
3091         rtl_writephy(tp, 0x1f, 0x0000);
3092
3093         /* PHY auto speed down */
3094         rtl_writephy(tp, 0x1f, 0x0007);
3095         rtl_writephy(tp, 0x1e, 0x002d);
3096         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3097         rtl_writephy(tp, 0x1f, 0x0000);
3098         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3099
3100         rtl_writephy(tp, 0x1f, 0x0005);
3101         rtl_writephy(tp, 0x05, 0x8b86);
3102         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3103         rtl_writephy(tp, 0x1f, 0x0000);
3104
3105         rtl_writephy(tp, 0x1f, 0x0005);
3106         rtl_writephy(tp, 0x05, 0x8b85);
3107         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3108         rtl_writephy(tp, 0x1f, 0x0007);
3109         rtl_writephy(tp, 0x1e, 0x0020);
3110         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3111         rtl_writephy(tp, 0x1f, 0x0006);
3112         rtl_writephy(tp, 0x00, 0x5a00);
3113         rtl_writephy(tp, 0x1f, 0x0000);
3114         rtl_writephy(tp, 0x0d, 0x0007);
3115         rtl_writephy(tp, 0x0e, 0x003c);
3116         rtl_writephy(tp, 0x0d, 0x4007);
3117         rtl_writephy(tp, 0x0e, 0x0000);
3118         rtl_writephy(tp, 0x0d, 0x0000);
3119 }
3120
3121 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3122 {
3123         const u16 w[] = {
3124                 addr[0] | (addr[1] << 8),
3125                 addr[2] | (addr[3] << 8),
3126                 addr[4] | (addr[5] << 8)
3127         };
3128         const struct exgmac_reg e[] = {
3129                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3130                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3131                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3132                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3133         };
3134
3135         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3136 }
3137
3138 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3139 {
3140         static const struct phy_reg phy_reg_init[] = {
3141                 /* Enable Delay cap */
3142                 { 0x1f, 0x0004 },
3143                 { 0x1f, 0x0007 },
3144                 { 0x1e, 0x00ac },
3145                 { 0x18, 0x0006 },
3146                 { 0x1f, 0x0002 },
3147                 { 0x1f, 0x0000 },
3148                 { 0x1f, 0x0000 },
3149
3150                 /* Channel estimation fine tune */
3151                 { 0x1f, 0x0003 },
3152                 { 0x09, 0xa20f },
3153                 { 0x1f, 0x0000 },
3154                 { 0x1f, 0x0000 },
3155
3156                 /* Green Setting */
3157                 { 0x1f, 0x0005 },
3158                 { 0x05, 0x8b5b },
3159                 { 0x06, 0x9222 },
3160                 { 0x05, 0x8b6d },
3161                 { 0x06, 0x8000 },
3162                 { 0x05, 0x8b76 },
3163                 { 0x06, 0x8000 },
3164                 { 0x1f, 0x0000 }
3165         };
3166
3167         rtl_apply_firmware(tp);
3168
3169         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3170
3171         /* For 4-corner performance improve */
3172         rtl_writephy(tp, 0x1f, 0x0005);
3173         rtl_writephy(tp, 0x05, 0x8b80);
3174         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3175         rtl_writephy(tp, 0x1f, 0x0000);
3176
3177         /* PHY auto speed down */
3178         rtl_writephy(tp, 0x1f, 0x0004);
3179         rtl_writephy(tp, 0x1f, 0x0007);
3180         rtl_writephy(tp, 0x1e, 0x002d);
3181         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3182         rtl_writephy(tp, 0x1f, 0x0002);
3183         rtl_writephy(tp, 0x1f, 0x0000);
3184         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3185
3186         /* improve 10M EEE waveform */
3187         rtl_writephy(tp, 0x1f, 0x0005);
3188         rtl_writephy(tp, 0x05, 0x8b86);
3189         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3190         rtl_writephy(tp, 0x1f, 0x0000);
3191
3192         /* Improve 2-pair detection performance */
3193         rtl_writephy(tp, 0x1f, 0x0005);
3194         rtl_writephy(tp, 0x05, 0x8b85);
3195         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3196         rtl_writephy(tp, 0x1f, 0x0000);
3197
3198         /* EEE setting */
3199         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3200         rtl_writephy(tp, 0x1f, 0x0005);
3201         rtl_writephy(tp, 0x05, 0x8b85);
3202         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3203         rtl_writephy(tp, 0x1f, 0x0004);
3204         rtl_writephy(tp, 0x1f, 0x0007);
3205         rtl_writephy(tp, 0x1e, 0x0020);
3206         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3207         rtl_writephy(tp, 0x1f, 0x0002);
3208         rtl_writephy(tp, 0x1f, 0x0000);
3209         rtl_writephy(tp, 0x0d, 0x0007);
3210         rtl_writephy(tp, 0x0e, 0x003c);
3211         rtl_writephy(tp, 0x0d, 0x4007);
3212         rtl_writephy(tp, 0x0e, 0x0000);
3213         rtl_writephy(tp, 0x0d, 0x0000);
3214
3215         /* Green feature */
3216         rtl_writephy(tp, 0x1f, 0x0003);
3217         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3218         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3219         rtl_writephy(tp, 0x1f, 0x0000);
3220
3221         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3222         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3223 }
3224
3225 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3226 {
3227         /* For 4-corner performance improve */
3228         rtl_writephy(tp, 0x1f, 0x0005);
3229         rtl_writephy(tp, 0x05, 0x8b80);
3230         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3231         rtl_writephy(tp, 0x1f, 0x0000);
3232
3233         /* PHY auto speed down */
3234         rtl_writephy(tp, 0x1f, 0x0007);
3235         rtl_writephy(tp, 0x1e, 0x002d);
3236         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3237         rtl_writephy(tp, 0x1f, 0x0000);
3238         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3239
3240         /* Improve 10M EEE waveform */
3241         rtl_writephy(tp, 0x1f, 0x0005);
3242         rtl_writephy(tp, 0x05, 0x8b86);
3243         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3244         rtl_writephy(tp, 0x1f, 0x0000);
3245 }
3246
3247 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3248 {
3249         static const struct phy_reg phy_reg_init[] = {
3250                 /* Channel estimation fine tune */
3251                 { 0x1f, 0x0003 },
3252                 { 0x09, 0xa20f },
3253                 { 0x1f, 0x0000 },
3254
3255                 /* Modify green table for giga & fnet */
3256                 { 0x1f, 0x0005 },
3257                 { 0x05, 0x8b55 },
3258                 { 0x06, 0x0000 },
3259                 { 0x05, 0x8b5e },
3260                 { 0x06, 0x0000 },
3261                 { 0x05, 0x8b67 },
3262                 { 0x06, 0x0000 },
3263                 { 0x05, 0x8b70 },
3264                 { 0x06, 0x0000 },
3265                 { 0x1f, 0x0000 },
3266                 { 0x1f, 0x0007 },
3267                 { 0x1e, 0x0078 },
3268                 { 0x17, 0x0000 },
3269                 { 0x19, 0x00fb },
3270                 { 0x1f, 0x0000 },
3271
3272                 /* Modify green table for 10M */
3273                 { 0x1f, 0x0005 },
3274                 { 0x05, 0x8b79 },
3275                 { 0x06, 0xaa00 },
3276                 { 0x1f, 0x0000 },
3277
3278                 /* Disable hiimpedance detection (RTCT) */
3279                 { 0x1f, 0x0003 },
3280                 { 0x01, 0x328a },
3281                 { 0x1f, 0x0000 }
3282         };
3283
3284         rtl_apply_firmware(tp);
3285
3286         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3287
3288         rtl8168f_hw_phy_config(tp);
3289
3290         /* Improve 2-pair detection performance */
3291         rtl_writephy(tp, 0x1f, 0x0005);
3292         rtl_writephy(tp, 0x05, 0x8b85);
3293         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3294         rtl_writephy(tp, 0x1f, 0x0000);
3295 }
3296
3297 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3298 {
3299         rtl_apply_firmware(tp);
3300
3301         rtl8168f_hw_phy_config(tp);
3302 }
3303
3304 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3305 {
3306         static const struct phy_reg phy_reg_init[] = {
3307                 /* Channel estimation fine tune */
3308                 { 0x1f, 0x0003 },
3309                 { 0x09, 0xa20f },
3310                 { 0x1f, 0x0000 },
3311
3312                 /* Modify green table for giga & fnet */
3313                 { 0x1f, 0x0005 },
3314                 { 0x05, 0x8b55 },
3315                 { 0x06, 0x0000 },
3316                 { 0x05, 0x8b5e },
3317                 { 0x06, 0x0000 },
3318                 { 0x05, 0x8b67 },
3319                 { 0x06, 0x0000 },
3320                 { 0x05, 0x8b70 },
3321                 { 0x06, 0x0000 },
3322                 { 0x1f, 0x0000 },
3323                 { 0x1f, 0x0007 },
3324                 { 0x1e, 0x0078 },
3325                 { 0x17, 0x0000 },
3326                 { 0x19, 0x00aa },
3327                 { 0x1f, 0x0000 },
3328
3329                 /* Modify green table for 10M */
3330                 { 0x1f, 0x0005 },
3331                 { 0x05, 0x8b79 },
3332                 { 0x06, 0xaa00 },
3333                 { 0x1f, 0x0000 },
3334
3335                 /* Disable hiimpedance detection (RTCT) */
3336                 { 0x1f, 0x0003 },
3337                 { 0x01, 0x328a },
3338                 { 0x1f, 0x0000 }
3339         };
3340
3341
3342         rtl_apply_firmware(tp);
3343
3344         rtl8168f_hw_phy_config(tp);
3345
3346         /* Improve 2-pair detection performance */
3347         rtl_writephy(tp, 0x1f, 0x0005);
3348         rtl_writephy(tp, 0x05, 0x8b85);
3349         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3350         rtl_writephy(tp, 0x1f, 0x0000);
3351
3352         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3353
3354         /* Modify green table for giga */
3355         rtl_writephy(tp, 0x1f, 0x0005);
3356         rtl_writephy(tp, 0x05, 0x8b54);
3357         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3358         rtl_writephy(tp, 0x05, 0x8b5d);
3359         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3360         rtl_writephy(tp, 0x05, 0x8a7c);
3361         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3362         rtl_writephy(tp, 0x05, 0x8a7f);
3363         rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3364         rtl_writephy(tp, 0x05, 0x8a82);
3365         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3366         rtl_writephy(tp, 0x05, 0x8a85);
3367         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3368         rtl_writephy(tp, 0x05, 0x8a88);
3369         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3370         rtl_writephy(tp, 0x1f, 0x0000);
3371
3372         /* uc same-seed solution */
3373         rtl_writephy(tp, 0x1f, 0x0005);
3374         rtl_writephy(tp, 0x05, 0x8b85);
3375         rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3376         rtl_writephy(tp, 0x1f, 0x0000);
3377
3378         /* eee setting */
3379         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3380         rtl_writephy(tp, 0x1f, 0x0005);
3381         rtl_writephy(tp, 0x05, 0x8b85);
3382         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3383         rtl_writephy(tp, 0x1f, 0x0004);
3384         rtl_writephy(tp, 0x1f, 0x0007);
3385         rtl_writephy(tp, 0x1e, 0x0020);
3386         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3387         rtl_writephy(tp, 0x1f, 0x0000);
3388         rtl_writephy(tp, 0x0d, 0x0007);
3389         rtl_writephy(tp, 0x0e, 0x003c);
3390         rtl_writephy(tp, 0x0d, 0x4007);
3391         rtl_writephy(tp, 0x0e, 0x0000);
3392         rtl_writephy(tp, 0x0d, 0x0000);
3393
3394         /* Green feature */
3395         rtl_writephy(tp, 0x1f, 0x0003);
3396         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3397         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3398         rtl_writephy(tp, 0x1f, 0x0000);
3399 }
3400
3401 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3402 {
3403         rtl_apply_firmware(tp);
3404
3405         rtl_writephy(tp, 0x1f, 0x0a46);
3406         if (rtl_readphy(tp, 0x10) & 0x0100) {
3407                 rtl_writephy(tp, 0x1f, 0x0bcc);
3408                 rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
3409         } else {
3410                 rtl_writephy(tp, 0x1f, 0x0bcc);
3411                 rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
3412         }
3413
3414         rtl_writephy(tp, 0x1f, 0x0a46);
3415         if (rtl_readphy(tp, 0x13) & 0x0100) {
3416                 rtl_writephy(tp, 0x1f, 0x0c41);
3417                 rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
3418         } else {
3419                 rtl_writephy(tp, 0x1f, 0x0c41);
3420                 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002);
3421         }
3422
3423         /* Enable PHY auto speed down */
3424         rtl_writephy(tp, 0x1f, 0x0a44);
3425         rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
3426
3427         rtl_writephy(tp, 0x1f, 0x0bcc);
3428         rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000);
3429         rtl_writephy(tp, 0x1f, 0x0a44);
3430         rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000);
3431         rtl_writephy(tp, 0x1f, 0x0a43);
3432         rtl_writephy(tp, 0x13, 0x8084);
3433         rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000);
3434         rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000);
3435
3436         /* EEE auto-fallback function */
3437         rtl_writephy(tp, 0x1f, 0x0a4b);
3438         rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
3439
3440         /* Enable UC LPF tune function */
3441         rtl_writephy(tp, 0x1f, 0x0a43);
3442         rtl_writephy(tp, 0x13, 0x8012);
3443         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3444
3445         rtl_writephy(tp, 0x1f, 0x0c42);
3446         rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
3447
3448         /* Improve SWR Efficiency */
3449         rtl_writephy(tp, 0x1f, 0x0bcd);
3450         rtl_writephy(tp, 0x14, 0x5065);
3451         rtl_writephy(tp, 0x14, 0xd065);
3452         rtl_writephy(tp, 0x1f, 0x0bc8);
3453         rtl_writephy(tp, 0x11, 0x5655);
3454         rtl_writephy(tp, 0x1f, 0x0bcd);
3455         rtl_writephy(tp, 0x14, 0x1065);
3456         rtl_writephy(tp, 0x14, 0x9065);
3457         rtl_writephy(tp, 0x14, 0x1065);
3458
3459         rtl_writephy(tp, 0x1f, 0x0000);
3460 }
3461
3462 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3463 {
3464         rtl_apply_firmware(tp);
3465 }
3466
3467 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3468 {
3469         static const struct phy_reg phy_reg_init[] = {
3470                 { 0x1f, 0x0003 },
3471                 { 0x08, 0x441d },
3472                 { 0x01, 0x9100 },
3473                 { 0x1f, 0x0000 }
3474         };
3475
3476         rtl_writephy(tp, 0x1f, 0x0000);
3477         rtl_patchphy(tp, 0x11, 1 << 12);
3478         rtl_patchphy(tp, 0x19, 1 << 13);
3479         rtl_patchphy(tp, 0x10, 1 << 15);
3480
3481         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3482 }
3483
3484 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3485 {
3486         static const struct phy_reg phy_reg_init[] = {
3487                 { 0x1f, 0x0005 },
3488                 { 0x1a, 0x0000 },
3489                 { 0x1f, 0x0000 },
3490
3491                 { 0x1f, 0x0004 },
3492                 { 0x1c, 0x0000 },
3493                 { 0x1f, 0x0000 },
3494
3495                 { 0x1f, 0x0001 },
3496                 { 0x15, 0x7701 },
3497                 { 0x1f, 0x0000 }
3498         };
3499
3500         /* Disable ALDPS before ram code */
3501         rtl_writephy(tp, 0x1f, 0x0000);
3502         rtl_writephy(tp, 0x18, 0x0310);
3503         msleep(100);
3504
3505         rtl_apply_firmware(tp);
3506
3507         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3508 }
3509
3510 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3511 {
3512         /* Disable ALDPS before setting firmware */
3513         rtl_writephy(tp, 0x1f, 0x0000);
3514         rtl_writephy(tp, 0x18, 0x0310);
3515         msleep(20);
3516
3517         rtl_apply_firmware(tp);
3518
3519         /* EEE setting */
3520         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3521         rtl_writephy(tp, 0x1f, 0x0004);
3522         rtl_writephy(tp, 0x10, 0x401f);
3523         rtl_writephy(tp, 0x19, 0x7030);
3524         rtl_writephy(tp, 0x1f, 0x0000);
3525 }
3526
3527 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3528 {
3529         static const struct phy_reg phy_reg_init[] = {
3530                 { 0x1f, 0x0004 },
3531                 { 0x10, 0xc07f },
3532                 { 0x19, 0x7030 },
3533                 { 0x1f, 0x0000 }
3534         };
3535
3536         /* Disable ALDPS before ram code */
3537         rtl_writephy(tp, 0x1f, 0x0000);
3538         rtl_writephy(tp, 0x18, 0x0310);
3539         msleep(100);
3540
3541         rtl_apply_firmware(tp);
3542
3543         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3544         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3545
3546         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3547 }
3548
3549 static void rtl_hw_phy_config(struct net_device *dev)
3550 {
3551         struct rtl8169_private *tp = netdev_priv(dev);
3552
3553         rtl8169_print_mac_version(tp);
3554
3555         switch (tp->mac_version) {
3556         case RTL_GIGA_MAC_VER_01:
3557                 break;
3558         case RTL_GIGA_MAC_VER_02:
3559         case RTL_GIGA_MAC_VER_03:
3560                 rtl8169s_hw_phy_config(tp);
3561                 break;
3562         case RTL_GIGA_MAC_VER_04:
3563                 rtl8169sb_hw_phy_config(tp);
3564                 break;
3565         case RTL_GIGA_MAC_VER_05:
3566                 rtl8169scd_hw_phy_config(tp);
3567                 break;
3568         case RTL_GIGA_MAC_VER_06:
3569                 rtl8169sce_hw_phy_config(tp);
3570                 break;
3571         case RTL_GIGA_MAC_VER_07:
3572         case RTL_GIGA_MAC_VER_08:
3573         case RTL_GIGA_MAC_VER_09:
3574                 rtl8102e_hw_phy_config(tp);
3575                 break;
3576         case RTL_GIGA_MAC_VER_11:
3577                 rtl8168bb_hw_phy_config(tp);
3578                 break;
3579         case RTL_GIGA_MAC_VER_12:
3580                 rtl8168bef_hw_phy_config(tp);
3581                 break;
3582         case RTL_GIGA_MAC_VER_17:
3583                 rtl8168bef_hw_phy_config(tp);
3584                 break;
3585         case RTL_GIGA_MAC_VER_18:
3586                 rtl8168cp_1_hw_phy_config(tp);
3587                 break;
3588         case RTL_GIGA_MAC_VER_19:
3589                 rtl8168c_1_hw_phy_config(tp);
3590                 break;
3591         case RTL_GIGA_MAC_VER_20:
3592                 rtl8168c_2_hw_phy_config(tp);
3593                 break;
3594         case RTL_GIGA_MAC_VER_21:
3595                 rtl8168c_3_hw_phy_config(tp);
3596                 break;
3597         case RTL_GIGA_MAC_VER_22:
3598                 rtl8168c_4_hw_phy_config(tp);
3599                 break;
3600         case RTL_GIGA_MAC_VER_23:
3601         case RTL_GIGA_MAC_VER_24:
3602                 rtl8168cp_2_hw_phy_config(tp);
3603                 break;
3604         case RTL_GIGA_MAC_VER_25:
3605                 rtl8168d_1_hw_phy_config(tp);
3606                 break;
3607         case RTL_GIGA_MAC_VER_26:
3608                 rtl8168d_2_hw_phy_config(tp);
3609                 break;
3610         case RTL_GIGA_MAC_VER_27:
3611                 rtl8168d_3_hw_phy_config(tp);
3612                 break;
3613         case RTL_GIGA_MAC_VER_28:
3614                 rtl8168d_4_hw_phy_config(tp);
3615                 break;
3616         case RTL_GIGA_MAC_VER_29:
3617         case RTL_GIGA_MAC_VER_30:
3618                 rtl8105e_hw_phy_config(tp);
3619                 break;
3620         case RTL_GIGA_MAC_VER_31:
3621                 /* None. */
3622                 break;
3623         case RTL_GIGA_MAC_VER_32:
3624         case RTL_GIGA_MAC_VER_33:
3625                 rtl8168e_1_hw_phy_config(tp);
3626                 break;
3627         case RTL_GIGA_MAC_VER_34:
3628                 rtl8168e_2_hw_phy_config(tp);
3629                 break;
3630         case RTL_GIGA_MAC_VER_35:
3631                 rtl8168f_1_hw_phy_config(tp);
3632                 break;
3633         case RTL_GIGA_MAC_VER_36:
3634                 rtl8168f_2_hw_phy_config(tp);
3635                 break;
3636
3637         case RTL_GIGA_MAC_VER_37:
3638                 rtl8402_hw_phy_config(tp);
3639                 break;
3640
3641         case RTL_GIGA_MAC_VER_38:
3642                 rtl8411_hw_phy_config(tp);
3643                 break;
3644
3645         case RTL_GIGA_MAC_VER_39:
3646                 rtl8106e_hw_phy_config(tp);
3647                 break;
3648
3649         case RTL_GIGA_MAC_VER_40:
3650                 rtl8168g_1_hw_phy_config(tp);
3651                 break;
3652         case RTL_GIGA_MAC_VER_42:
3653         case RTL_GIGA_MAC_VER_43:
3654                 rtl8168g_2_hw_phy_config(tp);
3655                 break;
3656
3657         case RTL_GIGA_MAC_VER_41:
3658         default:
3659                 break;
3660         }
3661 }
3662
3663 static void rtl_phy_work(struct rtl8169_private *tp)
3664 {
3665         struct timer_list *timer = &tp->timer;
3666         void __iomem *ioaddr = tp->mmio_addr;
3667         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3668
3669         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3670
3671         if (tp->phy_reset_pending(tp)) {
3672                 /*
3673                  * A busy loop could burn quite a few cycles on nowadays CPU.
3674                  * Let's delay the execution of the timer for a few ticks.
3675                  */
3676                 timeout = HZ/10;
3677                 goto out_mod_timer;
3678         }
3679
3680         if (tp->link_ok(ioaddr))
3681                 return;
3682
3683         netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3684
3685         tp->phy_reset_enable(tp);
3686
3687 out_mod_timer:
3688         mod_timer(timer, jiffies + timeout);
3689 }
3690
3691 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3692 {
3693         if (!test_and_set_bit(flag, tp->wk.flags))
3694                 schedule_work(&tp->wk.work);
3695 }
3696
3697 static void rtl8169_phy_timer(unsigned long __opaque)
3698 {
3699         struct net_device *dev = (struct net_device *)__opaque;
3700         struct rtl8169_private *tp = netdev_priv(dev);
3701
3702         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3703 }
3704
3705 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3706                                   void __iomem *ioaddr)
3707 {
3708         iounmap(ioaddr);
3709         pci_release_regions(pdev);
3710         pci_clear_mwi(pdev);
3711         pci_disable_device(pdev);
3712         free_netdev(dev);
3713 }
3714
3715 DECLARE_RTL_COND(rtl_phy_reset_cond)
3716 {
3717         return tp->phy_reset_pending(tp);
3718 }
3719
3720 static void rtl8169_phy_reset(struct net_device *dev,
3721                               struct rtl8169_private *tp)
3722 {
3723         tp->phy_reset_enable(tp);
3724         rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
3725 }
3726
3727 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3728 {
3729         void __iomem *ioaddr = tp->mmio_addr;
3730
3731         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3732             (RTL_R8(PHYstatus) & TBI_Enable);
3733 }
3734
3735 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3736 {
3737         void __iomem *ioaddr = tp->mmio_addr;
3738
3739         rtl_hw_phy_config(dev);
3740
3741         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3742                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3743                 RTL_W8(0x82, 0x01);
3744         }
3745
3746         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3747
3748         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3749                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3750
3751         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3752                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3753                 RTL_W8(0x82, 0x01);
3754                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3755                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3756         }
3757
3758         rtl8169_phy_reset(dev, tp);
3759
3760         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3761                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3762                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3763                           (tp->mii.supports_gmii ?
3764                            ADVERTISED_1000baseT_Half |
3765                            ADVERTISED_1000baseT_Full : 0));
3766
3767         if (rtl_tbi_enabled(tp))
3768                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3769 }
3770
3771 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3772 {
3773         void __iomem *ioaddr = tp->mmio_addr;
3774
3775         rtl_lock_work(tp);
3776
3777         RTL_W8(Cfg9346, Cfg9346_Unlock);
3778
3779         RTL_W32(MAC4, addr[4] | addr[5] << 8);
3780         RTL_R32(MAC4);
3781
3782         RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3783         RTL_R32(MAC0);
3784
3785         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3786                 rtl_rar_exgmac_set(tp, addr);
3787
3788         RTL_W8(Cfg9346, Cfg9346_Lock);
3789
3790         rtl_unlock_work(tp);
3791 }
3792
3793 static int rtl_set_mac_address(struct net_device *dev, void *p)
3794 {
3795         struct rtl8169_private *tp = netdev_priv(dev);
3796         struct sockaddr *addr = p;
3797
3798         if (!is_valid_ether_addr(addr->sa_data))
3799                 return -EADDRNOTAVAIL;
3800
3801         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3802
3803         rtl_rar_set(tp, dev->dev_addr);
3804
3805         return 0;
3806 }
3807
3808 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3809 {
3810         struct rtl8169_private *tp = netdev_priv(dev);
3811         struct mii_ioctl_data *data = if_mii(ifr);
3812
3813         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3814 }
3815
3816 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3817                           struct mii_ioctl_data *data, int cmd)
3818 {
3819         switch (cmd) {
3820         case SIOCGMIIPHY:
3821                 data->phy_id = 32; /* Internal PHY */
3822                 return 0;
3823
3824         case SIOCGMIIREG:
3825                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3826                 return 0;
3827
3828         case SIOCSMIIREG:
3829                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3830                 return 0;
3831         }
3832         return -EOPNOTSUPP;
3833 }
3834
3835 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3836 {
3837         return -EOPNOTSUPP;
3838 }
3839
3840 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3841 {
3842         if (tp->features & RTL_FEATURE_MSI) {
3843                 pci_disable_msi(pdev);
3844                 tp->features &= ~RTL_FEATURE_MSI;
3845         }
3846 }
3847
3848 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
3849 {
3850         struct mdio_ops *ops = &tp->mdio_ops;
3851
3852         switch (tp->mac_version) {
3853         case RTL_GIGA_MAC_VER_27:
3854                 ops->write      = r8168dp_1_mdio_write;
3855                 ops->read       = r8168dp_1_mdio_read;
3856                 break;
3857         case RTL_GIGA_MAC_VER_28:
3858         case RTL_GIGA_MAC_VER_31:
3859                 ops->write      = r8168dp_2_mdio_write;
3860                 ops->read       = r8168dp_2_mdio_read;
3861                 break;
3862         case RTL_GIGA_MAC_VER_40:
3863         case RTL_GIGA_MAC_VER_41:
3864         case RTL_GIGA_MAC_VER_42:
3865         case RTL_GIGA_MAC_VER_43:
3866                 ops->write      = r8168g_mdio_write;
3867                 ops->read       = r8168g_mdio_read;
3868                 break;
3869         default:
3870                 ops->write      = r8169_mdio_write;
3871                 ops->read       = r8169_mdio_read;
3872                 break;
3873         }
3874 }
3875
3876 static void rtl_speed_down(struct rtl8169_private *tp)
3877 {
3878         u32 adv;
3879         int lpa;
3880
3881         rtl_writephy(tp, 0x1f, 0x0000);
3882         lpa = rtl_readphy(tp, MII_LPA);
3883
3884         if (lpa & (LPA_10HALF | LPA_10FULL))
3885                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
3886         else if (lpa & (LPA_100HALF | LPA_100FULL))
3887                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3888                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3889         else
3890                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3891                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3892                       (tp->mii.supports_gmii ?
3893                        ADVERTISED_1000baseT_Half |
3894                        ADVERTISED_1000baseT_Full : 0);
3895
3896         rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3897                           adv);
3898 }
3899
3900 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3901 {
3902         void __iomem *ioaddr = tp->mmio_addr;
3903
3904         switch (tp->mac_version) {
3905         case RTL_GIGA_MAC_VER_25:
3906         case RTL_GIGA_MAC_VER_26:
3907         case RTL_GIGA_MAC_VER_29:
3908         case RTL_GIGA_MAC_VER_30:
3909         case RTL_GIGA_MAC_VER_32:
3910         case RTL_GIGA_MAC_VER_33:
3911         case RTL_GIGA_MAC_VER_34:
3912         case RTL_GIGA_MAC_VER_37:
3913         case RTL_GIGA_MAC_VER_38:
3914         case RTL_GIGA_MAC_VER_39:
3915         case RTL_GIGA_MAC_VER_40:
3916         case RTL_GIGA_MAC_VER_41:
3917         case RTL_GIGA_MAC_VER_42:
3918         case RTL_GIGA_MAC_VER_43:
3919                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3920                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3921                 break;
3922         default:
3923                 break;
3924         }
3925 }
3926
3927 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3928 {
3929         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3930                 return false;
3931
3932         rtl_speed_down(tp);
3933         rtl_wol_suspend_quirk(tp);
3934
3935         return true;
3936 }
3937
3938 static void r810x_phy_power_down(struct rtl8169_private *tp)
3939 {
3940         rtl_writephy(tp, 0x1f, 0x0000);
3941         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3942 }
3943
3944 static void r810x_phy_power_up(struct rtl8169_private *tp)
3945 {
3946         rtl_writephy(tp, 0x1f, 0x0000);
3947         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3948 }
3949
3950 static void r810x_pll_power_down(struct rtl8169_private *tp)
3951 {
3952         void __iomem *ioaddr = tp->mmio_addr;
3953
3954         if (rtl_wol_pll_power_down(tp))
3955                 return;
3956
3957         r810x_phy_power_down(tp);
3958
3959         switch (tp->mac_version) {
3960         case RTL_GIGA_MAC_VER_07:
3961         case RTL_GIGA_MAC_VER_08:
3962         case RTL_GIGA_MAC_VER_09:
3963         case RTL_GIGA_MAC_VER_10:
3964         case RTL_GIGA_MAC_VER_13:
3965         case RTL_GIGA_MAC_VER_16:
3966                 break;
3967         default:
3968                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3969                 break;
3970         }
3971 }
3972
3973 static void r810x_pll_power_up(struct rtl8169_private *tp)
3974 {
3975         void __iomem *ioaddr = tp->mmio_addr;
3976
3977         r810x_phy_power_up(tp);
3978
3979         switch (tp->mac_version) {
3980         case RTL_GIGA_MAC_VER_07:
3981         case RTL_GIGA_MAC_VER_08:
3982         case RTL_GIGA_MAC_VER_09:
3983         case RTL_GIGA_MAC_VER_10:
3984         case RTL_GIGA_MAC_VER_13:
3985         case RTL_GIGA_MAC_VER_16:
3986                 break;
3987         default:
3988                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3989                 break;
3990         }
3991 }
3992
3993 static void r8168_phy_power_up(struct rtl8169_private *tp)
3994 {
3995         rtl_writephy(tp, 0x1f, 0x0000);
3996         switch (tp->mac_version) {
3997         case RTL_GIGA_MAC_VER_11:
3998         case RTL_GIGA_MAC_VER_12:
3999         case RTL_GIGA_MAC_VER_17:
4000         case RTL_GIGA_MAC_VER_18:
4001         case RTL_GIGA_MAC_VER_19:
4002         case RTL_GIGA_MAC_VER_20:
4003         case RTL_GIGA_MAC_VER_21:
4004         case RTL_GIGA_MAC_VER_22:
4005         case RTL_GIGA_MAC_VER_23:
4006         case RTL_GIGA_MAC_VER_24:
4007         case RTL_GIGA_MAC_VER_25:
4008         case RTL_GIGA_MAC_VER_26:
4009         case RTL_GIGA_MAC_VER_27:
4010         case RTL_GIGA_MAC_VER_28:
4011         case RTL_GIGA_MAC_VER_31:
4012                 rtl_writephy(tp, 0x0e, 0x0000);
4013                 break;
4014         default:
4015                 break;
4016         }
4017         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4018 }
4019
4020 static void r8168_phy_power_down(struct rtl8169_private *tp)
4021 {
4022         rtl_writephy(tp, 0x1f, 0x0000);
4023         switch (tp->mac_version) {
4024         case RTL_GIGA_MAC_VER_32:
4025         case RTL_GIGA_MAC_VER_33:
4026         case RTL_GIGA_MAC_VER_40:
4027         case RTL_GIGA_MAC_VER_41:
4028                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4029                 break;
4030
4031         case RTL_GIGA_MAC_VER_11:
4032         case RTL_GIGA_MAC_VER_12:
4033         case RTL_GIGA_MAC_VER_17:
4034         case RTL_GIGA_MAC_VER_18:
4035         case RTL_GIGA_MAC_VER_19:
4036         case RTL_GIGA_MAC_VER_20:
4037         case RTL_GIGA_MAC_VER_21:
4038         case RTL_GIGA_MAC_VER_22:
4039         case RTL_GIGA_MAC_VER_23:
4040         case RTL_GIGA_MAC_VER_24:
4041         case RTL_GIGA_MAC_VER_25:
4042         case RTL_GIGA_MAC_VER_26:
4043         case RTL_GIGA_MAC_VER_27:
4044         case RTL_GIGA_MAC_VER_28:
4045         case RTL_GIGA_MAC_VER_31:
4046                 rtl_writephy(tp, 0x0e, 0x0200);
4047         default:
4048                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4049                 break;
4050         }
4051 }
4052
4053 static void r8168_pll_power_down(struct rtl8169_private *tp)
4054 {
4055         void __iomem *ioaddr = tp->mmio_addr;
4056
4057         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4058              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4059              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4060             r8168dp_check_dash(tp)) {
4061                 return;
4062         }
4063
4064         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4065              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4066             (RTL_R16(CPlusCmd) & ASF)) {
4067                 return;
4068         }
4069
4070         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4071             tp->mac_version == RTL_GIGA_MAC_VER_33)
4072                 rtl_ephy_write(tp, 0x19, 0xff64);
4073
4074         if (rtl_wol_pll_power_down(tp))
4075                 return;
4076
4077         r8168_phy_power_down(tp);
4078
4079         switch (tp->mac_version) {
4080         case RTL_GIGA_MAC_VER_25:
4081         case RTL_GIGA_MAC_VER_26:
4082         case RTL_GIGA_MAC_VER_27:
4083         case RTL_GIGA_MAC_VER_28:
4084         case RTL_GIGA_MAC_VER_31:
4085         case RTL_GIGA_MAC_VER_32:
4086         case RTL_GIGA_MAC_VER_33:
4087                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4088                 break;
4089         case RTL_GIGA_MAC_VER_40:
4090         case RTL_GIGA_MAC_VER_41:
4091                 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4092                              0xfc000000, ERIAR_EXGMAC);
4093                 break;
4094         }
4095 }
4096
4097 static void r8168_pll_power_up(struct rtl8169_private *tp)
4098 {
4099         void __iomem *ioaddr = tp->mmio_addr;
4100
4101         switch (tp->mac_version) {
4102         case RTL_GIGA_MAC_VER_25:
4103         case RTL_GIGA_MAC_VER_26:
4104         case RTL_GIGA_MAC_VER_27:
4105         case RTL_GIGA_MAC_VER_28:
4106         case RTL_GIGA_MAC_VER_31:
4107         case RTL_GIGA_MAC_VER_32:
4108         case RTL_GIGA_MAC_VER_33:
4109                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4110                 break;
4111         case RTL_GIGA_MAC_VER_40:
4112         case RTL_GIGA_MAC_VER_41:
4113                 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4114                              0x00000000, ERIAR_EXGMAC);
4115                 break;
4116         }
4117
4118         r8168_phy_power_up(tp);
4119 }
4120
4121 static void rtl_generic_op(struct rtl8169_private *tp,
4122                            void (*op)(struct rtl8169_private *))
4123 {
4124         if (op)
4125                 op(tp);
4126 }
4127
4128 static void rtl_pll_power_down(struct rtl8169_private *tp)
4129 {
4130         rtl_generic_op(tp, tp->pll_power_ops.down);
4131 }
4132
4133 static void rtl_pll_power_up(struct rtl8169_private *tp)
4134 {
4135         rtl_generic_op(tp, tp->pll_power_ops.up);
4136 }
4137
4138 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4139 {
4140         struct pll_power_ops *ops = &tp->pll_power_ops;
4141
4142         switch (tp->mac_version) {
4143         case RTL_GIGA_MAC_VER_07:
4144         case RTL_GIGA_MAC_VER_08:
4145         case RTL_GIGA_MAC_VER_09:
4146         case RTL_GIGA_MAC_VER_10:
4147         case RTL_GIGA_MAC_VER_16:
4148         case RTL_GIGA_MAC_VER_29:
4149         case RTL_GIGA_MAC_VER_30:
4150         case RTL_GIGA_MAC_VER_37:
4151         case RTL_GIGA_MAC_VER_39:
4152         case RTL_GIGA_MAC_VER_43:
4153                 ops->down       = r810x_pll_power_down;
4154                 ops->up         = r810x_pll_power_up;
4155                 break;
4156
4157         case RTL_GIGA_MAC_VER_11:
4158         case RTL_GIGA_MAC_VER_12:
4159         case RTL_GIGA_MAC_VER_17:
4160         case RTL_GIGA_MAC_VER_18:
4161         case RTL_GIGA_MAC_VER_19:
4162         case RTL_GIGA_MAC_VER_20:
4163         case RTL_GIGA_MAC_VER_21:
4164         case RTL_GIGA_MAC_VER_22:
4165         case RTL_GIGA_MAC_VER_23:
4166         case RTL_GIGA_MAC_VER_24:
4167         case RTL_GIGA_MAC_VER_25:
4168         case RTL_GIGA_MAC_VER_26:
4169         case RTL_GIGA_MAC_VER_27:
4170         case RTL_GIGA_MAC_VER_28:
4171         case RTL_GIGA_MAC_VER_31:
4172         case RTL_GIGA_MAC_VER_32:
4173         case RTL_GIGA_MAC_VER_33:
4174         case RTL_GIGA_MAC_VER_34:
4175         case RTL_GIGA_MAC_VER_35:
4176         case RTL_GIGA_MAC_VER_36:
4177         case RTL_GIGA_MAC_VER_38:
4178         case RTL_GIGA_MAC_VER_40:
4179         case RTL_GIGA_MAC_VER_41:
4180         case RTL_GIGA_MAC_VER_42:
4181                 ops->down       = r8168_pll_power_down;
4182                 ops->up         = r8168_pll_power_up;
4183                 break;
4184
4185         default:
4186                 ops->down       = NULL;
4187                 ops->up         = NULL;
4188                 break;
4189         }
4190 }
4191
4192 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4193 {
4194         void __iomem *ioaddr = tp->mmio_addr;
4195
4196         switch (tp->mac_version) {
4197         case RTL_GIGA_MAC_VER_01:
4198         case RTL_GIGA_MAC_VER_02:
4199         case RTL_GIGA_MAC_VER_03:
4200         case RTL_GIGA_MAC_VER_04:
4201         case RTL_GIGA_MAC_VER_05:
4202         case RTL_GIGA_MAC_VER_06:
4203         case RTL_GIGA_MAC_VER_10:
4204         case RTL_GIGA_MAC_VER_11:
4205         case RTL_GIGA_MAC_VER_12:
4206         case RTL_GIGA_MAC_VER_13:
4207         case RTL_GIGA_MAC_VER_14:
4208         case RTL_GIGA_MAC_VER_15:
4209         case RTL_GIGA_MAC_VER_16:
4210         case RTL_GIGA_MAC_VER_17:
4211                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4212                 break;
4213         case RTL_GIGA_MAC_VER_18:
4214         case RTL_GIGA_MAC_VER_19:
4215         case RTL_GIGA_MAC_VER_20:
4216         case RTL_GIGA_MAC_VER_21:
4217         case RTL_GIGA_MAC_VER_22:
4218         case RTL_GIGA_MAC_VER_23:
4219         case RTL_GIGA_MAC_VER_24:
4220         case RTL_GIGA_MAC_VER_34:
4221                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4222                 break;
4223         case RTL_GIGA_MAC_VER_40:
4224         case RTL_GIGA_MAC_VER_41:
4225         case RTL_GIGA_MAC_VER_42:
4226         case RTL_GIGA_MAC_VER_43:
4227                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4228                 break;
4229         default:
4230                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4231                 break;
4232         }
4233 }
4234
4235 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4236 {
4237         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4238 }
4239
4240 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4241 {
4242         void __iomem *ioaddr = tp->mmio_addr;
4243
4244         RTL_W8(Cfg9346, Cfg9346_Unlock);
4245         rtl_generic_op(tp, tp->jumbo_ops.enable);
4246         RTL_W8(Cfg9346, Cfg9346_Lock);
4247 }
4248
4249 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4250 {
4251         void __iomem *ioaddr = tp->mmio_addr;
4252
4253         RTL_W8(Cfg9346, Cfg9346_Unlock);
4254         rtl_generic_op(tp, tp->jumbo_ops.disable);
4255         RTL_W8(Cfg9346, Cfg9346_Lock);
4256 }
4257
4258 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4259 {
4260         void __iomem *ioaddr = tp->mmio_addr;
4261
4262         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4263         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4264         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4265 }
4266
4267 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4268 {
4269         void __iomem *ioaddr = tp->mmio_addr;
4270
4271         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4272         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4273         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4274 }
4275
4276 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4277 {
4278         void __iomem *ioaddr = tp->mmio_addr;
4279
4280         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4281 }
4282
4283 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4284 {
4285         void __iomem *ioaddr = tp->mmio_addr;
4286
4287         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4288 }
4289
4290 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4291 {
4292         void __iomem *ioaddr = tp->mmio_addr;
4293
4294         RTL_W8(MaxTxPacketSize, 0x3f);
4295         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4296         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4297         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4298 }
4299
4300 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4301 {
4302         void __iomem *ioaddr = tp->mmio_addr;
4303
4304         RTL_W8(MaxTxPacketSize, 0x0c);
4305         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4306         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4307         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4308 }
4309
4310 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4311 {
4312         rtl_tx_performance_tweak(tp->pci_dev,
4313                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4314 }
4315
4316 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4317 {
4318         rtl_tx_performance_tweak(tp->pci_dev,
4319                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4320 }
4321
4322 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4323 {
4324         void __iomem *ioaddr = tp->mmio_addr;
4325
4326         r8168b_0_hw_jumbo_enable(tp);
4327
4328         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4329 }
4330
4331 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4332 {
4333         void __iomem *ioaddr = tp->mmio_addr;
4334
4335         r8168b_0_hw_jumbo_disable(tp);
4336
4337         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4338 }
4339
4340 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4341 {
4342         struct jumbo_ops *ops = &tp->jumbo_ops;
4343
4344         switch (tp->mac_version) {
4345         case RTL_GIGA_MAC_VER_11:
4346                 ops->disable    = r8168b_0_hw_jumbo_disable;
4347                 ops->enable     = r8168b_0_hw_jumbo_enable;
4348                 break;
4349         case RTL_GIGA_MAC_VER_12:
4350         case RTL_GIGA_MAC_VER_17:
4351                 ops->disable    = r8168b_1_hw_jumbo_disable;
4352                 ops->enable     = r8168b_1_hw_jumbo_enable;
4353                 break;
4354         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4355         case RTL_GIGA_MAC_VER_19:
4356         case RTL_GIGA_MAC_VER_20:
4357         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4358         case RTL_GIGA_MAC_VER_22:
4359         case RTL_GIGA_MAC_VER_23:
4360         case RTL_GIGA_MAC_VER_24:
4361         case RTL_GIGA_MAC_VER_25:
4362         case RTL_GIGA_MAC_VER_26:
4363                 ops->disable    = r8168c_hw_jumbo_disable;
4364                 ops->enable     = r8168c_hw_jumbo_enable;
4365                 break;
4366         case RTL_GIGA_MAC_VER_27:
4367         case RTL_GIGA_MAC_VER_28:
4368                 ops->disable    = r8168dp_hw_jumbo_disable;
4369                 ops->enable     = r8168dp_hw_jumbo_enable;
4370                 break;
4371         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4372         case RTL_GIGA_MAC_VER_32:
4373         case RTL_GIGA_MAC_VER_33:
4374         case RTL_GIGA_MAC_VER_34:
4375                 ops->disable    = r8168e_hw_jumbo_disable;
4376                 ops->enable     = r8168e_hw_jumbo_enable;
4377                 break;
4378
4379         /*
4380          * No action needed for jumbo frames with 8169.
4381          * No jumbo for 810x at all.
4382          */
4383         case RTL_GIGA_MAC_VER_40:
4384         case RTL_GIGA_MAC_VER_41:
4385         case RTL_GIGA_MAC_VER_42:
4386         case RTL_GIGA_MAC_VER_43:
4387         default:
4388                 ops->disable    = NULL;
4389                 ops->enable     = NULL;
4390                 break;
4391         }
4392 }
4393
4394 DECLARE_RTL_COND(rtl_chipcmd_cond)
4395 {
4396         void __iomem *ioaddr = tp->mmio_addr;
4397
4398         return RTL_R8(ChipCmd) & CmdReset;
4399 }
4400
4401 static void rtl_hw_reset(struct rtl8169_private *tp)
4402 {
4403         void __iomem *ioaddr = tp->mmio_addr;
4404
4405         RTL_W8(ChipCmd, CmdReset);
4406
4407         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4408 }
4409
4410 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4411 {
4412         struct rtl_fw *rtl_fw;
4413         const char *name;
4414         int rc = -ENOMEM;
4415
4416         name = rtl_lookup_firmware_name(tp);
4417         if (!name)
4418                 goto out_no_firmware;
4419
4420         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4421         if (!rtl_fw)
4422                 goto err_warn;
4423
4424         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4425         if (rc < 0)
4426                 goto err_free;
4427
4428         rc = rtl_check_firmware(tp, rtl_fw);
4429         if (rc < 0)
4430                 goto err_release_firmware;
4431
4432         tp->rtl_fw = rtl_fw;
4433 out:
4434         return;
4435
4436 err_release_firmware:
4437         release_firmware(rtl_fw->fw);
4438 err_free:
4439         kfree(rtl_fw);
4440 err_warn:
4441         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4442                    name, rc);
4443 out_no_firmware:
4444         tp->rtl_fw = NULL;
4445         goto out;
4446 }
4447
4448 static void rtl_request_firmware(struct rtl8169_private *tp)
4449 {
4450         if (IS_ERR(tp->rtl_fw))
4451                 rtl_request_uncached_firmware(tp);
4452 }
4453
4454 static void rtl_rx_close(struct rtl8169_private *tp)
4455 {
4456         void __iomem *ioaddr = tp->mmio_addr;
4457
4458         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4459 }
4460
4461 DECLARE_RTL_COND(rtl_npq_cond)
4462 {
4463         void __iomem *ioaddr = tp->mmio_addr;
4464
4465         return RTL_R8(TxPoll) & NPQ;
4466 }
4467
4468 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4469 {
4470         void __iomem *ioaddr = tp->mmio_addr;
4471
4472         return RTL_R32(TxConfig) & TXCFG_EMPTY;
4473 }
4474
4475 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4476 {
4477         void __iomem *ioaddr = tp->mmio_addr;
4478
4479         /* Disable interrupts */
4480         rtl8169_irq_mask_and_ack(tp);
4481
4482         rtl_rx_close(tp);
4483
4484         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4485             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4486             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4487                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4488         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4489                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4490                    tp->mac_version == RTL_GIGA_MAC_VER_36 ||
4491                    tp->mac_version == RTL_GIGA_MAC_VER_37 ||
4492                    tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4493                    tp->mac_version == RTL_GIGA_MAC_VER_41 ||
4494                    tp->mac_version == RTL_GIGA_MAC_VER_42 ||
4495                    tp->mac_version == RTL_GIGA_MAC_VER_43 ||
4496                    tp->mac_version == RTL_GIGA_MAC_VER_38) {
4497                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4498                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4499         } else {
4500                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4501                 udelay(100);
4502         }
4503
4504         rtl_hw_reset(tp);
4505 }
4506
4507 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4508 {
4509         void __iomem *ioaddr = tp->mmio_addr;
4510
4511         /* Set DMA burst size and Interframe Gap Time */
4512         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4513                 (InterFrameGap << TxInterFrameGapShift));
4514 }
4515
4516 static void rtl_hw_start(struct net_device *dev)
4517 {
4518         struct rtl8169_private *tp = netdev_priv(dev);
4519
4520         tp->hw_start(dev);
4521
4522         rtl_irq_enable_all(tp);
4523 }
4524
4525 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4526                                          void __iomem *ioaddr)
4527 {
4528         /*
4529          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4530          * register to be written before TxDescAddrLow to work.
4531          * Switching from MMIO to I/O access fixes the issue as well.
4532          */
4533         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4534         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4535         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4536         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4537 }
4538
4539 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4540 {
4541         u16 cmd;
4542
4543         cmd = RTL_R16(CPlusCmd);
4544         RTL_W16(CPlusCmd, cmd);
4545         return cmd;
4546 }
4547
4548 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4549 {
4550         /* Low hurts. Let's disable the filtering. */
4551         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4552 }
4553
4554 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4555 {
4556         static const struct rtl_cfg2_info {
4557                 u32 mac_version;
4558                 u32 clk;
4559                 u32 val;
4560         } cfg2_info [] = {
4561                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4562                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4563                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4564                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4565         };
4566         const struct rtl_cfg2_info *p = cfg2_info;
4567         unsigned int i;
4568         u32 clk;
4569
4570         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4571         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4572                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4573                         RTL_W32(0x7c, p->val);
4574                         break;
4575                 }
4576         }
4577 }
4578
4579 static void rtl_set_rx_mode(struct net_device *dev)
4580 {
4581         struct rtl8169_private *tp = netdev_priv(dev);
4582         void __iomem *ioaddr = tp->mmio_addr;
4583         u32 mc_filter[2];       /* Multicast hash filter */
4584         int rx_mode;
4585         u32 tmp = 0;
4586
4587         if (dev->flags & IFF_PROMISC) {
4588                 /* Unconditionally log net taps. */
4589                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4590                 rx_mode =
4591                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4592                     AcceptAllPhys;
4593                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4594         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4595                    (dev->flags & IFF_ALLMULTI)) {
4596                 /* Too many to filter perfectly -- accept all multicasts. */
4597                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4598                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4599         } else {
4600                 struct netdev_hw_addr *ha;
4601
4602                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4603                 mc_filter[1] = mc_filter[0] = 0;
4604                 netdev_for_each_mc_addr(ha, dev) {
4605                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4606                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4607                         rx_mode |= AcceptMulticast;
4608                 }
4609         }
4610
4611         if (dev->features & NETIF_F_RXALL)
4612                 rx_mode |= (AcceptErr | AcceptRunt);
4613
4614         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4615
4616         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4617                 u32 data = mc_filter[0];
4618
4619                 mc_filter[0] = swab32(mc_filter[1]);
4620                 mc_filter[1] = swab32(data);
4621         }
4622
4623         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4624                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4625
4626         RTL_W32(MAR0 + 4, mc_filter[1]);
4627         RTL_W32(MAR0 + 0, mc_filter[0]);
4628
4629         RTL_W32(RxConfig, tmp);
4630 }
4631
4632 static void rtl_hw_start_8169(struct net_device *dev)
4633 {
4634         struct rtl8169_private *tp = netdev_priv(dev);
4635         void __iomem *ioaddr = tp->mmio_addr;
4636         struct pci_dev *pdev = tp->pci_dev;
4637
4638         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4639                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4640                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4641         }
4642
4643         RTL_W8(Cfg9346, Cfg9346_Unlock);
4644         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4645             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4646             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4647             tp->mac_version == RTL_GIGA_MAC_VER_04)
4648                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4649
4650         rtl_init_rxcfg(tp);
4651
4652         RTL_W8(EarlyTxThres, NoEarlyTx);
4653
4654         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4655
4656         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4657             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4658             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4659             tp->mac_version == RTL_GIGA_MAC_VER_04)
4660                 rtl_set_rx_tx_config_registers(tp);
4661
4662         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4663
4664         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4665             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4666                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4667                         "Bit-3 and bit-14 MUST be 1\n");
4668                 tp->cp_cmd |= (1 << 14);
4669         }
4670
4671         RTL_W16(CPlusCmd, tp->cp_cmd);
4672
4673         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4674
4675         /*
4676          * Undocumented corner. Supposedly:
4677          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4678          */
4679         RTL_W16(IntrMitigate, 0x0000);
4680
4681         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4682
4683         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4684             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4685             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4686             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4687                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4688                 rtl_set_rx_tx_config_registers(tp);
4689         }
4690
4691         RTL_W8(Cfg9346, Cfg9346_Lock);
4692
4693         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4694         RTL_R8(IntrMask);
4695
4696         RTL_W32(RxMissed, 0);
4697
4698         rtl_set_rx_mode(dev);
4699
4700         /* no early-rx interrupts */
4701         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4702 }
4703
4704 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4705 {
4706         if (tp->csi_ops.write)
4707                 tp->csi_ops.write(tp, addr, value);
4708 }
4709
4710 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4711 {
4712         return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
4713 }
4714
4715 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
4716 {
4717         u32 csi;
4718
4719         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4720         rtl_csi_write(tp, 0x070c, csi | bits);
4721 }
4722
4723 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4724 {
4725         rtl_csi_access_enable(tp, 0x17000000);
4726 }
4727
4728 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
4729 {
4730         rtl_csi_access_enable(tp, 0x27000000);
4731 }
4732
4733 DECLARE_RTL_COND(rtl_csiar_cond)
4734 {
4735         void __iomem *ioaddr = tp->mmio_addr;
4736
4737         return RTL_R32(CSIAR) & CSIAR_FLAG;
4738 }
4739
4740 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
4741 {
4742         void __iomem *ioaddr = tp->mmio_addr;
4743
4744         RTL_W32(CSIDR, value);
4745         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4746                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4747
4748         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4749 }
4750
4751 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
4752 {
4753         void __iomem *ioaddr = tp->mmio_addr;
4754
4755         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4756                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4757
4758         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4759                 RTL_R32(CSIDR) : ~0;
4760 }
4761
4762 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
4763 {
4764         void __iomem *ioaddr = tp->mmio_addr;
4765
4766         RTL_W32(CSIDR, value);
4767         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4768                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4769                 CSIAR_FUNC_NIC);
4770
4771         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4772 }
4773
4774 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
4775 {
4776         void __iomem *ioaddr = tp->mmio_addr;
4777
4778         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4779                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4780
4781         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4782                 RTL_R32(CSIDR) : ~0;
4783 }
4784
4785 static void rtl_init_csi_ops(struct rtl8169_private *tp)
4786 {
4787         struct csi_ops *ops = &tp->csi_ops;
4788
4789         switch (tp->mac_version) {
4790         case RTL_GIGA_MAC_VER_01:
4791         case RTL_GIGA_MAC_VER_02:
4792         case RTL_GIGA_MAC_VER_03:
4793         case RTL_GIGA_MAC_VER_04:
4794         case RTL_GIGA_MAC_VER_05:
4795         case RTL_GIGA_MAC_VER_06:
4796         case RTL_GIGA_MAC_VER_10:
4797         case RTL_GIGA_MAC_VER_11:
4798         case RTL_GIGA_MAC_VER_12:
4799         case RTL_GIGA_MAC_VER_13:
4800         case RTL_GIGA_MAC_VER_14:
4801         case RTL_GIGA_MAC_VER_15:
4802         case RTL_GIGA_MAC_VER_16:
4803         case RTL_GIGA_MAC_VER_17:
4804                 ops->write      = NULL;
4805                 ops->read       = NULL;
4806                 break;
4807
4808         case RTL_GIGA_MAC_VER_37:
4809         case RTL_GIGA_MAC_VER_38:
4810                 ops->write      = r8402_csi_write;
4811                 ops->read       = r8402_csi_read;
4812                 break;
4813
4814         default:
4815                 ops->write      = r8169_csi_write;
4816                 ops->read       = r8169_csi_read;
4817                 break;
4818         }
4819 }
4820
4821 struct ephy_info {
4822         unsigned int offset;
4823         u16 mask;
4824         u16 bits;
4825 };
4826
4827 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4828                           int len)
4829 {
4830         u16 w;
4831
4832         while (len-- > 0) {
4833                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4834                 rtl_ephy_write(tp, e->offset, w);
4835                 e++;
4836         }
4837 }
4838
4839 static void rtl_disable_clock_request(struct pci_dev *pdev)
4840 {
4841         pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
4842                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4843 }
4844
4845 static void rtl_enable_clock_request(struct pci_dev *pdev)
4846 {
4847         pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
4848                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4849 }
4850
4851 #define R8168_CPCMD_QUIRK_MASK (\
4852         EnableBist | \
4853         Mac_dbgo_oe | \
4854         Force_half_dup | \
4855         Force_rxflow_en | \
4856         Force_txflow_en | \
4857         Cxpl_dbg_sel | \
4858         ASF | \
4859         PktCntrDisable | \
4860         Mac_dbgo_sel)
4861
4862 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4863 {
4864         void __iomem *ioaddr = tp->mmio_addr;
4865         struct pci_dev *pdev = tp->pci_dev;
4866
4867         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4868
4869         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4870
4871         if (tp->dev->mtu <= ETH_DATA_LEN) {
4872                 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
4873                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4874         }
4875 }
4876
4877 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4878 {
4879         void __iomem *ioaddr = tp->mmio_addr;
4880
4881         rtl_hw_start_8168bb(tp);
4882
4883         RTL_W8(MaxTxPacketSize, TxPacketMax);
4884
4885         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4886 }
4887
4888 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4889 {
4890         void __iomem *ioaddr = tp->mmio_addr;
4891         struct pci_dev *pdev = tp->pci_dev;
4892
4893         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4894
4895         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4896
4897         if (tp->dev->mtu <= ETH_DATA_LEN)
4898                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4899
4900         rtl_disable_clock_request(pdev);
4901
4902         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4903 }
4904
4905 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4906 {
4907         static const struct ephy_info e_info_8168cp[] = {
4908                 { 0x01, 0,      0x0001 },
4909                 { 0x02, 0x0800, 0x1000 },
4910                 { 0x03, 0,      0x0042 },
4911                 { 0x06, 0x0080, 0x0000 },
4912                 { 0x07, 0,      0x2000 }
4913         };
4914
4915         rtl_csi_access_enable_2(tp);
4916
4917         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4918
4919         __rtl_hw_start_8168cp(tp);
4920 }
4921
4922 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4923 {
4924         void __iomem *ioaddr = tp->mmio_addr;
4925         struct pci_dev *pdev = tp->pci_dev;
4926
4927         rtl_csi_access_enable_2(tp);
4928
4929         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4930
4931         if (tp->dev->mtu <= ETH_DATA_LEN)
4932                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4933
4934         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4935 }
4936
4937 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4938 {
4939         void __iomem *ioaddr = tp->mmio_addr;
4940         struct pci_dev *pdev = tp->pci_dev;
4941
4942         rtl_csi_access_enable_2(tp);
4943
4944         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4945
4946         /* Magic. */
4947         RTL_W8(DBG_REG, 0x20);
4948
4949         RTL_W8(MaxTxPacketSize, TxPacketMax);
4950
4951         if (tp->dev->mtu <= ETH_DATA_LEN)
4952                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4953
4954         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4955 }
4956
4957 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4958 {
4959         void __iomem *ioaddr = tp->mmio_addr;
4960         static const struct ephy_info e_info_8168c_1[] = {
4961                 { 0x02, 0x0800, 0x1000 },
4962                 { 0x03, 0,      0x0002 },
4963                 { 0x06, 0x0080, 0x0000 }
4964         };
4965
4966         rtl_csi_access_enable_2(tp);
4967
4968         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4969
4970         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4971
4972         __rtl_hw_start_8168cp(tp);
4973 }
4974
4975 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4976 {
4977         static const struct ephy_info e_info_8168c_2[] = {
4978                 { 0x01, 0,      0x0001 },
4979                 { 0x03, 0x0400, 0x0220 }
4980         };
4981
4982         rtl_csi_access_enable_2(tp);
4983
4984         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4985
4986         __rtl_hw_start_8168cp(tp);
4987 }
4988
4989 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4990 {
4991         rtl_hw_start_8168c_2(tp);
4992 }
4993
4994 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4995 {
4996         rtl_csi_access_enable_2(tp);
4997
4998         __rtl_hw_start_8168cp(tp);
4999 }
5000
5001 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5002 {
5003         void __iomem *ioaddr = tp->mmio_addr;
5004         struct pci_dev *pdev = tp->pci_dev;
5005
5006         rtl_csi_access_enable_2(tp);
5007
5008         rtl_disable_clock_request(pdev);
5009
5010         RTL_W8(MaxTxPacketSize, TxPacketMax);
5011
5012         if (tp->dev->mtu <= ETH_DATA_LEN)
5013                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5014
5015         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5016 }
5017
5018 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5019 {
5020         void __iomem *ioaddr = tp->mmio_addr;
5021         struct pci_dev *pdev = tp->pci_dev;
5022
5023         rtl_csi_access_enable_1(tp);
5024
5025         if (tp->dev->mtu <= ETH_DATA_LEN)
5026                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5027
5028         RTL_W8(MaxTxPacketSize, TxPacketMax);
5029
5030         rtl_disable_clock_request(pdev);
5031 }
5032
5033 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5034 {
5035         void __iomem *ioaddr = tp->mmio_addr;
5036         struct pci_dev *pdev = tp->pci_dev;
5037         static const struct ephy_info e_info_8168d_4[] = {
5038                 { 0x0b, ~0,     0x48 },
5039                 { 0x19, 0x20,   0x50 },
5040                 { 0x0c, ~0,     0x20 }
5041         };
5042         int i;
5043
5044         rtl_csi_access_enable_1(tp);
5045
5046         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5047
5048         RTL_W8(MaxTxPacketSize, TxPacketMax);
5049
5050         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5051                 const struct ephy_info *e = e_info_8168d_4 + i;
5052                 u16 w;
5053
5054                 w = rtl_ephy_read(tp, e->offset);
5055                 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
5056         }
5057
5058         rtl_enable_clock_request(pdev);
5059 }
5060
5061 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5062 {
5063         void __iomem *ioaddr = tp->mmio_addr;
5064         struct pci_dev *pdev = tp->pci_dev;
5065         static const struct ephy_info e_info_8168e_1[] = {
5066                 { 0x00, 0x0200, 0x0100 },
5067                 { 0x00, 0x0000, 0x0004 },
5068                 { 0x06, 0x0002, 0x0001 },
5069                 { 0x06, 0x0000, 0x0030 },
5070                 { 0x07, 0x0000, 0x2000 },
5071                 { 0x00, 0x0000, 0x0020 },
5072                 { 0x03, 0x5800, 0x2000 },
5073                 { 0x03, 0x0000, 0x0001 },
5074                 { 0x01, 0x0800, 0x1000 },
5075                 { 0x07, 0x0000, 0x4000 },
5076                 { 0x1e, 0x0000, 0x2000 },
5077                 { 0x19, 0xffff, 0xfe6c },
5078                 { 0x0a, 0x0000, 0x0040 }
5079         };
5080
5081         rtl_csi_access_enable_2(tp);
5082
5083         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5084
5085         if (tp->dev->mtu <= ETH_DATA_LEN)
5086                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5087
5088         RTL_W8(MaxTxPacketSize, TxPacketMax);
5089
5090         rtl_disable_clock_request(pdev);
5091
5092         /* Reset tx FIFO pointer */
5093         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5094         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5095
5096         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5097 }
5098
5099 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5100 {
5101         void __iomem *ioaddr = tp->mmio_addr;
5102         struct pci_dev *pdev = tp->pci_dev;
5103         static const struct ephy_info e_info_8168e_2[] = {
5104                 { 0x09, 0x0000, 0x0080 },
5105                 { 0x19, 0x0000, 0x0224 }
5106         };
5107
5108         rtl_csi_access_enable_1(tp);
5109
5110         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5111
5112         if (tp->dev->mtu <= ETH_DATA_LEN)
5113                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5114
5115         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5116         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5117         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5118         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5119         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5120         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5121         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5122         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5123
5124         RTL_W8(MaxTxPacketSize, EarlySize);
5125
5126         rtl_disable_clock_request(pdev);
5127
5128         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5129         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5130
5131         /* Adjust EEE LED frequency */
5132         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5133
5134         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5135         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5136         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5137 }
5138
5139 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5140 {
5141         void __iomem *ioaddr = tp->mmio_addr;
5142         struct pci_dev *pdev = tp->pci_dev;
5143
5144         rtl_csi_access_enable_2(tp);
5145
5146         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5147
5148         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5149         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5150         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5151         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5152         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5153         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5154         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5155         rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5156         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5157         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5158
5159         RTL_W8(MaxTxPacketSize, EarlySize);
5160
5161         rtl_disable_clock_request(pdev);
5162
5163         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5164         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5165         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5166         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5167         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5168 }
5169
5170 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5171 {
5172         void __iomem *ioaddr = tp->mmio_addr;
5173         static const struct ephy_info e_info_8168f_1[] = {
5174                 { 0x06, 0x00c0, 0x0020 },
5175                 { 0x08, 0x0001, 0x0002 },
5176                 { 0x09, 0x0000, 0x0080 },
5177                 { 0x19, 0x0000, 0x0224 }
5178         };
5179
5180         rtl_hw_start_8168f(tp);
5181
5182         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5183
5184         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5185
5186         /* Adjust EEE LED frequency */
5187         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5188 }
5189
5190 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5191 {
5192         static const struct ephy_info e_info_8168f_1[] = {
5193                 { 0x06, 0x00c0, 0x0020 },
5194                 { 0x0f, 0xffff, 0x5200 },
5195                 { 0x1e, 0x0000, 0x4000 },
5196                 { 0x19, 0x0000, 0x0224 }
5197         };
5198
5199         rtl_hw_start_8168f(tp);
5200
5201         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5202
5203         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5204 }
5205
5206 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5207 {
5208         void __iomem *ioaddr = tp->mmio_addr;
5209         struct pci_dev *pdev = tp->pci_dev;
5210
5211         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5212
5213         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5214         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5215         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5216         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5217
5218         rtl_csi_access_enable_1(tp);
5219
5220         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5221
5222         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5223         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5224         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5225
5226         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5227         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5228         RTL_W8(MaxTxPacketSize, EarlySize);
5229
5230         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5231         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5232
5233         /* Adjust EEE LED frequency */
5234         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5235
5236         rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5237         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5238 }
5239
5240 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5241 {
5242         void __iomem *ioaddr = tp->mmio_addr;
5243         static const struct ephy_info e_info_8168g_2[] = {
5244                 { 0x00, 0x0000, 0x0008 },
5245                 { 0x0c, 0x3df0, 0x0200 },
5246                 { 0x19, 0xffff, 0xfc00 },
5247                 { 0x1e, 0xffff, 0x20eb }
5248         };
5249
5250         rtl_hw_start_8168g_1(tp);
5251
5252         /* disable aspm and clock request before access ephy */
5253         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5254         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5255         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5256 }
5257
5258 static void rtl_hw_start_8168(struct net_device *dev)
5259 {
5260         struct rtl8169_private *tp = netdev_priv(dev);
5261         void __iomem *ioaddr = tp->mmio_addr;
5262
5263         RTL_W8(Cfg9346, Cfg9346_Unlock);
5264
5265         RTL_W8(MaxTxPacketSize, TxPacketMax);
5266
5267         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5268
5269         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
5270
5271         RTL_W16(CPlusCmd, tp->cp_cmd);
5272
5273         RTL_W16(IntrMitigate, 0x5151);
5274
5275         /* Work around for RxFIFO overflow. */
5276         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5277                 tp->event_slow |= RxFIFOOver | PCSTimeout;
5278                 tp->event_slow &= ~RxOverflow;
5279         }
5280
5281         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5282
5283         rtl_set_rx_tx_config_registers(tp);
5284
5285         RTL_R8(IntrMask);
5286
5287         switch (tp->mac_version) {
5288         case RTL_GIGA_MAC_VER_11:
5289                 rtl_hw_start_8168bb(tp);
5290                 break;
5291
5292         case RTL_GIGA_MAC_VER_12:
5293         case RTL_GIGA_MAC_VER_17:
5294                 rtl_hw_start_8168bef(tp);
5295                 break;
5296
5297         case RTL_GIGA_MAC_VER_18:
5298                 rtl_hw_start_8168cp_1(tp);
5299                 break;
5300
5301         case RTL_GIGA_MAC_VER_19:
5302                 rtl_hw_start_8168c_1(tp);
5303                 break;
5304
5305         case RTL_GIGA_MAC_VER_20:
5306                 rtl_hw_start_8168c_2(tp);
5307                 break;
5308
5309         case RTL_GIGA_MAC_VER_21:
5310                 rtl_hw_start_8168c_3(tp);
5311                 break;
5312
5313         case RTL_GIGA_MAC_VER_22:
5314                 rtl_hw_start_8168c_4(tp);
5315                 break;
5316
5317         case RTL_GIGA_MAC_VER_23:
5318                 rtl_hw_start_8168cp_2(tp);
5319                 break;
5320
5321         case RTL_GIGA_MAC_VER_24:
5322                 rtl_hw_start_8168cp_3(tp);
5323                 break;
5324
5325         case RTL_GIGA_MAC_VER_25:
5326         case RTL_GIGA_MAC_VER_26:
5327         case RTL_GIGA_MAC_VER_27:
5328                 rtl_hw_start_8168d(tp);
5329                 break;
5330
5331         case RTL_GIGA_MAC_VER_28:
5332                 rtl_hw_start_8168d_4(tp);
5333                 break;
5334
5335         case RTL_GIGA_MAC_VER_31:
5336                 rtl_hw_start_8168dp(tp);
5337                 break;
5338
5339         case RTL_GIGA_MAC_VER_32:
5340         case RTL_GIGA_MAC_VER_33:
5341                 rtl_hw_start_8168e_1(tp);
5342                 break;
5343         case RTL_GIGA_MAC_VER_34:
5344                 rtl_hw_start_8168e_2(tp);
5345                 break;
5346
5347         case RTL_GIGA_MAC_VER_35:
5348         case RTL_GIGA_MAC_VER_36:
5349                 rtl_hw_start_8168f_1(tp);
5350                 break;
5351
5352         case RTL_GIGA_MAC_VER_38:
5353                 rtl_hw_start_8411(tp);
5354                 break;
5355
5356         case RTL_GIGA_MAC_VER_40:
5357         case RTL_GIGA_MAC_VER_41:
5358                 rtl_hw_start_8168g_1(tp);
5359                 break;
5360         case RTL_GIGA_MAC_VER_42:
5361                 rtl_hw_start_8168g_2(tp);
5362                 break;
5363
5364         default:
5365                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5366                         dev->name, tp->mac_version);
5367                 break;
5368         }
5369
5370         RTL_W8(Cfg9346, Cfg9346_Lock);
5371
5372         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5373
5374         rtl_set_rx_mode(dev);
5375
5376         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
5377 }
5378
5379 #define R810X_CPCMD_QUIRK_MASK (\
5380         EnableBist | \
5381         Mac_dbgo_oe | \
5382         Force_half_dup | \
5383         Force_rxflow_en | \
5384         Force_txflow_en | \
5385         Cxpl_dbg_sel | \
5386         ASF | \
5387         PktCntrDisable | \
5388         Mac_dbgo_sel)
5389
5390 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5391 {
5392         void __iomem *ioaddr = tp->mmio_addr;
5393         struct pci_dev *pdev = tp->pci_dev;
5394         static const struct ephy_info e_info_8102e_1[] = {
5395                 { 0x01, 0, 0x6e65 },
5396                 { 0x02, 0, 0x091f },
5397                 { 0x03, 0, 0xc2f9 },
5398                 { 0x06, 0, 0xafb5 },
5399                 { 0x07, 0, 0x0e00 },
5400                 { 0x19, 0, 0xec80 },
5401                 { 0x01, 0, 0x2e65 },
5402                 { 0x01, 0, 0x6e65 }
5403         };
5404         u8 cfg1;
5405
5406         rtl_csi_access_enable_2(tp);
5407
5408         RTL_W8(DBG_REG, FIX_NAK_1);
5409
5410         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5411
5412         RTL_W8(Config1,
5413                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5414         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5415
5416         cfg1 = RTL_R8(Config1);
5417         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5418                 RTL_W8(Config1, cfg1 & ~LEDS0);
5419
5420         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5421 }
5422
5423 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5424 {
5425         void __iomem *ioaddr = tp->mmio_addr;
5426         struct pci_dev *pdev = tp->pci_dev;
5427
5428         rtl_csi_access_enable_2(tp);
5429
5430         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5431
5432         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5433         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5434 }
5435
5436 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5437 {
5438         rtl_hw_start_8102e_2(tp);
5439
5440         rtl_ephy_write(tp, 0x03, 0xc2f9);
5441 }
5442
5443 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5444 {
5445         void __iomem *ioaddr = tp->mmio_addr;
5446         static const struct ephy_info e_info_8105e_1[] = {
5447                 { 0x07, 0, 0x4000 },
5448                 { 0x19, 0, 0x0200 },
5449                 { 0x19, 0, 0x0020 },
5450                 { 0x1e, 0, 0x2000 },
5451                 { 0x03, 0, 0x0001 },
5452                 { 0x19, 0, 0x0100 },
5453                 { 0x19, 0, 0x0004 },
5454                 { 0x0a, 0, 0x0020 }
5455         };
5456
5457         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5458         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5459
5460         /* Disable Early Tally Counter */
5461         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5462
5463         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5464         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5465
5466         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5467 }
5468
5469 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5470 {
5471         rtl_hw_start_8105e_1(tp);
5472         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5473 }
5474
5475 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5476 {
5477         void __iomem *ioaddr = tp->mmio_addr;
5478         static const struct ephy_info e_info_8402[] = {
5479                 { 0x19, 0xffff, 0xff64 },
5480                 { 0x1e, 0, 0x4000 }
5481         };
5482
5483         rtl_csi_access_enable_2(tp);
5484
5485         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5486         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5487
5488         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5489         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5490
5491         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5492
5493         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5494
5495         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5496         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5497         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5498         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5499         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5500         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5501         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5502 }
5503
5504 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5505 {
5506         void __iomem *ioaddr = tp->mmio_addr;
5507
5508         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5509         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5510
5511         RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5512         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5513         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5514 }
5515
5516 static void rtl_hw_start_8101(struct net_device *dev)
5517 {
5518         struct rtl8169_private *tp = netdev_priv(dev);
5519         void __iomem *ioaddr = tp->mmio_addr;
5520         struct pci_dev *pdev = tp->pci_dev;
5521
5522         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5523                 tp->event_slow &= ~RxFIFOOver;
5524
5525         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5526             tp->mac_version == RTL_GIGA_MAC_VER_16)
5527                 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
5528                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5529
5530         RTL_W8(Cfg9346, Cfg9346_Unlock);
5531
5532         RTL_W8(MaxTxPacketSize, TxPacketMax);
5533
5534         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5535
5536         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5537         RTL_W16(CPlusCmd, tp->cp_cmd);
5538
5539         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5540
5541         rtl_set_rx_tx_config_registers(tp);
5542
5543         switch (tp->mac_version) {
5544         case RTL_GIGA_MAC_VER_07:
5545                 rtl_hw_start_8102e_1(tp);
5546                 break;
5547
5548         case RTL_GIGA_MAC_VER_08:
5549                 rtl_hw_start_8102e_3(tp);
5550                 break;
5551
5552         case RTL_GIGA_MAC_VER_09:
5553                 rtl_hw_start_8102e_2(tp);
5554                 break;
5555
5556         case RTL_GIGA_MAC_VER_29:
5557                 rtl_hw_start_8105e_1(tp);
5558                 break;
5559         case RTL_GIGA_MAC_VER_30:
5560                 rtl_hw_start_8105e_2(tp);
5561                 break;
5562
5563         case RTL_GIGA_MAC_VER_37:
5564                 rtl_hw_start_8402(tp);
5565                 break;
5566
5567         case RTL_GIGA_MAC_VER_39:
5568                 rtl_hw_start_8106(tp);
5569                 break;
5570         case RTL_GIGA_MAC_VER_43:
5571                 rtl_hw_start_8168g_2(tp);
5572                 break;
5573         }
5574
5575         RTL_W8(Cfg9346, Cfg9346_Lock);
5576
5577         RTL_W16(IntrMitigate, 0x0000);
5578
5579         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5580
5581         rtl_set_rx_mode(dev);
5582
5583         RTL_R8(IntrMask);
5584
5585         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5586 }
5587
5588 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5589 {
5590         struct rtl8169_private *tp = netdev_priv(dev);
5591
5592         if (new_mtu < ETH_ZLEN ||
5593             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
5594                 return -EINVAL;
5595
5596         if (new_mtu > ETH_DATA_LEN)
5597                 rtl_hw_jumbo_enable(tp);
5598         else
5599                 rtl_hw_jumbo_disable(tp);
5600
5601         dev->mtu = new_mtu;
5602         netdev_update_features(dev);
5603
5604         return 0;
5605 }
5606
5607 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5608 {
5609         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5610         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5611 }
5612
5613 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5614                                      void **data_buff, struct RxDesc *desc)
5615 {
5616         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
5617                          DMA_FROM_DEVICE);
5618
5619         kfree(*data_buff);
5620         *data_buff = NULL;
5621         rtl8169_make_unusable_by_asic(desc);
5622 }
5623
5624 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5625 {
5626         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5627
5628         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5629 }
5630
5631 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5632                                        u32 rx_buf_sz)
5633 {
5634         desc->addr = cpu_to_le64(mapping);
5635         wmb();
5636         rtl8169_mark_to_asic(desc, rx_buf_sz);
5637 }
5638
5639 static inline void *rtl8169_align(void *data)
5640 {
5641         return (void *)ALIGN((long)data, 16);
5642 }
5643
5644 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5645                                              struct RxDesc *desc)
5646 {
5647         void *data;
5648         dma_addr_t mapping;
5649         struct device *d = &tp->pci_dev->dev;
5650         struct net_device *dev = tp->dev;
5651         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5652
5653         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5654         if (!data)
5655                 return NULL;
5656
5657         if (rtl8169_align(data) != data) {
5658                 kfree(data);
5659                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5660                 if (!data)
5661                         return NULL;
5662         }
5663
5664         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5665                                  DMA_FROM_DEVICE);
5666         if (unlikely(dma_mapping_error(d, mapping))) {
5667                 if (net_ratelimit())
5668                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5669                 goto err_out;
5670         }
5671
5672         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5673         return data;
5674
5675 err_out:
5676         kfree(data);
5677         return NULL;
5678 }
5679
5680 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5681 {
5682         unsigned int i;
5683
5684         for (i = 0; i < NUM_RX_DESC; i++) {
5685                 if (tp->Rx_databuff[i]) {
5686                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5687                                             tp->RxDescArray + i);
5688                 }
5689         }
5690 }
5691
5692 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5693 {
5694         desc->opts1 |= cpu_to_le32(RingEnd);
5695 }
5696
5697 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5698 {
5699         unsigned int i;
5700
5701         for (i = 0; i < NUM_RX_DESC; i++) {
5702                 void *data;
5703
5704                 if (tp->Rx_databuff[i])
5705                         continue;
5706
5707                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5708                 if (!data) {
5709                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5710                         goto err_out;
5711                 }
5712                 tp->Rx_databuff[i] = data;
5713         }
5714
5715         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5716         return 0;
5717
5718 err_out:
5719         rtl8169_rx_clear(tp);
5720         return -ENOMEM;
5721 }
5722
5723 static int rtl8169_init_ring(struct net_device *dev)
5724 {
5725         struct rtl8169_private *tp = netdev_priv(dev);
5726
5727         rtl8169_init_ring_indexes(tp);
5728
5729         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5730         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5731
5732         return rtl8169_rx_fill(tp);
5733 }
5734
5735 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5736                                  struct TxDesc *desc)
5737 {
5738         unsigned int len = tx_skb->len;
5739
5740         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5741
5742         desc->opts1 = 0x00;
5743         desc->opts2 = 0x00;
5744         desc->addr = 0x00;
5745         tx_skb->len = 0;
5746 }
5747
5748 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5749                                    unsigned int n)
5750 {
5751         unsigned int i;
5752
5753         for (i = 0; i < n; i++) {
5754                 unsigned int entry = (start + i) % NUM_TX_DESC;
5755                 struct ring_info *tx_skb = tp->tx_skb + entry;
5756                 unsigned int len = tx_skb->len;
5757
5758                 if (len) {
5759                         struct sk_buff *skb = tx_skb->skb;
5760
5761                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5762                                              tp->TxDescArray + entry);
5763                         if (skb) {
5764                                 tp->dev->stats.tx_dropped++;
5765                                 dev_kfree_skb(skb);
5766                                 tx_skb->skb = NULL;
5767                         }
5768                 }
5769         }
5770 }
5771
5772 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5773 {
5774         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5775         tp->cur_tx = tp->dirty_tx = 0;
5776 }
5777
5778 static void rtl_reset_work(struct rtl8169_private *tp)
5779 {
5780         struct net_device *dev = tp->dev;
5781         int i;
5782
5783         napi_disable(&tp->napi);
5784         netif_stop_queue(dev);
5785         synchronize_sched();
5786
5787         rtl8169_hw_reset(tp);
5788
5789         for (i = 0; i < NUM_RX_DESC; i++)
5790                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5791
5792         rtl8169_tx_clear(tp);
5793         rtl8169_init_ring_indexes(tp);
5794
5795         napi_enable(&tp->napi);
5796         rtl_hw_start(dev);
5797         netif_wake_queue(dev);
5798         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5799 }
5800
5801 static void rtl8169_tx_timeout(struct net_device *dev)
5802 {
5803         struct rtl8169_private *tp = netdev_priv(dev);
5804
5805         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5806 }
5807
5808 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5809                               u32 *opts)
5810 {
5811         struct skb_shared_info *info = skb_shinfo(skb);
5812         unsigned int cur_frag, entry;
5813         struct TxDesc * uninitialized_var(txd);
5814         struct device *d = &tp->pci_dev->dev;
5815
5816         entry = tp->cur_tx;
5817         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5818                 const skb_frag_t *frag = info->frags + cur_frag;
5819                 dma_addr_t mapping;
5820                 u32 status, len;
5821                 void *addr;
5822
5823                 entry = (entry + 1) % NUM_TX_DESC;
5824
5825                 txd = tp->TxDescArray + entry;
5826                 len = skb_frag_size(frag);
5827                 addr = skb_frag_address(frag);
5828                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5829                 if (unlikely(dma_mapping_error(d, mapping))) {
5830                         if (net_ratelimit())
5831                                 netif_err(tp, drv, tp->dev,
5832                                           "Failed to map TX fragments DMA!\n");
5833                         goto err_out;
5834                 }
5835
5836                 /* Anti gcc 2.95.3 bugware (sic) */
5837                 status = opts[0] | len |
5838                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5839
5840                 txd->opts1 = cpu_to_le32(status);
5841                 txd->opts2 = cpu_to_le32(opts[1]);
5842                 txd->addr = cpu_to_le64(mapping);
5843
5844                 tp->tx_skb[entry].len = len;
5845         }
5846
5847         if (cur_frag) {
5848                 tp->tx_skb[entry].skb = skb;
5849                 txd->opts1 |= cpu_to_le32(LastFrag);
5850         }
5851
5852         return cur_frag;
5853
5854 err_out:
5855         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5856         return -EIO;
5857 }
5858
5859 static bool rtl_skb_pad(struct sk_buff *skb)
5860 {
5861         if (skb_padto(skb, ETH_ZLEN))
5862                 return false;
5863         skb_put(skb, ETH_ZLEN - skb->len);
5864         return true;
5865 }
5866
5867 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5868 {
5869         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5870 }
5871
5872 static inline bool rtl8169_tso_csum(struct rtl8169_private *tp,
5873                                     struct sk_buff *skb, u32 *opts)
5874 {
5875         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5876         u32 mss = skb_shinfo(skb)->gso_size;
5877         int offset = info->opts_offset;
5878
5879         if (mss) {
5880                 opts[0] |= TD_LSO;
5881                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5882         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5883                 const struct iphdr *ip = ip_hdr(skb);
5884
5885                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5886                         return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb);
5887
5888                 if (ip->protocol == IPPROTO_TCP)
5889                         opts[offset] |= info->checksum.tcp;
5890                 else if (ip->protocol == IPPROTO_UDP)
5891                         opts[offset] |= info->checksum.udp;
5892                 else
5893                         WARN_ON_ONCE(1);
5894         } else {
5895                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5896                         return rtl_skb_pad(skb);
5897         }
5898         return true;
5899 }
5900
5901 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5902                                       struct net_device *dev)
5903 {
5904         struct rtl8169_private *tp = netdev_priv(dev);
5905         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5906         struct TxDesc *txd = tp->TxDescArray + entry;
5907         void __iomem *ioaddr = tp->mmio_addr;
5908         struct device *d = &tp->pci_dev->dev;
5909         dma_addr_t mapping;
5910         u32 status, len;
5911         u32 opts[2];
5912         int frags;
5913
5914         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5915                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5916                 goto err_stop_0;
5917         }
5918
5919         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5920                 goto err_stop_0;
5921
5922         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
5923         opts[0] = DescOwn;
5924
5925         if (!rtl8169_tso_csum(tp, skb, opts))
5926                 goto err_update_stats;
5927
5928         len = skb_headlen(skb);
5929         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5930         if (unlikely(dma_mapping_error(d, mapping))) {
5931                 if (net_ratelimit())
5932                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5933                 goto err_dma_0;
5934         }
5935
5936         tp->tx_skb[entry].len = len;
5937         txd->addr = cpu_to_le64(mapping);
5938
5939         frags = rtl8169_xmit_frags(tp, skb, opts);
5940         if (frags < 0)
5941                 goto err_dma_1;
5942         else if (frags)
5943                 opts[0] |= FirstFrag;
5944         else {
5945                 opts[0] |= FirstFrag | LastFrag;
5946                 tp->tx_skb[entry].skb = skb;
5947         }
5948
5949         txd->opts2 = cpu_to_le32(opts[1]);
5950
5951         skb_tx_timestamp(skb);
5952
5953         wmb();
5954
5955         /* Anti gcc 2.95.3 bugware (sic) */
5956         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5957         txd->opts1 = cpu_to_le32(status);
5958
5959         tp->cur_tx += frags + 1;
5960
5961         wmb();
5962
5963         RTL_W8(TxPoll, NPQ);
5964
5965         mmiowb();
5966
5967         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5968                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5969                  * not miss a ring update when it notices a stopped queue.
5970                  */
5971                 smp_wmb();
5972                 netif_stop_queue(dev);
5973                 /* Sync with rtl_tx:
5974                  * - publish queue status and cur_tx ring index (write barrier)
5975                  * - refresh dirty_tx ring index (read barrier).
5976                  * May the current thread have a pessimistic view of the ring
5977                  * status and forget to wake up queue, a racing rtl_tx thread
5978                  * can't.
5979                  */
5980                 smp_mb();
5981                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
5982                         netif_wake_queue(dev);
5983         }
5984
5985         return NETDEV_TX_OK;
5986
5987 err_dma_1:
5988         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5989 err_dma_0:
5990         dev_kfree_skb(skb);
5991 err_update_stats:
5992         dev->stats.tx_dropped++;
5993         return NETDEV_TX_OK;
5994
5995 err_stop_0:
5996         netif_stop_queue(dev);
5997         dev->stats.tx_dropped++;
5998         return NETDEV_TX_BUSY;
5999 }
6000
6001 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6002 {
6003         struct rtl8169_private *tp = netdev_priv(dev);
6004         struct pci_dev *pdev = tp->pci_dev;
6005         u16 pci_status, pci_cmd;
6006
6007         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6008         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6009
6010         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6011                   pci_cmd, pci_status);
6012
6013         /*
6014          * The recovery sequence below admits a very elaborated explanation:
6015          * - it seems to work;
6016          * - I did not see what else could be done;
6017          * - it makes iop3xx happy.
6018          *
6019          * Feel free to adjust to your needs.
6020          */
6021         if (pdev->broken_parity_status)
6022                 pci_cmd &= ~PCI_COMMAND_PARITY;
6023         else
6024                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6025
6026         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6027
6028         pci_write_config_word(pdev, PCI_STATUS,
6029                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6030                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6031                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6032
6033         /* The infamous DAC f*ckup only happens at boot time */
6034         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6035                 void __iomem *ioaddr = tp->mmio_addr;
6036
6037                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6038                 tp->cp_cmd &= ~PCIDAC;
6039                 RTL_W16(CPlusCmd, tp->cp_cmd);
6040                 dev->features &= ~NETIF_F_HIGHDMA;
6041         }
6042
6043         rtl8169_hw_reset(tp);
6044
6045         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6046 }
6047
6048 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6049 {
6050         unsigned int dirty_tx, tx_left;
6051
6052         dirty_tx = tp->dirty_tx;
6053         smp_rmb();
6054         tx_left = tp->cur_tx - dirty_tx;
6055
6056         while (tx_left > 0) {
6057                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6058                 struct ring_info *tx_skb = tp->tx_skb + entry;
6059                 u32 status;
6060
6061                 rmb();
6062                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6063                 if (status & DescOwn)
6064                         break;
6065
6066                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6067                                      tp->TxDescArray + entry);
6068                 if (status & LastFrag) {
6069                         u64_stats_update_begin(&tp->tx_stats.syncp);
6070                         tp->tx_stats.packets++;
6071                         tp->tx_stats.bytes += tx_skb->skb->len;
6072                         u64_stats_update_end(&tp->tx_stats.syncp);
6073                         dev_kfree_skb(tx_skb->skb);
6074                         tx_skb->skb = NULL;
6075                 }
6076                 dirty_tx++;
6077                 tx_left--;
6078         }
6079
6080         if (tp->dirty_tx != dirty_tx) {
6081                 tp->dirty_tx = dirty_tx;
6082                 /* Sync with rtl8169_start_xmit:
6083                  * - publish dirty_tx ring index (write barrier)
6084                  * - refresh cur_tx ring index and queue status (read barrier)
6085                  * May the current thread miss the stopped queue condition,
6086                  * a racing xmit thread can only have a right view of the
6087                  * ring status.
6088                  */
6089                 smp_mb();
6090                 if (netif_queue_stopped(dev) &&
6091                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6092                         netif_wake_queue(dev);
6093                 }
6094                 /*
6095                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6096                  * too close. Let's kick an extra TxPoll request when a burst
6097                  * of start_xmit activity is detected (if it is not detected,
6098                  * it is slow enough). -- FR
6099                  */
6100                 if (tp->cur_tx != dirty_tx) {
6101                         void __iomem *ioaddr = tp->mmio_addr;
6102
6103                         RTL_W8(TxPoll, NPQ);
6104                 }
6105         }
6106 }
6107
6108 static inline int rtl8169_fragmented_frame(u32 status)
6109 {
6110         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6111 }
6112
6113 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6114 {
6115         u32 status = opts1 & RxProtoMask;
6116
6117         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6118             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6119                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6120         else
6121                 skb_checksum_none_assert(skb);
6122 }
6123
6124 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6125                                            struct rtl8169_private *tp,
6126                                            int pkt_size,
6127                                            dma_addr_t addr)
6128 {
6129         struct sk_buff *skb;
6130         struct device *d = &tp->pci_dev->dev;
6131
6132         data = rtl8169_align(data);
6133         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6134         prefetch(data);
6135         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6136         if (skb)
6137                 memcpy(skb->data, data, pkt_size);
6138         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6139
6140         return skb;
6141 }
6142
6143 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6144 {
6145         unsigned int cur_rx, rx_left;
6146         unsigned int count;
6147
6148         cur_rx = tp->cur_rx;
6149
6150         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6151                 unsigned int entry = cur_rx % NUM_RX_DESC;
6152                 struct RxDesc *desc = tp->RxDescArray + entry;
6153                 u32 status;
6154
6155                 rmb();
6156                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
6157
6158                 if (status & DescOwn)
6159                         break;
6160                 if (unlikely(status & RxRES)) {
6161                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6162                                    status);
6163                         dev->stats.rx_errors++;
6164                         if (status & (RxRWT | RxRUNT))
6165                                 dev->stats.rx_length_errors++;
6166                         if (status & RxCRC)
6167                                 dev->stats.rx_crc_errors++;
6168                         if (status & RxFOVF) {
6169                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6170                                 dev->stats.rx_fifo_errors++;
6171                         }
6172                         if ((status & (RxRUNT | RxCRC)) &&
6173                             !(status & (RxRWT | RxFOVF)) &&
6174                             (dev->features & NETIF_F_RXALL))
6175                                 goto process_pkt;
6176                 } else {
6177                         struct sk_buff *skb;
6178                         dma_addr_t addr;
6179                         int pkt_size;
6180
6181 process_pkt:
6182                         addr = le64_to_cpu(desc->addr);
6183                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6184                                 pkt_size = (status & 0x00003fff) - 4;
6185                         else
6186                                 pkt_size = status & 0x00003fff;
6187
6188                         /*
6189                          * The driver does not support incoming fragmented
6190                          * frames. They are seen as a symptom of over-mtu
6191                          * sized frames.
6192                          */
6193                         if (unlikely(rtl8169_fragmented_frame(status))) {
6194                                 dev->stats.rx_dropped++;
6195                                 dev->stats.rx_length_errors++;
6196                                 goto release_descriptor;
6197                         }
6198
6199                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6200                                                   tp, pkt_size, addr);
6201                         if (!skb) {
6202                                 dev->stats.rx_dropped++;
6203                                 goto release_descriptor;
6204                         }
6205
6206                         rtl8169_rx_csum(skb, status);
6207                         skb_put(skb, pkt_size);
6208                         skb->protocol = eth_type_trans(skb, dev);
6209
6210                         rtl8169_rx_vlan_tag(desc, skb);
6211
6212                         napi_gro_receive(&tp->napi, skb);
6213
6214                         u64_stats_update_begin(&tp->rx_stats.syncp);
6215                         tp->rx_stats.packets++;
6216                         tp->rx_stats.bytes += pkt_size;
6217                         u64_stats_update_end(&tp->rx_stats.syncp);
6218                 }
6219 release_descriptor:
6220                 desc->opts2 = 0;
6221                 wmb();
6222                 rtl8169_mark_to_asic(desc, rx_buf_sz);
6223         }
6224
6225         count = cur_rx - tp->cur_rx;
6226         tp->cur_rx = cur_rx;
6227
6228         return count;
6229 }
6230
6231 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6232 {
6233         struct net_device *dev = dev_instance;
6234         struct rtl8169_private *tp = netdev_priv(dev);
6235         int handled = 0;
6236         u16 status;
6237
6238         status = rtl_get_events(tp);
6239         if (status && status != 0xffff) {
6240                 status &= RTL_EVENT_NAPI | tp->event_slow;
6241                 if (status) {
6242                         handled = 1;
6243
6244                         rtl_irq_disable(tp);
6245                         napi_schedule(&tp->napi);
6246                 }
6247         }
6248         return IRQ_RETVAL(handled);
6249 }
6250
6251 /*
6252  * Workqueue context.
6253  */
6254 static void rtl_slow_event_work(struct rtl8169_private *tp)
6255 {
6256         struct net_device *dev = tp->dev;
6257         u16 status;
6258
6259         status = rtl_get_events(tp) & tp->event_slow;
6260         rtl_ack_events(tp, status);
6261
6262         if (unlikely(status & RxFIFOOver)) {
6263                 switch (tp->mac_version) {
6264                 /* Work around for rx fifo overflow */
6265                 case RTL_GIGA_MAC_VER_11:
6266                         netif_stop_queue(dev);
6267                         /* XXX - Hack alert. See rtl_task(). */
6268                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6269                 default:
6270                         break;
6271                 }
6272         }
6273
6274         if (unlikely(status & SYSErr))
6275                 rtl8169_pcierr_interrupt(dev);
6276
6277         if (status & LinkChg)
6278                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
6279
6280         rtl_irq_enable_all(tp);
6281 }
6282
6283 static void rtl_task(struct work_struct *work)
6284 {
6285         static const struct {
6286                 int bitnr;
6287                 void (*action)(struct rtl8169_private *);
6288         } rtl_work[] = {
6289                 /* XXX - keep rtl_slow_event_work() as first element. */
6290                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
6291                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6292                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
6293         };
6294         struct rtl8169_private *tp =
6295                 container_of(work, struct rtl8169_private, wk.work);
6296         struct net_device *dev = tp->dev;
6297         int i;
6298
6299         rtl_lock_work(tp);
6300
6301         if (!netif_running(dev) ||
6302             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6303                 goto out_unlock;
6304
6305         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6306                 bool pending;
6307
6308                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6309                 if (pending)
6310                         rtl_work[i].action(tp);
6311         }
6312
6313 out_unlock:
6314         rtl_unlock_work(tp);
6315 }
6316
6317 static int rtl8169_poll(struct napi_struct *napi, int budget)
6318 {
6319         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6320         struct net_device *dev = tp->dev;
6321         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6322         int work_done= 0;
6323         u16 status;
6324
6325         status = rtl_get_events(tp);
6326         rtl_ack_events(tp, status & ~tp->event_slow);
6327
6328         if (status & RTL_EVENT_NAPI_RX)
6329                 work_done = rtl_rx(dev, tp, (u32) budget);
6330
6331         if (status & RTL_EVENT_NAPI_TX)
6332                 rtl_tx(dev, tp);
6333
6334         if (status & tp->event_slow) {
6335                 enable_mask &= ~tp->event_slow;
6336
6337                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6338         }
6339
6340         if (work_done < budget) {
6341                 napi_complete(napi);
6342
6343                 rtl_irq_enable(tp, enable_mask);
6344                 mmiowb();
6345         }
6346
6347         return work_done;
6348 }
6349
6350 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6351 {
6352         struct rtl8169_private *tp = netdev_priv(dev);
6353
6354         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6355                 return;
6356
6357         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6358         RTL_W32(RxMissed, 0);
6359 }
6360
6361 static void rtl8169_down(struct net_device *dev)
6362 {
6363         struct rtl8169_private *tp = netdev_priv(dev);
6364         void __iomem *ioaddr = tp->mmio_addr;
6365
6366         del_timer_sync(&tp->timer);
6367
6368         napi_disable(&tp->napi);
6369         netif_stop_queue(dev);
6370
6371         rtl8169_hw_reset(tp);
6372         /*
6373          * At this point device interrupts can not be enabled in any function,
6374          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6375          * and napi is disabled (rtl8169_poll).
6376          */
6377         rtl8169_rx_missed(dev, ioaddr);
6378
6379         /* Give a racing hard_start_xmit a few cycles to complete. */
6380         synchronize_sched();
6381
6382         rtl8169_tx_clear(tp);
6383
6384         rtl8169_rx_clear(tp);
6385
6386         rtl_pll_power_down(tp);
6387 }
6388
6389 static int rtl8169_close(struct net_device *dev)
6390 {
6391         struct rtl8169_private *tp = netdev_priv(dev);
6392         struct pci_dev *pdev = tp->pci_dev;
6393
6394         pm_runtime_get_sync(&pdev->dev);
6395
6396         /* Update counters before going down */
6397         rtl8169_update_counters(dev);
6398
6399         rtl_lock_work(tp);
6400         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6401
6402         rtl8169_down(dev);
6403         rtl_unlock_work(tp);
6404
6405         free_irq(pdev->irq, dev);
6406
6407         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6408                           tp->RxPhyAddr);
6409         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6410                           tp->TxPhyAddr);
6411         tp->TxDescArray = NULL;
6412         tp->RxDescArray = NULL;
6413
6414         pm_runtime_put_sync(&pdev->dev);
6415
6416         return 0;
6417 }
6418
6419 #ifdef CONFIG_NET_POLL_CONTROLLER
6420 static void rtl8169_netpoll(struct net_device *dev)
6421 {
6422         struct rtl8169_private *tp = netdev_priv(dev);
6423
6424         rtl8169_interrupt(tp->pci_dev->irq, dev);
6425 }
6426 #endif
6427
6428 static int rtl_open(struct net_device *dev)
6429 {
6430         struct rtl8169_private *tp = netdev_priv(dev);
6431         void __iomem *ioaddr = tp->mmio_addr;
6432         struct pci_dev *pdev = tp->pci_dev;
6433         int retval = -ENOMEM;
6434
6435         pm_runtime_get_sync(&pdev->dev);
6436
6437         /*
6438          * Rx and Tx descriptors needs 256 bytes alignment.
6439          * dma_alloc_coherent provides more.
6440          */
6441         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6442                                              &tp->TxPhyAddr, GFP_KERNEL);
6443         if (!tp->TxDescArray)
6444                 goto err_pm_runtime_put;
6445
6446         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6447                                              &tp->RxPhyAddr, GFP_KERNEL);
6448         if (!tp->RxDescArray)
6449                 goto err_free_tx_0;
6450
6451         retval = rtl8169_init_ring(dev);
6452         if (retval < 0)
6453                 goto err_free_rx_1;
6454
6455         INIT_WORK(&tp->wk.work, rtl_task);
6456
6457         smp_mb();
6458
6459         rtl_request_firmware(tp);
6460
6461         retval = request_irq(pdev->irq, rtl8169_interrupt,
6462                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6463                              dev->name, dev);
6464         if (retval < 0)
6465                 goto err_release_fw_2;
6466
6467         rtl_lock_work(tp);
6468
6469         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6470
6471         napi_enable(&tp->napi);
6472
6473         rtl8169_init_phy(dev, tp);
6474
6475         __rtl8169_set_features(dev, dev->features);
6476
6477         rtl_pll_power_up(tp);
6478
6479         rtl_hw_start(dev);
6480
6481         netif_start_queue(dev);
6482
6483         rtl_unlock_work(tp);
6484
6485         tp->saved_wolopts = 0;
6486         pm_runtime_put_noidle(&pdev->dev);
6487
6488         rtl8169_check_link_status(dev, tp, ioaddr);
6489 out:
6490         return retval;
6491
6492 err_release_fw_2:
6493         rtl_release_firmware(tp);
6494         rtl8169_rx_clear(tp);
6495 err_free_rx_1:
6496         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6497                           tp->RxPhyAddr);
6498         tp->RxDescArray = NULL;
6499 err_free_tx_0:
6500         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6501                           tp->TxPhyAddr);
6502         tp->TxDescArray = NULL;
6503 err_pm_runtime_put:
6504         pm_runtime_put_noidle(&pdev->dev);
6505         goto out;
6506 }
6507
6508 static struct rtnl_link_stats64 *
6509 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6510 {
6511         struct rtl8169_private *tp = netdev_priv(dev);
6512         void __iomem *ioaddr = tp->mmio_addr;
6513         unsigned int start;
6514
6515         if (netif_running(dev))
6516                 rtl8169_rx_missed(dev, ioaddr);
6517
6518         do {
6519                 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6520                 stats->rx_packets = tp->rx_stats.packets;
6521                 stats->rx_bytes = tp->rx_stats.bytes;
6522         } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6523
6524
6525         do {
6526                 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6527                 stats->tx_packets = tp->tx_stats.packets;
6528                 stats->tx_bytes = tp->tx_stats.bytes;
6529         } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6530
6531         stats->rx_dropped       = dev->stats.rx_dropped;
6532         stats->tx_dropped       = dev->stats.tx_dropped;
6533         stats->rx_length_errors = dev->stats.rx_length_errors;
6534         stats->rx_errors        = dev->stats.rx_errors;
6535         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6536         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6537         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6538
6539         return stats;
6540 }
6541
6542 static void rtl8169_net_suspend(struct net_device *dev)
6543 {
6544         struct rtl8169_private *tp = netdev_priv(dev);
6545
6546         if (!netif_running(dev))
6547                 return;
6548
6549         netif_device_detach(dev);
6550         netif_stop_queue(dev);
6551
6552         rtl_lock_work(tp);
6553         napi_disable(&tp->napi);
6554         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6555         rtl_unlock_work(tp);
6556
6557         rtl_pll_power_down(tp);
6558 }
6559
6560 #ifdef CONFIG_PM
6561
6562 static int rtl8169_suspend(struct device *device)
6563 {
6564         struct pci_dev *pdev = to_pci_dev(device);
6565         struct net_device *dev = pci_get_drvdata(pdev);
6566
6567         rtl8169_net_suspend(dev);
6568
6569         return 0;
6570 }
6571
6572 static void __rtl8169_resume(struct net_device *dev)
6573 {
6574         struct rtl8169_private *tp = netdev_priv(dev);
6575
6576         netif_device_attach(dev);
6577
6578         rtl_pll_power_up(tp);
6579
6580         rtl_lock_work(tp);
6581         napi_enable(&tp->napi);
6582         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6583         rtl_unlock_work(tp);
6584
6585         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6586 }
6587
6588 static int rtl8169_resume(struct device *device)
6589 {
6590         struct pci_dev *pdev = to_pci_dev(device);
6591         struct net_device *dev = pci_get_drvdata(pdev);
6592         struct rtl8169_private *tp = netdev_priv(dev);
6593
6594         rtl8169_init_phy(dev, tp);
6595
6596         if (netif_running(dev))
6597                 __rtl8169_resume(dev);
6598
6599         return 0;
6600 }
6601
6602 static int rtl8169_runtime_suspend(struct device *device)
6603 {
6604         struct pci_dev *pdev = to_pci_dev(device);
6605         struct net_device *dev = pci_get_drvdata(pdev);
6606         struct rtl8169_private *tp = netdev_priv(dev);
6607
6608         if (!tp->TxDescArray)
6609                 return 0;
6610
6611         rtl_lock_work(tp);
6612         tp->saved_wolopts = __rtl8169_get_wol(tp);
6613         __rtl8169_set_wol(tp, WAKE_ANY);
6614         rtl_unlock_work(tp);
6615
6616         rtl8169_net_suspend(dev);
6617
6618         return 0;
6619 }
6620
6621 static int rtl8169_runtime_resume(struct device *device)
6622 {
6623         struct pci_dev *pdev = to_pci_dev(device);
6624         struct net_device *dev = pci_get_drvdata(pdev);
6625         struct rtl8169_private *tp = netdev_priv(dev);
6626
6627         if (!tp->TxDescArray)
6628                 return 0;
6629
6630         rtl_lock_work(tp);
6631         __rtl8169_set_wol(tp, tp->saved_wolopts);
6632         tp->saved_wolopts = 0;
6633         rtl_unlock_work(tp);
6634
6635         rtl8169_init_phy(dev, tp);
6636
6637         __rtl8169_resume(dev);
6638
6639         return 0;
6640 }
6641
6642 static int rtl8169_runtime_idle(struct device *device)
6643 {
6644         struct pci_dev *pdev = to_pci_dev(device);
6645         struct net_device *dev = pci_get_drvdata(pdev);
6646         struct rtl8169_private *tp = netdev_priv(dev);
6647
6648         return tp->TxDescArray ? -EBUSY : 0;
6649 }
6650
6651 static const struct dev_pm_ops rtl8169_pm_ops = {
6652         .suspend                = rtl8169_suspend,
6653         .resume                 = rtl8169_resume,
6654         .freeze                 = rtl8169_suspend,
6655         .thaw                   = rtl8169_resume,
6656         .poweroff               = rtl8169_suspend,
6657         .restore                = rtl8169_resume,
6658         .runtime_suspend        = rtl8169_runtime_suspend,
6659         .runtime_resume         = rtl8169_runtime_resume,
6660         .runtime_idle           = rtl8169_runtime_idle,
6661 };
6662
6663 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6664
6665 #else /* !CONFIG_PM */
6666
6667 #define RTL8169_PM_OPS  NULL
6668
6669 #endif /* !CONFIG_PM */
6670
6671 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6672 {
6673         void __iomem *ioaddr = tp->mmio_addr;
6674
6675         /* WoL fails with 8168b when the receiver is disabled. */
6676         switch (tp->mac_version) {
6677         case RTL_GIGA_MAC_VER_11:
6678         case RTL_GIGA_MAC_VER_12:
6679         case RTL_GIGA_MAC_VER_17:
6680                 pci_clear_master(tp->pci_dev);
6681
6682                 RTL_W8(ChipCmd, CmdRxEnb);
6683                 /* PCI commit */
6684                 RTL_R8(ChipCmd);
6685                 break;
6686         default:
6687                 break;
6688         }
6689 }
6690
6691 static void rtl_shutdown(struct pci_dev *pdev)
6692 {
6693         struct net_device *dev = pci_get_drvdata(pdev);
6694         struct rtl8169_private *tp = netdev_priv(dev);
6695         struct device *d = &pdev->dev;
6696
6697         pm_runtime_get_sync(d);
6698
6699         rtl8169_net_suspend(dev);
6700
6701         /* Restore original MAC address */
6702         rtl_rar_set(tp, dev->perm_addr);
6703
6704         rtl8169_hw_reset(tp);
6705
6706         if (system_state == SYSTEM_POWER_OFF) {
6707                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6708                         rtl_wol_suspend_quirk(tp);
6709                         rtl_wol_shutdown_quirk(tp);
6710                 }
6711
6712                 pci_wake_from_d3(pdev, true);
6713                 pci_set_power_state(pdev, PCI_D3hot);
6714         }
6715
6716         pm_runtime_put_noidle(d);
6717 }
6718
6719 static void rtl_remove_one(struct pci_dev *pdev)
6720 {
6721         struct net_device *dev = pci_get_drvdata(pdev);
6722         struct rtl8169_private *tp = netdev_priv(dev);
6723
6724         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6725             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6726             tp->mac_version == RTL_GIGA_MAC_VER_31) {
6727                 rtl8168_driver_stop(tp);
6728         }
6729
6730         cancel_work_sync(&tp->wk.work);
6731
6732         netif_napi_del(&tp->napi);
6733
6734         unregister_netdev(dev);
6735
6736         rtl_release_firmware(tp);
6737
6738         if (pci_dev_run_wake(pdev))
6739                 pm_runtime_get_noresume(&pdev->dev);
6740
6741         /* restore original MAC address */
6742         rtl_rar_set(tp, dev->perm_addr);
6743
6744         rtl_disable_msi(pdev, tp);
6745         rtl8169_release_board(pdev, dev, tp->mmio_addr);
6746         pci_set_drvdata(pdev, NULL);
6747 }
6748
6749 static const struct net_device_ops rtl_netdev_ops = {
6750         .ndo_open               = rtl_open,
6751         .ndo_stop               = rtl8169_close,
6752         .ndo_get_stats64        = rtl8169_get_stats64,
6753         .ndo_start_xmit         = rtl8169_start_xmit,
6754         .ndo_tx_timeout         = rtl8169_tx_timeout,
6755         .ndo_validate_addr      = eth_validate_addr,
6756         .ndo_change_mtu         = rtl8169_change_mtu,
6757         .ndo_fix_features       = rtl8169_fix_features,
6758         .ndo_set_features       = rtl8169_set_features,
6759         .ndo_set_mac_address    = rtl_set_mac_address,
6760         .ndo_do_ioctl           = rtl8169_ioctl,
6761         .ndo_set_rx_mode        = rtl_set_rx_mode,
6762 #ifdef CONFIG_NET_POLL_CONTROLLER
6763         .ndo_poll_controller    = rtl8169_netpoll,
6764 #endif
6765
6766 };
6767
6768 static const struct rtl_cfg_info {
6769         void (*hw_start)(struct net_device *);
6770         unsigned int region;
6771         unsigned int align;
6772         u16 event_slow;
6773         unsigned features;
6774         u8 default_ver;
6775 } rtl_cfg_infos [] = {
6776         [RTL_CFG_0] = {
6777                 .hw_start       = rtl_hw_start_8169,
6778                 .region         = 1,
6779                 .align          = 0,
6780                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6781                 .features       = RTL_FEATURE_GMII,
6782                 .default_ver    = RTL_GIGA_MAC_VER_01,
6783         },
6784         [RTL_CFG_1] = {
6785                 .hw_start       = rtl_hw_start_8168,
6786                 .region         = 2,
6787                 .align          = 8,
6788                 .event_slow     = SYSErr | LinkChg | RxOverflow,
6789                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6790                 .default_ver    = RTL_GIGA_MAC_VER_11,
6791         },
6792         [RTL_CFG_2] = {
6793                 .hw_start       = rtl_hw_start_8101,
6794                 .region         = 2,
6795                 .align          = 8,
6796                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6797                                   PCSTimeout,
6798                 .features       = RTL_FEATURE_MSI,
6799                 .default_ver    = RTL_GIGA_MAC_VER_13,
6800         }
6801 };
6802
6803 /* Cfg9346_Unlock assumed. */
6804 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6805                             const struct rtl_cfg_info *cfg)
6806 {
6807         void __iomem *ioaddr = tp->mmio_addr;
6808         unsigned msi = 0;
6809         u8 cfg2;
6810
6811         cfg2 = RTL_R8(Config2) & ~MSIEnable;
6812         if (cfg->features & RTL_FEATURE_MSI) {
6813                 if (pci_enable_msi(tp->pci_dev)) {
6814                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6815                 } else {
6816                         cfg2 |= MSIEnable;
6817                         msi = RTL_FEATURE_MSI;
6818                 }
6819         }
6820         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6821                 RTL_W8(Config2, cfg2);
6822         return msi;
6823 }
6824
6825 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6826 {
6827         void __iomem *ioaddr = tp->mmio_addr;
6828
6829         return RTL_R8(MCU) & LINK_LIST_RDY;
6830 }
6831
6832 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6833 {
6834         void __iomem *ioaddr = tp->mmio_addr;
6835
6836         return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6837 }
6838
6839 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6840 {
6841         void __iomem *ioaddr = tp->mmio_addr;
6842         u32 data;
6843
6844         tp->ocp_base = OCP_STD_PHY_BASE;
6845
6846         RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
6847
6848         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6849                 return;
6850
6851         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6852                 return;
6853
6854         RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6855         msleep(1);
6856         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6857
6858         data = r8168_mac_ocp_read(tp, 0xe8de);
6859         data &= ~(1 << 14);
6860         r8168_mac_ocp_write(tp, 0xe8de, data);
6861
6862         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6863                 return;
6864
6865         data = r8168_mac_ocp_read(tp, 0xe8de);
6866         data |= (1 << 15);
6867         r8168_mac_ocp_write(tp, 0xe8de, data);
6868
6869         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6870                 return;
6871 }
6872
6873 static void rtl_hw_initialize(struct rtl8169_private *tp)
6874 {
6875         switch (tp->mac_version) {
6876         case RTL_GIGA_MAC_VER_40:
6877         case RTL_GIGA_MAC_VER_41:
6878         case RTL_GIGA_MAC_VER_42:
6879         case RTL_GIGA_MAC_VER_43:
6880                 rtl_hw_init_8168g(tp);
6881                 break;
6882
6883         default:
6884                 break;
6885         }
6886 }
6887
6888 static int
6889 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6890 {
6891         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6892         const unsigned int region = cfg->region;
6893         struct rtl8169_private *tp;
6894         struct mii_if_info *mii;
6895         struct net_device *dev;
6896         void __iomem *ioaddr;
6897         int chipset, i;
6898         int rc;
6899
6900         if (netif_msg_drv(&debug)) {
6901                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6902                        MODULENAME, RTL8169_VERSION);
6903         }
6904
6905         dev = alloc_etherdev(sizeof (*tp));
6906         if (!dev) {
6907                 rc = -ENOMEM;
6908                 goto out;
6909         }
6910
6911         SET_NETDEV_DEV(dev, &pdev->dev);
6912         dev->netdev_ops = &rtl_netdev_ops;
6913         tp = netdev_priv(dev);
6914         tp->dev = dev;
6915         tp->pci_dev = pdev;
6916         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6917
6918         mii = &tp->mii;
6919         mii->dev = dev;
6920         mii->mdio_read = rtl_mdio_read;
6921         mii->mdio_write = rtl_mdio_write;
6922         mii->phy_id_mask = 0x1f;
6923         mii->reg_num_mask = 0x1f;
6924         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6925
6926         /* disable ASPM completely as that cause random device stop working
6927          * problems as well as full system hangs for some PCIe devices users */
6928         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6929                                      PCIE_LINK_STATE_CLKPM);
6930
6931         /* enable device (incl. PCI PM wakeup and hotplug setup) */
6932         rc = pci_enable_device(pdev);
6933         if (rc < 0) {
6934                 netif_err(tp, probe, dev, "enable failure\n");
6935                 goto err_out_free_dev_1;
6936         }
6937
6938         if (pci_set_mwi(pdev) < 0)
6939                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6940
6941         /* make sure PCI base addr 1 is MMIO */
6942         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6943                 netif_err(tp, probe, dev,
6944                           "region #%d not an MMIO resource, aborting\n",
6945                           region);
6946                 rc = -ENODEV;
6947                 goto err_out_mwi_2;
6948         }
6949
6950         /* check for weird/broken PCI region reporting */
6951         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6952                 netif_err(tp, probe, dev,
6953                           "Invalid PCI region size(s), aborting\n");
6954                 rc = -ENODEV;
6955                 goto err_out_mwi_2;
6956         }
6957
6958         rc = pci_request_regions(pdev, MODULENAME);
6959         if (rc < 0) {
6960                 netif_err(tp, probe, dev, "could not request regions\n");
6961                 goto err_out_mwi_2;
6962         }
6963
6964         tp->cp_cmd = RxChkSum;
6965
6966         if ((sizeof(dma_addr_t) > 4) &&
6967             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6968                 tp->cp_cmd |= PCIDAC;
6969                 dev->features |= NETIF_F_HIGHDMA;
6970         } else {
6971                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6972                 if (rc < 0) {
6973                         netif_err(tp, probe, dev, "DMA configuration failed\n");
6974                         goto err_out_free_res_3;
6975                 }
6976         }
6977
6978         /* ioremap MMIO region */
6979         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6980         if (!ioaddr) {
6981                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6982                 rc = -EIO;
6983                 goto err_out_free_res_3;
6984         }
6985         tp->mmio_addr = ioaddr;
6986
6987         if (!pci_is_pcie(pdev))
6988                 netif_info(tp, probe, dev, "not PCI Express\n");
6989
6990         /* Identify chip attached to board */
6991         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6992
6993         rtl_init_rxcfg(tp);
6994
6995         rtl_irq_disable(tp);
6996
6997         rtl_hw_initialize(tp);
6998
6999         rtl_hw_reset(tp);
7000
7001         rtl_ack_events(tp, 0xffff);
7002
7003         pci_set_master(pdev);
7004
7005         /*
7006          * Pretend we are using VLANs; This bypasses a nasty bug where
7007          * Interrupts stop flowing on high load on 8110SCd controllers.
7008          */
7009         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7010                 tp->cp_cmd |= RxVlan;
7011
7012         rtl_init_mdio_ops(tp);
7013         rtl_init_pll_power_ops(tp);
7014         rtl_init_jumbo_ops(tp);
7015         rtl_init_csi_ops(tp);
7016
7017         rtl8169_print_mac_version(tp);
7018
7019         chipset = tp->mac_version;
7020         tp->txd_version = rtl_chip_infos[chipset].txd_version;
7021
7022         RTL_W8(Cfg9346, Cfg9346_Unlock);
7023         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
7024         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
7025         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
7026                 tp->features |= RTL_FEATURE_WOL;
7027         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
7028                 tp->features |= RTL_FEATURE_WOL;
7029         tp->features |= rtl_try_msi(tp, cfg);
7030         RTL_W8(Cfg9346, Cfg9346_Lock);
7031
7032         if (rtl_tbi_enabled(tp)) {
7033                 tp->set_speed = rtl8169_set_speed_tbi;
7034                 tp->get_settings = rtl8169_gset_tbi;
7035                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
7036                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
7037                 tp->link_ok = rtl8169_tbi_link_ok;
7038                 tp->do_ioctl = rtl_tbi_ioctl;
7039         } else {
7040                 tp->set_speed = rtl8169_set_speed_xmii;
7041                 tp->get_settings = rtl8169_gset_xmii;
7042                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
7043                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
7044                 tp->link_ok = rtl8169_xmii_link_ok;
7045                 tp->do_ioctl = rtl_xmii_ioctl;
7046         }
7047
7048         mutex_init(&tp->wk.mutex);
7049
7050         /* Get MAC address */
7051         for (i = 0; i < ETH_ALEN; i++)
7052                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
7053
7054         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
7055         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
7056
7057         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
7058
7059         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7060          * properly for all devices */
7061         dev->features |= NETIF_F_RXCSUM |
7062                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7063
7064         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7065                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7066                 NETIF_F_HW_VLAN_CTAG_RX;
7067         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7068                 NETIF_F_HIGHDMA;
7069
7070         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7071                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
7072                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7073
7074         dev->hw_features |= NETIF_F_RXALL;
7075         dev->hw_features |= NETIF_F_RXFCS;
7076
7077         tp->hw_start = cfg->hw_start;
7078         tp->event_slow = cfg->event_slow;
7079
7080         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
7081                 ~(RxBOVF | RxFOVF) : ~0;
7082
7083         init_timer(&tp->timer);
7084         tp->timer.data = (unsigned long) dev;
7085         tp->timer.function = rtl8169_phy_timer;
7086
7087         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7088
7089         rc = register_netdev(dev);
7090         if (rc < 0)
7091                 goto err_out_msi_4;
7092
7093         pci_set_drvdata(pdev, dev);
7094
7095         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
7096                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
7097                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
7098         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7099                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7100                            "tx checksumming: %s]\n",
7101                            rtl_chip_infos[chipset].jumbo_max,
7102                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
7103         }
7104
7105         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7106             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7107             tp->mac_version == RTL_GIGA_MAC_VER_31) {
7108                 rtl8168_driver_start(tp);
7109         }
7110
7111         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
7112
7113         if (pci_dev_run_wake(pdev))
7114                 pm_runtime_put_noidle(&pdev->dev);
7115
7116         netif_carrier_off(dev);
7117
7118 out:
7119         return rc;
7120
7121 err_out_msi_4:
7122         netif_napi_del(&tp->napi);
7123         rtl_disable_msi(pdev, tp);
7124         iounmap(ioaddr);
7125 err_out_free_res_3:
7126         pci_release_regions(pdev);
7127 err_out_mwi_2:
7128         pci_clear_mwi(pdev);
7129         pci_disable_device(pdev);
7130 err_out_free_dev_1:
7131         free_netdev(dev);
7132         goto out;
7133 }
7134
7135 static struct pci_driver rtl8169_pci_driver = {
7136         .name           = MODULENAME,
7137         .id_table       = rtl8169_pci_tbl,
7138         .probe          = rtl_init_one,
7139         .remove         = rtl_remove_one,
7140         .shutdown       = rtl_shutdown,
7141         .driver.pm      = RTL8169_PM_OPS,
7142 };
7143
7144 module_pci_driver(rtl8169_pci_driver);