2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 * Copyright (C) 2012 Marvell
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/kernel.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/platform_device.h>
18 #include <linux/skbuff.h>
19 #include <linux/inetdevice.h>
20 #include <linux/mbus.h>
21 #include <linux/module.h>
22 #include <linux/interrupt.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_net.h>
29 #include <linux/of_address.h>
30 #include <linux/phy.h>
31 #include <linux/clk.h>
34 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
35 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
36 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
37 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
38 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
39 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
40 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
41 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
42 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
43 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
44 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
45 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
46 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
47 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
48 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
49 #define MVNETA_PORT_RX_RESET 0x1cc0
50 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
51 #define MVNETA_PHY_ADDR 0x2000
52 #define MVNETA_PHY_ADDR_MASK 0x1f
53 #define MVNETA_MBUS_RETRY 0x2010
54 #define MVNETA_UNIT_INTR_CAUSE 0x2080
55 #define MVNETA_UNIT_CONTROL 0x20B0
56 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
57 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
58 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
59 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
60 #define MVNETA_BASE_ADDR_ENABLE 0x2290
61 #define MVNETA_PORT_CONFIG 0x2400
62 #define MVNETA_UNI_PROMISC_MODE BIT(0)
63 #define MVNETA_DEF_RXQ(q) ((q) << 1)
64 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
65 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
66 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
67 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
68 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
69 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
70 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
71 MVNETA_DEF_RXQ_ARP(q) | \
72 MVNETA_DEF_RXQ_TCP(q) | \
73 MVNETA_DEF_RXQ_UDP(q) | \
74 MVNETA_DEF_RXQ_BPDU(q) | \
75 MVNETA_TX_UNSET_ERR_SUM | \
76 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
77 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
78 #define MVNETA_MAC_ADDR_LOW 0x2414
79 #define MVNETA_MAC_ADDR_HIGH 0x2418
80 #define MVNETA_SDMA_CONFIG 0x241c
81 #define MVNETA_SDMA_BRST_SIZE_16 4
82 #define MVNETA_NO_DESC_SWAP 0x0
83 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
84 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
85 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
86 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
87 #define MVNETA_PORT_STATUS 0x2444
88 #define MVNETA_TX_IN_PRGRS BIT(1)
89 #define MVNETA_TX_FIFO_EMPTY BIT(8)
90 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
91 #define MVNETA_TYPE_PRIO 0x24bc
92 #define MVNETA_FORCE_UNI BIT(21)
93 #define MVNETA_TXQ_CMD_1 0x24e4
94 #define MVNETA_TXQ_CMD 0x2448
95 #define MVNETA_TXQ_DISABLE_SHIFT 8
96 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
97 #define MVNETA_ACC_MODE 0x2500
98 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
99 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
100 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
101 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
102 #define MVNETA_INTR_NEW_CAUSE 0x25a0
103 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
104 #define MVNETA_INTR_NEW_MASK 0x25a4
105 #define MVNETA_INTR_OLD_CAUSE 0x25a8
106 #define MVNETA_INTR_OLD_MASK 0x25ac
107 #define MVNETA_INTR_MISC_CAUSE 0x25b0
108 #define MVNETA_INTR_MISC_MASK 0x25b4
109 #define MVNETA_INTR_ENABLE 0x25b8
110 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
111 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0xff000000
112 #define MVNETA_RXQ_CMD 0x2680
113 #define MVNETA_RXQ_DISABLE_SHIFT 8
114 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
115 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
116 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
117 #define MVNETA_GMAC_CTRL_0 0x2c00
118 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
119 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
120 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
121 #define MVNETA_GMAC_CTRL_2 0x2c08
122 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
123 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
124 #define MVNETA_GMAC2_PORT_RESET BIT(6)
125 #define MVNETA_GMAC_STATUS 0x2c10
126 #define MVNETA_GMAC_LINK_UP BIT(0)
127 #define MVNETA_GMAC_SPEED_1000 BIT(1)
128 #define MVNETA_GMAC_SPEED_100 BIT(2)
129 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
130 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
131 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
132 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
133 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
134 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
135 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
136 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
137 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
138 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
139 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
140 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
141 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
142 #define MVNETA_MIB_COUNTERS_BASE 0x3080
143 #define MVNETA_MIB_LATE_COLLISION 0x7c
144 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
145 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
146 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
147 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
148 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
149 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
150 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
151 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
152 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
153 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
154 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
155 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
156 #define MVNETA_PORT_TX_RESET 0x3cf0
157 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
158 #define MVNETA_TX_MTU 0x3e0c
159 #define MVNETA_TX_TOKEN_SIZE 0x3e14
160 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
161 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
162 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
164 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
166 /* Descriptor ring Macros */
167 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
168 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
170 /* Various constants */
173 #define MVNETA_TXDONE_COAL_PKTS 16
174 #define MVNETA_RX_COAL_PKTS 32
175 #define MVNETA_RX_COAL_USEC 100
178 #define MVNETA_TX_DONE_TIMER_PERIOD 10
180 /* Napi polling weight */
181 #define MVNETA_RX_POLL_WEIGHT 64
183 /* The two bytes Marvell header. Either contains a special value used
184 * by Marvell switches when a specific hardware mode is enabled (not
185 * supported by this driver) or is filled automatically by zeroes on
186 * the RX side. Those two bytes being at the front of the Ethernet
187 * header, they allow to have the IP header aligned on a 4 bytes
188 * boundary automatically: the hardware skips those two bytes on its
191 #define MVNETA_MH_SIZE 2
193 #define MVNETA_VLAN_TAG_LEN 4
195 #define MVNETA_CPU_D_CACHE_LINE_SIZE 32
196 #define MVNETA_TX_CSUM_MAX_SIZE 9800
197 #define MVNETA_ACC_MODE_EXT 1
199 /* Timeout constants */
200 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
201 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
202 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
204 #define MVNETA_TX_MTU_MAX 0x3ffff
206 /* Max number of Rx descriptors */
207 #define MVNETA_MAX_RXD 128
209 /* Max number of Tx descriptors */
210 #define MVNETA_MAX_TXD 532
212 /* descriptor aligned size */
213 #define MVNETA_DESC_ALIGNED_SIZE 32
215 #define MVNETA_RX_PKT_SIZE(mtu) \
216 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
217 ETH_HLEN + ETH_FCS_LEN, \
218 MVNETA_CPU_D_CACHE_LINE_SIZE)
220 #define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
222 struct mvneta_stats {
223 struct u64_stats_sync syncp;
231 struct mvneta_rx_queue *rxqs;
232 struct mvneta_tx_queue *txqs;
233 struct timer_list tx_done_timer;
234 struct net_device *dev;
237 struct napi_struct napi;
241 #define MVNETA_F_TX_DONE_TIMER_BIT 0
251 struct mvneta_stats tx_stats;
252 struct mvneta_stats rx_stats;
254 struct mii_bus *mii_bus;
255 struct phy_device *phy_dev;
256 phy_interface_t phy_interface;
257 struct device_node *phy_node;
263 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
264 * layout of the transmit and reception DMA descriptors, and their
265 * layout is therefore defined by the hardware design
267 struct mvneta_tx_desc {
268 u32 command; /* Options used by HW for packet transmitting.*/
269 #define MVNETA_TX_L3_OFF_SHIFT 0
270 #define MVNETA_TX_IP_HLEN_SHIFT 8
271 #define MVNETA_TX_L4_UDP BIT(16)
272 #define MVNETA_TX_L3_IP6 BIT(17)
273 #define MVNETA_TXD_IP_CSUM BIT(18)
274 #define MVNETA_TXD_Z_PAD BIT(19)
275 #define MVNETA_TXD_L_DESC BIT(20)
276 #define MVNETA_TXD_F_DESC BIT(21)
277 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
278 MVNETA_TXD_L_DESC | \
280 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
281 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
283 u16 reserverd1; /* csum_l4 (for future use) */
284 u16 data_size; /* Data size of transmitted packet in bytes */
285 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
286 u32 reserved2; /* hw_cmd - (for future use, PMT) */
287 u32 reserved3[4]; /* Reserved - (for future use) */
290 struct mvneta_rx_desc {
291 u32 status; /* Info about received packet */
292 #define MVNETA_RXD_ERR_CRC 0x0
293 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
294 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
295 #define MVNETA_RXD_ERR_LEN BIT(18)
296 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
297 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
298 #define MVNETA_RXD_L3_IP4 BIT(25)
299 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
300 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
302 u16 reserved1; /* pnc_info - (for future use, PnC) */
303 u16 data_size; /* Size of received packet in bytes */
304 u32 buf_phys_addr; /* Physical address of the buffer */
305 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
306 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
307 u16 reserved3; /* prefetch_cmd, for future use */
308 u16 reserved4; /* csum_l4 - (for future use, PnC) */
309 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
310 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
313 struct mvneta_tx_queue {
314 /* Number of this TX queue, in the range 0-7 */
317 /* Number of TX DMA descriptors in the descriptor ring */
320 /* Number of currently used TX DMA descriptor in the
325 /* Array of transmitted skb */
326 struct sk_buff **tx_skb;
328 /* Index of last TX DMA descriptor that was inserted */
331 /* Index of the TX DMA descriptor to be cleaned up */
336 /* Virtual address of the TX DMA descriptors array */
337 struct mvneta_tx_desc *descs;
339 /* DMA address of the TX DMA descriptors array */
340 dma_addr_t descs_phys;
342 /* Index of the last TX DMA descriptor */
345 /* Index of the next TX DMA descriptor to process */
346 int next_desc_to_proc;
349 struct mvneta_rx_queue {
350 /* rx queue number, in the range 0-7 */
353 /* num of rx descriptors in the rx descriptor ring */
356 /* counter of times when mvneta_refill() failed */
362 /* Virtual address of the RX DMA descriptors array */
363 struct mvneta_rx_desc *descs;
365 /* DMA address of the RX DMA descriptors array */
366 dma_addr_t descs_phys;
368 /* Index of the last RX DMA descriptor */
371 /* Index of the next RX DMA descriptor to process */
372 int next_desc_to_proc;
375 static int rxq_number = 8;
376 static int txq_number = 8;
380 #define MVNETA_DRIVER_NAME "mvneta"
381 #define MVNETA_DRIVER_VERSION "1.0"
383 /* Utility/helper methods */
385 /* Write helper method */
386 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
388 writel(data, pp->base + offset);
391 /* Read helper method */
392 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
394 return readl(pp->base + offset);
397 /* Increment txq get counter */
398 static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
400 txq->txq_get_index++;
401 if (txq->txq_get_index == txq->size)
402 txq->txq_get_index = 0;
405 /* Increment txq put counter */
406 static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
408 txq->txq_put_index++;
409 if (txq->txq_put_index == txq->size)
410 txq->txq_put_index = 0;
414 /* Clear all MIB counters */
415 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
420 /* Perform dummy reads from MIB counters */
421 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
422 dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
425 /* Get System Network Statistics */
426 struct rtnl_link_stats64 *mvneta_get_stats64(struct net_device *dev,
427 struct rtnl_link_stats64 *stats)
429 struct mvneta_port *pp = netdev_priv(dev);
432 memset(stats, 0, sizeof(struct rtnl_link_stats64));
435 start = u64_stats_fetch_begin_bh(&pp->rx_stats.syncp);
436 stats->rx_packets = pp->rx_stats.packets;
437 stats->rx_bytes = pp->rx_stats.bytes;
438 } while (u64_stats_fetch_retry_bh(&pp->rx_stats.syncp, start));
442 start = u64_stats_fetch_begin_bh(&pp->tx_stats.syncp);
443 stats->tx_packets = pp->tx_stats.packets;
444 stats->tx_bytes = pp->tx_stats.bytes;
445 } while (u64_stats_fetch_retry_bh(&pp->tx_stats.syncp, start));
447 stats->rx_errors = dev->stats.rx_errors;
448 stats->rx_dropped = dev->stats.rx_dropped;
450 stats->tx_dropped = dev->stats.tx_dropped;
455 /* Rx descriptors helper methods */
457 /* Checks whether the given RX descriptor is both the first and the
458 * last descriptor for the RX packet. Each RX packet is currently
459 * received through a single RX descriptor, so not having each RX
460 * descriptor with its first and last bits set is an error
462 static int mvneta_rxq_desc_is_first_last(struct mvneta_rx_desc *desc)
464 return (desc->status & MVNETA_RXD_FIRST_LAST_DESC) ==
465 MVNETA_RXD_FIRST_LAST_DESC;
468 /* Add number of descriptors ready to receive new packets */
469 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
470 struct mvneta_rx_queue *rxq,
473 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
476 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
477 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
478 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
479 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
480 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
483 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
484 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
487 /* Get number of RX descriptors occupied by received packets */
488 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
489 struct mvneta_rx_queue *rxq)
493 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
494 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
497 /* Update num of rx desc called upon return from rx path or
498 * from mvneta_rxq_drop_pkts().
500 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
501 struct mvneta_rx_queue *rxq,
502 int rx_done, int rx_filled)
506 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
508 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
509 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
513 /* Only 255 descriptors can be added at once */
514 while ((rx_done > 0) || (rx_filled > 0)) {
515 if (rx_done <= 0xff) {
522 if (rx_filled <= 0xff) {
523 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
526 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
529 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
533 /* Get pointer to next RX descriptor to be processed by SW */
534 static struct mvneta_rx_desc *
535 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
537 int rx_desc = rxq->next_desc_to_proc;
539 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
540 return rxq->descs + rx_desc;
543 /* Change maximum receive size of the port. */
544 static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
548 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
549 val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
550 val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
551 MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
552 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
556 /* Set rx queue offset */
557 static void mvneta_rxq_offset_set(struct mvneta_port *pp,
558 struct mvneta_rx_queue *rxq,
563 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
564 val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
567 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
568 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
572 /* Tx descriptors helper methods */
574 /* Update HW with number of TX descriptors to be sent */
575 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
576 struct mvneta_tx_queue *txq,
581 /* Only 255 descriptors can be added at once ; Assume caller
582 * process TX desriptors in quanta less than 256
585 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
588 /* Get pointer to next TX descriptor to be processed (send) by HW */
589 static struct mvneta_tx_desc *
590 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
592 int tx_desc = txq->next_desc_to_proc;
594 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
595 return txq->descs + tx_desc;
598 /* Release the last allocated TX descriptor. Useful to handle DMA
599 * mapping failures in the TX path.
601 static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
603 if (txq->next_desc_to_proc == 0)
604 txq->next_desc_to_proc = txq->last_desc - 1;
606 txq->next_desc_to_proc--;
609 /* Set rxq buf size */
610 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
611 struct mvneta_rx_queue *rxq,
616 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
618 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
619 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
621 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
624 /* Disable buffer management (BM) */
625 static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
626 struct mvneta_rx_queue *rxq)
630 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
631 val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
632 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
637 /* Sets the RGMII Enable bit (RGMIIEn) in port MAC control register */
638 static void mvneta_gmac_rgmii_set(struct mvneta_port *pp, int enable)
642 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
645 val |= MVNETA_GMAC2_PORT_RGMII;
647 val &= ~MVNETA_GMAC2_PORT_RGMII;
649 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
652 /* Config SGMII port */
653 static void mvneta_port_sgmii_config(struct mvneta_port *pp)
657 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
658 val |= MVNETA_GMAC2_PCS_ENABLE;
659 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
662 /* Start the Ethernet port RX and TX activity */
663 static void mvneta_port_up(struct mvneta_port *pp)
668 /* Enable all initialized TXs. */
669 mvneta_mib_counters_clear(pp);
671 for (queue = 0; queue < txq_number; queue++) {
672 struct mvneta_tx_queue *txq = &pp->txqs[queue];
673 if (txq->descs != NULL)
674 q_map |= (1 << queue);
676 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
678 /* Enable all initialized RXQs. */
680 for (queue = 0; queue < rxq_number; queue++) {
681 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
682 if (rxq->descs != NULL)
683 q_map |= (1 << queue);
686 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
689 /* Stop the Ethernet port activity */
690 static void mvneta_port_down(struct mvneta_port *pp)
695 /* Stop Rx port activity. Check port Rx activity. */
696 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
698 /* Issue stop command for active channels only */
700 mvreg_write(pp, MVNETA_RXQ_CMD,
701 val << MVNETA_RXQ_DISABLE_SHIFT);
703 /* Wait for all Rx activity to terminate. */
706 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
708 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
714 val = mvreg_read(pp, MVNETA_RXQ_CMD);
715 } while (val & 0xff);
717 /* Stop Tx port activity. Check port Tx activity. Issue stop
718 * command for active channels only
720 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
723 mvreg_write(pp, MVNETA_TXQ_CMD,
724 (val << MVNETA_TXQ_DISABLE_SHIFT));
726 /* Wait for all Tx activity to terminate. */
729 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
731 "TIMEOUT for TX stopped status=0x%08x\n",
737 /* Check TX Command reg that all Txqs are stopped */
738 val = mvreg_read(pp, MVNETA_TXQ_CMD);
740 } while (val & 0xff);
742 /* Double check to verify that TX FIFO is empty */
745 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
747 "TX FIFO empty timeout status=0x08%x\n",
753 val = mvreg_read(pp, MVNETA_PORT_STATUS);
754 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
755 (val & MVNETA_TX_IN_PRGRS));
760 /* Enable the port by setting the port enable bit of the MAC control register */
761 static void mvneta_port_enable(struct mvneta_port *pp)
766 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
767 val |= MVNETA_GMAC0_PORT_ENABLE;
768 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
771 /* Disable the port and wait for about 200 usec before retuning */
772 static void mvneta_port_disable(struct mvneta_port *pp)
776 /* Reset the Enable bit in the Serial Control Register */
777 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
778 val &= ~MVNETA_GMAC0_PORT_ENABLE;
779 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
784 /* Multicast tables methods */
786 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
787 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
795 val = 0x1 | (queue << 1);
796 val |= (val << 24) | (val << 16) | (val << 8);
799 for (offset = 0; offset <= 0xc; offset += 4)
800 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
803 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
804 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
812 val = 0x1 | (queue << 1);
813 val |= (val << 24) | (val << 16) | (val << 8);
816 for (offset = 0; offset <= 0xfc; offset += 4)
817 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
821 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
822 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
828 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
831 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
832 val = 0x1 | (queue << 1);
833 val |= (val << 24) | (val << 16) | (val << 8);
836 for (offset = 0; offset <= 0xfc; offset += 4)
837 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
840 /* This method sets defaults to the NETA port:
841 * Clears interrupt Cause and Mask registers.
842 * Clears all MAC tables.
843 * Sets defaults to all registers.
844 * Resets RX and TX descriptor rings.
846 * This method can be called after mvneta_port_down() to return the port
847 * settings to defaults.
849 static void mvneta_defaults_set(struct mvneta_port *pp)
855 /* Clear all Cause registers */
856 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
857 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
858 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
860 /* Mask all interrupts */
861 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
862 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
863 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
864 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
866 /* Enable MBUS Retry bit16 */
867 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
869 /* Set CPU queue access map - all CPUs have access to all RX
870 * queues and to all TX queues
872 for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++)
873 mvreg_write(pp, MVNETA_CPU_MAP(cpu),
874 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
875 MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
877 /* Reset RX and TX DMAs */
878 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
879 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
881 /* Disable Legacy WRR, Disable EJP, Release from reset */
882 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
883 for (queue = 0; queue < txq_number; queue++) {
884 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
885 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
888 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
889 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
891 /* Set Port Acceleration Mode */
892 val = MVNETA_ACC_MODE_EXT;
893 mvreg_write(pp, MVNETA_ACC_MODE, val);
895 /* Update val of portCfg register accordingly with all RxQueue types */
896 val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
897 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
900 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
901 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
903 /* Build PORT_SDMA_CONFIG_REG */
906 /* Default burst size */
907 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
908 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
910 val |= (MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP |
911 MVNETA_NO_DESC_SWAP);
913 /* Assign port SDMA configuration */
914 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
916 /* Disable PHY polling in hardware, since we're using the
917 * kernel phylib to do this.
919 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
920 val &= ~MVNETA_PHY_POLLING_ENABLE;
921 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
923 mvneta_set_ucast_table(pp, -1);
924 mvneta_set_special_mcast_table(pp, -1);
925 mvneta_set_other_mcast_table(pp, -1);
927 /* Set port interrupt enable register - default enable all */
928 mvreg_write(pp, MVNETA_INTR_ENABLE,
929 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
930 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
933 /* Set max sizes for tx queues */
934 static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
940 mtu = max_tx_size * 8;
941 if (mtu > MVNETA_TX_MTU_MAX)
942 mtu = MVNETA_TX_MTU_MAX;
945 val = mvreg_read(pp, MVNETA_TX_MTU);
946 val &= ~MVNETA_TX_MTU_MAX;
948 mvreg_write(pp, MVNETA_TX_MTU, val);
950 /* TX token size and all TXQs token size must be larger that MTU */
951 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
953 size = val & MVNETA_TX_TOKEN_SIZE_MAX;
956 val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
958 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
960 for (queue = 0; queue < txq_number; queue++) {
961 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
963 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
966 val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
968 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
973 /* Set unicast address */
974 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
977 unsigned int unicast_reg;
978 unsigned int tbl_offset;
979 unsigned int reg_offset;
981 /* Locate the Unicast table entry */
982 last_nibble = (0xf & last_nibble);
984 /* offset from unicast tbl base */
985 tbl_offset = (last_nibble / 4) * 4;
987 /* offset within the above reg */
988 reg_offset = last_nibble % 4;
990 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
993 /* Clear accepts frame bit at specified unicast DA tbl entry */
994 unicast_reg &= ~(0xff << (8 * reg_offset));
996 unicast_reg &= ~(0xff << (8 * reg_offset));
997 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1000 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
1003 /* Set mac address */
1004 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
1011 mac_l = (addr[4] << 8) | (addr[5]);
1012 mac_h = (addr[0] << 24) | (addr[1] << 16) |
1013 (addr[2] << 8) | (addr[3] << 0);
1015 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1016 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1019 /* Accept frames of this address */
1020 mvneta_set_ucast_addr(pp, addr[5], queue);
1023 /* Set the number of packets that will be received before RX interrupt
1024 * will be generated by HW.
1026 static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1027 struct mvneta_rx_queue *rxq, u32 value)
1029 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1030 value | MVNETA_RXQ_NON_OCCUPIED(0));
1031 rxq->pkts_coal = value;
1034 /* Set the time delay in usec before RX interrupt will be generated by
1037 static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1038 struct mvneta_rx_queue *rxq, u32 value)
1041 unsigned long clk_rate;
1043 clk_rate = clk_get_rate(pp->clk);
1044 val = (clk_rate / 1000000) * value;
1046 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1047 rxq->time_coal = value;
1050 /* Set threshold for TX_DONE pkts coalescing */
1051 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
1052 struct mvneta_tx_queue *txq, u32 value)
1056 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1058 val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
1059 val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
1061 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1063 txq->done_pkts_coal = value;
1066 /* Trigger tx done timer in MVNETA_TX_DONE_TIMER_PERIOD msecs */
1067 static void mvneta_add_tx_done_timer(struct mvneta_port *pp)
1069 if (test_and_set_bit(MVNETA_F_TX_DONE_TIMER_BIT, &pp->flags) == 0) {
1070 pp->tx_done_timer.expires = jiffies +
1071 msecs_to_jiffies(MVNETA_TX_DONE_TIMER_PERIOD);
1072 add_timer(&pp->tx_done_timer);
1077 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1078 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
1079 u32 phys_addr, u32 cookie)
1081 rx_desc->buf_cookie = cookie;
1082 rx_desc->buf_phys_addr = phys_addr;
1085 /* Decrement sent descriptors counter */
1086 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
1087 struct mvneta_tx_queue *txq,
1092 /* Only 255 TX descriptors can be updated at once */
1093 while (sent_desc > 0xff) {
1094 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
1095 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1096 sent_desc = sent_desc - 0xff;
1099 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
1100 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1103 /* Get number of TX descriptors already sent by HW */
1104 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
1105 struct mvneta_tx_queue *txq)
1110 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
1111 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
1112 MVNETA_TXQ_SENT_DESC_SHIFT;
1117 /* Get number of sent descriptors and decrement counter.
1118 * The number of sent descriptors is returned.
1120 static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
1121 struct mvneta_tx_queue *txq)
1125 /* Get number of sent descriptors */
1126 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1128 /* Decrement sent descriptors counter */
1130 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1135 /* Set TXQ descriptors fields relevant for CSUM calculation */
1136 static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
1137 int ip_hdr_len, int l4_proto)
1141 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1142 * G_L4_chk, L4_type; required only for checksum
1145 command = l3_offs << MVNETA_TX_L3_OFF_SHIFT;
1146 command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
1148 if (l3_proto == htons(ETH_P_IP))
1149 command |= MVNETA_TXD_IP_CSUM;
1151 command |= MVNETA_TX_L3_IP6;
1153 if (l4_proto == IPPROTO_TCP)
1154 command |= MVNETA_TX_L4_CSUM_FULL;
1155 else if (l4_proto == IPPROTO_UDP)
1156 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
1158 command |= MVNETA_TX_L4_CSUM_NOT;
1164 /* Display more error info */
1165 static void mvneta_rx_error(struct mvneta_port *pp,
1166 struct mvneta_rx_desc *rx_desc)
1168 u32 status = rx_desc->status;
1170 if (!mvneta_rxq_desc_is_first_last(rx_desc)) {
1172 "bad rx status %08x (buffer oversize), size=%d\n",
1173 rx_desc->status, rx_desc->data_size);
1177 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
1178 case MVNETA_RXD_ERR_CRC:
1179 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
1180 status, rx_desc->data_size);
1182 case MVNETA_RXD_ERR_OVERRUN:
1183 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
1184 status, rx_desc->data_size);
1186 case MVNETA_RXD_ERR_LEN:
1187 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
1188 status, rx_desc->data_size);
1190 case MVNETA_RXD_ERR_RESOURCE:
1191 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
1192 status, rx_desc->data_size);
1197 /* Handle RX checksum offload */
1198 static void mvneta_rx_csum(struct mvneta_port *pp,
1199 struct mvneta_rx_desc *rx_desc,
1200 struct sk_buff *skb)
1202 if ((rx_desc->status & MVNETA_RXD_L3_IP4) &&
1203 (rx_desc->status & MVNETA_RXD_L4_CSUM_OK)) {
1205 skb->ip_summed = CHECKSUM_UNNECESSARY;
1209 skb->ip_summed = CHECKSUM_NONE;
1212 /* Return tx queue pointer (find last set bit) according to causeTxDone reg */
1213 static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
1216 int queue = fls(cause) - 1;
1218 return (queue < 0 || queue >= txq_number) ? NULL : &pp->txqs[queue];
1221 /* Free tx queue skbuffs */
1222 static void mvneta_txq_bufs_free(struct mvneta_port *pp,
1223 struct mvneta_tx_queue *txq, int num)
1227 for (i = 0; i < num; i++) {
1228 struct mvneta_tx_desc *tx_desc = txq->descs +
1230 struct sk_buff *skb = txq->tx_skb[txq->txq_get_index];
1232 mvneta_txq_inc_get(txq);
1237 dma_unmap_single(pp->dev->dev.parent, tx_desc->buf_phys_addr,
1238 tx_desc->data_size, DMA_TO_DEVICE);
1239 dev_kfree_skb_any(skb);
1243 /* Handle end of transmission */
1244 static int mvneta_txq_done(struct mvneta_port *pp,
1245 struct mvneta_tx_queue *txq)
1247 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
1250 tx_done = mvneta_txq_sent_desc_proc(pp, txq);
1253 mvneta_txq_bufs_free(pp, txq, tx_done);
1255 txq->count -= tx_done;
1257 if (netif_tx_queue_stopped(nq)) {
1258 if (txq->size - txq->count >= MAX_SKB_FRAGS + 1)
1259 netif_tx_wake_queue(nq);
1265 /* Refill processing */
1266 static int mvneta_rx_refill(struct mvneta_port *pp,
1267 struct mvneta_rx_desc *rx_desc)
1270 dma_addr_t phys_addr;
1271 struct sk_buff *skb;
1273 skb = netdev_alloc_skb(pp->dev, pp->pkt_size);
1277 phys_addr = dma_map_single(pp->dev->dev.parent, skb->head,
1278 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1280 if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) {
1285 mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)skb);
1290 /* Handle tx checksum */
1291 static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb)
1293 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1297 if (skb->protocol == htons(ETH_P_IP)) {
1298 struct iphdr *ip4h = ip_hdr(skb);
1300 /* Calculate IPv4 checksum and L4 checksum */
1301 ip_hdr_len = ip4h->ihl;
1302 l4_proto = ip4h->protocol;
1303 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1304 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1306 /* Read l4_protocol from one of IPv6 extra headers */
1307 if (skb_network_header_len(skb) > 0)
1308 ip_hdr_len = (skb_network_header_len(skb) >> 2);
1309 l4_proto = ip6h->nexthdr;
1311 return MVNETA_TX_L4_CSUM_NOT;
1313 return mvneta_txq_desc_csum(skb_network_offset(skb),
1314 skb->protocol, ip_hdr_len, l4_proto);
1317 return MVNETA_TX_L4_CSUM_NOT;
1320 /* Returns rx queue pointer (find last set bit) according to causeRxTx
1323 static struct mvneta_rx_queue *mvneta_rx_policy(struct mvneta_port *pp,
1326 int queue = fls(cause >> 8) - 1;
1328 return (queue < 0 || queue >= rxq_number) ? NULL : &pp->rxqs[queue];
1331 /* Drop packets received by the RXQ and free buffers */
1332 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
1333 struct mvneta_rx_queue *rxq)
1337 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1338 for (i = 0; i < rxq->size; i++) {
1339 struct mvneta_rx_desc *rx_desc = rxq->descs + i;
1340 struct sk_buff *skb = (struct sk_buff *)rx_desc->buf_cookie;
1342 dev_kfree_skb_any(skb);
1343 dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
1344 rx_desc->data_size, DMA_FROM_DEVICE);
1348 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1351 /* Main rx processing */
1352 static int mvneta_rx(struct mvneta_port *pp, int rx_todo,
1353 struct mvneta_rx_queue *rxq)
1355 struct net_device *dev = pp->dev;
1356 int rx_done, rx_filled;
1358 /* Get number of received packets */
1359 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1361 if (rx_todo > rx_done)
1367 /* Fairness NAPI loop */
1368 while (rx_done < rx_todo) {
1369 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
1370 struct sk_buff *skb;
1377 rx_status = rx_desc->status;
1378 skb = (struct sk_buff *)rx_desc->buf_cookie;
1380 if (!mvneta_rxq_desc_is_first_last(rx_desc) ||
1381 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1382 dev->stats.rx_errors++;
1383 mvneta_rx_error(pp, rx_desc);
1384 mvneta_rx_desc_fill(rx_desc, rx_desc->buf_phys_addr,
1389 dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
1390 rx_desc->data_size, DMA_FROM_DEVICE);
1392 rx_bytes = rx_desc->data_size -
1393 (ETH_FCS_LEN + MVNETA_MH_SIZE);
1394 u64_stats_update_begin(&pp->rx_stats.syncp);
1395 pp->rx_stats.packets++;
1396 pp->rx_stats.bytes += rx_bytes;
1397 u64_stats_update_end(&pp->rx_stats.syncp);
1399 /* Linux processing */
1400 skb_reserve(skb, MVNETA_MH_SIZE);
1401 skb_put(skb, rx_bytes);
1403 skb->protocol = eth_type_trans(skb, dev);
1405 mvneta_rx_csum(pp, rx_desc, skb);
1407 napi_gro_receive(&pp->napi, skb);
1409 /* Refill processing */
1410 err = mvneta_rx_refill(pp, rx_desc);
1412 netdev_err(pp->dev, "Linux processing - Can't refill\n");
1418 /* Update rxq management counters */
1419 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_filled);
1424 /* Handle tx fragmentation processing */
1425 static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
1426 struct mvneta_tx_queue *txq)
1428 struct mvneta_tx_desc *tx_desc;
1431 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1432 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1433 void *addr = page_address(frag->page.p) + frag->page_offset;
1435 tx_desc = mvneta_txq_next_desc_get(txq);
1436 tx_desc->data_size = frag->size;
1438 tx_desc->buf_phys_addr =
1439 dma_map_single(pp->dev->dev.parent, addr,
1440 tx_desc->data_size, DMA_TO_DEVICE);
1442 if (dma_mapping_error(pp->dev->dev.parent,
1443 tx_desc->buf_phys_addr)) {
1444 mvneta_txq_desc_put(txq);
1448 if (i == (skb_shinfo(skb)->nr_frags - 1)) {
1449 /* Last descriptor */
1450 tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
1452 txq->tx_skb[txq->txq_put_index] = skb;
1454 mvneta_txq_inc_put(txq);
1456 /* Descriptor in the middle: Not First, Not Last */
1457 tx_desc->command = 0;
1459 txq->tx_skb[txq->txq_put_index] = NULL;
1460 mvneta_txq_inc_put(txq);
1467 /* Release all descriptors that were used to map fragments of
1468 * this packet, as well as the corresponding DMA mappings
1470 for (i = i - 1; i >= 0; i--) {
1471 tx_desc = txq->descs + i;
1472 dma_unmap_single(pp->dev->dev.parent,
1473 tx_desc->buf_phys_addr,
1476 mvneta_txq_desc_put(txq);
1482 /* Main tx processing */
1483 static int mvneta_tx(struct sk_buff *skb, struct net_device *dev)
1485 struct mvneta_port *pp = netdev_priv(dev);
1486 u16 txq_id = skb_get_queue_mapping(skb);
1487 struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
1488 struct mvneta_tx_desc *tx_desc;
1489 struct netdev_queue *nq;
1493 if (!netif_running(dev))
1496 frags = skb_shinfo(skb)->nr_frags + 1;
1497 nq = netdev_get_tx_queue(dev, txq_id);
1499 /* Get a descriptor for the first part of the packet */
1500 tx_desc = mvneta_txq_next_desc_get(txq);
1502 tx_cmd = mvneta_skb_tx_csum(pp, skb);
1504 tx_desc->data_size = skb_headlen(skb);
1506 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
1509 if (unlikely(dma_mapping_error(dev->dev.parent,
1510 tx_desc->buf_phys_addr))) {
1511 mvneta_txq_desc_put(txq);
1517 /* First and Last descriptor */
1518 tx_cmd |= MVNETA_TXD_FLZ_DESC;
1519 tx_desc->command = tx_cmd;
1520 txq->tx_skb[txq->txq_put_index] = skb;
1521 mvneta_txq_inc_put(txq);
1523 /* First but not Last */
1524 tx_cmd |= MVNETA_TXD_F_DESC;
1525 txq->tx_skb[txq->txq_put_index] = NULL;
1526 mvneta_txq_inc_put(txq);
1527 tx_desc->command = tx_cmd;
1528 /* Continue with other skb fragments */
1529 if (mvneta_tx_frag_process(pp, skb, txq)) {
1530 dma_unmap_single(dev->dev.parent,
1531 tx_desc->buf_phys_addr,
1534 mvneta_txq_desc_put(txq);
1540 txq->count += frags;
1541 mvneta_txq_pend_desc_add(pp, txq, frags);
1543 if (txq->size - txq->count < MAX_SKB_FRAGS + 1)
1544 netif_tx_stop_queue(nq);
1548 u64_stats_update_begin(&pp->tx_stats.syncp);
1549 pp->tx_stats.packets++;
1550 pp->tx_stats.bytes += skb->len;
1551 u64_stats_update_end(&pp->tx_stats.syncp);
1554 dev->stats.tx_dropped++;
1555 dev_kfree_skb_any(skb);
1558 if (txq->count >= MVNETA_TXDONE_COAL_PKTS)
1559 mvneta_txq_done(pp, txq);
1561 /* If after calling mvneta_txq_done, count equals
1562 * frags, we need to set the timer
1564 if (txq->count == frags && frags > 0)
1565 mvneta_add_tx_done_timer(pp);
1567 return NETDEV_TX_OK;
1571 /* Free tx resources, when resetting a port */
1572 static void mvneta_txq_done_force(struct mvneta_port *pp,
1573 struct mvneta_tx_queue *txq)
1576 int tx_done = txq->count;
1578 mvneta_txq_bufs_free(pp, txq, tx_done);
1582 txq->txq_put_index = 0;
1583 txq->txq_get_index = 0;
1586 /* handle tx done - called from tx done timer callback */
1587 static u32 mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done,
1590 struct mvneta_tx_queue *txq;
1592 struct netdev_queue *nq;
1595 while (cause_tx_done != 0) {
1596 txq = mvneta_tx_done_policy(pp, cause_tx_done);
1600 nq = netdev_get_tx_queue(pp->dev, txq->id);
1601 __netif_tx_lock(nq, smp_processor_id());
1604 tx_done += mvneta_txq_done(pp, txq);
1605 *tx_todo += txq->count;
1608 __netif_tx_unlock(nq);
1609 cause_tx_done &= ~((1 << txq->id));
1615 /* Compute crc8 of the specified address, using a unique algorithm ,
1616 * according to hw spec, different than generic crc8 algorithm
1618 static int mvneta_addr_crc(unsigned char *addr)
1623 for (i = 0; i < ETH_ALEN; i++) {
1626 crc = (crc ^ addr[i]) << 8;
1627 for (j = 7; j >= 0; j--) {
1628 if (crc & (0x100 << j))
1636 /* This method controls the net device special MAC multicast support.
1637 * The Special Multicast Table for MAC addresses supports MAC of the form
1638 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1639 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1640 * Table entries in the DA-Filter table. This method set the Special
1641 * Multicast Table appropriate entry.
1643 static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
1644 unsigned char last_byte,
1647 unsigned int smc_table_reg;
1648 unsigned int tbl_offset;
1649 unsigned int reg_offset;
1651 /* Register offset from SMC table base */
1652 tbl_offset = (last_byte / 4);
1653 /* Entry offset within the above reg */
1654 reg_offset = last_byte % 4;
1656 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
1660 smc_table_reg &= ~(0xff << (8 * reg_offset));
1662 smc_table_reg &= ~(0xff << (8 * reg_offset));
1663 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1666 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
1670 /* This method controls the network device Other MAC multicast support.
1671 * The Other Multicast Table is used for multicast of another type.
1672 * A CRC-8 is used as an index to the Other Multicast Table entries
1673 * in the DA-Filter table.
1674 * The method gets the CRC-8 value from the calling routine and
1675 * sets the Other Multicast Table appropriate entry according to the
1678 static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
1682 unsigned int omc_table_reg;
1683 unsigned int tbl_offset;
1684 unsigned int reg_offset;
1686 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
1687 reg_offset = crc8 % 4; /* Entry offset within the above reg */
1689 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
1692 /* Clear accepts frame bit at specified Other DA table entry */
1693 omc_table_reg &= ~(0xff << (8 * reg_offset));
1695 omc_table_reg &= ~(0xff << (8 * reg_offset));
1696 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1699 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
1702 /* The network device supports multicast using two tables:
1703 * 1) Special Multicast Table for MAC addresses of the form
1704 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1705 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1706 * Table entries in the DA-Filter table.
1707 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
1708 * is used as an index to the Other Multicast Table entries in the
1711 static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
1714 unsigned char crc_result = 0;
1716 if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
1717 mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
1721 crc_result = mvneta_addr_crc(p_addr);
1723 if (pp->mcast_count[crc_result] == 0) {
1724 netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
1729 pp->mcast_count[crc_result]--;
1730 if (pp->mcast_count[crc_result] != 0) {
1731 netdev_info(pp->dev,
1732 "After delete there are %d valid Mcast for crc8=0x%02x\n",
1733 pp->mcast_count[crc_result], crc_result);
1737 pp->mcast_count[crc_result]++;
1739 mvneta_set_other_mcast_addr(pp, crc_result, queue);
1744 /* Configure Fitering mode of Ethernet port */
1745 static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
1748 u32 port_cfg_reg, val;
1750 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
1752 val = mvreg_read(pp, MVNETA_TYPE_PRIO);
1754 /* Set / Clear UPM bit in port configuration register */
1756 /* Accept all Unicast addresses */
1757 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
1758 val |= MVNETA_FORCE_UNI;
1759 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
1760 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
1762 /* Reject all Unicast addresses */
1763 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
1764 val &= ~MVNETA_FORCE_UNI;
1767 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
1768 mvreg_write(pp, MVNETA_TYPE_PRIO, val);
1771 /* register unicast and multicast addresses */
1772 static void mvneta_set_rx_mode(struct net_device *dev)
1774 struct mvneta_port *pp = netdev_priv(dev);
1775 struct netdev_hw_addr *ha;
1777 if (dev->flags & IFF_PROMISC) {
1778 /* Accept all: Multicast + Unicast */
1779 mvneta_rx_unicast_promisc_set(pp, 1);
1780 mvneta_set_ucast_table(pp, rxq_def);
1781 mvneta_set_special_mcast_table(pp, rxq_def);
1782 mvneta_set_other_mcast_table(pp, rxq_def);
1784 /* Accept single Unicast */
1785 mvneta_rx_unicast_promisc_set(pp, 0);
1786 mvneta_set_ucast_table(pp, -1);
1787 mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def);
1789 if (dev->flags & IFF_ALLMULTI) {
1790 /* Accept all multicast */
1791 mvneta_set_special_mcast_table(pp, rxq_def);
1792 mvneta_set_other_mcast_table(pp, rxq_def);
1794 /* Accept only initialized multicast */
1795 mvneta_set_special_mcast_table(pp, -1);
1796 mvneta_set_other_mcast_table(pp, -1);
1798 if (!netdev_mc_empty(dev)) {
1799 netdev_for_each_mc_addr(ha, dev) {
1800 mvneta_mcast_addr_set(pp, ha->addr,
1808 /* Interrupt handling - the callback for request_irq() */
1809 static irqreturn_t mvneta_isr(int irq, void *dev_id)
1811 struct mvneta_port *pp = (struct mvneta_port *)dev_id;
1813 /* Mask all interrupts */
1814 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
1816 napi_schedule(&pp->napi);
1822 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
1823 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
1824 * Bits 8 -15 of the cause Rx Tx register indicate that are received
1825 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
1826 * Each CPU has its own causeRxTx register
1828 static int mvneta_poll(struct napi_struct *napi, int budget)
1832 unsigned long flags;
1833 struct mvneta_port *pp = netdev_priv(napi->dev);
1835 if (!netif_running(pp->dev)) {
1836 napi_complete(napi);
1840 /* Read cause register */
1841 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE) &
1842 MVNETA_RX_INTR_MASK(rxq_number);
1844 /* For the case where the last mvneta_poll did not process all
1847 cause_rx_tx |= pp->cause_rx_tx;
1848 if (rxq_number > 1) {
1849 while ((cause_rx_tx != 0) && (budget > 0)) {
1851 struct mvneta_rx_queue *rxq;
1852 /* get rx queue number from cause_rx_tx */
1853 rxq = mvneta_rx_policy(pp, cause_rx_tx);
1857 /* process the packet in that rx queue */
1858 count = mvneta_rx(pp, budget, rxq);
1862 /* set off the rx bit of the
1863 * corresponding bit in the cause rx
1864 * tx register, so that next iteration
1865 * will find the next rx queue where
1866 * packets are received on
1868 cause_rx_tx &= ~((1 << rxq->id) << 8);
1872 rx_done = mvneta_rx(pp, budget, &pp->rxqs[rxq_def]);
1878 napi_complete(napi);
1879 local_irq_save(flags);
1880 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
1881 MVNETA_RX_INTR_MASK(rxq_number));
1882 local_irq_restore(flags);
1885 pp->cause_rx_tx = cause_rx_tx;
1889 /* tx done timer callback */
1890 static void mvneta_tx_done_timer_callback(unsigned long data)
1892 struct net_device *dev = (struct net_device *)data;
1893 struct mvneta_port *pp = netdev_priv(dev);
1894 int tx_done = 0, tx_todo = 0;
1896 if (!netif_running(dev))
1899 clear_bit(MVNETA_F_TX_DONE_TIMER_BIT, &pp->flags);
1901 tx_done = mvneta_tx_done_gbe(pp,
1902 (((1 << txq_number) - 1) &
1903 MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK),
1906 mvneta_add_tx_done_timer(pp);
1909 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
1910 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
1913 struct net_device *dev = pp->dev;
1916 for (i = 0; i < num; i++) {
1917 struct sk_buff *skb;
1918 struct mvneta_rx_desc *rx_desc;
1919 unsigned long phys_addr;
1921 skb = dev_alloc_skb(pp->pkt_size);
1923 netdev_err(dev, "%s:rxq %d, %d of %d buffs filled\n",
1924 __func__, rxq->id, i, num);
1928 rx_desc = rxq->descs + i;
1929 memset(rx_desc, 0, sizeof(struct mvneta_rx_desc));
1930 phys_addr = dma_map_single(dev->dev.parent, skb->head,
1931 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1933 if (unlikely(dma_mapping_error(dev->dev.parent, phys_addr))) {
1938 mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)skb);
1941 /* Add this number of RX descriptors as non occupied (ready to
1944 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
1949 /* Free all packets pending transmit from all TXQs and reset TX port */
1950 static void mvneta_tx_reset(struct mvneta_port *pp)
1954 /* free the skb's in the hal tx ring */
1955 for (queue = 0; queue < txq_number; queue++)
1956 mvneta_txq_done_force(pp, &pp->txqs[queue]);
1958 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
1959 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
1962 static void mvneta_rx_reset(struct mvneta_port *pp)
1964 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
1965 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
1968 /* Rx/Tx queue initialization/cleanup methods */
1970 /* Create a specified RX queue */
1971 static int mvneta_rxq_init(struct mvneta_port *pp,
1972 struct mvneta_rx_queue *rxq)
1975 rxq->size = pp->rx_ring_size;
1977 /* Allocate memory for RX descriptors */
1978 rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
1979 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
1980 &rxq->descs_phys, GFP_KERNEL);
1981 if (rxq->descs == NULL)
1984 BUG_ON(rxq->descs !=
1985 PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
1987 rxq->last_desc = rxq->size - 1;
1989 /* Set Rx descriptors queue starting address */
1990 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
1991 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
1994 mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD);
1996 /* Set coalescing pkts and time */
1997 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
1998 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2000 /* Fill RXQ with buffers from RX pool */
2001 mvneta_rxq_buf_size_set(pp, rxq, MVNETA_RX_BUF_SIZE(pp->pkt_size));
2002 mvneta_rxq_bm_disable(pp, rxq);
2003 mvneta_rxq_fill(pp, rxq, rxq->size);
2008 /* Cleanup Rx queue */
2009 static void mvneta_rxq_deinit(struct mvneta_port *pp,
2010 struct mvneta_rx_queue *rxq)
2012 mvneta_rxq_drop_pkts(pp, rxq);
2015 dma_free_coherent(pp->dev->dev.parent,
2016 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2022 rxq->next_desc_to_proc = 0;
2023 rxq->descs_phys = 0;
2026 /* Create and initialize a tx queue */
2027 static int mvneta_txq_init(struct mvneta_port *pp,
2028 struct mvneta_tx_queue *txq)
2030 txq->size = pp->tx_ring_size;
2032 /* Allocate memory for TX descriptors */
2033 txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2034 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2035 &txq->descs_phys, GFP_KERNEL);
2036 if (txq->descs == NULL)
2039 /* Make sure descriptor address is cache line size aligned */
2040 BUG_ON(txq->descs !=
2041 PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
2043 txq->last_desc = txq->size - 1;
2045 /* Set maximum bandwidth for enabled TXQs */
2046 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
2047 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
2049 /* Set Tx descriptors queue starting address */
2050 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
2051 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
2053 txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL);
2054 if (txq->tx_skb == NULL) {
2055 dma_free_coherent(pp->dev->dev.parent,
2056 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2057 txq->descs, txq->descs_phys);
2060 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2065 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
2066 static void mvneta_txq_deinit(struct mvneta_port *pp,
2067 struct mvneta_tx_queue *txq)
2072 dma_free_coherent(pp->dev->dev.parent,
2073 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2074 txq->descs, txq->descs_phys);
2078 txq->next_desc_to_proc = 0;
2079 txq->descs_phys = 0;
2081 /* Set minimum bandwidth for disabled TXQs */
2082 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
2083 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
2085 /* Set Tx descriptors queue starting address and size */
2086 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
2087 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
2090 /* Cleanup all Tx queues */
2091 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
2095 for (queue = 0; queue < txq_number; queue++)
2096 mvneta_txq_deinit(pp, &pp->txqs[queue]);
2099 /* Cleanup all Rx queues */
2100 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
2104 for (queue = 0; queue < rxq_number; queue++)
2105 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
2109 /* Init all Rx queues */
2110 static int mvneta_setup_rxqs(struct mvneta_port *pp)
2114 for (queue = 0; queue < rxq_number; queue++) {
2115 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
2117 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
2119 mvneta_cleanup_rxqs(pp);
2127 /* Init all tx queues */
2128 static int mvneta_setup_txqs(struct mvneta_port *pp)
2132 for (queue = 0; queue < txq_number; queue++) {
2133 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
2135 netdev_err(pp->dev, "%s: can't create txq=%d\n",
2137 mvneta_cleanup_txqs(pp);
2145 static void mvneta_start_dev(struct mvneta_port *pp)
2147 mvneta_max_rx_size_set(pp, pp->pkt_size);
2148 mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
2150 /* start the Rx/Tx activity */
2151 mvneta_port_enable(pp);
2153 /* Enable polling on the port */
2154 napi_enable(&pp->napi);
2156 /* Unmask interrupts */
2157 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2158 MVNETA_RX_INTR_MASK(rxq_number));
2160 phy_start(pp->phy_dev);
2161 netif_tx_start_all_queues(pp->dev);
2164 static void mvneta_stop_dev(struct mvneta_port *pp)
2166 phy_stop(pp->phy_dev);
2168 napi_disable(&pp->napi);
2170 netif_carrier_off(pp->dev);
2172 mvneta_port_down(pp);
2173 netif_tx_stop_all_queues(pp->dev);
2175 /* Stop the port activity */
2176 mvneta_port_disable(pp);
2178 /* Clear all ethernet port interrupts */
2179 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2180 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
2182 /* Mask all ethernet port interrupts */
2183 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2184 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
2185 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
2187 mvneta_tx_reset(pp);
2188 mvneta_rx_reset(pp);
2191 /* tx timeout callback - display a message and stop/start the network device */
2192 static void mvneta_tx_timeout(struct net_device *dev)
2194 struct mvneta_port *pp = netdev_priv(dev);
2196 netdev_info(dev, "tx timeout\n");
2197 mvneta_stop_dev(pp);
2198 mvneta_start_dev(pp);
2201 /* Return positive if MTU is valid */
2202 static int mvneta_check_mtu_valid(struct net_device *dev, int mtu)
2205 netdev_err(dev, "cannot change mtu to less than 68\n");
2209 /* 9676 == 9700 - 20 and rounding to 8 */
2211 netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu);
2215 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
2216 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
2217 mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
2218 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
2224 /* Change the device mtu */
2225 static int mvneta_change_mtu(struct net_device *dev, int mtu)
2227 struct mvneta_port *pp = netdev_priv(dev);
2230 mtu = mvneta_check_mtu_valid(dev, mtu);
2236 if (!netif_running(dev))
2239 /* The interface is running, so we have to force a
2240 * reallocation of the RXQs
2242 mvneta_stop_dev(pp);
2244 mvneta_cleanup_txqs(pp);
2245 mvneta_cleanup_rxqs(pp);
2247 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
2249 ret = mvneta_setup_rxqs(pp);
2251 netdev_err(pp->dev, "unable to setup rxqs after MTU change\n");
2255 mvneta_setup_txqs(pp);
2257 mvneta_start_dev(pp);
2263 /* Handle setting mac address */
2264 static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
2266 struct mvneta_port *pp = netdev_priv(dev);
2270 if (netif_running(dev))
2273 /* Remove previous address table entry */
2274 mvneta_mac_addr_set(pp, dev->dev_addr, -1);
2276 /* Set new addr in hw */
2277 mvneta_mac_addr_set(pp, mac, rxq_def);
2279 /* Set addr in the device */
2280 for (i = 0; i < ETH_ALEN; i++)
2281 dev->dev_addr[i] = mac[i];
2286 static void mvneta_adjust_link(struct net_device *ndev)
2288 struct mvneta_port *pp = netdev_priv(ndev);
2289 struct phy_device *phydev = pp->phy_dev;
2290 int status_change = 0;
2293 if ((pp->speed != phydev->speed) ||
2294 (pp->duplex != phydev->duplex)) {
2297 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
2298 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
2299 MVNETA_GMAC_CONFIG_GMII_SPEED |
2300 MVNETA_GMAC_CONFIG_FULL_DUPLEX |
2301 MVNETA_GMAC_AN_SPEED_EN |
2302 MVNETA_GMAC_AN_DUPLEX_EN);
2305 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
2307 if (phydev->speed == SPEED_1000)
2308 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
2309 else if (phydev->speed == SPEED_100)
2310 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
2312 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
2314 pp->duplex = phydev->duplex;
2315 pp->speed = phydev->speed;
2319 if (phydev->link != pp->link) {
2320 if (!phydev->link) {
2325 pp->link = phydev->link;
2329 if (status_change) {
2331 u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
2332 val |= (MVNETA_GMAC_FORCE_LINK_PASS |
2333 MVNETA_GMAC_FORCE_LINK_DOWN);
2334 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
2336 netdev_info(pp->dev, "link up\n");
2338 mvneta_port_down(pp);
2339 netdev_info(pp->dev, "link down\n");
2344 static int mvneta_mdio_probe(struct mvneta_port *pp)
2346 struct phy_device *phy_dev;
2348 phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0,
2351 netdev_err(pp->dev, "could not find the PHY\n");
2355 phy_dev->supported &= PHY_GBIT_FEATURES;
2356 phy_dev->advertising = phy_dev->supported;
2358 pp->phy_dev = phy_dev;
2366 static void mvneta_mdio_remove(struct mvneta_port *pp)
2368 phy_disconnect(pp->phy_dev);
2372 static int mvneta_open(struct net_device *dev)
2374 struct mvneta_port *pp = netdev_priv(dev);
2377 mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def);
2379 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
2381 ret = mvneta_setup_rxqs(pp);
2385 ret = mvneta_setup_txqs(pp);
2387 goto err_cleanup_rxqs;
2389 /* Connect to port interrupt line */
2390 ret = request_irq(pp->dev->irq, mvneta_isr, 0,
2391 MVNETA_DRIVER_NAME, pp);
2393 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
2394 goto err_cleanup_txqs;
2397 /* In default link is down */
2398 netif_carrier_off(pp->dev);
2400 ret = mvneta_mdio_probe(pp);
2402 netdev_err(dev, "cannot probe MDIO bus\n");
2406 mvneta_start_dev(pp);
2411 free_irq(pp->dev->irq, pp);
2413 mvneta_cleanup_txqs(pp);
2415 mvneta_cleanup_rxqs(pp);
2419 /* Stop the port, free port interrupt line */
2420 static int mvneta_stop(struct net_device *dev)
2422 struct mvneta_port *pp = netdev_priv(dev);
2424 mvneta_stop_dev(pp);
2425 mvneta_mdio_remove(pp);
2426 free_irq(dev->irq, pp);
2427 mvneta_cleanup_rxqs(pp);
2428 mvneta_cleanup_txqs(pp);
2429 del_timer(&pp->tx_done_timer);
2430 clear_bit(MVNETA_F_TX_DONE_TIMER_BIT, &pp->flags);
2435 /* Ethtool methods */
2437 /* Get settings (phy address, speed) for ethtools */
2438 int mvneta_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2440 struct mvneta_port *pp = netdev_priv(dev);
2445 return phy_ethtool_gset(pp->phy_dev, cmd);
2448 /* Set settings (phy address, speed) for ethtools */
2449 int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2451 struct mvneta_port *pp = netdev_priv(dev);
2456 return phy_ethtool_sset(pp->phy_dev, cmd);
2459 /* Set interrupt coalescing for ethtools */
2460 static int mvneta_ethtool_set_coalesce(struct net_device *dev,
2461 struct ethtool_coalesce *c)
2463 struct mvneta_port *pp = netdev_priv(dev);
2466 for (queue = 0; queue < rxq_number; queue++) {
2467 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
2468 rxq->time_coal = c->rx_coalesce_usecs;
2469 rxq->pkts_coal = c->rx_max_coalesced_frames;
2470 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2471 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2474 for (queue = 0; queue < txq_number; queue++) {
2475 struct mvneta_tx_queue *txq = &pp->txqs[queue];
2476 txq->done_pkts_coal = c->tx_max_coalesced_frames;
2477 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2483 /* get coalescing for ethtools */
2484 static int mvneta_ethtool_get_coalesce(struct net_device *dev,
2485 struct ethtool_coalesce *c)
2487 struct mvneta_port *pp = netdev_priv(dev);
2489 c->rx_coalesce_usecs = pp->rxqs[0].time_coal;
2490 c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal;
2492 c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal;
2497 static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
2498 struct ethtool_drvinfo *drvinfo)
2500 strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME,
2501 sizeof(drvinfo->driver));
2502 strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION,
2503 sizeof(drvinfo->version));
2504 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
2505 sizeof(drvinfo->bus_info));
2509 static void mvneta_ethtool_get_ringparam(struct net_device *netdev,
2510 struct ethtool_ringparam *ring)
2512 struct mvneta_port *pp = netdev_priv(netdev);
2514 ring->rx_max_pending = MVNETA_MAX_RXD;
2515 ring->tx_max_pending = MVNETA_MAX_TXD;
2516 ring->rx_pending = pp->rx_ring_size;
2517 ring->tx_pending = pp->tx_ring_size;
2520 static int mvneta_ethtool_set_ringparam(struct net_device *dev,
2521 struct ethtool_ringparam *ring)
2523 struct mvneta_port *pp = netdev_priv(dev);
2525 if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
2527 pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
2528 ring->rx_pending : MVNETA_MAX_RXD;
2529 pp->tx_ring_size = ring->tx_pending < MVNETA_MAX_TXD ?
2530 ring->tx_pending : MVNETA_MAX_TXD;
2532 if (netif_running(dev)) {
2534 if (mvneta_open(dev)) {
2536 "error on opening device after ring param change\n");
2544 static const struct net_device_ops mvneta_netdev_ops = {
2545 .ndo_open = mvneta_open,
2546 .ndo_stop = mvneta_stop,
2547 .ndo_start_xmit = mvneta_tx,
2548 .ndo_set_rx_mode = mvneta_set_rx_mode,
2549 .ndo_set_mac_address = mvneta_set_mac_addr,
2550 .ndo_change_mtu = mvneta_change_mtu,
2551 .ndo_tx_timeout = mvneta_tx_timeout,
2552 .ndo_get_stats64 = mvneta_get_stats64,
2555 const struct ethtool_ops mvneta_eth_tool_ops = {
2556 .get_link = ethtool_op_get_link,
2557 .get_settings = mvneta_ethtool_get_settings,
2558 .set_settings = mvneta_ethtool_set_settings,
2559 .set_coalesce = mvneta_ethtool_set_coalesce,
2560 .get_coalesce = mvneta_ethtool_get_coalesce,
2561 .get_drvinfo = mvneta_ethtool_get_drvinfo,
2562 .get_ringparam = mvneta_ethtool_get_ringparam,
2563 .set_ringparam = mvneta_ethtool_set_ringparam,
2567 static int mvneta_init(struct mvneta_port *pp, int phy_addr)
2572 mvneta_port_disable(pp);
2574 /* Set port default values */
2575 mvneta_defaults_set(pp);
2577 pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue),
2582 /* Initialize TX descriptor rings */
2583 for (queue = 0; queue < txq_number; queue++) {
2584 struct mvneta_tx_queue *txq = &pp->txqs[queue];
2586 txq->size = pp->tx_ring_size;
2587 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
2590 pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue),
2597 /* Create Rx descriptor rings */
2598 for (queue = 0; queue < rxq_number; queue++) {
2599 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
2601 rxq->size = pp->rx_ring_size;
2602 rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
2603 rxq->time_coal = MVNETA_RX_COAL_USEC;
2609 static void mvneta_deinit(struct mvneta_port *pp)
2615 /* platform glue : initialize decoding windows */
2616 static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
2617 const struct mbus_dram_target_info *dram)
2623 for (i = 0; i < 6; i++) {
2624 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
2625 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
2628 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
2634 for (i = 0; i < dram->num_cs; i++) {
2635 const struct mbus_dram_window *cs = dram->cs + i;
2636 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
2637 (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
2639 mvreg_write(pp, MVNETA_WIN_SIZE(i),
2640 (cs->size - 1) & 0xffff0000);
2642 win_enable &= ~(1 << i);
2643 win_protect |= 3 << (2 * i);
2646 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
2649 /* Power up the port */
2650 static void mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
2654 /* MAC Cause register should be cleared */
2655 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
2657 if (phy_mode == PHY_INTERFACE_MODE_SGMII)
2658 mvneta_port_sgmii_config(pp);
2660 mvneta_gmac_rgmii_set(pp, 1);
2662 /* Cancel Port Reset */
2663 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
2664 val &= ~MVNETA_GMAC2_PORT_RESET;
2665 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
2667 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
2668 MVNETA_GMAC2_PORT_RESET) != 0)
2672 /* Device initialization routine */
2673 static int mvneta_probe(struct platform_device *pdev)
2675 const struct mbus_dram_target_info *dram_target_info;
2676 struct device_node *dn = pdev->dev.of_node;
2677 struct device_node *phy_node;
2679 struct mvneta_port *pp;
2680 struct net_device *dev;
2681 const char *mac_addr;
2685 /* Our multiqueue support is not complete, so for now, only
2686 * allow the usage of the first RX queue
2689 dev_err(&pdev->dev, "Invalid rxq_def argument: %d\n", rxq_def);
2693 dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number);
2697 dev->irq = irq_of_parse_and_map(dn, 0);
2698 if (dev->irq == 0) {
2700 goto err_free_netdev;
2703 phy_node = of_parse_phandle(dn, "phy", 0);
2705 dev_err(&pdev->dev, "no associated PHY\n");
2710 phy_mode = of_get_phy_mode(dn);
2712 dev_err(&pdev->dev, "incorrect phy-mode\n");
2717 mac_addr = of_get_mac_address(dn);
2719 if (!mac_addr || !is_valid_ether_addr(mac_addr))
2720 eth_hw_addr_random(dev);
2722 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
2724 dev->tx_queue_len = MVNETA_MAX_TXD;
2725 dev->watchdog_timeo = 5 * HZ;
2726 dev->netdev_ops = &mvneta_netdev_ops;
2728 SET_ETHTOOL_OPS(dev, &mvneta_eth_tool_ops);
2730 pp = netdev_priv(dev);
2732 pp->tx_done_timer.function = mvneta_tx_done_timer_callback;
2733 init_timer(&pp->tx_done_timer);
2734 clear_bit(MVNETA_F_TX_DONE_TIMER_BIT, &pp->flags);
2736 pp->weight = MVNETA_RX_POLL_WEIGHT;
2737 pp->phy_node = phy_node;
2738 pp->phy_interface = phy_mode;
2740 pp->base = of_iomap(dn, 0);
2741 if (pp->base == NULL) {
2746 pp->clk = devm_clk_get(&pdev->dev, NULL);
2747 if (IS_ERR(pp->clk)) {
2748 err = PTR_ERR(pp->clk);
2752 clk_prepare_enable(pp->clk);
2754 pp->tx_done_timer.data = (unsigned long)dev;
2756 pp->tx_ring_size = MVNETA_MAX_TXD;
2757 pp->rx_ring_size = MVNETA_MAX_RXD;
2760 SET_NETDEV_DEV(dev, &pdev->dev);
2762 err = mvneta_init(pp, phy_addr);
2764 dev_err(&pdev->dev, "can't init eth hal\n");
2767 mvneta_port_power_up(pp, phy_mode);
2769 dram_target_info = mv_mbus_dram_info();
2770 if (dram_target_info)
2771 mvneta_conf_mbus_windows(pp, dram_target_info);
2773 netif_napi_add(dev, &pp->napi, mvneta_poll, pp->weight);
2775 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2776 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2777 dev->vlan_features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2778 dev->priv_flags |= IFF_UNICAST_FLT;
2780 err = register_netdev(dev);
2782 dev_err(&pdev->dev, "failed to register\n");
2786 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
2788 platform_set_drvdata(pdev, pp->dev);
2795 clk_disable_unprepare(pp->clk);
2799 irq_dispose_mapping(dev->irq);
2805 /* Device removal routine */
2806 static int mvneta_remove(struct platform_device *pdev)
2808 struct net_device *dev = platform_get_drvdata(pdev);
2809 struct mvneta_port *pp = netdev_priv(dev);
2811 unregister_netdev(dev);
2813 clk_disable_unprepare(pp->clk);
2815 irq_dispose_mapping(dev->irq);
2818 platform_set_drvdata(pdev, NULL);
2823 static const struct of_device_id mvneta_match[] = {
2824 { .compatible = "marvell,armada-370-neta" },
2827 MODULE_DEVICE_TABLE(of, mvneta_match);
2829 static struct platform_driver mvneta_driver = {
2830 .probe = mvneta_probe,
2831 .remove = mvneta_remove,
2833 .name = MVNETA_DRIVER_NAME,
2834 .of_match_table = mvneta_match,
2838 module_platform_driver(mvneta_driver);
2840 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
2841 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
2842 MODULE_LICENSE("GPL");
2844 module_param(rxq_number, int, S_IRUGO);
2845 module_param(txq_number, int, S_IRUGO);
2847 module_param(rxq_def, int, S_IRUGO);