2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de>
25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License
27 * as published by the Free Software Foundation; either version 2
28 * of the License, or (at your option) any later version.
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software
37 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42 #include <linux/init.h>
43 #include <linux/dma-mapping.h>
46 #include <linux/tcp.h>
47 #include <linux/udp.h>
48 #include <linux/etherdevice.h>
49 #include <linux/delay.h>
50 #include <linux/ethtool.h>
51 #include <linux/platform_device.h>
52 #include <linux/module.h>
53 #include <linux/kernel.h>
54 #include <linux/spinlock.h>
55 #include <linux/workqueue.h>
56 #include <linux/phy.h>
57 #include <linux/mv643xx_eth.h>
59 #include <linux/interrupt.h>
60 #include <linux/types.h>
61 #include <linux/slab.h>
62 #include <linux/clk.h>
64 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
65 static char mv643xx_eth_driver_version[] = "1.4";
69 * Registers shared between all ports.
71 #define PHY_ADDR 0x0000
72 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
73 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
74 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
75 #define WINDOW_BAR_ENABLE 0x0290
76 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
79 * Main per-port registers. These live at offset 0x0400 for
80 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
82 #define PORT_CONFIG 0x0000
83 #define UNICAST_PROMISCUOUS_MODE 0x00000001
84 #define PORT_CONFIG_EXT 0x0004
85 #define MAC_ADDR_LOW 0x0014
86 #define MAC_ADDR_HIGH 0x0018
87 #define SDMA_CONFIG 0x001c
88 #define TX_BURST_SIZE_16_64BIT 0x01000000
89 #define TX_BURST_SIZE_4_64BIT 0x00800000
90 #define BLM_TX_NO_SWAP 0x00000020
91 #define BLM_RX_NO_SWAP 0x00000010
92 #define RX_BURST_SIZE_16_64BIT 0x00000008
93 #define RX_BURST_SIZE_4_64BIT 0x00000004
94 #define PORT_SERIAL_CONTROL 0x003c
95 #define SET_MII_SPEED_TO_100 0x01000000
96 #define SET_GMII_SPEED_TO_1000 0x00800000
97 #define SET_FULL_DUPLEX_MODE 0x00200000
98 #define MAX_RX_PACKET_9700BYTE 0x000a0000
99 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
100 #define DO_NOT_FORCE_LINK_FAIL 0x00000400
101 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
102 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
103 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
104 #define FORCE_LINK_PASS 0x00000002
105 #define SERIAL_PORT_ENABLE 0x00000001
106 #define PORT_STATUS 0x0044
107 #define TX_FIFO_EMPTY 0x00000400
108 #define TX_IN_PROGRESS 0x00000080
109 #define PORT_SPEED_MASK 0x00000030
110 #define PORT_SPEED_1000 0x00000010
111 #define PORT_SPEED_100 0x00000020
112 #define PORT_SPEED_10 0x00000000
113 #define FLOW_CONTROL_ENABLED 0x00000008
114 #define FULL_DUPLEX 0x00000004
115 #define LINK_UP 0x00000002
116 #define TXQ_COMMAND 0x0048
117 #define TXQ_FIX_PRIO_CONF 0x004c
118 #define TX_BW_RATE 0x0050
119 #define TX_BW_MTU 0x0058
120 #define TX_BW_BURST 0x005c
121 #define INT_CAUSE 0x0060
122 #define INT_TX_END 0x07f80000
123 #define INT_TX_END_0 0x00080000
124 #define INT_RX 0x000003fc
125 #define INT_RX_0 0x00000004
126 #define INT_EXT 0x00000002
127 #define INT_CAUSE_EXT 0x0064
128 #define INT_EXT_LINK_PHY 0x00110000
129 #define INT_EXT_TX 0x000000ff
130 #define INT_MASK 0x0068
131 #define INT_MASK_EXT 0x006c
132 #define TX_FIFO_URGENT_THRESHOLD 0x0074
133 #define RX_DISCARD_FRAME_CNT 0x0084
134 #define RX_OVERRUN_FRAME_CNT 0x0088
135 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
136 #define TX_BW_RATE_MOVED 0x00e0
137 #define TX_BW_MTU_MOVED 0x00e8
138 #define TX_BW_BURST_MOVED 0x00ec
139 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
140 #define RXQ_COMMAND 0x0280
141 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
142 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
143 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
144 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
147 * Misc per-port registers.
149 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
150 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
151 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
152 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
156 * SDMA configuration register default value.
158 #if defined(__BIG_ENDIAN)
159 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
160 (RX_BURST_SIZE_4_64BIT | \
161 TX_BURST_SIZE_4_64BIT)
162 #elif defined(__LITTLE_ENDIAN)
163 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
164 (RX_BURST_SIZE_4_64BIT | \
167 TX_BURST_SIZE_4_64BIT)
169 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
176 #define DEFAULT_RX_QUEUE_SIZE 128
177 #define DEFAULT_TX_QUEUE_SIZE 256
178 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
184 #if defined(__BIG_ENDIAN)
186 u16 byte_cnt; /* Descriptor buffer byte count */
187 u16 buf_size; /* Buffer size */
188 u32 cmd_sts; /* Descriptor command status */
189 u32 next_desc_ptr; /* Next descriptor pointer */
190 u32 buf_ptr; /* Descriptor buffer pointer */
194 u16 byte_cnt; /* buffer byte count */
195 u16 l4i_chk; /* CPU provided TCP checksum */
196 u32 cmd_sts; /* Command/status field */
197 u32 next_desc_ptr; /* Pointer to next descriptor */
198 u32 buf_ptr; /* pointer to buffer for this descriptor*/
200 #elif defined(__LITTLE_ENDIAN)
202 u32 cmd_sts; /* Descriptor command status */
203 u16 buf_size; /* Buffer size */
204 u16 byte_cnt; /* Descriptor buffer byte count */
205 u32 buf_ptr; /* Descriptor buffer pointer */
206 u32 next_desc_ptr; /* Next descriptor pointer */
210 u32 cmd_sts; /* Command/status field */
211 u16 l4i_chk; /* CPU provided TCP checksum */
212 u16 byte_cnt; /* buffer byte count */
213 u32 buf_ptr; /* pointer to buffer for this descriptor*/
214 u32 next_desc_ptr; /* Pointer to next descriptor */
217 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
220 /* RX & TX descriptor command */
221 #define BUFFER_OWNED_BY_DMA 0x80000000
223 /* RX & TX descriptor status */
224 #define ERROR_SUMMARY 0x00000001
226 /* RX descriptor status */
227 #define LAYER_4_CHECKSUM_OK 0x40000000
228 #define RX_ENABLE_INTERRUPT 0x20000000
229 #define RX_FIRST_DESC 0x08000000
230 #define RX_LAST_DESC 0x04000000
231 #define RX_IP_HDR_OK 0x02000000
232 #define RX_PKT_IS_IPV4 0x01000000
233 #define RX_PKT_IS_ETHERNETV2 0x00800000
234 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
235 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
236 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
238 /* TX descriptor command */
239 #define TX_ENABLE_INTERRUPT 0x00800000
240 #define GEN_CRC 0x00400000
241 #define TX_FIRST_DESC 0x00200000
242 #define TX_LAST_DESC 0x00100000
243 #define ZERO_PADDING 0x00080000
244 #define GEN_IP_V4_CHECKSUM 0x00040000
245 #define GEN_TCP_UDP_CHECKSUM 0x00020000
246 #define UDP_FRAME 0x00010000
247 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
248 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
250 #define TX_IHL_SHIFT 11
253 /* global *******************************************************************/
254 struct mv643xx_eth_shared_private {
256 * Ethernet controller base address.
261 * Per-port MBUS window access register value.
266 * Hardware-specific parameters.
268 int extended_rx_coal_limit;
274 #define TX_BW_CONTROL_ABSENT 0
275 #define TX_BW_CONTROL_OLD_LAYOUT 1
276 #define TX_BW_CONTROL_NEW_LAYOUT 2
278 static int mv643xx_eth_open(struct net_device *dev);
279 static int mv643xx_eth_stop(struct net_device *dev);
282 /* per-port *****************************************************************/
283 struct mib_counters {
284 u64 good_octets_received;
285 u32 bad_octets_received;
286 u32 internal_mac_transmit_err;
287 u32 good_frames_received;
288 u32 bad_frames_received;
289 u32 broadcast_frames_received;
290 u32 multicast_frames_received;
291 u32 frames_64_octets;
292 u32 frames_65_to_127_octets;
293 u32 frames_128_to_255_octets;
294 u32 frames_256_to_511_octets;
295 u32 frames_512_to_1023_octets;
296 u32 frames_1024_to_max_octets;
297 u64 good_octets_sent;
298 u32 good_frames_sent;
299 u32 excessive_collision;
300 u32 multicast_frames_sent;
301 u32 broadcast_frames_sent;
302 u32 unrec_mac_control_received;
304 u32 good_fc_received;
306 u32 undersize_received;
307 u32 fragments_received;
308 u32 oversize_received;
310 u32 mac_receive_error;
314 /* Non MIB hardware counters */
328 struct rx_desc *rx_desc_area;
329 dma_addr_t rx_desc_dma;
330 int rx_desc_area_size;
331 struct sk_buff **rx_skb;
343 struct tx_desc *tx_desc_area;
344 dma_addr_t tx_desc_dma;
345 int tx_desc_area_size;
347 struct sk_buff_head tx_skb;
349 unsigned long tx_packets;
350 unsigned long tx_bytes;
351 unsigned long tx_dropped;
354 struct mv643xx_eth_private {
355 struct mv643xx_eth_shared_private *shared;
359 struct net_device *dev;
361 struct phy_device *phy;
363 struct timer_list mib_counters_timer;
364 spinlock_t mib_counters_lock;
365 struct mib_counters mib_counters;
367 struct work_struct tx_timeout_task;
369 struct napi_struct napi;
384 unsigned long rx_desc_sram_addr;
385 int rx_desc_sram_size;
387 struct timer_list rx_oom;
388 struct rx_queue rxq[8];
394 unsigned long tx_desc_sram_addr;
395 int tx_desc_sram_size;
397 struct tx_queue txq[8];
400 * Hardware-specific parameters.
407 /* port register accessors **************************************************/
408 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
410 return readl(mp->shared->base + offset);
413 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
415 return readl(mp->base + offset);
418 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
420 writel(data, mp->shared->base + offset);
423 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
425 writel(data, mp->base + offset);
429 /* rxq/txq helper functions *************************************************/
430 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
432 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
435 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
437 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
440 static void rxq_enable(struct rx_queue *rxq)
442 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
443 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
446 static void rxq_disable(struct rx_queue *rxq)
448 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
449 u8 mask = 1 << rxq->index;
451 wrlp(mp, RXQ_COMMAND, mask << 8);
452 while (rdlp(mp, RXQ_COMMAND) & mask)
456 static void txq_reset_hw_ptr(struct tx_queue *txq)
458 struct mv643xx_eth_private *mp = txq_to_mp(txq);
461 addr = (u32)txq->tx_desc_dma;
462 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
463 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
466 static void txq_enable(struct tx_queue *txq)
468 struct mv643xx_eth_private *mp = txq_to_mp(txq);
469 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
472 static void txq_disable(struct tx_queue *txq)
474 struct mv643xx_eth_private *mp = txq_to_mp(txq);
475 u8 mask = 1 << txq->index;
477 wrlp(mp, TXQ_COMMAND, mask << 8);
478 while (rdlp(mp, TXQ_COMMAND) & mask)
482 static void txq_maybe_wake(struct tx_queue *txq)
484 struct mv643xx_eth_private *mp = txq_to_mp(txq);
485 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
487 if (netif_tx_queue_stopped(nq)) {
488 __netif_tx_lock(nq, smp_processor_id());
489 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
490 netif_tx_wake_queue(nq);
491 __netif_tx_unlock(nq);
495 static int rxq_process(struct rx_queue *rxq, int budget)
497 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
498 struct net_device_stats *stats = &mp->dev->stats;
502 while (rx < budget && rxq->rx_desc_count) {
503 struct rx_desc *rx_desc;
504 unsigned int cmd_sts;
508 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
510 cmd_sts = rx_desc->cmd_sts;
511 if (cmd_sts & BUFFER_OWNED_BY_DMA)
515 skb = rxq->rx_skb[rxq->rx_curr_desc];
516 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
519 if (rxq->rx_curr_desc == rxq->rx_ring_size)
520 rxq->rx_curr_desc = 0;
522 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
523 rx_desc->buf_size, DMA_FROM_DEVICE);
524 rxq->rx_desc_count--;
527 mp->work_rx_refill |= 1 << rxq->index;
529 byte_cnt = rx_desc->byte_cnt;
534 * Note that the descriptor byte count includes 2 dummy
535 * bytes automatically inserted by the hardware at the
536 * start of the packet (which we don't count), and a 4
537 * byte CRC at the end of the packet (which we do count).
540 stats->rx_bytes += byte_cnt - 2;
543 * In case we received a packet without first / last bits
544 * on, or the error summary bit is set, the packet needs
547 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
548 != (RX_FIRST_DESC | RX_LAST_DESC))
552 * The -4 is for the CRC in the trailer of the
555 skb_put(skb, byte_cnt - 2 - 4);
557 if (cmd_sts & LAYER_4_CHECKSUM_OK)
558 skb->ip_summed = CHECKSUM_UNNECESSARY;
559 skb->protocol = eth_type_trans(skb, mp->dev);
561 napi_gro_receive(&mp->napi, skb);
568 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
569 (RX_FIRST_DESC | RX_LAST_DESC)) {
572 "received packet spanning multiple descriptors\n");
575 if (cmd_sts & ERROR_SUMMARY)
582 mp->work_rx &= ~(1 << rxq->index);
587 static int rxq_refill(struct rx_queue *rxq, int budget)
589 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
593 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
596 struct rx_desc *rx_desc;
599 skb = netdev_alloc_skb(mp->dev, mp->skb_size);
607 skb_reserve(skb, SKB_DMA_REALIGN);
610 rxq->rx_desc_count++;
612 rx = rxq->rx_used_desc++;
613 if (rxq->rx_used_desc == rxq->rx_ring_size)
614 rxq->rx_used_desc = 0;
616 rx_desc = rxq->rx_desc_area + rx;
618 size = skb->end - skb->data;
619 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
622 rx_desc->buf_size = size;
623 rxq->rx_skb[rx] = skb;
625 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
629 * The hardware automatically prepends 2 bytes of
630 * dummy data to each received packet, so that the
631 * IP header ends up 16-byte aligned.
636 if (refilled < budget)
637 mp->work_rx_refill &= ~(1 << rxq->index);
644 /* tx ***********************************************************************/
645 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
649 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
650 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
652 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7)
659 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
661 struct mv643xx_eth_private *mp = txq_to_mp(txq);
662 int nr_frags = skb_shinfo(skb)->nr_frags;
665 for (frag = 0; frag < nr_frags; frag++) {
666 skb_frag_t *this_frag;
668 struct tx_desc *desc;
670 this_frag = &skb_shinfo(skb)->frags[frag];
671 tx_index = txq->tx_curr_desc++;
672 if (txq->tx_curr_desc == txq->tx_ring_size)
673 txq->tx_curr_desc = 0;
674 desc = &txq->tx_desc_area[tx_index];
677 * The last fragment will generate an interrupt
678 * which will free the skb on TX completion.
680 if (frag == nr_frags - 1) {
681 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
682 ZERO_PADDING | TX_LAST_DESC |
685 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
689 desc->byte_cnt = skb_frag_size(this_frag);
690 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
692 skb_frag_size(this_frag),
697 static inline __be16 sum16_as_be(__sum16 sum)
699 return (__force __be16)sum;
702 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
704 struct mv643xx_eth_private *mp = txq_to_mp(txq);
705 int nr_frags = skb_shinfo(skb)->nr_frags;
707 struct tx_desc *desc;
712 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
715 if (skb->ip_summed == CHECKSUM_PARTIAL) {
719 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
720 skb->protocol != htons(ETH_P_8021Q));
722 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
723 tag_bytes = hdr_len - ETH_HLEN;
724 if (skb->len - hdr_len > mp->shared->tx_csum_limit ||
725 unlikely(tag_bytes & ~12)) {
726 if (skb_checksum_help(skb) == 0)
733 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
735 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
737 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
739 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
741 switch (ip_hdr(skb)->protocol) {
743 cmd_sts |= UDP_FRAME;
744 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
747 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
754 /* Errata BTS #50, IHL must be 5 if no HW checksum */
755 cmd_sts |= 5 << TX_IHL_SHIFT;
758 tx_index = txq->tx_curr_desc++;
759 if (txq->tx_curr_desc == txq->tx_ring_size)
760 txq->tx_curr_desc = 0;
761 desc = &txq->tx_desc_area[tx_index];
764 txq_submit_frag_skb(txq, skb);
765 length = skb_headlen(skb);
767 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
771 desc->l4i_chk = l4i_chk;
772 desc->byte_cnt = length;
773 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
774 length, DMA_TO_DEVICE);
776 __skb_queue_tail(&txq->tx_skb, skb);
778 skb_tx_timestamp(skb);
780 /* ensure all other descriptors are written before first cmd_sts */
782 desc->cmd_sts = cmd_sts;
784 /* clear TX_END status */
785 mp->work_tx_end &= ~(1 << txq->index);
787 /* ensure all descriptors are written before poking hardware */
791 txq->tx_desc_count += nr_frags + 1;
796 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
798 struct mv643xx_eth_private *mp = netdev_priv(dev);
800 struct tx_queue *txq;
801 struct netdev_queue *nq;
803 queue = skb_get_queue_mapping(skb);
804 txq = mp->txq + queue;
805 nq = netdev_get_tx_queue(dev, queue);
807 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
809 netdev_printk(KERN_DEBUG, dev,
810 "failed to linearize skb with tiny unaligned fragment\n");
811 return NETDEV_TX_BUSY;
814 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
816 netdev_err(dev, "tx queue full?!\n");
823 if (!txq_submit_skb(txq, skb)) {
826 txq->tx_bytes += length;
829 entries_left = txq->tx_ring_size - txq->tx_desc_count;
830 if (entries_left < MAX_SKB_FRAGS + 1)
831 netif_tx_stop_queue(nq);
838 /* tx napi ******************************************************************/
839 static void txq_kick(struct tx_queue *txq)
841 struct mv643xx_eth_private *mp = txq_to_mp(txq);
842 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
846 __netif_tx_lock(nq, smp_processor_id());
848 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
851 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
852 expected_ptr = (u32)txq->tx_desc_dma +
853 txq->tx_curr_desc * sizeof(struct tx_desc);
855 if (hw_desc_ptr != expected_ptr)
859 __netif_tx_unlock(nq);
861 mp->work_tx_end &= ~(1 << txq->index);
864 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
866 struct mv643xx_eth_private *mp = txq_to_mp(txq);
867 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
870 __netif_tx_lock_bh(nq);
873 while (reclaimed < budget && txq->tx_desc_count > 0) {
875 struct tx_desc *desc;
879 tx_index = txq->tx_used_desc;
880 desc = &txq->tx_desc_area[tx_index];
881 cmd_sts = desc->cmd_sts;
883 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
886 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
889 txq->tx_used_desc = tx_index + 1;
890 if (txq->tx_used_desc == txq->tx_ring_size)
891 txq->tx_used_desc = 0;
894 txq->tx_desc_count--;
897 if (cmd_sts & TX_LAST_DESC)
898 skb = __skb_dequeue(&txq->tx_skb);
900 if (cmd_sts & ERROR_SUMMARY) {
901 netdev_info(mp->dev, "tx error\n");
902 mp->dev->stats.tx_errors++;
905 if (cmd_sts & TX_FIRST_DESC) {
906 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
907 desc->byte_cnt, DMA_TO_DEVICE);
909 dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr,
910 desc->byte_cnt, DMA_TO_DEVICE);
916 __netif_tx_unlock_bh(nq);
918 if (reclaimed < budget)
919 mp->work_tx &= ~(1 << txq->index);
925 /* tx rate control **********************************************************/
927 * Set total maximum TX rate (shared by all TX queues for this port)
928 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
930 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
936 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
937 if (token_rate > 1023)
940 mtu = (mp->dev->mtu + 255) >> 8;
944 bucket_size = (burst + 255) >> 8;
945 if (bucket_size > 65535)
948 switch (mp->shared->tx_bw_control) {
949 case TX_BW_CONTROL_OLD_LAYOUT:
950 wrlp(mp, TX_BW_RATE, token_rate);
951 wrlp(mp, TX_BW_MTU, mtu);
952 wrlp(mp, TX_BW_BURST, bucket_size);
954 case TX_BW_CONTROL_NEW_LAYOUT:
955 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
956 wrlp(mp, TX_BW_MTU_MOVED, mtu);
957 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
962 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
964 struct mv643xx_eth_private *mp = txq_to_mp(txq);
968 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
969 if (token_rate > 1023)
972 bucket_size = (burst + 255) >> 8;
973 if (bucket_size > 65535)
976 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
977 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
980 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
982 struct mv643xx_eth_private *mp = txq_to_mp(txq);
987 * Turn on fixed priority mode.
990 switch (mp->shared->tx_bw_control) {
991 case TX_BW_CONTROL_OLD_LAYOUT:
992 off = TXQ_FIX_PRIO_CONF;
994 case TX_BW_CONTROL_NEW_LAYOUT:
995 off = TXQ_FIX_PRIO_CONF_MOVED;
1000 val = rdlp(mp, off);
1001 val |= 1 << txq->index;
1007 /* mii management interface *************************************************/
1008 static void mv643xx_adjust_pscr(struct mv643xx_eth_private *mp)
1010 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
1011 u32 autoneg_disable = FORCE_LINK_PASS |
1012 DISABLE_AUTO_NEG_SPEED_GMII |
1013 DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1014 DISABLE_AUTO_NEG_FOR_DUPLEX;
1016 if (mp->phy->autoneg == AUTONEG_ENABLE) {
1017 /* enable auto negotiation */
1018 pscr &= ~autoneg_disable;
1022 pscr |= autoneg_disable;
1024 if (mp->phy->speed == SPEED_1000) {
1025 /* force gigabit, half duplex not supported */
1026 pscr |= SET_GMII_SPEED_TO_1000;
1027 pscr |= SET_FULL_DUPLEX_MODE;
1031 pscr &= ~SET_GMII_SPEED_TO_1000;
1033 if (mp->phy->speed == SPEED_100)
1034 pscr |= SET_MII_SPEED_TO_100;
1036 pscr &= ~SET_MII_SPEED_TO_100;
1038 if (mp->phy->duplex == DUPLEX_FULL)
1039 pscr |= SET_FULL_DUPLEX_MODE;
1041 pscr &= ~SET_FULL_DUPLEX_MODE;
1044 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1047 /* statistics ***************************************************************/
1048 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1050 struct mv643xx_eth_private *mp = netdev_priv(dev);
1051 struct net_device_stats *stats = &dev->stats;
1052 unsigned long tx_packets = 0;
1053 unsigned long tx_bytes = 0;
1054 unsigned long tx_dropped = 0;
1057 for (i = 0; i < mp->txq_count; i++) {
1058 struct tx_queue *txq = mp->txq + i;
1060 tx_packets += txq->tx_packets;
1061 tx_bytes += txq->tx_bytes;
1062 tx_dropped += txq->tx_dropped;
1065 stats->tx_packets = tx_packets;
1066 stats->tx_bytes = tx_bytes;
1067 stats->tx_dropped = tx_dropped;
1072 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1074 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1077 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1081 for (i = 0; i < 0x80; i += 4)
1084 /* Clear non MIB hw counters also */
1085 rdlp(mp, RX_DISCARD_FRAME_CNT);
1086 rdlp(mp, RX_OVERRUN_FRAME_CNT);
1089 static void mib_counters_update(struct mv643xx_eth_private *mp)
1091 struct mib_counters *p = &mp->mib_counters;
1093 spin_lock_bh(&mp->mib_counters_lock);
1094 p->good_octets_received += mib_read(mp, 0x00);
1095 p->bad_octets_received += mib_read(mp, 0x08);
1096 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1097 p->good_frames_received += mib_read(mp, 0x10);
1098 p->bad_frames_received += mib_read(mp, 0x14);
1099 p->broadcast_frames_received += mib_read(mp, 0x18);
1100 p->multicast_frames_received += mib_read(mp, 0x1c);
1101 p->frames_64_octets += mib_read(mp, 0x20);
1102 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1103 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1104 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1105 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1106 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1107 p->good_octets_sent += mib_read(mp, 0x38);
1108 p->good_frames_sent += mib_read(mp, 0x40);
1109 p->excessive_collision += mib_read(mp, 0x44);
1110 p->multicast_frames_sent += mib_read(mp, 0x48);
1111 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1112 p->unrec_mac_control_received += mib_read(mp, 0x50);
1113 p->fc_sent += mib_read(mp, 0x54);
1114 p->good_fc_received += mib_read(mp, 0x58);
1115 p->bad_fc_received += mib_read(mp, 0x5c);
1116 p->undersize_received += mib_read(mp, 0x60);
1117 p->fragments_received += mib_read(mp, 0x64);
1118 p->oversize_received += mib_read(mp, 0x68);
1119 p->jabber_received += mib_read(mp, 0x6c);
1120 p->mac_receive_error += mib_read(mp, 0x70);
1121 p->bad_crc_event += mib_read(mp, 0x74);
1122 p->collision += mib_read(mp, 0x78);
1123 p->late_collision += mib_read(mp, 0x7c);
1124 /* Non MIB hardware counters */
1125 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1126 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
1127 spin_unlock_bh(&mp->mib_counters_lock);
1130 static void mib_counters_timer_wrapper(unsigned long _mp)
1132 struct mv643xx_eth_private *mp = (void *)_mp;
1133 mib_counters_update(mp);
1134 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1138 /* interrupt coalescing *****************************************************/
1140 * Hardware coalescing parameters are set in units of 64 t_clk
1143 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1145 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1147 * In the ->set*() methods, we round the computed register value
1148 * to the nearest integer.
1150 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1152 u32 val = rdlp(mp, SDMA_CONFIG);
1155 if (mp->shared->extended_rx_coal_limit)
1156 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1158 temp = (val & 0x003fff00) >> 8;
1161 do_div(temp, mp->t_clk);
1163 return (unsigned int)temp;
1166 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1171 temp = (u64)usec * mp->t_clk;
1173 do_div(temp, 64000000);
1175 val = rdlp(mp, SDMA_CONFIG);
1176 if (mp->shared->extended_rx_coal_limit) {
1180 val |= (temp & 0x8000) << 10;
1181 val |= (temp & 0x7fff) << 7;
1186 val |= (temp & 0x3fff) << 8;
1188 wrlp(mp, SDMA_CONFIG, val);
1191 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1195 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1197 do_div(temp, mp->t_clk);
1199 return (unsigned int)temp;
1202 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1206 temp = (u64)usec * mp->t_clk;
1208 do_div(temp, 64000000);
1213 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1217 /* ethtool ******************************************************************/
1218 struct mv643xx_eth_stats {
1219 char stat_string[ETH_GSTRING_LEN];
1226 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1227 offsetof(struct net_device, stats.m), -1 }
1229 #define MIBSTAT(m) \
1230 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1231 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1233 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1242 MIBSTAT(good_octets_received),
1243 MIBSTAT(bad_octets_received),
1244 MIBSTAT(internal_mac_transmit_err),
1245 MIBSTAT(good_frames_received),
1246 MIBSTAT(bad_frames_received),
1247 MIBSTAT(broadcast_frames_received),
1248 MIBSTAT(multicast_frames_received),
1249 MIBSTAT(frames_64_octets),
1250 MIBSTAT(frames_65_to_127_octets),
1251 MIBSTAT(frames_128_to_255_octets),
1252 MIBSTAT(frames_256_to_511_octets),
1253 MIBSTAT(frames_512_to_1023_octets),
1254 MIBSTAT(frames_1024_to_max_octets),
1255 MIBSTAT(good_octets_sent),
1256 MIBSTAT(good_frames_sent),
1257 MIBSTAT(excessive_collision),
1258 MIBSTAT(multicast_frames_sent),
1259 MIBSTAT(broadcast_frames_sent),
1260 MIBSTAT(unrec_mac_control_received),
1262 MIBSTAT(good_fc_received),
1263 MIBSTAT(bad_fc_received),
1264 MIBSTAT(undersize_received),
1265 MIBSTAT(fragments_received),
1266 MIBSTAT(oversize_received),
1267 MIBSTAT(jabber_received),
1268 MIBSTAT(mac_receive_error),
1269 MIBSTAT(bad_crc_event),
1271 MIBSTAT(late_collision),
1272 MIBSTAT(rx_discard),
1273 MIBSTAT(rx_overrun),
1277 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1278 struct ethtool_cmd *cmd)
1282 err = phy_read_status(mp->phy);
1284 err = phy_ethtool_gset(mp->phy, cmd);
1287 * The MAC does not support 1000baseT_Half.
1289 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1290 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1296 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
1297 struct ethtool_cmd *cmd)
1301 port_status = rdlp(mp, PORT_STATUS);
1303 cmd->supported = SUPPORTED_MII;
1304 cmd->advertising = ADVERTISED_MII;
1305 switch (port_status & PORT_SPEED_MASK) {
1307 ethtool_cmd_speed_set(cmd, SPEED_10);
1309 case PORT_SPEED_100:
1310 ethtool_cmd_speed_set(cmd, SPEED_100);
1312 case PORT_SPEED_1000:
1313 ethtool_cmd_speed_set(cmd, SPEED_1000);
1319 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1320 cmd->port = PORT_MII;
1321 cmd->phy_address = 0;
1322 cmd->transceiver = XCVR_INTERNAL;
1323 cmd->autoneg = AUTONEG_DISABLE;
1331 mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1333 struct mv643xx_eth_private *mp = netdev_priv(dev);
1337 phy_ethtool_get_wol(mp->phy, wol);
1341 mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1343 struct mv643xx_eth_private *mp = netdev_priv(dev);
1346 if (mp->phy == NULL)
1349 err = phy_ethtool_set_wol(mp->phy, wol);
1350 /* Given that mv643xx_eth works without the marvell-specific PHY driver,
1351 * this debugging hint is useful to have.
1353 if (err == -EOPNOTSUPP)
1354 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n");
1359 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1361 struct mv643xx_eth_private *mp = netdev_priv(dev);
1363 if (mp->phy != NULL)
1364 return mv643xx_eth_get_settings_phy(mp, cmd);
1366 return mv643xx_eth_get_settings_phyless(mp, cmd);
1370 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1372 struct mv643xx_eth_private *mp = netdev_priv(dev);
1375 if (mp->phy == NULL)
1379 * The MAC does not support 1000baseT_Half.
1381 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1383 ret = phy_ethtool_sset(mp->phy, cmd);
1385 mv643xx_adjust_pscr(mp);
1389 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1390 struct ethtool_drvinfo *drvinfo)
1392 strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1393 sizeof(drvinfo->driver));
1394 strlcpy(drvinfo->version, mv643xx_eth_driver_version,
1395 sizeof(drvinfo->version));
1396 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1397 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
1398 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1401 static int mv643xx_eth_nway_reset(struct net_device *dev)
1403 struct mv643xx_eth_private *mp = netdev_priv(dev);
1405 if (mp->phy == NULL)
1408 return genphy_restart_aneg(mp->phy);
1412 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1414 struct mv643xx_eth_private *mp = netdev_priv(dev);
1416 ec->rx_coalesce_usecs = get_rx_coal(mp);
1417 ec->tx_coalesce_usecs = get_tx_coal(mp);
1423 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1425 struct mv643xx_eth_private *mp = netdev_priv(dev);
1427 set_rx_coal(mp, ec->rx_coalesce_usecs);
1428 set_tx_coal(mp, ec->tx_coalesce_usecs);
1434 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1436 struct mv643xx_eth_private *mp = netdev_priv(dev);
1438 er->rx_max_pending = 4096;
1439 er->tx_max_pending = 4096;
1441 er->rx_pending = mp->rx_ring_size;
1442 er->tx_pending = mp->tx_ring_size;
1446 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1448 struct mv643xx_eth_private *mp = netdev_priv(dev);
1450 if (er->rx_mini_pending || er->rx_jumbo_pending)
1453 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1454 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1456 if (netif_running(dev)) {
1457 mv643xx_eth_stop(dev);
1458 if (mv643xx_eth_open(dev)) {
1460 "fatal error on re-opening device after ring param change\n");
1470 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
1472 struct mv643xx_eth_private *mp = netdev_priv(dev);
1473 bool rx_csum = features & NETIF_F_RXCSUM;
1475 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1480 static void mv643xx_eth_get_strings(struct net_device *dev,
1481 uint32_t stringset, uint8_t *data)
1485 if (stringset == ETH_SS_STATS) {
1486 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1487 memcpy(data + i * ETH_GSTRING_LEN,
1488 mv643xx_eth_stats[i].stat_string,
1494 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1495 struct ethtool_stats *stats,
1498 struct mv643xx_eth_private *mp = netdev_priv(dev);
1501 mv643xx_eth_get_stats(dev);
1502 mib_counters_update(mp);
1504 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1505 const struct mv643xx_eth_stats *stat;
1508 stat = mv643xx_eth_stats + i;
1510 if (stat->netdev_off >= 0)
1511 p = ((void *)mp->dev) + stat->netdev_off;
1513 p = ((void *)mp) + stat->mp_off;
1515 data[i] = (stat->sizeof_stat == 8) ?
1516 *(uint64_t *)p : *(uint32_t *)p;
1520 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1522 if (sset == ETH_SS_STATS)
1523 return ARRAY_SIZE(mv643xx_eth_stats);
1528 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1529 .get_settings = mv643xx_eth_get_settings,
1530 .set_settings = mv643xx_eth_set_settings,
1531 .get_drvinfo = mv643xx_eth_get_drvinfo,
1532 .nway_reset = mv643xx_eth_nway_reset,
1533 .get_link = ethtool_op_get_link,
1534 .get_coalesce = mv643xx_eth_get_coalesce,
1535 .set_coalesce = mv643xx_eth_set_coalesce,
1536 .get_ringparam = mv643xx_eth_get_ringparam,
1537 .set_ringparam = mv643xx_eth_set_ringparam,
1538 .get_strings = mv643xx_eth_get_strings,
1539 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1540 .get_sset_count = mv643xx_eth_get_sset_count,
1541 .get_ts_info = ethtool_op_get_ts_info,
1542 .get_wol = mv643xx_eth_get_wol,
1543 .set_wol = mv643xx_eth_set_wol,
1547 /* address handling *********************************************************/
1548 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1550 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1551 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1553 addr[0] = (mac_h >> 24) & 0xff;
1554 addr[1] = (mac_h >> 16) & 0xff;
1555 addr[2] = (mac_h >> 8) & 0xff;
1556 addr[3] = mac_h & 0xff;
1557 addr[4] = (mac_l >> 8) & 0xff;
1558 addr[5] = mac_l & 0xff;
1561 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1563 wrlp(mp, MAC_ADDR_HIGH,
1564 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1565 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1568 static u32 uc_addr_filter_mask(struct net_device *dev)
1570 struct netdev_hw_addr *ha;
1573 if (dev->flags & IFF_PROMISC)
1576 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1577 netdev_for_each_uc_addr(ha, dev) {
1578 if (memcmp(dev->dev_addr, ha->addr, 5))
1580 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
1583 nibbles |= 1 << (ha->addr[5] & 0x0f);
1589 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1591 struct mv643xx_eth_private *mp = netdev_priv(dev);
1596 uc_addr_set(mp, dev->dev_addr);
1598 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1600 nibbles = uc_addr_filter_mask(dev);
1602 port_config |= UNICAST_PROMISCUOUS_MODE;
1606 for (i = 0; i < 16; i += 4) {
1607 int off = UNICAST_TABLE(mp->port_num) + i;
1624 wrlp(mp, PORT_CONFIG, port_config);
1627 static int addr_crc(unsigned char *addr)
1632 for (i = 0; i < 6; i++) {
1635 crc = (crc ^ addr[i]) << 8;
1636 for (j = 7; j >= 0; j--) {
1637 if (crc & (0x100 << j))
1645 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1647 struct mv643xx_eth_private *mp = netdev_priv(dev);
1650 struct netdev_hw_addr *ha;
1653 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1658 port_num = mp->port_num;
1659 accept = 0x01010101;
1660 for (i = 0; i < 0x100; i += 4) {
1661 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1662 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1667 mc_spec = kmalloc(0x200, GFP_ATOMIC);
1668 if (mc_spec == NULL)
1670 mc_other = mc_spec + (0x100 >> 2);
1672 memset(mc_spec, 0, 0x100);
1673 memset(mc_other, 0, 0x100);
1675 netdev_for_each_mc_addr(ha, dev) {
1680 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1685 entry = addr_crc(a);
1688 table[entry >> 2] |= 1 << (8 * (entry & 3));
1691 for (i = 0; i < 0x100; i += 4) {
1692 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1693 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1699 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1701 mv643xx_eth_program_unicast_filter(dev);
1702 mv643xx_eth_program_multicast_filter(dev);
1705 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1707 struct sockaddr *sa = addr;
1709 if (!is_valid_ether_addr(sa->sa_data))
1710 return -EADDRNOTAVAIL;
1712 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1714 netif_addr_lock_bh(dev);
1715 mv643xx_eth_program_unicast_filter(dev);
1716 netif_addr_unlock_bh(dev);
1722 /* rx/tx queue initialisation ***********************************************/
1723 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1725 struct rx_queue *rxq = mp->rxq + index;
1726 struct rx_desc *rx_desc;
1732 rxq->rx_ring_size = mp->rx_ring_size;
1734 rxq->rx_desc_count = 0;
1735 rxq->rx_curr_desc = 0;
1736 rxq->rx_used_desc = 0;
1738 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1740 if (index == 0 && size <= mp->rx_desc_sram_size) {
1741 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1742 mp->rx_desc_sram_size);
1743 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1745 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1746 size, &rxq->rx_desc_dma,
1750 if (rxq->rx_desc_area == NULL) {
1752 "can't allocate rx ring (%d bytes)\n", size);
1755 memset(rxq->rx_desc_area, 0, size);
1757 rxq->rx_desc_area_size = size;
1758 rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
1760 if (rxq->rx_skb == NULL)
1763 rx_desc = rxq->rx_desc_area;
1764 for (i = 0; i < rxq->rx_ring_size; i++) {
1768 if (nexti == rxq->rx_ring_size)
1771 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1772 nexti * sizeof(struct rx_desc);
1779 if (index == 0 && size <= mp->rx_desc_sram_size)
1780 iounmap(rxq->rx_desc_area);
1782 dma_free_coherent(mp->dev->dev.parent, size,
1790 static void rxq_deinit(struct rx_queue *rxq)
1792 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1797 for (i = 0; i < rxq->rx_ring_size; i++) {
1798 if (rxq->rx_skb[i]) {
1799 dev_kfree_skb(rxq->rx_skb[i]);
1800 rxq->rx_desc_count--;
1804 if (rxq->rx_desc_count) {
1805 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
1806 rxq->rx_desc_count);
1809 if (rxq->index == 0 &&
1810 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1811 iounmap(rxq->rx_desc_area);
1813 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
1814 rxq->rx_desc_area, rxq->rx_desc_dma);
1819 static int txq_init(struct mv643xx_eth_private *mp, int index)
1821 struct tx_queue *txq = mp->txq + index;
1822 struct tx_desc *tx_desc;
1828 txq->tx_ring_size = mp->tx_ring_size;
1830 txq->tx_desc_count = 0;
1831 txq->tx_curr_desc = 0;
1832 txq->tx_used_desc = 0;
1834 size = txq->tx_ring_size * sizeof(struct tx_desc);
1836 if (index == 0 && size <= mp->tx_desc_sram_size) {
1837 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1838 mp->tx_desc_sram_size);
1839 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1841 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1842 size, &txq->tx_desc_dma,
1846 if (txq->tx_desc_area == NULL) {
1848 "can't allocate tx ring (%d bytes)\n", size);
1851 memset(txq->tx_desc_area, 0, size);
1853 txq->tx_desc_area_size = size;
1855 tx_desc = txq->tx_desc_area;
1856 for (i = 0; i < txq->tx_ring_size; i++) {
1857 struct tx_desc *txd = tx_desc + i;
1861 if (nexti == txq->tx_ring_size)
1865 txd->next_desc_ptr = txq->tx_desc_dma +
1866 nexti * sizeof(struct tx_desc);
1869 skb_queue_head_init(&txq->tx_skb);
1874 static void txq_deinit(struct tx_queue *txq)
1876 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1879 txq_reclaim(txq, txq->tx_ring_size, 1);
1881 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1883 if (txq->index == 0 &&
1884 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1885 iounmap(txq->tx_desc_area);
1887 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
1888 txq->tx_desc_area, txq->tx_desc_dma);
1892 /* netdev ops and related ***************************************************/
1893 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1898 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
1903 if (int_cause & INT_EXT) {
1904 int_cause &= ~INT_EXT;
1905 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
1909 wrlp(mp, INT_CAUSE, ~int_cause);
1910 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
1911 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1912 mp->work_rx |= (int_cause & INT_RX) >> 2;
1915 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1916 if (int_cause_ext) {
1917 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1918 if (int_cause_ext & INT_EXT_LINK_PHY)
1920 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1926 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1928 struct net_device *dev = (struct net_device *)dev_id;
1929 struct mv643xx_eth_private *mp = netdev_priv(dev);
1931 if (unlikely(!mv643xx_eth_collect_events(mp)))
1934 wrlp(mp, INT_MASK, 0);
1935 napi_schedule(&mp->napi);
1940 static void handle_link_event(struct mv643xx_eth_private *mp)
1942 struct net_device *dev = mp->dev;
1948 port_status = rdlp(mp, PORT_STATUS);
1949 if (!(port_status & LINK_UP)) {
1950 if (netif_carrier_ok(dev)) {
1953 netdev_info(dev, "link down\n");
1955 netif_carrier_off(dev);
1957 for (i = 0; i < mp->txq_count; i++) {
1958 struct tx_queue *txq = mp->txq + i;
1960 txq_reclaim(txq, txq->tx_ring_size, 1);
1961 txq_reset_hw_ptr(txq);
1967 switch (port_status & PORT_SPEED_MASK) {
1971 case PORT_SPEED_100:
1974 case PORT_SPEED_1000:
1981 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1982 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1984 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
1985 speed, duplex ? "full" : "half", fc ? "en" : "dis");
1987 if (!netif_carrier_ok(dev))
1988 netif_carrier_on(dev);
1991 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
1993 struct mv643xx_eth_private *mp;
1996 mp = container_of(napi, struct mv643xx_eth_private, napi);
1998 if (unlikely(mp->oom)) {
2000 del_timer(&mp->rx_oom);
2004 while (work_done < budget) {
2009 if (mp->work_link) {
2011 handle_link_event(mp);
2016 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2017 if (likely(!mp->oom))
2018 queue_mask |= mp->work_rx_refill;
2021 if (mv643xx_eth_collect_events(mp))
2026 queue = fls(queue_mask) - 1;
2027 queue_mask = 1 << queue;
2029 work_tbd = budget - work_done;
2033 if (mp->work_tx_end & queue_mask) {
2034 txq_kick(mp->txq + queue);
2035 } else if (mp->work_tx & queue_mask) {
2036 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2037 txq_maybe_wake(mp->txq + queue);
2038 } else if (mp->work_rx & queue_mask) {
2039 work_done += rxq_process(mp->rxq + queue, work_tbd);
2040 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2041 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2047 if (work_done < budget) {
2049 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2050 napi_complete(napi);
2051 wrlp(mp, INT_MASK, mp->int_mask);
2057 static inline void oom_timer_wrapper(unsigned long data)
2059 struct mv643xx_eth_private *mp = (void *)data;
2061 napi_schedule(&mp->napi);
2064 static void phy_reset(struct mv643xx_eth_private *mp)
2068 data = phy_read(mp->phy, MII_BMCR);
2073 if (phy_write(mp->phy, MII_BMCR, data) < 0)
2077 data = phy_read(mp->phy, MII_BMCR);
2078 } while (data >= 0 && data & BMCR_RESET);
2081 static void port_start(struct mv643xx_eth_private *mp)
2087 * Perform PHY reset, if there is a PHY.
2089 if (mp->phy != NULL) {
2090 struct ethtool_cmd cmd;
2092 mv643xx_eth_get_settings(mp->dev, &cmd);
2094 mv643xx_eth_set_settings(mp->dev, &cmd);
2098 * Configure basic link parameters.
2100 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2102 pscr |= SERIAL_PORT_ENABLE;
2103 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2105 pscr |= DO_NOT_FORCE_LINK_FAIL;
2106 if (mp->phy == NULL)
2107 pscr |= FORCE_LINK_PASS;
2108 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2111 * Configure TX path and queues.
2113 tx_set_rate(mp, 1000000000, 16777216);
2114 for (i = 0; i < mp->txq_count; i++) {
2115 struct tx_queue *txq = mp->txq + i;
2117 txq_reset_hw_ptr(txq);
2118 txq_set_rate(txq, 1000000000, 16777216);
2119 txq_set_fixed_prio_mode(txq);
2123 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2124 * frames to RX queue #0, and include the pseudo-header when
2125 * calculating receive checksums.
2127 mv643xx_eth_set_features(mp->dev, mp->dev->features);
2130 * Treat BPDUs as normal multicasts, and disable partition mode.
2132 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2135 * Add configured unicast addresses to address filter table.
2137 mv643xx_eth_program_unicast_filter(mp->dev);
2140 * Enable the receive queues.
2142 for (i = 0; i < mp->rxq_count; i++) {
2143 struct rx_queue *rxq = mp->rxq + i;
2146 addr = (u32)rxq->rx_desc_dma;
2147 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2148 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2154 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2159 * Reserve 2+14 bytes for an ethernet header (the hardware
2160 * automatically prepends 2 bytes of dummy data to each
2161 * received packet), 16 bytes for up to four VLAN tags, and
2162 * 4 bytes for the trailing FCS -- 36 bytes total.
2164 skb_size = mp->dev->mtu + 36;
2167 * Make sure that the skb size is a multiple of 8 bytes, as
2168 * the lower three bits of the receive descriptor's buffer
2169 * size field are ignored by the hardware.
2171 mp->skb_size = (skb_size + 7) & ~7;
2174 * If NET_SKB_PAD is smaller than a cache line,
2175 * netdev_alloc_skb() will cause skb->data to be misaligned
2176 * to a cache line boundary. If this is the case, include
2177 * some extra space to allow re-aligning the data area.
2179 mp->skb_size += SKB_DMA_REALIGN;
2182 static int mv643xx_eth_open(struct net_device *dev)
2184 struct mv643xx_eth_private *mp = netdev_priv(dev);
2188 wrlp(mp, INT_CAUSE, 0);
2189 wrlp(mp, INT_CAUSE_EXT, 0);
2190 rdlp(mp, INT_CAUSE_EXT);
2192 err = request_irq(dev->irq, mv643xx_eth_irq,
2193 IRQF_SHARED, dev->name, dev);
2195 netdev_err(dev, "can't assign irq\n");
2199 mv643xx_eth_recalc_skb_size(mp);
2201 napi_enable(&mp->napi);
2203 mp->int_mask = INT_EXT;
2205 for (i = 0; i < mp->rxq_count; i++) {
2206 err = rxq_init(mp, i);
2209 rxq_deinit(mp->rxq + i);
2213 rxq_refill(mp->rxq + i, INT_MAX);
2214 mp->int_mask |= INT_RX_0 << i;
2218 mp->rx_oom.expires = jiffies + (HZ / 10);
2219 add_timer(&mp->rx_oom);
2222 for (i = 0; i < mp->txq_count; i++) {
2223 err = txq_init(mp, i);
2226 txq_deinit(mp->txq + i);
2229 mp->int_mask |= INT_TX_END_0 << i;
2232 add_timer(&mp->mib_counters_timer);
2235 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2236 wrlp(mp, INT_MASK, mp->int_mask);
2242 for (i = 0; i < mp->rxq_count; i++)
2243 rxq_deinit(mp->rxq + i);
2245 free_irq(dev->irq, dev);
2250 static void port_reset(struct mv643xx_eth_private *mp)
2255 for (i = 0; i < mp->rxq_count; i++)
2256 rxq_disable(mp->rxq + i);
2257 for (i = 0; i < mp->txq_count; i++)
2258 txq_disable(mp->txq + i);
2261 u32 ps = rdlp(mp, PORT_STATUS);
2263 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2268 /* Reset the Enable bit in the Configuration Register */
2269 data = rdlp(mp, PORT_SERIAL_CONTROL);
2270 data &= ~(SERIAL_PORT_ENABLE |
2271 DO_NOT_FORCE_LINK_FAIL |
2273 wrlp(mp, PORT_SERIAL_CONTROL, data);
2276 static int mv643xx_eth_stop(struct net_device *dev)
2278 struct mv643xx_eth_private *mp = netdev_priv(dev);
2281 wrlp(mp, INT_MASK_EXT, 0x00000000);
2282 wrlp(mp, INT_MASK, 0x00000000);
2285 napi_disable(&mp->napi);
2287 del_timer_sync(&mp->rx_oom);
2289 netif_carrier_off(dev);
2291 free_irq(dev->irq, dev);
2294 mv643xx_eth_get_stats(dev);
2295 mib_counters_update(mp);
2296 del_timer_sync(&mp->mib_counters_timer);
2298 for (i = 0; i < mp->rxq_count; i++)
2299 rxq_deinit(mp->rxq + i);
2300 for (i = 0; i < mp->txq_count; i++)
2301 txq_deinit(mp->txq + i);
2306 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2308 struct mv643xx_eth_private *mp = netdev_priv(dev);
2311 if (mp->phy == NULL)
2314 ret = phy_mii_ioctl(mp->phy, ifr, cmd);
2316 mv643xx_adjust_pscr(mp);
2320 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2322 struct mv643xx_eth_private *mp = netdev_priv(dev);
2324 if (new_mtu < 64 || new_mtu > 9500)
2328 mv643xx_eth_recalc_skb_size(mp);
2329 tx_set_rate(mp, 1000000000, 16777216);
2331 if (!netif_running(dev))
2335 * Stop and then re-open the interface. This will allocate RX
2336 * skbs of the new MTU.
2337 * There is a possible danger that the open will not succeed,
2338 * due to memory being full.
2340 mv643xx_eth_stop(dev);
2341 if (mv643xx_eth_open(dev)) {
2343 "fatal error on re-opening device after MTU change\n");
2349 static void tx_timeout_task(struct work_struct *ugly)
2351 struct mv643xx_eth_private *mp;
2353 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2354 if (netif_running(mp->dev)) {
2355 netif_tx_stop_all_queues(mp->dev);
2358 netif_tx_wake_all_queues(mp->dev);
2362 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2364 struct mv643xx_eth_private *mp = netdev_priv(dev);
2366 netdev_info(dev, "tx timeout\n");
2368 schedule_work(&mp->tx_timeout_task);
2371 #ifdef CONFIG_NET_POLL_CONTROLLER
2372 static void mv643xx_eth_netpoll(struct net_device *dev)
2374 struct mv643xx_eth_private *mp = netdev_priv(dev);
2376 wrlp(mp, INT_MASK, 0x00000000);
2379 mv643xx_eth_irq(dev->irq, dev);
2381 wrlp(mp, INT_MASK, mp->int_mask);
2386 /* platform glue ************************************************************/
2388 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2389 const struct mbus_dram_target_info *dram)
2391 void __iomem *base = msp->base;
2396 for (i = 0; i < 6; i++) {
2397 writel(0, base + WINDOW_BASE(i));
2398 writel(0, base + WINDOW_SIZE(i));
2400 writel(0, base + WINDOW_REMAP_HIGH(i));
2406 for (i = 0; i < dram->num_cs; i++) {
2407 const struct mbus_dram_window *cs = dram->cs + i;
2409 writel((cs->base & 0xffff0000) |
2410 (cs->mbus_attr << 8) |
2411 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2412 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2414 win_enable &= ~(1 << i);
2415 win_protect |= 3 << (2 * i);
2418 writel(win_enable, base + WINDOW_BAR_ENABLE);
2419 msp->win_protect = win_protect;
2422 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2425 * Check whether we have a 14-bit coal limit field in bits
2426 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2427 * SDMA config register.
2429 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2430 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2431 msp->extended_rx_coal_limit = 1;
2433 msp->extended_rx_coal_limit = 0;
2436 * Check whether the MAC supports TX rate control, and if
2437 * yes, whether its associated registers are in the old or
2440 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2441 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2442 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2444 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2445 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2446 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2448 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2452 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2454 static int mv643xx_eth_version_printed;
2455 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2456 struct mv643xx_eth_shared_private *msp;
2457 const struct mbus_dram_target_info *dram;
2458 struct resource *res;
2460 if (!mv643xx_eth_version_printed++)
2461 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2462 mv643xx_eth_driver_version);
2464 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2468 msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
2472 msp->base = ioremap(res->start, resource_size(res));
2473 if (msp->base == NULL)
2476 msp->clk = devm_clk_get(&pdev->dev, NULL);
2477 if (!IS_ERR(msp->clk))
2478 clk_prepare_enable(msp->clk);
2481 * (Re-)program MBUS remapping windows if we are asked to.
2483 dram = mv_mbus_dram_info();
2485 mv643xx_eth_conf_mbus_windows(msp, dram);
2487 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2488 pd->tx_csum_limit : 9 * 1024;
2489 infer_hw_params(msp);
2491 platform_set_drvdata(pdev, msp);
2496 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2498 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2501 if (!IS_ERR(msp->clk))
2502 clk_disable_unprepare(msp->clk);
2507 static struct platform_driver mv643xx_eth_shared_driver = {
2508 .probe = mv643xx_eth_shared_probe,
2509 .remove = mv643xx_eth_shared_remove,
2511 .name = MV643XX_ETH_SHARED_NAME,
2512 .owner = THIS_MODULE,
2516 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2518 int addr_shift = 5 * mp->port_num;
2521 data = rdl(mp, PHY_ADDR);
2522 data &= ~(0x1f << addr_shift);
2523 data |= (phy_addr & 0x1f) << addr_shift;
2524 wrl(mp, PHY_ADDR, data);
2527 static int phy_addr_get(struct mv643xx_eth_private *mp)
2531 data = rdl(mp, PHY_ADDR);
2533 return (data >> (5 * mp->port_num)) & 0x1f;
2536 static void set_params(struct mv643xx_eth_private *mp,
2537 struct mv643xx_eth_platform_data *pd)
2539 struct net_device *dev = mp->dev;
2541 if (is_valid_ether_addr(pd->mac_addr))
2542 memcpy(dev->dev_addr, pd->mac_addr, 6);
2544 uc_addr_get(mp, dev->dev_addr);
2546 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2547 if (pd->rx_queue_size)
2548 mp->rx_ring_size = pd->rx_queue_size;
2549 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2550 mp->rx_desc_sram_size = pd->rx_sram_size;
2552 mp->rxq_count = pd->rx_queue_count ? : 1;
2554 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2555 if (pd->tx_queue_size)
2556 mp->tx_ring_size = pd->tx_queue_size;
2557 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2558 mp->tx_desc_sram_size = pd->tx_sram_size;
2560 mp->txq_count = pd->tx_queue_count ? : 1;
2563 static void mv643xx_eth_adjust_link(struct net_device *dev)
2565 struct mv643xx_eth_private *mp = netdev_priv(dev);
2567 mv643xx_adjust_pscr(mp);
2570 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2573 struct phy_device *phydev;
2577 char phy_id[MII_BUS_ID_SIZE + 3];
2579 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2580 start = phy_addr_get(mp) & 0x1f;
2583 start = phy_addr & 0x1f;
2587 /* Attempt to connect to the PHY using orion-mdio */
2588 phydev = ERR_PTR(-ENODEV);
2589 for (i = 0; i < num; i++) {
2590 int addr = (start + i) & 0x1f;
2592 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2593 "orion-mdio-mii", addr);
2595 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link,
2596 PHY_INTERFACE_MODE_GMII);
2597 if (!IS_ERR(phydev)) {
2598 phy_addr_set(mp, addr);
2606 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2608 struct phy_device *phy = mp->phy;
2613 phy->autoneg = AUTONEG_ENABLE;
2616 phy->advertising = phy->supported | ADVERTISED_Autoneg;
2618 phy->autoneg = AUTONEG_DISABLE;
2619 phy->advertising = 0;
2621 phy->duplex = duplex;
2623 phy_start_aneg(phy);
2626 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2630 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2631 if (pscr & SERIAL_PORT_ENABLE) {
2632 pscr &= ~SERIAL_PORT_ENABLE;
2633 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2636 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2637 if (mp->phy == NULL) {
2638 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2639 if (speed == SPEED_1000)
2640 pscr |= SET_GMII_SPEED_TO_1000;
2641 else if (speed == SPEED_100)
2642 pscr |= SET_MII_SPEED_TO_100;
2644 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2646 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2647 if (duplex == DUPLEX_FULL)
2648 pscr |= SET_FULL_DUPLEX_MODE;
2651 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2654 static const struct net_device_ops mv643xx_eth_netdev_ops = {
2655 .ndo_open = mv643xx_eth_open,
2656 .ndo_stop = mv643xx_eth_stop,
2657 .ndo_start_xmit = mv643xx_eth_xmit,
2658 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2659 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
2660 .ndo_validate_addr = eth_validate_addr,
2661 .ndo_do_ioctl = mv643xx_eth_ioctl,
2662 .ndo_change_mtu = mv643xx_eth_change_mtu,
2663 .ndo_set_features = mv643xx_eth_set_features,
2664 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2665 .ndo_get_stats = mv643xx_eth_get_stats,
2666 #ifdef CONFIG_NET_POLL_CONTROLLER
2667 .ndo_poll_controller = mv643xx_eth_netpoll,
2671 static int mv643xx_eth_probe(struct platform_device *pdev)
2673 struct mv643xx_eth_platform_data *pd;
2674 struct mv643xx_eth_private *mp;
2675 struct net_device *dev;
2676 struct resource *res;
2679 pd = pdev->dev.platform_data;
2681 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
2685 if (pd->shared == NULL) {
2686 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
2690 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2694 mp = netdev_priv(dev);
2695 platform_set_drvdata(pdev, mp);
2697 mp->shared = platform_get_drvdata(pd->shared);
2698 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
2699 mp->port_num = pd->port_number;
2704 * Start with a default rate, and if there is a clock, allow
2705 * it to override the default.
2707 mp->t_clk = 133000000;
2708 mp->clk = devm_clk_get(&pdev->dev, NULL);
2709 if (!IS_ERR(mp->clk)) {
2710 clk_prepare_enable(mp->clk);
2711 mp->t_clk = clk_get_rate(mp->clk);
2715 netif_set_real_num_tx_queues(dev, mp->txq_count);
2716 netif_set_real_num_rx_queues(dev, mp->rxq_count);
2718 if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
2719 mp->phy = phy_scan(mp, pd->phy_addr);
2721 if (IS_ERR(mp->phy)) {
2722 err = PTR_ERR(mp->phy);
2724 err = -EPROBE_DEFER;
2727 phy_init(mp, pd->speed, pd->duplex);
2730 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2732 init_pscr(mp, pd->speed, pd->duplex);
2735 mib_counters_clear(mp);
2737 init_timer(&mp->mib_counters_timer);
2738 mp->mib_counters_timer.data = (unsigned long)mp;
2739 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2740 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2742 spin_lock_init(&mp->mib_counters_lock);
2744 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2746 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT);
2748 init_timer(&mp->rx_oom);
2749 mp->rx_oom.data = (unsigned long)mp;
2750 mp->rx_oom.function = oom_timer_wrapper;
2753 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2755 dev->irq = res->start;
2757 dev->netdev_ops = &mv643xx_eth_netdev_ops;
2759 dev->watchdog_timeo = 2 * HZ;
2762 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
2763 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
2764 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2766 dev->priv_flags |= IFF_UNICAST_FLT;
2768 SET_NETDEV_DEV(dev, &pdev->dev);
2770 if (mp->shared->win_protect)
2771 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2773 netif_carrier_off(dev);
2775 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2777 set_rx_coal(mp, 250);
2780 err = register_netdev(dev);
2784 netdev_notice(dev, "port %d with MAC address %pM\n",
2785 mp->port_num, dev->dev_addr);
2787 if (mp->tx_desc_sram_size > 0)
2788 netdev_notice(dev, "configured with sram\n");
2793 if (!IS_ERR(mp->clk))
2794 clk_disable_unprepare(mp->clk);
2800 static int mv643xx_eth_remove(struct platform_device *pdev)
2802 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2804 unregister_netdev(mp->dev);
2805 if (mp->phy != NULL)
2806 phy_detach(mp->phy);
2807 cancel_work_sync(&mp->tx_timeout_task);
2809 if (!IS_ERR(mp->clk))
2810 clk_disable_unprepare(mp->clk);
2812 free_netdev(mp->dev);
2814 platform_set_drvdata(pdev, NULL);
2819 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2821 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2823 /* Mask all interrupts on ethernet port */
2824 wrlp(mp, INT_MASK, 0);
2827 if (netif_running(mp->dev))
2831 static struct platform_driver mv643xx_eth_driver = {
2832 .probe = mv643xx_eth_probe,
2833 .remove = mv643xx_eth_remove,
2834 .shutdown = mv643xx_eth_shutdown,
2836 .name = MV643XX_ETH_NAME,
2837 .owner = THIS_MODULE,
2841 static int __init mv643xx_eth_init_module(void)
2845 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2847 rc = platform_driver_register(&mv643xx_eth_driver);
2849 platform_driver_unregister(&mv643xx_eth_shared_driver);
2854 module_init(mv643xx_eth_init_module);
2856 static void __exit mv643xx_eth_cleanup_module(void)
2858 platform_driver_unregister(&mv643xx_eth_driver);
2859 platform_driver_unregister(&mv643xx_eth_shared_driver);
2861 module_exit(mv643xx_eth_cleanup_module);
2863 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2864 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2865 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2866 MODULE_LICENSE("GPL");
2867 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2868 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);