drivers/mtd/nand/atmel_nand.c

   1 /*
   2  *  Copyright © 2003 Rick Bronson
   3  *
   4  *  Derived from drivers/mtd/nand/autcpu12.c
   5  *       Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
   6  *
   7  *  Derived from drivers/mtd/spia.c
   8  *       Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
   9  *
  10  *
  11  *  Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
  12  *     Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
  13  *
  14  *     Derived from Das U-Boot source code
  15  *              (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
  16  *     © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
  17  *
  18  *  Add Programmable Multibit ECC support for various AT91 SoC
  19  *     © Copyright 2012 ATMEL, Hong Xu
  20  *
  21  * This program is free software; you can redistribute it and/or modify
  22  * it under the terms of the GNU General Public License version 2 as
  23  * published by the Free Software Foundation.
  24  *
  25  */
  26
  27 #include <linux/dma-mapping.h>
  28 #include <linux/slab.h>
  29 #include <linux/module.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/of.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_gpio.h>
  35 #include <linux/of_mtd.h>
  36 #include <linux/mtd/mtd.h>
  37 #include <linux/mtd/nand.h>
  38 #include <linux/mtd/partitions.h>
  39
  40 #include <linux/dmaengine.h>
  41 #include <linux/gpio.h>
  42 #include <linux/io.h>
  43 #include <linux/platform_data/atmel.h>
  44 #include <linux/pinctrl/consumer.h>
  45
  46 #include <mach/cpu.h>
  47
  48 static int use_dma = 1;
  49 module_param(use_dma, int, 0);
  50
  51 static int on_flash_bbt = 0;
  52 module_param(on_flash_bbt, int, 0);
  53
  54 /* Register access macros */
  55 #define ecc_readl(add, reg)                             \
  56         __raw_readl(add + ATMEL_ECC_##reg)
  57 #define ecc_writel(add, reg, value)                     \
  58         __raw_writel((value), add + ATMEL_ECC_##reg)
  59
  60 #include "atmel_nand_ecc.h"     /* Hardware ECC registers */
  61
  62 /* oob layout for large page size
  63  * bad block info is on bytes 0 and 1
  64  * the bytes have to be consecutives to avoid
  65  * several NAND_CMD_RNDOUT during read
  66  */
  67 static struct nand_ecclayout atmel_oobinfo_large = {
  68         .eccbytes = 4,
  69         .eccpos = {60, 61, 62, 63},
  70         .oobfree = {
  71                 {2, 58}
  72         },
  73 };
  74
  75 /* oob layout for small page size
  76  * bad block info is on bytes 4 and 5
  77  * the bytes have to be consecutives to avoid
  78  * several NAND_CMD_RNDOUT during read
  79  */
  80 static struct nand_ecclayout atmel_oobinfo_small = {
  81         .eccbytes = 4,
  82         .eccpos = {0, 1, 2, 3},
  83         .oobfree = {
  84                 {6, 10}
  85         },
  86 };
  87
  88 struct atmel_nand_host {
  89         struct nand_chip        nand_chip;
  90         struct mtd_info         mtd;
  91         void __iomem            *io_base;
  92         dma_addr_t              io_phys;
  93         struct atmel_nand_data  board;
  94         struct device           *dev;
  95         void __iomem            *ecc;
  96
  97         struct completion       comp;
  98         struct dma_chan         *dma_chan;
  99
 100         bool                    has_pmecc;
 101         u8                      pmecc_corr_cap;
 102         u16                     pmecc_sector_size;
 103         u32                     pmecc_lookup_table_offset;
 104         u32                     pmecc_lookup_table_offset_512;
 105         u32                     pmecc_lookup_table_offset_1024;
 106
 107         int                     pmecc_bytes_per_sector;
 108         int                     pmecc_sector_number;
 109         int                     pmecc_degree;   /* Degree of remainders */
 110         int                     pmecc_cw_len;   /* Length of codeword */
 111
 112         void __iomem            *pmerrloc_base;
 113         void __iomem            *pmecc_rom_base;
 114
 115         /* lookup table for alpha_to and index_of */
 116         void __iomem            *pmecc_alpha_to;
 117         void __iomem            *pmecc_index_of;
 118
 119         /* data for pmecc computation */
 120         int16_t                 *pmecc_partial_syn;
 121         int16_t                 *pmecc_si;
 122         int16_t                 *pmecc_smu;     /* Sigma table */
 123         int16_t                 *pmecc_lmu;     /* polynomal order */
 124         int                     *pmecc_mu;
 125         int                     *pmecc_dmu;
 126         int                     *pmecc_delta;
 127 };
 128
 129 static struct nand_ecclayout atmel_pmecc_oobinfo;
 130
 131 static int cpu_has_dma(void)
 132 {
 133         return cpu_is_at91sam9rl() || cpu_is_at91sam9g45();
 134 }
 135
 136 /*
 137  * Enable NAND.
 138  */
 139 static void atmel_nand_enable(struct atmel_nand_host *host)
 140 {
 141         if (gpio_is_valid(host->board.enable_pin))
 142                 gpio_set_value(host->board.enable_pin, 0);
 143 }
 144
 145 /*
 146  * Disable NAND.
 147  */
 148 static void atmel_nand_disable(struct atmel_nand_host *host)
 149 {
 150         if (gpio_is_valid(host->board.enable_pin))
 151                 gpio_set_value(host->board.enable_pin, 1);
 152 }
 153
 154 /*
 155  * Hardware specific access to control-lines
 156  */
 157 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 158 {
 159         struct nand_chip *nand_chip = mtd->priv;
 160         struct atmel_nand_host *host = nand_chip->priv;
 161
 162         if (ctrl & NAND_CTRL_CHANGE) {
 163                 if (ctrl & NAND_NCE)
 164                         atmel_nand_enable(host);
 165                 else
 166                         atmel_nand_disable(host);
 167         }
 168         if (cmd == NAND_CMD_NONE)
 169                 return;
 170
 171         if (ctrl & NAND_CLE)
 172                 writeb(cmd, host->io_base + (1 << host->board.cle));
 173         else
 174                 writeb(cmd, host->io_base + (1 << host->board.ale));
 175 }
 176
 177 /*
 178  * Read the Device Ready pin.
 179  */
 180 static int atmel_nand_device_ready(struct mtd_info *mtd)
 181 {
 182         struct nand_chip *nand_chip = mtd->priv;
 183         struct atmel_nand_host *host = nand_chip->priv;
 184
 185         return gpio_get_value(host->board.rdy_pin) ^
 186                 !!host->board.rdy_pin_active_low;
 187 }
 188
 189 /*
 190  * Minimal-overhead PIO for data access.
 191  */
 192 static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
 193 {
 194         struct nand_chip        *nand_chip = mtd->priv;
 195
 196         __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
 197 }
 198
 199 static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
 200 {
 201         struct nand_chip        *nand_chip = mtd->priv;
 202
 203         __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
 204 }
 205
 206 static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
 207 {
 208         struct nand_chip        *nand_chip = mtd->priv;
 209
 210         __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
 211 }
 212
 213 static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
 214 {
 215         struct nand_chip        *nand_chip = mtd->priv;
 216
 217         __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
 218 }
 219
 220 static void dma_complete_func(void *completion)
 221 {
 222         complete(completion);
 223 }
 224
 225 static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
 226                                int is_read)
 227 {
 228         struct dma_device *dma_dev;
 229         enum dma_ctrl_flags flags;
 230         dma_addr_t dma_src_addr, dma_dst_addr, phys_addr;
 231         struct dma_async_tx_descriptor *tx = NULL;
 232         dma_cookie_t cookie;
 233         struct nand_chip *chip = mtd->priv;
 234         struct atmel_nand_host *host = chip->priv;
 235         void *p = buf;
 236         int err = -EIO;
 237         enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
 238
 239         if (buf >= high_memory)
 240                 goto err_buf;
 241
 242         dma_dev = host->dma_chan->device;
 243
 244         flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_SRC_UNMAP |
 245                 DMA_COMPL_SKIP_DEST_UNMAP;
 246
 247         phys_addr = dma_map_single(dma_dev->dev, p, len, dir);
 248         if (dma_mapping_error(dma_dev->dev, phys_addr)) {
 249                 dev_err(host->dev, "Failed to dma_map_single\n");
 250                 goto err_buf;
 251         }
 252
 253         if (is_read) {
 254                 dma_src_addr = host->io_phys;
 255                 dma_dst_addr = phys_addr;
 256         } else {
 257                 dma_src_addr = phys_addr;
 258                 dma_dst_addr = host->io_phys;
 259         }
 260
 261         tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr,
 262                                              dma_src_addr, len, flags);
 263         if (!tx) {
 264                 dev_err(host->dev, "Failed to prepare DMA memcpy\n");
 265                 goto err_dma;
 266         }
 267
 268         init_completion(&host->comp);
 269         tx->callback = dma_complete_func;
 270         tx->callback_param = &host->comp;
 271
 272         cookie = tx->tx_submit(tx);
 273         if (dma_submit_error(cookie)) {
 274                 dev_err(host->dev, "Failed to do DMA tx_submit\n");
 275                 goto err_dma;
 276         }
 277
 278         dma_async_issue_pending(host->dma_chan);
 279         wait_for_completion(&host->comp);
 280
 281         err = 0;
 282
 283 err_dma:
 284         dma_unmap_single(dma_dev->dev, phys_addr, len, dir);
 285 err_buf:
 286         if (err != 0)
 287                 dev_warn(host->dev, "Fall back to CPU I/O\n");
 288         return err;
 289 }
 290
 291 static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 292 {
 293         struct nand_chip *chip = mtd->priv;
 294         struct atmel_nand_host *host = chip->priv;
 295
 296         if (use_dma && len > mtd->oobsize)
 297                 /* only use DMA for bigger than oob size: better performances */
 298                 if (atmel_nand_dma_op(mtd, buf, len, 1) == 0)
 299                         return;
 300
 301         if (host->board.bus_width_16)
 302                 atmel_read_buf16(mtd, buf, len);
 303         else
 304                 atmel_read_buf8(mtd, buf, len);
 305 }
 306
 307 static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 308 {
 309         struct nand_chip *chip = mtd->priv;
 310         struct atmel_nand_host *host = chip->priv;
 311
 312         if (use_dma && len > mtd->oobsize)
 313                 /* only use DMA for bigger than oob size: better performances */
 314                 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0)
 315                         return;
 316
 317         if (host->board.bus_width_16)
 318                 atmel_write_buf16(mtd, buf, len);
 319         else
 320                 atmel_write_buf8(mtd, buf, len);
 321 }
 322
 323 /*
 324  * Return number of ecc bytes per sector according to sector size and
 325  * correction capability
 326  *
 327  * Following table shows what at91 PMECC supported:
 328  * Correction Capability        Sector_512_bytes        Sector_1024_bytes
 329  * =====================        ================        =================
 330  *                2-bits                 4-bytes                  4-bytes
 331  *                4-bits                 7-bytes                  7-bytes
 332  *                8-bits                13-bytes                 14-bytes
 333  *               12-bits                20-bytes                 21-bytes
 334  *               24-bits                39-bytes                 42-bytes
 335  */
 336 static int pmecc_get_ecc_bytes(int cap, int sector_size)
 337 {
 338         int m = 12 + sector_size / 512;
 339         return (m * cap + 7) / 8;
 340 }
 341
 342 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
 343                                     int oobsize, int ecc_len)
 344 {
 345         int i;
 346
 347         layout->eccbytes = ecc_len;
 348
 349         /* ECC will occupy the last ecc_len bytes continuously */
 350         for (i = 0; i < ecc_len; i++)
 351                 layout->eccpos[i] = oobsize - ecc_len + i;
 352
 353         layout->oobfree[0].offset = 2;
 354         layout->oobfree[0].length =
 355                 oobsize - ecc_len - layout->oobfree[0].offset;
 356 }
 357
 358 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
 359 {
 360         int table_size;
 361
 362         table_size = host->pmecc_sector_size == 512 ?
 363                 PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024;
 364
 365         return host->pmecc_rom_base + host->pmecc_lookup_table_offset +
 366                         table_size * sizeof(int16_t);
 367 }
 368
 369 static void pmecc_data_free(struct atmel_nand_host *host)
 370 {
 371         kfree(host->pmecc_partial_syn);
 372         kfree(host->pmecc_si);
 373         kfree(host->pmecc_lmu);
 374         kfree(host->pmecc_smu);
 375         kfree(host->pmecc_mu);
 376         kfree(host->pmecc_dmu);
 377         kfree(host->pmecc_delta);
 378 }
 379
 380 static int pmecc_data_alloc(struct atmel_nand_host *host)
 381 {
 382         const int cap = host->pmecc_corr_cap;
 383
 384         host->pmecc_partial_syn = kzalloc((2 * cap + 1) * sizeof(int16_t),
 385                                         GFP_KERNEL);
 386         host->pmecc_si = kzalloc((2 * cap + 1) * sizeof(int16_t), GFP_KERNEL);
 387         host->pmecc_lmu = kzalloc((cap + 1) * sizeof(int16_t), GFP_KERNEL);
 388         host->pmecc_smu = kzalloc((cap + 2) * (2 * cap + 1) * sizeof(int16_t),
 389                                         GFP_KERNEL);
 390         host->pmecc_mu = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL);
 391         host->pmecc_dmu = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL);
 392         host->pmecc_delta = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL);
 393
 394         if (host->pmecc_partial_syn &&
 395                         host->pmecc_si &&
 396                         host->pmecc_lmu &&
 397                         host->pmecc_smu &&
 398                         host->pmecc_mu &&
 399                         host->pmecc_dmu &&
 400                         host->pmecc_delta)
 401                 return 0;
 402
 403         /* error happened */
 404         pmecc_data_free(host);
 405         return -ENOMEM;
 406 }
 407
 408 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
 409 {
 410         struct nand_chip *nand_chip = mtd->priv;
 411         struct atmel_nand_host *host = nand_chip->priv;
 412         int i;
 413         uint32_t value;
 414
 415         /* Fill odd syndromes */
 416         for (i = 0; i < host->pmecc_corr_cap; i++) {
 417                 value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2);
 418                 if (i & 1)
 419                         value >>= 16;
 420                 value &= 0xffff;
 421                 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
 422         }
 423 }
 424
 425 static void pmecc_substitute(struct mtd_info *mtd)
 426 {
 427         struct nand_chip *nand_chip = mtd->priv;
 428         struct atmel_nand_host *host = nand_chip->priv;
 429         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
 430         int16_t __iomem *index_of = host->pmecc_index_of;
 431         int16_t *partial_syn = host->pmecc_partial_syn;
 432         const int cap = host->pmecc_corr_cap;
 433         int16_t *si;
 434         int i, j;
 435
 436         /* si[] is a table that holds the current syndrome value,
 437          * an element of that table belongs to the field
 438          */
 439         si = host->pmecc_si;
 440
 441         memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
 442
 443         /* Computation 2t syndromes based on S(x) */
 444         /* Odd syndromes */
 445         for (i = 1; i < 2 * cap; i += 2) {
 446                 for (j = 0; j < host->pmecc_degree; j++) {
 447                         if (partial_syn[i] & ((unsigned short)0x1 << j))
 448                                 si[i] = readw_relaxed(alpha_to + i * j) ^ si[i];
 449                 }
 450         }
 451         /* Even syndrome = (Odd syndrome) ** 2 */
 452         for (i = 2, j = 1; j <= cap; i = ++j << 1) {
 453                 if (si[j] == 0) {
 454                         si[i] = 0;
 455                 } else {
 456                         int16_t tmp;
 457
 458                         tmp = readw_relaxed(index_of + si[j]);
 459                         tmp = (tmp * 2) % host->pmecc_cw_len;
 460                         si[i] = readw_relaxed(alpha_to + tmp);
 461                 }
 462         }
 463
 464         return;
 465 }
 466
 467 static void pmecc_get_sigma(struct mtd_info *mtd)
 468 {
 469         struct nand_chip *nand_chip = mtd->priv;
 470         struct atmel_nand_host *host = nand_chip->priv;
 471
 472         int16_t *lmu = host->pmecc_lmu;
 473         int16_t *si = host->pmecc_si;
 474         int *mu = host->pmecc_mu;
 475         int *dmu = host->pmecc_dmu;     /* Discrepancy */
 476         int *delta = host->pmecc_delta; /* Delta order */
 477         int cw_len = host->pmecc_cw_len;
 478         const int16_t cap = host->pmecc_corr_cap;
 479         const int num = 2 * cap + 1;
 480         int16_t __iomem *index_of = host->pmecc_index_of;
 481         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
 482         int i, j, k;
 483         uint32_t dmu_0_count, tmp;
 484         int16_t *smu = host->pmecc_smu;
 485
 486         /* index of largest delta */
 487         int ro;
 488         int largest;
 489         int diff;
 490
 491         dmu_0_count = 0;
 492
 493         /* First Row */
 494
 495         /* Mu */
 496         mu[0] = -1;
 497
 498         memset(smu, 0, sizeof(int16_t) * num);
 499         smu[0] = 1;
 500
 501         /* discrepancy set to 1 */
 502         dmu[0] = 1;
 503         /* polynom order set to 0 */
 504         lmu[0] = 0;
 505         delta[0] = (mu[0] * 2 - lmu[0]) >> 1;
 506
 507         /* Second Row */
 508
 509         /* Mu */
 510         mu[1] = 0;
 511         /* Sigma(x) set to 1 */
 512         memset(&smu[num], 0, sizeof(int16_t) * num);
 513         smu[num] = 1;
 514
 515         /* discrepancy set to S1 */
 516         dmu[1] = si[1];
 517
 518         /* polynom order set to 0 */
 519         lmu[1] = 0;
 520
 521         delta[1] = (mu[1] * 2 - lmu[1]) >> 1;
 522
 523         /* Init the Sigma(x) last row */
 524         memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num);
 525
 526         for (i = 1; i <= cap; i++) {
 527                 mu[i + 1] = i << 1;
 528                 /* Begin Computing Sigma (Mu+1) and L(mu) */
 529                 /* check if discrepancy is set to 0 */
 530                 if (dmu[i] == 0) {
 531                         dmu_0_count++;
 532
 533                         tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
 534                         if ((cap - (lmu[i] >> 1) - 1) & 0x1)
 535                                 tmp += 2;
 536                         else
 537                                 tmp += 1;
 538
 539                         if (dmu_0_count == tmp) {
 540                                 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
 541                                         smu[(cap + 1) * num + j] =
 542                                                         smu[i * num + j];
 543
 544                                 lmu[cap + 1] = lmu[i];
 545                                 return;
 546                         }
 547
 548                         /* copy polynom */
 549                         for (j = 0; j <= lmu[i] >> 1; j++)
 550                                 smu[(i + 1) * num + j] = smu[i * num + j];
 551
 552                         /* copy previous polynom order to the next */
 553                         lmu[i + 1] = lmu[i];
 554                 } else {
 555                         ro = 0;
 556                         largest = -1;
 557                         /* find largest delta with dmu != 0 */
 558                         for (j = 0; j < i; j++) {
 559                                 if ((dmu[j]) && (delta[j] > largest)) {
 560                                         largest = delta[j];
 561                                         ro = j;
 562                                 }
 563                         }
 564
 565                         /* compute difference */
 566                         diff = (mu[i] - mu[ro]);
 567
 568                         /* Compute degree of the new smu polynomial */
 569                         if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
 570                                 lmu[i + 1] = lmu[i];
 571                         else
 572                                 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
 573
 574                         /* Init smu[i+1] with 0 */
 575                         for (k = 0; k < num; k++)
 576                                 smu[(i + 1) * num + k] = 0;
 577
 578                         /* Compute smu[i+1] */
 579                         for (k = 0; k <= lmu[ro] >> 1; k++) {
 580                                 int16_t a, b, c;
 581
 582                                 if (!(smu[ro * num + k] && dmu[i]))
 583                                         continue;
 584                                 a = readw_relaxed(index_of + dmu[i]);
 585                                 b = readw_relaxed(index_of + dmu[ro]);
 586                                 c = readw_relaxed(index_of + smu[ro * num + k]);
 587                                 tmp = a + (cw_len - b) + c;
 588                                 a = readw_relaxed(alpha_to + tmp % cw_len);
 589                                 smu[(i + 1) * num + (k + diff)] = a;
 590                         }
 591
 592                         for (k = 0; k <= lmu[i] >> 1; k++)
 593                                 smu[(i + 1) * num + k] ^= smu[i * num + k];
 594                 }
 595
 596                 /* End Computing Sigma (Mu+1) and L(mu) */
 597                 /* In either case compute delta */
 598                 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
 599
 600                 /* Do not compute discrepancy for the last iteration */
 601                 if (i >= cap)
 602                         continue;
 603
 604                 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
 605                         tmp = 2 * (i - 1);
 606                         if (k == 0) {
 607                                 dmu[i + 1] = si[tmp + 3];
 608                         } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
 609                                 int16_t a, b, c;
 610                                 a = readw_relaxed(index_of +
 611                                                 smu[(i + 1) * num + k]);
 612                                 b = si[2 * (i - 1) + 3 - k];
 613                                 c = readw_relaxed(index_of + b);
 614                                 tmp = a + c;
 615                                 tmp %= cw_len;
 616                                 dmu[i + 1] = readw_relaxed(alpha_to + tmp) ^
 617                                         dmu[i + 1];
 618                         }
 619                 }
 620         }
 621
 622         return;
 623 }
 624
 625 static int pmecc_err_location(struct mtd_info *mtd)
 626 {
 627         struct nand_chip *nand_chip = mtd->priv;
 628         struct atmel_nand_host *host = nand_chip->priv;
 629         unsigned long end_time;
 630         const int cap = host->pmecc_corr_cap;
 631         const int num = 2 * cap + 1;
 632         int sector_size = host->pmecc_sector_size;
 633         int err_nbr = 0;        /* number of error */
 634         int roots_nbr;          /* number of roots */
 635         int i;
 636         uint32_t val;
 637         int16_t *smu = host->pmecc_smu;
 638
 639         pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE);
 640
 641         for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
 642                 pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i,
 643                                       smu[(cap + 1) * num + i]);
 644                 err_nbr++;
 645         }
 646
 647         val = (err_nbr - 1) << 16;
 648         if (sector_size == 1024)
 649                 val |= 1;
 650
 651         pmerrloc_writel(host->pmerrloc_base, ELCFG, val);
 652         pmerrloc_writel(host->pmerrloc_base, ELEN,
 653                         sector_size * 8 + host->pmecc_degree * cap);
 654
 655         end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
 656         while (!(pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
 657                  & PMERRLOC_CALC_DONE)) {
 658                 if (unlikely(time_after(jiffies, end_time))) {
 659                         dev_err(host->dev, "PMECC: Timeout to calculate error location.\n");
 660                         return -1;
 661                 }
 662                 cpu_relax();
 663         }
 664
 665         roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
 666                 & PMERRLOC_ERR_NUM_MASK) >> 8;
 667         /* Number of roots == degree of smu hence <= cap */
 668         if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
 669                 return err_nbr - 1;
 670
 671         /* Number of roots does not match the degree of smu
 672          * unable to correct error */
 673         return -1;
 674 }
 675
 676 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 677                 int sector_num, int extra_bytes, int err_nbr)
 678 {
 679         struct nand_chip *nand_chip = mtd->priv;
 680         struct atmel_nand_host *host = nand_chip->priv;
 681         int i = 0;
 682         int byte_pos, bit_pos, sector_size, pos;
 683         uint32_t tmp;
 684         uint8_t err_byte;
 685
 686         sector_size = host->pmecc_sector_size;
 687
 688         while (err_nbr) {
 689                 tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1;
 690                 byte_pos = tmp / 8;
 691                 bit_pos  = tmp % 8;
 692
 693                 if (byte_pos >= (sector_size + extra_bytes))
 694                         BUG();  /* should never happen */
 695
 696                 if (byte_pos < sector_size) {
 697                         err_byte = *(buf + byte_pos);
 698                         *(buf + byte_pos) ^= (1 << bit_pos);
 699
 700                         pos = sector_num * host->pmecc_sector_size + byte_pos;
 701                         dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 702                                 pos, bit_pos, err_byte, *(buf + byte_pos));
 703                 } else {
 704                         /* Bit flip in OOB area */
 705                         tmp = sector_num * host->pmecc_bytes_per_sector
 706                                         + (byte_pos - sector_size);
 707                         err_byte = ecc[tmp];
 708                         ecc[tmp] ^= (1 << bit_pos);
 709
 710                         pos = tmp + nand_chip->ecc.layout->eccpos[0];
 711                         dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 712                                 pos, bit_pos, err_byte, ecc[tmp]);
 713                 }
 714
 715                 i++;
 716                 err_nbr--;
 717         }
 718
 719         return;
 720 }
 721
 722 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
 723         u8 *ecc)
 724 {
 725         struct nand_chip *nand_chip = mtd->priv;
 726         struct atmel_nand_host *host = nand_chip->priv;
 727         int i, err_nbr, eccbytes;
 728         uint8_t *buf_pos;
 729         int total_err = 0;
 730
 731         eccbytes = nand_chip->ecc.bytes;
 732         for (i = 0; i < eccbytes; i++)
 733                 if (ecc[i] != 0xff)
 734                         goto normal_check;
 735         /* Erased page, return OK */
 736         return 0;
 737
 738 normal_check:
 739         for (i = 0; i < host->pmecc_sector_number; i++) {
 740                 err_nbr = 0;
 741                 if (pmecc_stat & 0x1) {
 742                         buf_pos = buf + i * host->pmecc_sector_size;
 743
 744                         pmecc_gen_syndrome(mtd, i);
 745                         pmecc_substitute(mtd);
 746                         pmecc_get_sigma(mtd);
 747
 748                         err_nbr = pmecc_err_location(mtd);
 749                         if (err_nbr == -1) {
 750                                 dev_err(host->dev, "PMECC: Too many errors\n");
 751                                 mtd->ecc_stats.failed++;
 752                                 return -EIO;
 753                         } else {
 754                                 pmecc_correct_data(mtd, buf_pos, ecc, i,
 755                                         host->pmecc_bytes_per_sector, err_nbr);
 756                                 mtd->ecc_stats.corrected += err_nbr;
 757                                 total_err += err_nbr;
 758                         }
 759                 }
 760                 pmecc_stat >>= 1;
 761         }
 762
 763         return total_err;
 764 }
 765
 766 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 767         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 768 {
 769         struct atmel_nand_host *host = chip->priv;
 770         int eccsize = chip->ecc.size;
 771         uint8_t *oob = chip->oob_poi;
 772         uint32_t *eccpos = chip->ecc.layout->eccpos;
 773         uint32_t stat;
 774         unsigned long end_time;
 775         int bitflips = 0;
 776
 777         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
 778         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
 779         pmecc_writel(host->ecc, CFG, (pmecc_readl_relaxed(host->ecc, CFG)
 780                 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
 781
 782         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
 783         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
 784
 785         chip->read_buf(mtd, buf, eccsize);
 786         chip->read_buf(mtd, oob, mtd->oobsize);
 787
 788         end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
 789         while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
 790                 if (unlikely(time_after(jiffies, end_time))) {
 791                         dev_err(host->dev, "PMECC: Timeout to get error status.\n");
 792                         return -EIO;
 793                 }
 794                 cpu_relax();
 795         }
 796
 797         stat = pmecc_readl_relaxed(host->ecc, ISR);
 798         if (stat != 0) {
 799                 bitflips = pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]);
 800                 if (bitflips < 0)
 801                         /* uncorrectable errors */
 802                         return 0;
 803         }
 804
 805         return bitflips;
 806 }
 807
 808 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
 809                 struct nand_chip *chip, const uint8_t *buf, int oob_required)
 810 {
 811         struct atmel_nand_host *host = chip->priv;
 812         uint32_t *eccpos = chip->ecc.layout->eccpos;
 813         int i, j;
 814         unsigned long end_time;
 815
 816         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
 817         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
 818
 819         pmecc_writel(host->ecc, CFG, (pmecc_readl_relaxed(host->ecc, CFG) |
 820                 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
 821
 822         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
 823         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
 824
 825         chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
 826
 827         end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
 828         while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
 829                 if (unlikely(time_after(jiffies, end_time))) {
 830                         dev_err(host->dev, "PMECC: Timeout to get ECC value.\n");
 831                         return -EIO;
 832                 }
 833                 cpu_relax();
 834         }
 835
 836         for (i = 0; i < host->pmecc_sector_number; i++) {
 837                 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
 838                         int pos;
 839
 840                         pos = i * host->pmecc_bytes_per_sector + j;
 841                         chip->oob_poi[eccpos[pos]] =
 842                                 pmecc_readb_ecc_relaxed(host->ecc, i, j);
 843                 }
 844         }
 845         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 846
 847         return 0;
 848 }
 849
 850 static void atmel_pmecc_core_init(struct mtd_info *mtd)
 851 {
 852         struct nand_chip *nand_chip = mtd->priv;
 853         struct atmel_nand_host *host = nand_chip->priv;
 854         uint32_t val = 0;
 855         struct nand_ecclayout *ecc_layout;
 856
 857         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
 858         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
 859
 860         switch (host->pmecc_corr_cap) {
 861         case 2:
 862                 val = PMECC_CFG_BCH_ERR2;
 863                 break;
 864         case 4:
 865                 val = PMECC_CFG_BCH_ERR4;
 866                 break;
 867         case 8:
 868                 val = PMECC_CFG_BCH_ERR8;
 869                 break;
 870         case 12:
 871                 val = PMECC_CFG_BCH_ERR12;
 872                 break;
 873         case 24:
 874                 val = PMECC_CFG_BCH_ERR24;
 875                 break;
 876         }
 877
 878         if (host->pmecc_sector_size == 512)
 879                 val |= PMECC_CFG_SECTOR512;
 880         else if (host->pmecc_sector_size == 1024)
 881                 val |= PMECC_CFG_SECTOR1024;
 882
 883         switch (host->pmecc_sector_number) {
 884         case 1:
 885                 val |= PMECC_CFG_PAGE_1SECTOR;
 886                 break;
 887         case 2:
 888                 val |= PMECC_CFG_PAGE_2SECTORS;
 889                 break;
 890         case 4:
 891                 val |= PMECC_CFG_PAGE_4SECTORS;
 892                 break;
 893         case 8:
 894                 val |= PMECC_CFG_PAGE_8SECTORS;
 895                 break;
 896         }
 897
 898         val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
 899                 | PMECC_CFG_AUTO_DISABLE);
 900         pmecc_writel(host->ecc, CFG, val);
 901
 902         ecc_layout = nand_chip->ecc.layout;
 903         pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1);
 904         pmecc_writel(host->ecc, SADDR, ecc_layout->eccpos[0]);
 905         pmecc_writel(host->ecc, EADDR,
 906                         ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
 907         /* See datasheet about PMECC Clock Control Register */
 908         pmecc_writel(host->ecc, CLK, 2);
 909         pmecc_writel(host->ecc, IDR, 0xff);
 910         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
 911 }
 912
 913 /*
 914  * Get ECC requirement in ONFI parameters, returns -1 if ONFI
 915  * parameters is not supported.
 916  * return 0 if success to get the ECC requirement.
 917  */
 918 static int get_onfi_ecc_param(struct nand_chip *chip,
 919                 int *ecc_bits, int *sector_size)
 920 {
 921         *ecc_bits = *sector_size = 0;
 922
 923         if (chip->onfi_params.ecc_bits == 0xff)
 924                 /* TODO: the sector_size and ecc_bits need to be find in
 925                  * extended ecc parameter, currently we don't support it.
 926                  */
 927                 return -1;
 928
 929         *ecc_bits = chip->onfi_params.ecc_bits;
 930
 931         /* The default sector size (ecc codeword size) is 512 */
 932         *sector_size = 512;
 933
 934         return 0;
 935 }
 936
 937 /*
 938  * Get ecc requirement from ONFI parameters ecc requirement.
 939  * If pmecc-cap, pmecc-sector-size in DTS are not specified, this function
 940  * will set them according to ONFI ecc requirement. Otherwise, use the
 941  * value in DTS file.
 942  * return 0 if success. otherwise return error code.
 943  */
 944 static int pmecc_choose_ecc(struct atmel_nand_host *host,
 945                 int *cap, int *sector_size)
 946 {
 947         /* Get ECC requirement from ONFI parameters */
 948         *cap = *sector_size = 0;
 949         if (host->nand_chip.onfi_version) {
 950                 if (!get_onfi_ecc_param(&host->nand_chip, cap, sector_size))
 951                         dev_info(host->dev, "ONFI params, minimum required ECC: %d bits in %d bytes\n",
 952                                 *cap, *sector_size);
 953                 else
 954                         dev_info(host->dev, "NAND chip ECC reqirement is in Extended ONFI parameter, we don't support yet.\n");
 955         } else {
 956                 dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes");
 957         }
 958         if (*cap == 0 && *sector_size == 0) {
 959                 *cap = 2;
 960                 *sector_size = 512;
 961         }
 962
 963         /* If dts file doesn't specify then use the one in ONFI parameters */
 964         if (host->pmecc_corr_cap == 0) {
 965                 /* use the most fitable ecc bits (the near bigger one ) */
 966                 if (*cap <= 2)
 967                         host->pmecc_corr_cap = 2;
 968                 else if (*cap <= 4)
 969                         host->pmecc_corr_cap = 4;
 970                 else if (*cap < 8)
 971                         host->pmecc_corr_cap = 8;
 972                 else if (*cap < 12)
 973                         host->pmecc_corr_cap = 12;
 974                 else if (*cap < 24)
 975                         host->pmecc_corr_cap = 24;
 976                 else
 977                         return -EINVAL;
 978         }
 979         if (host->pmecc_sector_size == 0) {
 980                 /* use the most fitable sector size (the near smaller one ) */
 981                 if (*sector_size >= 1024)
 982                         host->pmecc_sector_size = 1024;
 983                 else if (*sector_size >= 512)
 984                         host->pmecc_sector_size = 512;
 985                 else
 986                         return -EINVAL;
 987         }
 988         return 0;
 989 }
 990
 991 static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev,
 992                                          struct atmel_nand_host *host)
 993 {
 994         struct mtd_info *mtd = &host->mtd;
 995         struct nand_chip *nand_chip = &host->nand_chip;
 996         struct resource *regs, *regs_pmerr, *regs_rom;
 997         int cap, sector_size, err_no;
 998
 999         err_no = pmecc_choose_ecc(host, &cap, &sector_size);
1000         if (err_no) {
1001                 dev_err(host->dev, "The NAND flash's ECC requirement are not support!");
1002                 return err_no;
1003         }
1004
1005         if (cap != host->pmecc_corr_cap ||
1006                         sector_size != host->pmecc_sector_size)
1007                 dev_info(host->dev, "WARNING: Be Caution! Using different PMECC parameters from Nand ONFI ECC reqirement.\n");
1008
1009         cap = host->pmecc_corr_cap;
1010         sector_size = host->pmecc_sector_size;
1011         host->pmecc_lookup_table_offset = (sector_size == 512) ?
1012                         host->pmecc_lookup_table_offset_512 :
1013                         host->pmecc_lookup_table_offset_1024;
1014
1015         dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
1016                  cap, sector_size);
1017
1018         regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1019         if (!regs) {
1020                 dev_warn(host->dev,
1021                         "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
1022                 nand_chip->ecc.mode = NAND_ECC_SOFT;
1023                 return 0;
1024         }
1025
1026         host->ecc = ioremap(regs->start, resource_size(regs));
1027         if (host->ecc == NULL) {
1028                 dev_err(host->dev, "ioremap failed\n");
1029                 err_no = -EIO;
1030                 goto err_pmecc_ioremap;
1031         }
1032
1033         regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1034         regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1035         if (regs_pmerr && regs_rom) {
1036                 host->pmerrloc_base = ioremap(regs_pmerr->start,
1037                         resource_size(regs_pmerr));
1038                 host->pmecc_rom_base = ioremap(regs_rom->start,
1039                         resource_size(regs_rom));
1040         }
1041
1042         if (!host->pmerrloc_base || !host->pmecc_rom_base) {
1043                 dev_err(host->dev,
1044                         "Can not get I/O resource for PMECC ERRLOC controller or ROM!\n");
1045                 err_no = -EIO;
1046                 goto err_pmloc_ioremap;
1047         }
1048
1049         /* ECC is calculated for the whole page (1 step) */
1050         nand_chip->ecc.size = mtd->writesize;
1051
1052         /* set ECC page size and oob layout */
1053         switch (mtd->writesize) {
1054         case 2048:
1055                 host->pmecc_degree = PMECC_GF_DIMENSION_13;
1056                 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
1057                 host->pmecc_sector_number = mtd->writesize / sector_size;
1058                 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
1059                         cap, sector_size);
1060                 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
1061                 host->pmecc_index_of = host->pmecc_rom_base +
1062                         host->pmecc_lookup_table_offset;
1063
1064                 nand_chip->ecc.steps = 1;
1065                 nand_chip->ecc.strength = cap;
1066                 nand_chip->ecc.bytes = host->pmecc_bytes_per_sector *
1067                                        host->pmecc_sector_number;
1068                 if (nand_chip->ecc.bytes > mtd->oobsize - 2) {
1069                         dev_err(host->dev, "No room for ECC bytes\n");
1070                         err_no = -EINVAL;
1071                         goto err_no_ecc_room;
1072                 }
1073                 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
1074                                         mtd->oobsize,
1075                                         nand_chip->ecc.bytes);
1076                 nand_chip->ecc.layout = &atmel_pmecc_oobinfo;
1077                 break;
1078         case 512:
1079         case 1024:
1080         case 4096:
1081                 /* TODO */
1082                 dev_warn(host->dev,
1083                         "Unsupported page size for PMECC, use Software ECC\n");
1084         default:
1085                 /* page size not handled by HW ECC */
1086                 /* switching back to soft ECC */
1087                 nand_chip->ecc.mode = NAND_ECC_SOFT;
1088                 return 0;
1089         }
1090
1091         /* Allocate data for PMECC computation */
1092         err_no = pmecc_data_alloc(host);
1093         if (err_no) {
1094                 dev_err(host->dev,
1095                                 "Cannot allocate memory for PMECC computation!\n");
1096                 goto err_pmecc_data_alloc;
1097         }
1098
1099         nand_chip->options |= NAND_NO_SUBPAGE_WRITE;
1100         nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
1101         nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;
1102
1103         atmel_pmecc_core_init(mtd);
1104
1105         return 0;
1106
1107 err_pmecc_data_alloc:
1108 err_no_ecc_room:
1109 err_pmloc_ioremap:
1110         iounmap(host->ecc);
1111         if (host->pmerrloc_base)
1112                 iounmap(host->pmerrloc_base);
1113         if (host->pmecc_rom_base)
1114                 iounmap(host->pmecc_rom_base);
1115 err_pmecc_ioremap:
1116         return err_no;
1117 }
1118
1119 /*
1120  * Calculate HW ECC
1121  *
1122  * function called after a write
1123  *
1124  * mtd:        MTD block structure
1125  * dat:        raw data (unused)
1126  * ecc_code:   buffer for ECC
1127  */
1128 static int atmel_nand_calculate(struct mtd_info *mtd,
1129                 const u_char *dat, unsigned char *ecc_code)
1130 {
1131         struct nand_chip *nand_chip = mtd->priv;
1132         struct atmel_nand_host *host = nand_chip->priv;
1133         unsigned int ecc_value;
1134
1135         /* get the first 2 ECC bytes */
1136         ecc_value = ecc_readl(host->ecc, PR);
1137
1138         ecc_code[0] = ecc_value & 0xFF;
1139         ecc_code[1] = (ecc_value >> 8) & 0xFF;
1140
1141         /* get the last 2 ECC bytes */
1142         ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
1143
1144         ecc_code[2] = ecc_value & 0xFF;
1145         ecc_code[3] = (ecc_value >> 8) & 0xFF;
1146
1147         return 0;
1148 }
1149
1150 /*
1151  * HW ECC read page function
1152  *
1153  * mtd:        mtd info structure
1154  * chip:       nand chip info structure
1155  * buf:        buffer to store read data
1156  * oob_required:    caller expects OOB data read to chip->oob_poi
1157  */
1158 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1159                                 uint8_t *buf, int oob_required, int page)
1160 {
1161         int eccsize = chip->ecc.size;
1162         int eccbytes = chip->ecc.bytes;
1163         uint32_t *eccpos = chip->ecc.layout->eccpos;
1164         uint8_t *p = buf;
1165         uint8_t *oob = chip->oob_poi;
1166         uint8_t *ecc_pos;
1167         int stat;
1168         unsigned int max_bitflips = 0;
1169
1170         /*
1171          * Errata: ALE is incorrectly wired up to the ECC controller
1172          * on the AP7000, so it will include the address cycles in the
1173          * ECC calculation.
1174          *
1175          * Workaround: Reset the parity registers before reading the
1176          * actual data.
1177          */
1178         if (cpu_is_at32ap7000()) {
1179                 struct atmel_nand_host *host = chip->priv;
1180                 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1181         }
1182
1183         /* read the page */
1184         chip->read_buf(mtd, p, eccsize);
1185
1186         /* move to ECC position if needed */
1187         if (eccpos[0] != 0) {
1188                 /* This only works on large pages
1189                  * because the ECC controller waits for
1190                  * NAND_CMD_RNDOUTSTART after the
1191                  * NAND_CMD_RNDOUT.
1192                  * anyway, for small pages, the eccpos[0] == 0
1193                  */
1194                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1195                                 mtd->writesize + eccpos[0], -1);
1196         }
1197
1198         /* the ECC controller needs to read the ECC just after the data */
1199         ecc_pos = oob + eccpos[0];
1200         chip->read_buf(mtd, ecc_pos, eccbytes);
1201
1202         /* check if there's an error */
1203         stat = chip->ecc.correct(mtd, p, oob, NULL);
1204
1205         if (stat < 0) {
1206                 mtd->ecc_stats.failed++;
1207         } else {
1208                 mtd->ecc_stats.corrected += stat;
1209                 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1210         }
1211
1212         /* get back to oob start (end of page) */
1213         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1214
1215         /* read the oob */
1216         chip->read_buf(mtd, oob, mtd->oobsize);
1217
1218         return max_bitflips;
1219 }
1220
1221 /*
1222  * HW ECC Correction
1223  *
1224  * function called after a read
1225  *
1226  * mtd:        MTD block structure
1227  * dat:        raw data read from the chip
1228  * read_ecc:   ECC from the chip (unused)
1229  * isnull:     unused
1230  *
1231  * Detect and correct a 1 bit error for a page
1232  */
1233 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1234                 u_char *read_ecc, u_char *isnull)
1235 {
1236         struct nand_chip *nand_chip = mtd->priv;
1237         struct atmel_nand_host *host = nand_chip->priv;
1238         unsigned int ecc_status;
1239         unsigned int ecc_word, ecc_bit;
1240
1241         /* get the status from the Status Register */
1242         ecc_status = ecc_readl(host->ecc, SR);
1243
1244         /* if there's no error */
1245         if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1246                 return 0;
1247
1248         /* get error bit offset (4 bits) */
1249         ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
1250         /* get word address (12 bits) */
1251         ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
1252         ecc_word >>= 4;
1253
1254         /* if there are multiple errors */
1255         if (ecc_status & ATMEL_ECC_MULERR) {
1256                 /* check if it is a freshly erased block
1257                  * (filled with 0xff) */
1258                 if ((ecc_bit == ATMEL_ECC_BITADDR)
1259                                 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1260                         /* the block has just been erased, return OK */
1261                         return 0;
1262                 }
1263                 /* it doesn't seems to be a freshly
1264                  * erased block.
1265                  * We can't correct so many errors */
1266                 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
1267                                 " Unable to correct.\n");
1268                 return -EIO;
1269         }
1270
1271         /* if there's a single bit error : we can correct it */
1272         if (ecc_status & ATMEL_ECC_ECCERR) {
1273                 /* there's nothing much to do here.
1274                  * the bit error is on the ECC itself.
1275                  */
1276                 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
1277                                 " Nothing to correct\n");
1278                 return 0;
1279         }
1280
1281         dev_dbg(host->dev, "atmel_nand : one bit error on data."
1282                         " (word offset in the page :"
1283                         " 0x%x bit offset : 0x%x)\n",
1284                         ecc_word, ecc_bit);
1285         /* correct the error */
1286         if (nand_chip->options & NAND_BUSWIDTH_16) {
1287                 /* 16 bits words */
1288                 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1289         } else {
1290                 /* 8 bits words */
1291                 dat[ecc_word] ^= (1 << ecc_bit);
1292         }
1293         dev_dbg(host->dev, "atmel_nand : error corrected\n");
1294         return 1;
1295 }
1296
1297 /*
1298  * Enable HW ECC : unused on most chips
1299  */
1300 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1301 {
1302         if (cpu_is_at32ap7000()) {
1303                 struct nand_chip *nand_chip = mtd->priv;
1304                 struct atmel_nand_host *host = nand_chip->priv;
1305                 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1306         }
1307 }
1308
1309 #if defined(CONFIG_OF)
1310 static int atmel_of_init_port(struct atmel_nand_host *host,
1311                               struct device_node *np)
1312 {
1313         u32 val;
1314         u32 offset[2];
1315         int ecc_mode;
1316         struct atmel_nand_data *board = &host->board;
1317         enum of_gpio_flags flags;
1318
1319         if (of_property_read_u32(np, "atmel,nand-addr-offset", &val) == 0) {
1320                 if (val >= 32) {
1321                         dev_err(host->dev, "invalid addr-offset %u\n", val);
1322                         return -EINVAL;
1323                 }
1324                 board->ale = val;
1325         }
1326
1327         if (of_property_read_u32(np, "atmel,nand-cmd-offset", &val) == 0) {
1328                 if (val >= 32) {
1329                         dev_err(host->dev, "invalid cmd-offset %u\n", val);
1330                         return -EINVAL;
1331                 }
1332                 board->cle = val;
1333         }
1334
1335         ecc_mode = of_get_nand_ecc_mode(np);
1336
1337         board->ecc_mode = ecc_mode < 0 ? NAND_ECC_SOFT : ecc_mode;
1338
1339         board->on_flash_bbt = of_get_nand_on_flash_bbt(np);
1340
1341         if (of_get_nand_bus_width(np) == 16)
1342                 board->bus_width_16 = 1;
1343
1344         board->rdy_pin = of_get_gpio_flags(np, 0, &flags);
1345         board->rdy_pin_active_low = (flags == OF_GPIO_ACTIVE_LOW);
1346
1347         board->enable_pin = of_get_gpio(np, 1);
1348         board->det_pin = of_get_gpio(np, 2);
1349
1350         host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
1351
1352         if (!(board->ecc_mode == NAND_ECC_HW) || !host->has_pmecc)
1353                 return 0;       /* Not using PMECC */
1354
1355         /* use PMECC, get correction capability, sector size and lookup
1356          * table offset.
1357          * If correction bits and sector size are not specified, then find
1358          * them from NAND ONFI parameters.
1359          */
1360         if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
1361                 if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
1362                                 (val != 24)) {
1363                         dev_err(host->dev,
1364                                 "Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n",
1365                                 val);
1366                         return -EINVAL;
1367                 }
1368                 host->pmecc_corr_cap = (u8)val;
1369         }
1370
1371         if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
1372                 if ((val != 512) && (val != 1024)) {
1373                         dev_err(host->dev,
1374                                 "Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n",
1375                                 val);
1376                         return -EINVAL;
1377                 }
1378                 host->pmecc_sector_size = (u16)val;
1379         }
1380
1381         if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset",
1382                         offset, 2) != 0) {
1383                 dev_err(host->dev, "Cannot get PMECC lookup table offset\n");
1384                 return -EINVAL;
1385         }
1386         if (!offset[0] && !offset[1]) {
1387                 dev_err(host->dev, "Invalid PMECC lookup table offset\n");
1388                 return -EINVAL;
1389         }
1390         host->pmecc_lookup_table_offset_512 = offset[0];
1391         host->pmecc_lookup_table_offset_1024 = offset[1];
1392
1393         return 0;
1394 }
1395 #else
1396 static int atmel_of_init_port(struct atmel_nand_host *host,
1397                               struct device_node *np)
1398 {
1399         return -EINVAL;
1400 }
1401 #endif
1402
1403 static int __init atmel_hw_nand_init_params(struct platform_device *pdev,
1404                                          struct atmel_nand_host *host)
1405 {
1406         struct mtd_info *mtd = &host->mtd;
1407         struct nand_chip *nand_chip = &host->nand_chip;
1408         struct resource         *regs;
1409
1410         regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1411         if (!regs) {
1412                 dev_err(host->dev,
1413                         "Can't get I/O resource regs, use software ECC\n");
1414                 nand_chip->ecc.mode = NAND_ECC_SOFT;
1415                 return 0;
1416         }
1417
1418         host->ecc = ioremap(regs->start, resource_size(regs));
1419         if (host->ecc == NULL) {
1420                 dev_err(host->dev, "ioremap failed\n");
1421                 return -EIO;
1422         }
1423
1424         /* ECC is calculated for the whole page (1 step) */
1425         nand_chip->ecc.size = mtd->writesize;
1426
1427         /* set ECC page size and oob layout */
1428         switch (mtd->writesize) {
1429         case 512:
1430                 nand_chip->ecc.layout = &atmel_oobinfo_small;
1431                 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
1432                 break;
1433         case 1024:
1434                 nand_chip->ecc.layout = &atmel_oobinfo_large;
1435                 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
1436                 break;
1437         case 2048:
1438                 nand_chip->ecc.layout = &atmel_oobinfo_large;
1439                 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
1440                 break;
1441         case 4096:
1442                 nand_chip->ecc.layout = &atmel_oobinfo_large;
1443                 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
1444                 break;
1445         default:
1446                 /* page size not handled by HW ECC */
1447                 /* switching back to soft ECC */
1448                 nand_chip->ecc.mode = NAND_ECC_SOFT;
1449                 return 0;
1450         }
1451
1452         /* set up for HW ECC */
1453         nand_chip->ecc.calculate = atmel_nand_calculate;
1454         nand_chip->ecc.correct = atmel_nand_correct;
1455         nand_chip->ecc.hwctl = atmel_nand_hwctl;
1456         nand_chip->ecc.read_page = atmel_nand_read_page;
1457         nand_chip->ecc.bytes = 4;
1458         nand_chip->ecc.strength = 1;
1459
1460         return 0;
1461 }
1462
1463 /*
1464  * Probe for the NAND device.
1465  */
1466 static int __init atmel_nand_probe(struct platform_device *pdev)
1467 {
1468         struct atmel_nand_host *host;
1469         struct mtd_info *mtd;
1470         struct nand_chip *nand_chip;
1471         struct resource *mem;
1472         struct mtd_part_parser_data ppdata = {};
1473         int res;
1474         struct pinctrl *pinctrl;
1475
1476         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1477         if (!mem) {
1478                 printk(KERN_ERR "atmel_nand: can't get I/O resource mem\n");
1479                 return -ENXIO;
1480         }
1481
1482         /* Allocate memory for the device structure (and zero it) */
1483         host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL);
1484         if (!host) {
1485                 printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n");
1486                 return -ENOMEM;
1487         }
1488
1489         host->io_phys = (dma_addr_t)mem->start;
1490
1491         host->io_base = ioremap(mem->start, resource_size(mem));
1492         if (host->io_base == NULL) {
1493                 printk(KERN_ERR "atmel_nand: ioremap failed\n");
1494                 res = -EIO;
1495                 goto err_nand_ioremap;
1496         }
1497
1498         mtd = &host->mtd;
1499         nand_chip = &host->nand_chip;
1500         host->dev = &pdev->dev;
1501         if (pdev->dev.of_node) {
1502                 res = atmel_of_init_port(host, pdev->dev.of_node);
1503                 if (res)
1504                         goto err_ecc_ioremap;
1505         } else {
1506                 memcpy(&host->board, pdev->dev.platform_data,
1507                        sizeof(struct atmel_nand_data));
1508         }
1509
1510         nand_chip->priv = host;         /* link the private data structures */
1511         mtd->priv = nand_chip;
1512         mtd->owner = THIS_MODULE;
1513
1514         /* Set address of NAND IO lines */
1515         nand_chip->IO_ADDR_R = host->io_base;
1516         nand_chip->IO_ADDR_W = host->io_base;
1517         nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
1518
1519         pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1520         if (IS_ERR(pinctrl)) {
1521                 dev_err(host->dev, "Failed to request pinctrl\n");
1522                 res = PTR_ERR(pinctrl);
1523                 goto err_ecc_ioremap;
1524         }
1525
1526         if (gpio_is_valid(host->board.rdy_pin)) {
1527                 res = gpio_request(host->board.rdy_pin, "nand_rdy");
1528                 if (res < 0) {
1529                         dev_err(&pdev->dev,
1530                                 "can't request rdy gpio %d\n",
1531                                 host->board.rdy_pin);
1532                         goto err_ecc_ioremap;
1533                 }
1534
1535                 res = gpio_direction_input(host->board.rdy_pin);
1536                 if (res < 0) {
1537                         dev_err(&pdev->dev,
1538                                 "can't request input direction rdy gpio %d\n",
1539                                 host->board.rdy_pin);
1540                         goto err_ecc_ioremap;
1541                 }
1542
1543                 nand_chip->dev_ready = atmel_nand_device_ready;
1544         }
1545
1546         if (gpio_is_valid(host->board.enable_pin)) {
1547                 res = gpio_request(host->board.enable_pin, "nand_enable");
1548                 if (res < 0) {
1549                         dev_err(&pdev->dev,
1550                                 "can't request enable gpio %d\n",
1551                                 host->board.enable_pin);
1552                         goto err_ecc_ioremap;
1553                 }
1554
1555                 res = gpio_direction_output(host->board.enable_pin, 1);
1556                 if (res < 0) {
1557                         dev_err(&pdev->dev,
1558                                 "can't request output direction enable gpio %d\n",
1559                                 host->board.enable_pin);
1560                         goto err_ecc_ioremap;
1561                 }
1562         }
1563
1564         nand_chip->ecc.mode = host->board.ecc_mode;
1565         nand_chip->chip_delay = 20;             /* 20us command delay time */
1566
1567         if (host->board.bus_width_16)   /* 16-bit bus width */
1568                 nand_chip->options |= NAND_BUSWIDTH_16;
1569
1570         nand_chip->read_buf = atmel_read_buf;
1571         nand_chip->write_buf = atmel_write_buf;
1572
1573         platform_set_drvdata(pdev, host);
1574         atmel_nand_enable(host);
1575
1576         if (gpio_is_valid(host->board.det_pin)) {
1577                 res = gpio_request(host->board.det_pin, "nand_det");
1578                 if (res < 0) {
1579                         dev_err(&pdev->dev,
1580                                 "can't request det gpio %d\n",
1581                                 host->board.det_pin);
1582                         goto err_no_card;
1583                 }
1584
1585                 res = gpio_direction_input(host->board.det_pin);
1586                 if (res < 0) {
1587                         dev_err(&pdev->dev,
1588                                 "can't request input direction det gpio %d\n",
1589                                 host->board.det_pin);
1590                         goto err_no_card;
1591                 }
1592
1593                 if (gpio_get_value(host->board.det_pin)) {
1594                         printk(KERN_INFO "No SmartMedia card inserted.\n");
1595                         res = -ENXIO;
1596                         goto err_no_card;
1597                 }
1598         }
1599
1600         if (host->board.on_flash_bbt || on_flash_bbt) {
1601                 printk(KERN_INFO "atmel_nand: Use On Flash BBT\n");
1602                 nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
1603         }
1604
1605         if (!cpu_has_dma())
1606                 use_dma = 0;
1607
1608         if (use_dma) {
1609                 dma_cap_mask_t mask;
1610
1611                 dma_cap_zero(mask);
1612                 dma_cap_set(DMA_MEMCPY, mask);
1613                 host->dma_chan = dma_request_channel(mask, NULL, NULL);
1614                 if (!host->dma_chan) {
1615                         dev_err(host->dev, "Failed to request DMA channel\n");
1616                         use_dma = 0;
1617                 }
1618         }
1619         if (use_dma)
1620                 dev_info(host->dev, "Using %s for DMA transfers.\n",
1621                                         dma_chan_name(host->dma_chan));
1622         else
1623                 dev_info(host->dev, "No DMA support for NAND access.\n");
1624
1625         /* first scan to find the device and get the page size */
1626         if (nand_scan_ident(mtd, 1, NULL)) {
1627                 res = -ENXIO;
1628                 goto err_scan_ident;
1629         }
1630
1631         if (nand_chip->ecc.mode == NAND_ECC_HW) {
1632                 if (host->has_pmecc)
1633                         res = atmel_pmecc_nand_init_params(pdev, host);
1634                 else
1635                         res = atmel_hw_nand_init_params(pdev, host);
1636
1637                 if (res != 0)
1638                         goto err_hw_ecc;
1639         }
1640
1641         /* second phase scan */
1642         if (nand_scan_tail(mtd)) {
1643                 res = -ENXIO;
1644                 goto err_scan_tail;
1645         }
1646
1647         mtd->name = "atmel_nand";
1648         ppdata.of_node = pdev->dev.of_node;
1649         res = mtd_device_parse_register(mtd, NULL, &ppdata,
1650                         host->board.parts, host->board.num_parts);
1651         if (!res)
1652                 return res;
1653
1654 err_scan_tail:
1655         if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
1656                 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1657                 pmecc_data_free(host);
1658         }
1659         if (host->ecc)
1660                 iounmap(host->ecc);
1661         if (host->pmerrloc_base)
1662                 iounmap(host->pmerrloc_base);
1663         if (host->pmecc_rom_base)
1664                 iounmap(host->pmecc_rom_base);
1665 err_hw_ecc:
1666 err_scan_ident:
1667 err_no_card:
1668         atmel_nand_disable(host);
1669         platform_set_drvdata(pdev, NULL);
1670         if (host->dma_chan)
1671                 dma_release_channel(host->dma_chan);
1672 err_ecc_ioremap:
1673         iounmap(host->io_base);
1674 err_nand_ioremap:
1675         kfree(host);
1676         return res;
1677 }
1678
1679 /*
1680  * Remove a NAND device.
1681  */
1682 static int __exit atmel_nand_remove(struct platform_device *pdev)
1683 {
1684         struct atmel_nand_host *host = platform_get_drvdata(pdev);
1685         struct mtd_info *mtd = &host->mtd;
1686
1687         nand_release(mtd);
1688
1689         atmel_nand_disable(host);
1690
1691         if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
1692                 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1693                 pmerrloc_writel(host->pmerrloc_base, ELDIS,
1694                                 PMERRLOC_DISABLE);
1695                 pmecc_data_free(host);
1696         }
1697
1698         if (gpio_is_valid(host->board.det_pin))
1699                 gpio_free(host->board.det_pin);
1700
1701         if (gpio_is_valid(host->board.enable_pin))
1702                 gpio_free(host->board.enable_pin);
1703
1704         if (gpio_is_valid(host->board.rdy_pin))
1705                 gpio_free(host->board.rdy_pin);
1706
1707         if (host->ecc)
1708                 iounmap(host->ecc);
1709         if (host->pmecc_rom_base)
1710                 iounmap(host->pmecc_rom_base);
1711         if (host->pmerrloc_base)
1712                 iounmap(host->pmerrloc_base);
1713
1714         if (host->dma_chan)
1715                 dma_release_channel(host->dma_chan);
1716
1717         iounmap(host->io_base);
1718         kfree(host);
1719
1720         return 0;
1721 }
1722
1723 #if defined(CONFIG_OF)
1724 static const struct of_device_id atmel_nand_dt_ids[] = {
1725         { .compatible = "atmel,at91rm9200-nand" },
1726         { /* sentinel */ }
1727 };
1728
1729 MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);
1730 #endif
1731
1732 static struct platform_driver atmel_nand_driver = {
1733         .remove         = __exit_p(atmel_nand_remove),
1734         .driver         = {
1735                 .name   = "atmel_nand",
1736                 .owner  = THIS_MODULE,
1737                 .of_match_table = of_match_ptr(atmel_nand_dt_ids),
1738         },
1739 };
1740
1741 module_platform_driver_probe(atmel_nand_driver, atmel_nand_probe);
1742
1743 MODULE_LICENSE("GPL");
1744 MODULE_AUTHOR("Rick Bronson");
1745 MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
1746 MODULE_ALIAS("platform:atmel_nand");