drivers/mmc/host/omap.c

   1 /*
   2  *  linux/drivers/mmc/host/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dmaengine.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/delay.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/timer.h>
  25 #include <linux/omap-dma.h>
  26 #include <linux/mmc/host.h>
  27 #include <linux/mmc/card.h>
  28 #include <linux/clk.h>
  29 #include <linux/scatterlist.h>
  30 #include <linux/i2c/tps65010.h>
  31 #include <linux/slab.h>
  32
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #include <plat/board.h>
  37 #include <plat/mmc.h>
  38 #include <asm/gpio.h>
  39 #include <plat/dma.h>
  40 #include <plat/mux.h>
  41 #include <plat/fpga.h>
  42
  43 #define OMAP_MMC_REG_CMD        0x00
  44 #define OMAP_MMC_REG_ARGL       0x01
  45 #define OMAP_MMC_REG_ARGH       0x02
  46 #define OMAP_MMC_REG_CON        0x03
  47 #define OMAP_MMC_REG_STAT       0x04
  48 #define OMAP_MMC_REG_IE         0x05
  49 #define OMAP_MMC_REG_CTO        0x06
  50 #define OMAP_MMC_REG_DTO        0x07
  51 #define OMAP_MMC_REG_DATA       0x08
  52 #define OMAP_MMC_REG_BLEN       0x09
  53 #define OMAP_MMC_REG_NBLK       0x0a
  54 #define OMAP_MMC_REG_BUF        0x0b
  55 #define OMAP_MMC_REG_SDIO       0x0d
  56 #define OMAP_MMC_REG_REV        0x0f
  57 #define OMAP_MMC_REG_RSP0       0x10
  58 #define OMAP_MMC_REG_RSP1       0x11
  59 #define OMAP_MMC_REG_RSP2       0x12
  60 #define OMAP_MMC_REG_RSP3       0x13
  61 #define OMAP_MMC_REG_RSP4       0x14
  62 #define OMAP_MMC_REG_RSP5       0x15
  63 #define OMAP_MMC_REG_RSP6       0x16
  64 #define OMAP_MMC_REG_RSP7       0x17
  65 #define OMAP_MMC_REG_IOSR       0x18
  66 #define OMAP_MMC_REG_SYSC       0x19
  67 #define OMAP_MMC_REG_SYSS       0x1a
  68
  69 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  70 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  71 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  72 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  73 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  74 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  75 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  76 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  77 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  78 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  79 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  80 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  81 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  82
  83 #define OMAP_MMC_REG(host, reg)         (OMAP_MMC_REG_##reg << (host)->reg_shift)
  84 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
  85 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
  86
  87 /*
  88  * Command types
  89  */
  90 #define OMAP_MMC_CMDTYPE_BC     0
  91 #define OMAP_MMC_CMDTYPE_BCR    1
  92 #define OMAP_MMC_CMDTYPE_AC     2
  93 #define OMAP_MMC_CMDTYPE_ADTC   3
  94
  95
  96 #define DRIVER_NAME "mmci-omap"
  97
  98 /* Specifies how often in millisecs to poll for card status changes
  99  * when the cover switch is open */
 100 #define OMAP_MMC_COVER_POLL_DELAY       500
 101
 102 struct mmc_omap_host;
 103
 104 struct mmc_omap_slot {
 105         int                     id;
 106         unsigned int            vdd;
 107         u16                     saved_con;
 108         u16                     bus_mode;
 109         unsigned int            fclk_freq;
 110         unsigned                powered:1;
 111
 112         struct tasklet_struct   cover_tasklet;
 113         struct timer_list       cover_timer;
 114         unsigned                cover_open;
 115
 116         struct mmc_request      *mrq;
 117         struct mmc_omap_host    *host;
 118         struct mmc_host         *mmc;
 119         struct omap_mmc_slot_data *pdata;
 120 };
 121
 122 struct mmc_omap_host {
 123         int                     initialized;
 124         int                     suspended;
 125         struct mmc_request *    mrq;
 126         struct mmc_command *    cmd;
 127         struct mmc_data *       data;
 128         struct mmc_host *       mmc;
 129         struct device *         dev;
 130         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 131         struct clk *            iclk;
 132         struct clk *            fclk;
 133         struct dma_chan         *dma_rx;
 134         u32                     dma_rx_burst;
 135         struct dma_chan         *dma_tx;
 136         u32                     dma_tx_burst;
 137         struct resource         *mem_res;
 138         void __iomem            *virt_base;
 139         unsigned int            phys_base;
 140         int                     irq;
 141         unsigned char           bus_mode;
 142         unsigned char           hw_bus_mode;
 143         unsigned int            reg_shift;
 144
 145         struct work_struct      cmd_abort_work;
 146         unsigned                abort:1;
 147         struct timer_list       cmd_abort_timer;
 148
 149         struct work_struct      slot_release_work;
 150         struct mmc_omap_slot    *next_slot;
 151         struct work_struct      send_stop_work;
 152         struct mmc_data         *stop_data;
 153
 154         unsigned int            sg_len;
 155         int                     sg_idx;
 156         u16 *                   buffer;
 157         u32                     buffer_bytes_left;
 158         u32                     total_bytes_left;
 159
 160         unsigned                use_dma:1;
 161         unsigned                brs_received:1, dma_done:1;
 162         unsigned                dma_in_use:1;
 163         spinlock_t              dma_lock;
 164
 165         struct mmc_omap_slot    *slots[OMAP_MMC_MAX_SLOTS];
 166         struct mmc_omap_slot    *current_slot;
 167         spinlock_t              slot_lock;
 168         wait_queue_head_t       slot_wq;
 169         int                     nr_slots;
 170
 171         struct timer_list       clk_timer;
 172         spinlock_t              clk_lock;     /* for changing enabled state */
 173         unsigned int            fclk_enabled:1;
 174         struct workqueue_struct *mmc_omap_wq;
 175
 176         struct omap_mmc_platform_data *pdata;
 177 };
 178
 179
 180 static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
 181 {
 182         unsigned long tick_ns;
 183
 184         if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
 185                 tick_ns = (1000000000 + slot->fclk_freq - 1) / slot->fclk_freq;
 186                 ndelay(8 * tick_ns);
 187         }
 188 }
 189
 190 static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
 191 {
 192         unsigned long flags;
 193
 194         spin_lock_irqsave(&host->clk_lock, flags);
 195         if (host->fclk_enabled != enable) {
 196                 host->fclk_enabled = enable;
 197                 if (enable)
 198                         clk_enable(host->fclk);
 199                 else
 200                         clk_disable(host->fclk);
 201         }
 202         spin_unlock_irqrestore(&host->clk_lock, flags);
 203 }
 204
 205 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
 206 {
 207         struct mmc_omap_host *host = slot->host;
 208         unsigned long flags;
 209
 210         if (claimed)
 211                 goto no_claim;
 212         spin_lock_irqsave(&host->slot_lock, flags);
 213         while (host->mmc != NULL) {
 214                 spin_unlock_irqrestore(&host->slot_lock, flags);
 215                 wait_event(host->slot_wq, host->mmc == NULL);
 216                 spin_lock_irqsave(&host->slot_lock, flags);
 217         }
 218         host->mmc = slot->mmc;
 219         spin_unlock_irqrestore(&host->slot_lock, flags);
 220 no_claim:
 221         del_timer(&host->clk_timer);
 222         if (host->current_slot != slot || !claimed)
 223                 mmc_omap_fclk_offdelay(host->current_slot);
 224
 225         if (host->current_slot != slot) {
 226                 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
 227                 if (host->pdata->switch_slot != NULL)
 228                         host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
 229                 host->current_slot = slot;
 230         }
 231
 232         if (claimed) {
 233                 mmc_omap_fclk_enable(host, 1);
 234
 235                 /* Doing the dummy read here seems to work around some bug
 236                  * at least in OMAP24xx silicon where the command would not
 237                  * start after writing the CMD register. Sigh. */
 238                 OMAP_MMC_READ(host, CON);
 239
 240                 OMAP_MMC_WRITE(host, CON, slot->saved_con);
 241         } else
 242                 mmc_omap_fclk_enable(host, 0);
 243 }
 244
 245 static void mmc_omap_start_request(struct mmc_omap_host *host,
 246                                    struct mmc_request *req);
 247
 248 static void mmc_omap_slot_release_work(struct work_struct *work)
 249 {
 250         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 251                                                   slot_release_work);
 252         struct mmc_omap_slot *next_slot = host->next_slot;
 253         struct mmc_request *rq;
 254
 255         host->next_slot = NULL;
 256         mmc_omap_select_slot(next_slot, 1);
 257
 258         rq = next_slot->mrq;
 259         next_slot->mrq = NULL;
 260         mmc_omap_start_request(host, rq);
 261 }
 262
 263 static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
 264 {
 265         struct mmc_omap_host *host = slot->host;
 266         unsigned long flags;
 267         int i;
 268
 269         BUG_ON(slot == NULL || host->mmc == NULL);
 270
 271         if (clk_enabled)
 272                 /* Keeps clock running for at least 8 cycles on valid freq */
 273                 mod_timer(&host->clk_timer, jiffies  + HZ/10);
 274         else {
 275                 del_timer(&host->clk_timer);
 276                 mmc_omap_fclk_offdelay(slot);
 277                 mmc_omap_fclk_enable(host, 0);
 278         }
 279
 280         spin_lock_irqsave(&host->slot_lock, flags);
 281         /* Check for any pending requests */
 282         for (i = 0; i < host->nr_slots; i++) {
 283                 struct mmc_omap_slot *new_slot;
 284
 285                 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
 286                         continue;
 287
 288                 BUG_ON(host->next_slot != NULL);
 289                 new_slot = host->slots[i];
 290                 /* The current slot should not have a request in queue */
 291                 BUG_ON(new_slot == host->current_slot);
 292
 293                 host->next_slot = new_slot;
 294                 host->mmc = new_slot->mmc;
 295                 spin_unlock_irqrestore(&host->slot_lock, flags);
 296                 queue_work(host->mmc_omap_wq, &host->slot_release_work);
 297                 return;
 298         }
 299
 300         host->mmc = NULL;
 301         wake_up(&host->slot_wq);
 302         spin_unlock_irqrestore(&host->slot_lock, flags);
 303 }
 304
 305 static inline
 306 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
 307 {
 308         if (slot->pdata->get_cover_state)
 309                 return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
 310                                                     slot->id);
 311         return 0;
 312 }
 313
 314 static ssize_t
 315 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 316                            char *buf)
 317 {
 318         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 319         struct mmc_omap_slot *slot = mmc_priv(mmc);
 320
 321         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
 322                        "closed");
 323 }
 324
 325 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 326
 327 static ssize_t
 328 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 329                         char *buf)
 330 {
 331         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 332         struct mmc_omap_slot *slot = mmc_priv(mmc);
 333
 334         return sprintf(buf, "%s\n", slot->pdata->name);
 335 }
 336
 337 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 338
 339 static void
 340 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 341 {
 342         u32 cmdreg;
 343         u32 resptype;
 344         u32 cmdtype;
 345
 346         host->cmd = cmd;
 347
 348         resptype = 0;
 349         cmdtype = 0;
 350
 351         /* Our hardware needs to know exact type */
 352         switch (mmc_resp_type(cmd)) {
 353         case MMC_RSP_NONE:
 354                 break;
 355         case MMC_RSP_R1:
 356         case MMC_RSP_R1B:
 357                 /* resp 1, 1b, 6, 7 */
 358                 resptype = 1;
 359                 break;
 360         case MMC_RSP_R2:
 361                 resptype = 2;
 362                 break;
 363         case MMC_RSP_R3:
 364                 resptype = 3;
 365                 break;
 366         default:
 367                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 368                 break;
 369         }
 370
 371         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 372                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 373         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 374                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 375         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 376                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 377         } else {
 378                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 379         }
 380
 381         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 382
 383         if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
 384                 cmdreg |= 1 << 6;
 385
 386         if (cmd->flags & MMC_RSP_BUSY)
 387                 cmdreg |= 1 << 11;
 388
 389         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 390                 cmdreg |= 1 << 15;
 391
 392         mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
 393
 394         OMAP_MMC_WRITE(host, CTO, 200);
 395         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 396         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 397         OMAP_MMC_WRITE(host, IE,
 398                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 399                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 400                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 401                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 402                        OMAP_MMC_STAT_END_OF_DATA);
 403         OMAP_MMC_WRITE(host, CMD, cmdreg);
 404 }
 405
 406 static void
 407 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
 408                      int abort)
 409 {
 410         enum dma_data_direction dma_data_dir;
 411         struct device *dev = mmc_dev(host->mmc);
 412         struct dma_chan *c;
 413
 414         if (data->flags & MMC_DATA_WRITE) {
 415                 dma_data_dir = DMA_TO_DEVICE;
 416                 c = host->dma_tx;
 417         } else {
 418                 dma_data_dir = DMA_FROM_DEVICE;
 419                 c = host->dma_rx;
 420         }
 421         if (c) {
 422                 if (data->error) {
 423                         dmaengine_terminate_all(c);
 424                         /* Claim nothing transferred on error... */
 425                         data->bytes_xfered = 0;
 426                 }
 427                 dev = c->device->dev;
 428         }
 429         dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
 430 }
 431
 432 static void mmc_omap_send_stop_work(struct work_struct *work)
 433 {
 434         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 435                                                   send_stop_work);
 436         struct mmc_omap_slot *slot = host->current_slot;
 437         struct mmc_data *data = host->stop_data;
 438         unsigned long tick_ns;
 439
 440         tick_ns = (1000000000 + slot->fclk_freq - 1)/slot->fclk_freq;
 441         ndelay(8*tick_ns);
 442
 443         mmc_omap_start_command(host, data->stop);
 444 }
 445
 446 static void
 447 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 448 {
 449         if (host->dma_in_use)
 450                 mmc_omap_release_dma(host, data, data->error);
 451
 452         host->data = NULL;
 453         host->sg_len = 0;
 454
 455         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 456          * dozens of requests until the card finishes writing data.
 457          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 458          */
 459
 460         if (!data->stop) {
 461                 struct mmc_host *mmc;
 462
 463                 host->mrq = NULL;
 464                 mmc = host->mmc;
 465                 mmc_omap_release_slot(host->current_slot, 1);
 466                 mmc_request_done(mmc, data->mrq);
 467                 return;
 468         }
 469
 470         host->stop_data = data;
 471         queue_work(host->mmc_omap_wq, &host->send_stop_work);
 472 }
 473
 474 static void
 475 mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
 476 {
 477         struct mmc_omap_slot *slot = host->current_slot;
 478         unsigned int restarts, passes, timeout;
 479         u16 stat = 0;
 480
 481         /* Sending abort takes 80 clocks. Have some extra and round up */
 482         timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq;
 483         restarts = 0;
 484         while (restarts < maxloops) {
 485                 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
 486                 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
 487
 488                 passes = 0;
 489                 while (passes < timeout) {
 490                         stat = OMAP_MMC_READ(host, STAT);
 491                         if (stat & OMAP_MMC_STAT_END_OF_CMD)
 492                                 goto out;
 493                         udelay(1);
 494                         passes++;
 495                 }
 496
 497                 restarts++;
 498         }
 499 out:
 500         OMAP_MMC_WRITE(host, STAT, stat);
 501 }
 502
 503 static void
 504 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
 505 {
 506         if (host->dma_in_use)
 507                 mmc_omap_release_dma(host, data, 1);
 508
 509         host->data = NULL;
 510         host->sg_len = 0;
 511
 512         mmc_omap_send_abort(host, 10000);
 513 }
 514
 515 static void
 516 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 517 {
 518         unsigned long flags;
 519         int done;
 520
 521         if (!host->dma_in_use) {
 522                 mmc_omap_xfer_done(host, data);
 523                 return;
 524         }
 525         done = 0;
 526         spin_lock_irqsave(&host->dma_lock, flags);
 527         if (host->dma_done)
 528                 done = 1;
 529         else
 530                 host->brs_received = 1;
 531         spin_unlock_irqrestore(&host->dma_lock, flags);
 532         if (done)
 533                 mmc_omap_xfer_done(host, data);
 534 }
 535
 536 static void
 537 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 538 {
 539         unsigned long flags;
 540         int done;
 541
 542         done = 0;
 543         spin_lock_irqsave(&host->dma_lock, flags);
 544         if (host->brs_received)
 545                 done = 1;
 546         else
 547                 host->dma_done = 1;
 548         spin_unlock_irqrestore(&host->dma_lock, flags);
 549         if (done)
 550                 mmc_omap_xfer_done(host, data);
 551 }
 552
 553 static void
 554 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 555 {
 556         host->cmd = NULL;
 557
 558         del_timer(&host->cmd_abort_timer);
 559
 560         if (cmd->flags & MMC_RSP_PRESENT) {
 561                 if (cmd->flags & MMC_RSP_136) {
 562                         /* response type 2 */
 563                         cmd->resp[3] =
 564                                 OMAP_MMC_READ(host, RSP0) |
 565                                 (OMAP_MMC_READ(host, RSP1) << 16);
 566                         cmd->resp[2] =
 567                                 OMAP_MMC_READ(host, RSP2) |
 568                                 (OMAP_MMC_READ(host, RSP3) << 16);
 569                         cmd->resp[1] =
 570                                 OMAP_MMC_READ(host, RSP4) |
 571                                 (OMAP_MMC_READ(host, RSP5) << 16);
 572                         cmd->resp[0] =
 573                                 OMAP_MMC_READ(host, RSP6) |
 574                                 (OMAP_MMC_READ(host, RSP7) << 16);
 575                 } else {
 576                         /* response types 1, 1b, 3, 4, 5, 6 */
 577                         cmd->resp[0] =
 578                                 OMAP_MMC_READ(host, RSP6) |
 579                                 (OMAP_MMC_READ(host, RSP7) << 16);
 580                 }
 581         }
 582
 583         if (host->data == NULL || cmd->error) {
 584                 struct mmc_host *mmc;
 585
 586                 if (host->data != NULL)
 587                         mmc_omap_abort_xfer(host, host->data);
 588                 host->mrq = NULL;
 589                 mmc = host->mmc;
 590                 mmc_omap_release_slot(host->current_slot, 1);
 591                 mmc_request_done(mmc, cmd->mrq);
 592         }
 593 }
 594
 595 /*
 596  * Abort stuck command. Can occur when card is removed while it is being
 597  * read.
 598  */
 599 static void mmc_omap_abort_command(struct work_struct *work)
 600 {
 601         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 602                                                   cmd_abort_work);
 603         BUG_ON(!host->cmd);
 604
 605         dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
 606                 host->cmd->opcode);
 607
 608         if (host->cmd->error == 0)
 609                 host->cmd->error = -ETIMEDOUT;
 610
 611         if (host->data == NULL) {
 612                 struct mmc_command *cmd;
 613                 struct mmc_host    *mmc;
 614
 615                 cmd = host->cmd;
 616                 host->cmd = NULL;
 617                 mmc_omap_send_abort(host, 10000);
 618
 619                 host->mrq = NULL;
 620                 mmc = host->mmc;
 621                 mmc_omap_release_slot(host->current_slot, 1);
 622                 mmc_request_done(mmc, cmd->mrq);
 623         } else
 624                 mmc_omap_cmd_done(host, host->cmd);
 625
 626         host->abort = 0;
 627         enable_irq(host->irq);
 628 }
 629
 630 static void
 631 mmc_omap_cmd_timer(unsigned long data)
 632 {
 633         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 634         unsigned long flags;
 635
 636         spin_lock_irqsave(&host->slot_lock, flags);
 637         if (host->cmd != NULL && !host->abort) {
 638                 OMAP_MMC_WRITE(host, IE, 0);
 639                 disable_irq(host->irq);
 640                 host->abort = 1;
 641                 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
 642         }
 643         spin_unlock_irqrestore(&host->slot_lock, flags);
 644 }
 645
 646 /* PIO only */
 647 static void
 648 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 649 {
 650         struct scatterlist *sg;
 651
 652         sg = host->data->sg + host->sg_idx;
 653         host->buffer_bytes_left = sg->length;
 654         host->buffer = sg_virt(sg);
 655         if (host->buffer_bytes_left > host->total_bytes_left)
 656                 host->buffer_bytes_left = host->total_bytes_left;
 657 }
 658
 659 static void
 660 mmc_omap_clk_timer(unsigned long data)
 661 {
 662         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 663
 664         mmc_omap_fclk_enable(host, 0);
 665 }
 666
 667 /* PIO only */
 668 static void
 669 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 670 {
 671         int n;
 672
 673         if (host->buffer_bytes_left == 0) {
 674                 host->sg_idx++;
 675                 BUG_ON(host->sg_idx == host->sg_len);
 676                 mmc_omap_sg_to_buf(host);
 677         }
 678         n = 64;
 679         if (n > host->buffer_bytes_left)
 680                 n = host->buffer_bytes_left;
 681         host->buffer_bytes_left -= n;
 682         host->total_bytes_left -= n;
 683         host->data->bytes_xfered += n;
 684
 685         if (write) {
 686                 __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA), host->buffer, n);
 687         } else {
 688                 __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA), host->buffer, n);
 689         }
 690 }
 691
 692 static inline void mmc_omap_report_irq(u16 status)
 693 {
 694         static const char *mmc_omap_status_bits[] = {
 695                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 696                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 697         };
 698         int i, c = 0;
 699
 700         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 701                 if (status & (1 << i)) {
 702                         if (c)
 703                                 printk(" ");
 704                         printk("%s", mmc_omap_status_bits[i]);
 705                         c++;
 706                 }
 707 }
 708
 709 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 710 {
 711         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 712         u16 status;
 713         int end_command;
 714         int end_transfer;
 715         int transfer_error, cmd_error;
 716
 717         if (host->cmd == NULL && host->data == NULL) {
 718                 status = OMAP_MMC_READ(host, STAT);
 719                 dev_info(mmc_dev(host->slots[0]->mmc),
 720                          "Spurious IRQ 0x%04x\n", status);
 721                 if (status != 0) {
 722                         OMAP_MMC_WRITE(host, STAT, status);
 723                         OMAP_MMC_WRITE(host, IE, 0);
 724                 }
 725                 return IRQ_HANDLED;
 726         }
 727
 728         end_command = 0;
 729         end_transfer = 0;
 730         transfer_error = 0;
 731         cmd_error = 0;
 732
 733         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 734                 int cmd;
 735
 736                 OMAP_MMC_WRITE(host, STAT, status);
 737                 if (host->cmd != NULL)
 738                         cmd = host->cmd->opcode;
 739                 else
 740                         cmd = -1;
 741 #ifdef CONFIG_MMC_DEBUG
 742                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 743                         status, cmd);
 744                 mmc_omap_report_irq(status);
 745                 printk("\n");
 746 #endif
 747                 if (host->total_bytes_left) {
 748                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 749                             (status & OMAP_MMC_STAT_END_OF_DATA))
 750                                 mmc_omap_xfer_data(host, 0);
 751                         if (status & OMAP_MMC_STAT_A_EMPTY)
 752                                 mmc_omap_xfer_data(host, 1);
 753                 }
 754
 755                 if (status & OMAP_MMC_STAT_END_OF_DATA)
 756                         end_transfer = 1;
 757
 758                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 759                         dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
 760                                 cmd);
 761                         if (host->data) {
 762                                 host->data->error = -ETIMEDOUT;
 763                                 transfer_error = 1;
 764                         }
 765                 }
 766
 767                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 768                         if (host->data) {
 769                                 host->data->error = -EILSEQ;
 770                                 dev_dbg(mmc_dev(host->mmc),
 771                                          "data CRC error, bytes left %d\n",
 772                                         host->total_bytes_left);
 773                                 transfer_error = 1;
 774                         } else {
 775                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 776                         }
 777                 }
 778
 779                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 780                         /* Timeouts are routine with some commands */
 781                         if (host->cmd) {
 782                                 struct mmc_omap_slot *slot =
 783                                         host->current_slot;
 784                                 if (slot == NULL ||
 785                                     !mmc_omap_cover_is_open(slot))
 786                                         dev_err(mmc_dev(host->mmc),
 787                                                 "command timeout (CMD%d)\n",
 788                                                 cmd);
 789                                 host->cmd->error = -ETIMEDOUT;
 790                                 end_command = 1;
 791                                 cmd_error = 1;
 792                         }
 793                 }
 794
 795                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 796                         if (host->cmd) {
 797                                 dev_err(mmc_dev(host->mmc),
 798                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 799                                         cmd, host->cmd->arg);
 800                                 host->cmd->error = -EILSEQ;
 801                                 end_command = 1;
 802                                 cmd_error = 1;
 803                         } else
 804                                 dev_err(mmc_dev(host->mmc),
 805                                         "command CRC error without cmd?\n");
 806                 }
 807
 808                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 809                         dev_dbg(mmc_dev(host->mmc),
 810                                 "ignoring card status error (CMD%d)\n",
 811                                 cmd);
 812                         end_command = 1;
 813                 }
 814
 815                 /*
 816                  * NOTE: On 1610 the END_OF_CMD may come too early when
 817                  * starting a write
 818                  */
 819                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 820                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 821                         end_command = 1;
 822                 }
 823         }
 824
 825         if (cmd_error && host->data) {
 826                 del_timer(&host->cmd_abort_timer);
 827                 host->abort = 1;
 828                 OMAP_MMC_WRITE(host, IE, 0);
 829                 disable_irq_nosync(host->irq);
 830                 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
 831                 return IRQ_HANDLED;
 832         }
 833
 834         if (end_command && host->cmd)
 835                 mmc_omap_cmd_done(host, host->cmd);
 836         if (host->data != NULL) {
 837                 if (transfer_error)
 838                         mmc_omap_xfer_done(host, host->data);
 839                 else if (end_transfer)
 840                         mmc_omap_end_of_data(host, host->data);
 841         }
 842
 843         return IRQ_HANDLED;
 844 }
 845
 846 void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
 847 {
 848         int cover_open;
 849         struct mmc_omap_host *host = dev_get_drvdata(dev);
 850         struct mmc_omap_slot *slot = host->slots[num];
 851
 852         BUG_ON(num >= host->nr_slots);
 853
 854         /* Other subsystems can call in here before we're initialised. */
 855         if (host->nr_slots == 0 || !host->slots[num])
 856                 return;
 857
 858         cover_open = mmc_omap_cover_is_open(slot);
 859         if (cover_open != slot->cover_open) {
 860                 slot->cover_open = cover_open;
 861                 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
 862         }
 863
 864         tasklet_hi_schedule(&slot->cover_tasklet);
 865 }
 866
 867 static void mmc_omap_cover_timer(unsigned long arg)
 868 {
 869         struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
 870         tasklet_schedule(&slot->cover_tasklet);
 871 }
 872
 873 static void mmc_omap_cover_handler(unsigned long param)
 874 {
 875         struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
 876         int cover_open = mmc_omap_cover_is_open(slot);
 877
 878         mmc_detect_change(slot->mmc, 0);
 879         if (!cover_open)
 880                 return;
 881
 882         /*
 883          * If no card is inserted, we postpone polling until
 884          * the cover has been closed.
 885          */
 886         if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card))
 887                 return;
 888
 889         mod_timer(&slot->cover_timer,
 890                   jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
 891 }
 892
 893 static void mmc_omap_dma_callback(void *priv)
 894 {
 895         struct mmc_omap_host *host = priv;
 896         struct mmc_data *data = host->data;
 897
 898         /* If we got to the end of DMA, assume everything went well */
 899         data->bytes_xfered += data->blocks * data->blksz;
 900
 901         mmc_omap_dma_done(host, data);
 902 }
 903
 904 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 905 {
 906         u16 reg;
 907
 908         reg = OMAP_MMC_READ(host, SDIO);
 909         reg &= ~(1 << 5);
 910         OMAP_MMC_WRITE(host, SDIO, reg);
 911         /* Set maximum timeout */
 912         OMAP_MMC_WRITE(host, CTO, 0xff);
 913 }
 914
 915 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 916 {
 917         unsigned int timeout, cycle_ns;
 918         u16 reg;
 919
 920         cycle_ns = 1000000000 / host->current_slot->fclk_freq;
 921         timeout = req->data->timeout_ns / cycle_ns;
 922         timeout += req->data->timeout_clks;
 923
 924         /* Check if we need to use timeout multiplier register */
 925         reg = OMAP_MMC_READ(host, SDIO);
 926         if (timeout > 0xffff) {
 927                 reg |= (1 << 5);
 928                 timeout /= 1024;
 929         } else
 930                 reg &= ~(1 << 5);
 931         OMAP_MMC_WRITE(host, SDIO, reg);
 932         OMAP_MMC_WRITE(host, DTO, timeout);
 933 }
 934
 935 static void
 936 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 937 {
 938         struct mmc_data *data = req->data;
 939         int i, use_dma, block_size;
 940         unsigned sg_len;
 941
 942         host->data = data;
 943         if (data == NULL) {
 944                 OMAP_MMC_WRITE(host, BLEN, 0);
 945                 OMAP_MMC_WRITE(host, NBLK, 0);
 946                 OMAP_MMC_WRITE(host, BUF, 0);
 947                 host->dma_in_use = 0;
 948                 set_cmd_timeout(host, req);
 949                 return;
 950         }
 951
 952         block_size = data->blksz;
 953
 954         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
 955         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
 956         set_data_timeout(host, req);
 957
 958         /* cope with calling layer confusion; it issues "single
 959          * block" writes using multi-block scatterlists.
 960          */
 961         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
 962
 963         /* Only do DMA for entire blocks */
 964         use_dma = host->use_dma;
 965         if (use_dma) {
 966                 for (i = 0; i < sg_len; i++) {
 967                         if ((data->sg[i].length % block_size) != 0) {
 968                                 use_dma = 0;
 969                                 break;
 970                         }
 971                 }
 972         }
 973
 974         host->sg_idx = 0;
 975         if (use_dma) {
 976                 enum dma_data_direction dma_data_dir;
 977                 struct dma_async_tx_descriptor *tx;
 978                 struct dma_chan *c;
 979                 u32 burst, *bp;
 980                 u16 buf;
 981
 982                 /*
 983                  * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
 984                  * and 24xx. Use 16 or 32 word frames when the
 985                  * blocksize is at least that large. Blocksize is
 986                  * usually 512 bytes; but not for some SD reads.
 987                  */
 988                 burst = cpu_is_omap15xx() ? 32 : 64;
 989                 if (burst > data->blksz)
 990                         burst = data->blksz;
 991
 992                 burst >>= 1;
 993
 994                 if (data->flags & MMC_DATA_WRITE) {
 995                         c = host->dma_tx;
 996                         bp = &host->dma_tx_burst;
 997                         buf = 0x0f80 | (burst - 1) << 0;
 998                         dma_data_dir = DMA_TO_DEVICE;
 999                 } else {
1000                         c = host->dma_rx;
1001                         bp = &host->dma_rx_burst;
1002                         buf = 0x800f | (burst - 1) << 8;
1003                         dma_data_dir = DMA_FROM_DEVICE;
1004                 }
1005
1006                 if (!c)
1007                         goto use_pio;
1008
1009                 /* Only reconfigure if we have a different burst size */
1010                 if (*bp != burst) {
1011                         struct dma_slave_config cfg;
1012
1013                         cfg.src_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1014                         cfg.dst_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1015                         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1016                         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1017                         cfg.src_maxburst = burst;
1018                         cfg.dst_maxburst = burst;
1019
1020                         if (dmaengine_slave_config(c, &cfg))
1021                                 goto use_pio;
1022
1023                         *bp = burst;
1024                 }
1025
1026                 host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
1027                                           dma_data_dir);
1028                 if (host->sg_len == 0)
1029                         goto use_pio;
1030
1031                 tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
1032                         data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1033                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1034                 if (!tx)
1035                         goto use_pio;
1036
1037                 OMAP_MMC_WRITE(host, BUF, buf);
1038
1039                 tx->callback = mmc_omap_dma_callback;
1040                 tx->callback_param = host;
1041                 dmaengine_submit(tx);
1042                 host->brs_received = 0;
1043                 host->dma_done = 0;
1044                 host->dma_in_use = 1;
1045                 return;
1046         }
1047  use_pio:
1048
1049         /* Revert to PIO? */
1050         OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1051         host->total_bytes_left = data->blocks * block_size;
1052         host->sg_len = sg_len;
1053         mmc_omap_sg_to_buf(host);
1054         host->dma_in_use = 0;
1055 }
1056
1057 static void mmc_omap_start_request(struct mmc_omap_host *host,
1058                                    struct mmc_request *req)
1059 {
1060         BUG_ON(host->mrq != NULL);
1061
1062         host->mrq = req;
1063
1064         /* only touch fifo AFTER the controller readies it */
1065         mmc_omap_prepare_data(host, req);
1066         mmc_omap_start_command(host, req->cmd);
1067         if (host->dma_in_use) {
1068                 struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
1069                                 host->dma_tx : host->dma_rx;
1070
1071                 dma_async_issue_pending(c);
1072         }
1073 }
1074
1075 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1076 {
1077         struct mmc_omap_slot *slot = mmc_priv(mmc);
1078         struct mmc_omap_host *host = slot->host;
1079         unsigned long flags;
1080
1081         spin_lock_irqsave(&host->slot_lock, flags);
1082         if (host->mmc != NULL) {
1083                 BUG_ON(slot->mrq != NULL);
1084                 slot->mrq = req;
1085                 spin_unlock_irqrestore(&host->slot_lock, flags);
1086                 return;
1087         } else
1088                 host->mmc = mmc;
1089         spin_unlock_irqrestore(&host->slot_lock, flags);
1090         mmc_omap_select_slot(slot, 1);
1091         mmc_omap_start_request(host, req);
1092 }
1093
1094 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1095                                 int vdd)
1096 {
1097         struct mmc_omap_host *host;
1098
1099         host = slot->host;
1100
1101         if (slot->pdata->set_power != NULL)
1102                 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1103                                         vdd);
1104
1105         if (cpu_is_omap24xx()) {
1106                 u16 w;
1107
1108                 if (power_on) {
1109                         w = OMAP_MMC_READ(host, CON);
1110                         OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1111                 } else {
1112                         w = OMAP_MMC_READ(host, CON);
1113                         OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1114                 }
1115         }
1116 }
1117
1118 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1119 {
1120         struct mmc_omap_slot *slot = mmc_priv(mmc);
1121         struct mmc_omap_host *host = slot->host;
1122         int func_clk_rate = clk_get_rate(host->fclk);
1123         int dsor;
1124
1125         if (ios->clock == 0)
1126                 return 0;
1127
1128         dsor = func_clk_rate / ios->clock;
1129         if (dsor < 1)
1130                 dsor = 1;
1131
1132         if (func_clk_rate / dsor > ios->clock)
1133                 dsor++;
1134
1135         if (dsor > 250)
1136                 dsor = 250;
1137
1138         slot->fclk_freq = func_clk_rate / dsor;
1139
1140         if (ios->bus_width == MMC_BUS_WIDTH_4)
1141                 dsor |= 1 << 15;
1142
1143         return dsor;
1144 }
1145
1146 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1147 {
1148         struct mmc_omap_slot *slot = mmc_priv(mmc);
1149         struct mmc_omap_host *host = slot->host;
1150         int i, dsor;
1151         int clk_enabled;
1152
1153         mmc_omap_select_slot(slot, 0);
1154
1155         dsor = mmc_omap_calc_divisor(mmc, ios);
1156
1157         if (ios->vdd != slot->vdd)
1158                 slot->vdd = ios->vdd;
1159
1160         clk_enabled = 0;
1161         switch (ios->power_mode) {
1162         case MMC_POWER_OFF:
1163                 mmc_omap_set_power(slot, 0, ios->vdd);
1164                 break;
1165         case MMC_POWER_UP:
1166                 /* Cannot touch dsor yet, just power up MMC */
1167                 mmc_omap_set_power(slot, 1, ios->vdd);
1168                 goto exit;
1169         case MMC_POWER_ON:
1170                 mmc_omap_fclk_enable(host, 1);
1171                 clk_enabled = 1;
1172                 dsor |= 1 << 11;
1173                 break;
1174         }
1175
1176         if (slot->bus_mode != ios->bus_mode) {
1177                 if (slot->pdata->set_bus_mode != NULL)
1178                         slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1179                                                   ios->bus_mode);
1180                 slot->bus_mode = ios->bus_mode;
1181         }
1182
1183         /* On insanely high arm_per frequencies something sometimes
1184          * goes somehow out of sync, and the POW bit is not being set,
1185          * which results in the while loop below getting stuck.
1186          * Writing to the CON register twice seems to do the trick. */
1187         for (i = 0; i < 2; i++)
1188                 OMAP_MMC_WRITE(host, CON, dsor);
1189         slot->saved_con = dsor;
1190         if (ios->power_mode == MMC_POWER_ON) {
1191                 /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1192                 int usecs = 250;
1193
1194                 /* Send clock cycles, poll completion */
1195                 OMAP_MMC_WRITE(host, IE, 0);
1196                 OMAP_MMC_WRITE(host, STAT, 0xffff);
1197                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1198                 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1199                         udelay(1);
1200                         usecs--;
1201                 }
1202                 OMAP_MMC_WRITE(host, STAT, 1);
1203         }
1204
1205 exit:
1206         mmc_omap_release_slot(slot, clk_enabled);
1207 }
1208
1209 static const struct mmc_host_ops mmc_omap_ops = {
1210         .request        = mmc_omap_request,
1211         .set_ios        = mmc_omap_set_ios,
1212 };
1213
1214 static int __devinit mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1215 {
1216         struct mmc_omap_slot *slot = NULL;
1217         struct mmc_host *mmc;
1218         int r;
1219
1220         mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1221         if (mmc == NULL)
1222                 return -ENOMEM;
1223
1224         slot = mmc_priv(mmc);
1225         slot->host = host;
1226         slot->mmc = mmc;
1227         slot->id = id;
1228         slot->pdata = &host->pdata->slots[id];
1229
1230         host->slots[id] = slot;
1231
1232         mmc->caps = 0;
1233         if (host->pdata->slots[id].wires >= 4)
1234                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1235
1236         mmc->ops = &mmc_omap_ops;
1237         mmc->f_min = 400000;
1238
1239         if (cpu_class_is_omap2())
1240                 mmc->f_max = 48000000;
1241         else
1242                 mmc->f_max = 24000000;
1243         if (host->pdata->max_freq)
1244                 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1245         mmc->ocr_avail = slot->pdata->ocr_mask;
1246
1247         /* Use scatterlist DMA to reduce per-transfer costs.
1248          * NOTE max_seg_size assumption that small blocks aren't
1249          * normally used (except e.g. for reading SD registers).
1250          */
1251         mmc->max_segs = 32;
1252         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
1253         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
1254         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1255         mmc->max_seg_size = mmc->max_req_size;
1256
1257         r = mmc_add_host(mmc);
1258         if (r < 0)
1259                 goto err_remove_host;
1260
1261         if (slot->pdata->name != NULL) {
1262                 r = device_create_file(&mmc->class_dev,
1263                                         &dev_attr_slot_name);
1264                 if (r < 0)
1265                         goto err_remove_host;
1266         }
1267
1268         if (slot->pdata->get_cover_state != NULL) {
1269                 r = device_create_file(&mmc->class_dev,
1270                                         &dev_attr_cover_switch);
1271                 if (r < 0)
1272                         goto err_remove_slot_name;
1273
1274                 setup_timer(&slot->cover_timer, mmc_omap_cover_timer,
1275                             (unsigned long)slot);
1276                 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
1277                              (unsigned long)slot);
1278                 tasklet_schedule(&slot->cover_tasklet);
1279         }
1280
1281         return 0;
1282
1283 err_remove_slot_name:
1284         if (slot->pdata->name != NULL)
1285                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1286 err_remove_host:
1287         mmc_remove_host(mmc);
1288         mmc_free_host(mmc);
1289         return r;
1290 }
1291
1292 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1293 {
1294         struct mmc_host *mmc = slot->mmc;
1295
1296         if (slot->pdata->name != NULL)
1297                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1298         if (slot->pdata->get_cover_state != NULL)
1299                 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1300
1301         tasklet_kill(&slot->cover_tasklet);
1302         del_timer_sync(&slot->cover_timer);
1303         flush_workqueue(slot->host->mmc_omap_wq);
1304
1305         mmc_remove_host(mmc);
1306         mmc_free_host(mmc);
1307 }
1308
1309 static int __devinit mmc_omap_probe(struct platform_device *pdev)
1310 {
1311         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1312         struct mmc_omap_host *host = NULL;
1313         struct resource *res;
1314         dma_cap_mask_t mask;
1315         unsigned sig;
1316         int i, ret = 0;
1317         int irq;
1318
1319         if (pdata == NULL) {
1320                 dev_err(&pdev->dev, "platform data missing\n");
1321                 return -ENXIO;
1322         }
1323         if (pdata->nr_slots == 0) {
1324                 dev_err(&pdev->dev, "no slots\n");
1325                 return -ENXIO;
1326         }
1327
1328         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1329         irq = platform_get_irq(pdev, 0);
1330         if (res == NULL || irq < 0)
1331                 return -ENXIO;
1332
1333         res = request_mem_region(res->start, resource_size(res),
1334                                  pdev->name);
1335         if (res == NULL)
1336                 return -EBUSY;
1337
1338         host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1339         if (host == NULL) {
1340                 ret = -ENOMEM;
1341                 goto err_free_mem_region;
1342         }
1343
1344         INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1345         INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1346
1347         INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1348         setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer,
1349                     (unsigned long) host);
1350
1351         spin_lock_init(&host->clk_lock);
1352         setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host);
1353
1354         spin_lock_init(&host->dma_lock);
1355         spin_lock_init(&host->slot_lock);
1356         init_waitqueue_head(&host->slot_wq);
1357
1358         host->pdata = pdata;
1359         host->dev = &pdev->dev;
1360         platform_set_drvdata(pdev, host);
1361
1362         host->id = pdev->id;
1363         host->mem_res = res;
1364         host->irq = irq;
1365         host->use_dma = 1;
1366         host->irq = irq;
1367         host->phys_base = host->mem_res->start;
1368         host->virt_base = ioremap(res->start, resource_size(res));
1369         if (!host->virt_base)
1370                 goto err_ioremap;
1371
1372         host->iclk = clk_get(&pdev->dev, "ick");
1373         if (IS_ERR(host->iclk)) {
1374                 ret = PTR_ERR(host->iclk);
1375                 goto err_free_mmc_host;
1376         }
1377         clk_enable(host->iclk);
1378
1379         host->fclk = clk_get(&pdev->dev, "fck");
1380         if (IS_ERR(host->fclk)) {
1381                 ret = PTR_ERR(host->fclk);
1382                 goto err_free_iclk;
1383         }
1384
1385         dma_cap_zero(mask);
1386         dma_cap_set(DMA_SLAVE, mask);
1387
1388         host->dma_tx_burst = -1;
1389         host->dma_rx_burst = -1;
1390
1391         if (cpu_is_omap24xx())
1392                 sig = host->id == 0 ? OMAP24XX_DMA_MMC1_TX : OMAP24XX_DMA_MMC2_TX;
1393         else
1394                 sig = host->id == 0 ? OMAP_DMA_MMC_TX : OMAP_DMA_MMC2_TX;
1395         host->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1396 #if 0
1397         if (!host->dma_tx) {
1398                 dev_err(host->dev, "unable to obtain TX DMA engine channel %u\n",
1399                         sig);
1400                 goto err_dma;
1401         }
1402 #else
1403         if (!host->dma_tx)
1404                 dev_warn(host->dev, "unable to obtain TX DMA engine channel %u\n",
1405                         sig);
1406 #endif
1407         if (cpu_is_omap24xx())
1408                 sig = host->id == 0 ? OMAP24XX_DMA_MMC1_RX : OMAP24XX_DMA_MMC2_RX;
1409         else
1410                 sig = host->id == 0 ? OMAP_DMA_MMC_RX : OMAP_DMA_MMC2_RX;
1411         host->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1412 #if 0
1413         if (!host->dma_rx) {
1414                 dev_err(host->dev, "unable to obtain RX DMA engine channel %u\n",
1415                         sig);
1416                 goto err_dma;
1417         }
1418 #else
1419         if (!host->dma_rx)
1420                 dev_warn(host->dev, "unable to obtain RX DMA engine channel %u\n",
1421                         sig);
1422 #endif
1423
1424         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1425         if (ret)
1426                 goto err_free_dma;
1427
1428         if (pdata->init != NULL) {
1429                 ret = pdata->init(&pdev->dev);
1430                 if (ret < 0)
1431                         goto err_free_irq;
1432         }
1433
1434         host->nr_slots = pdata->nr_slots;
1435         host->reg_shift = (cpu_is_omap7xx() ? 1 : 2);
1436
1437         host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
1438         if (!host->mmc_omap_wq)
1439                 goto err_plat_cleanup;
1440
1441         for (i = 0; i < pdata->nr_slots; i++) {
1442                 ret = mmc_omap_new_slot(host, i);
1443                 if (ret < 0) {
1444                         while (--i >= 0)
1445                                 mmc_omap_remove_slot(host->slots[i]);
1446
1447                         goto err_destroy_wq;
1448                 }
1449         }
1450
1451         return 0;
1452
1453 err_destroy_wq:
1454         destroy_workqueue(host->mmc_omap_wq);
1455 err_plat_cleanup:
1456         if (pdata->cleanup)
1457                 pdata->cleanup(&pdev->dev);
1458 err_free_irq:
1459         free_irq(host->irq, host);
1460 err_free_dma:
1461         if (host->dma_tx)
1462                 dma_release_channel(host->dma_tx);
1463         if (host->dma_rx)
1464                 dma_release_channel(host->dma_rx);
1465         clk_put(host->fclk);
1466 err_free_iclk:
1467         clk_disable(host->iclk);
1468         clk_put(host->iclk);
1469 err_free_mmc_host:
1470         iounmap(host->virt_base);
1471 err_ioremap:
1472         kfree(host);
1473 err_free_mem_region:
1474         release_mem_region(res->start, resource_size(res));
1475         return ret;
1476 }
1477
1478 static int __devexit mmc_omap_remove(struct platform_device *pdev)
1479 {
1480         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1481         int i;
1482
1483         platform_set_drvdata(pdev, NULL);
1484
1485         BUG_ON(host == NULL);
1486
1487         for (i = 0; i < host->nr_slots; i++)
1488                 mmc_omap_remove_slot(host->slots[i]);
1489
1490         if (host->pdata->cleanup)
1491                 host->pdata->cleanup(&pdev->dev);
1492
1493         mmc_omap_fclk_enable(host, 0);
1494         free_irq(host->irq, host);
1495         clk_put(host->fclk);
1496         clk_disable(host->iclk);
1497         clk_put(host->iclk);
1498
1499         if (host->dma_tx)
1500                 dma_release_channel(host->dma_tx);
1501         if (host->dma_rx)
1502                 dma_release_channel(host->dma_rx);
1503
1504         iounmap(host->virt_base);
1505         release_mem_region(pdev->resource[0].start,
1506                            pdev->resource[0].end - pdev->resource[0].start + 1);
1507         destroy_workqueue(host->mmc_omap_wq);
1508
1509         kfree(host);
1510
1511         return 0;
1512 }
1513
1514 #ifdef CONFIG_PM
1515 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1516 {
1517         int i, ret = 0;
1518         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1519
1520         if (host == NULL || host->suspended)
1521                 return 0;
1522
1523         for (i = 0; i < host->nr_slots; i++) {
1524                 struct mmc_omap_slot *slot;
1525
1526                 slot = host->slots[i];
1527                 ret = mmc_suspend_host(slot->mmc);
1528                 if (ret < 0) {
1529                         while (--i >= 0) {
1530                                 slot = host->slots[i];
1531                                 mmc_resume_host(slot->mmc);
1532                         }
1533                         return ret;
1534                 }
1535         }
1536         host->suspended = 1;
1537         return 0;
1538 }
1539
1540 static int mmc_omap_resume(struct platform_device *pdev)
1541 {
1542         int i, ret = 0;
1543         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1544
1545         if (host == NULL || !host->suspended)
1546                 return 0;
1547
1548         for (i = 0; i < host->nr_slots; i++) {
1549                 struct mmc_omap_slot *slot;
1550                 slot = host->slots[i];
1551                 ret = mmc_resume_host(slot->mmc);
1552                 if (ret < 0)
1553                         return ret;
1554
1555                 host->suspended = 0;
1556         }
1557         return 0;
1558 }
1559 #else
1560 #define mmc_omap_suspend        NULL
1561 #define mmc_omap_resume         NULL
1562 #endif
1563
1564 static struct platform_driver mmc_omap_driver = {
1565         .probe          = mmc_omap_probe,
1566         .remove         = __devexit_p(mmc_omap_remove),
1567         .suspend        = mmc_omap_suspend,
1568         .resume         = mmc_omap_resume,
1569         .driver         = {
1570                 .name   = DRIVER_NAME,
1571                 .owner  = THIS_MODULE,
1572         },
1573 };
1574
1575 module_platform_driver(mmc_omap_driver);
1576 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1577 MODULE_LICENSE("GPL");
1578 MODULE_ALIAS("platform:" DRIVER_NAME);
1579 MODULE_AUTHOR("Juha Yrjölä");