drivers/mmc/host/dw_mmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/blkdev.h>
  15 #include <linux/clk.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/ioport.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/seq_file.h>
  26 #include <linux/slab.h>
  27 #include <linux/stat.h>
  28 #include <linux/delay.h>
  29 #include <linux/irq.h>
  30 #include <linux/mmc/card.h>
  31 #include <linux/mmc/host.h>
  32 #include <linux/mmc/mmc.h>
  33 #include <linux/mmc/sd.h>
  34 #include <linux/mmc/sdio.h>
  35 #include <linux/mmc/dw_mmc.h>
  36 #include <linux/bitops.h>
  37 #include <linux/regulator/consumer.h>
  38 #include <linux/of.h>
  39 #include <linux/of_gpio.h>
  40 #include <linux/mmc/slot-gpio.h>
  41
  42 #include "dw_mmc.h"
  43
  44 /* Common flag combinations */
  45 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
  46                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
  47                                  SDMMC_INT_EBE | SDMMC_INT_HLE)
  48 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  49                                  SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
  50 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  51                                  DW_MCI_CMD_ERROR_FLAGS)
  52 #define DW_MCI_SEND_STATUS      1
  53 #define DW_MCI_RECV_STATUS      2
  54 #define DW_MCI_DMA_THRESHOLD    16
  55
  56 #define DW_MCI_FREQ_MAX 200000000       /* unit: HZ */
  57 #define DW_MCI_FREQ_MIN 400000          /* unit: HZ */
  58
  59 #define IDMAC_INT_CLR           (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  60                                  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  61                                  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
  62                                  SDMMC_IDMAC_INT_TI)
  63
  64 struct idmac_desc_64addr {
  65         u32             des0;   /* Control Descriptor */
  66
  67         u32             des1;   /* Reserved */
  68
  69         u32             des2;   /*Buffer sizes */
  70 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
  71         ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
  72          ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
  73
  74         u32             des3;   /* Reserved */
  75
  76         u32             des4;   /* Lower 32-bits of Buffer Address Pointer 1*/
  77         u32             des5;   /* Upper 32-bits of Buffer Address Pointer 1*/
  78
  79         u32             des6;   /* Lower 32-bits of Next Descriptor Address */
  80         u32             des7;   /* Upper 32-bits of Next Descriptor Address */
  81 };
  82
  83 struct idmac_desc {
  84         __le32          des0;   /* Control Descriptor */
  85 #define IDMAC_DES0_DIC  BIT(1)
  86 #define IDMAC_DES0_LD   BIT(2)
  87 #define IDMAC_DES0_FD   BIT(3)
  88 #define IDMAC_DES0_CH   BIT(4)
  89 #define IDMAC_DES0_ER   BIT(5)
  90 #define IDMAC_DES0_CES  BIT(30)
  91 #define IDMAC_DES0_OWN  BIT(31)
  92
  93         __le32          des1;   /* Buffer sizes */
  94 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  95         ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
  96
  97         __le32          des2;   /* buffer 1 physical address */
  98
  99         __le32          des3;   /* buffer 2 physical address */
 100 };
 101
 102 /* Each descriptor can transfer up to 4KB of data in chained mode */
 103 #define DW_MCI_DESC_DATA_LENGTH 0x1000
 104
 105 static bool dw_mci_reset(struct dw_mci *host);
 106 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
 107 static int dw_mci_card_busy(struct mmc_host *mmc);
 108 static int dw_mci_get_cd(struct mmc_host *mmc);
 109
 110 #if defined(CONFIG_DEBUG_FS)
 111 static int dw_mci_req_show(struct seq_file *s, void *v)
 112 {
 113         struct dw_mci_slot *slot = s->private;
 114         struct mmc_request *mrq;
 115         struct mmc_command *cmd;
 116         struct mmc_command *stop;
 117         struct mmc_data *data;
 118
 119         /* Make sure we get a consistent snapshot */
 120         spin_lock_bh(&slot->host->lock);
 121         mrq = slot->mrq;
 122
 123         if (mrq) {
 124                 cmd = mrq->cmd;
 125                 data = mrq->data;
 126                 stop = mrq->stop;
 127
 128                 if (cmd)
 129                         seq_printf(s,
 130                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 131                                    cmd->opcode, cmd->arg, cmd->flags,
 132                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 133                                    cmd->resp[2], cmd->error);
 134                 if (data)
 135                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 136                                    data->bytes_xfered, data->blocks,
 137                                    data->blksz, data->flags, data->error);
 138                 if (stop)
 139                         seq_printf(s,
 140                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 141                                    stop->opcode, stop->arg, stop->flags,
 142                                    stop->resp[0], stop->resp[1], stop->resp[2],
 143                                    stop->resp[2], stop->error);
 144         }
 145
 146         spin_unlock_bh(&slot->host->lock);
 147
 148         return 0;
 149 }
 150
 151 static int dw_mci_req_open(struct inode *inode, struct file *file)
 152 {
 153         return single_open(file, dw_mci_req_show, inode->i_private);
 154 }
 155
 156 static const struct file_operations dw_mci_req_fops = {
 157         .owner          = THIS_MODULE,
 158         .open           = dw_mci_req_open,
 159         .read           = seq_read,
 160         .llseek         = seq_lseek,
 161         .release        = single_release,
 162 };
 163
 164 static int dw_mci_regs_show(struct seq_file *s, void *v)
 165 {
 166         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
 167         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
 168         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
 169         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
 170         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
 171         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
 172
 173         return 0;
 174 }
 175
 176 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 177 {
 178         return single_open(file, dw_mci_regs_show, inode->i_private);
 179 }
 180
 181 static const struct file_operations dw_mci_regs_fops = {
 182         .owner          = THIS_MODULE,
 183         .open           = dw_mci_regs_open,
 184         .read           = seq_read,
 185         .llseek         = seq_lseek,
 186         .release        = single_release,
 187 };
 188
 189 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 190 {
 191         struct mmc_host *mmc = slot->mmc;
 192         struct dw_mci *host = slot->host;
 193         struct dentry *root;
 194         struct dentry *node;
 195
 196         root = mmc->debugfs_root;
 197         if (!root)
 198                 return;
 199
 200         node = debugfs_create_file("regs", S_IRUSR, root, host,
 201                                    &dw_mci_regs_fops);
 202         if (!node)
 203                 goto err;
 204
 205         node = debugfs_create_file("req", S_IRUSR, root, slot,
 206                                    &dw_mci_req_fops);
 207         if (!node)
 208                 goto err;
 209
 210         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 211         if (!node)
 212                 goto err;
 213
 214         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 215                                   (u32 *)&host->pending_events);
 216         if (!node)
 217                 goto err;
 218
 219         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 220                                   (u32 *)&host->completed_events);
 221         if (!node)
 222                 goto err;
 223
 224         return;
 225
 226 err:
 227         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 228 }
 229 #endif /* defined(CONFIG_DEBUG_FS) */
 230
 231 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
 232
 233 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 234 {
 235         struct mmc_data *data;
 236         struct dw_mci_slot *slot = mmc_priv(mmc);
 237         struct dw_mci *host = slot->host;
 238         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
 239         u32 cmdr;
 240
 241         cmd->error = -EINPROGRESS;
 242         cmdr = cmd->opcode;
 243
 244         if (cmd->opcode == MMC_STOP_TRANSMISSION ||
 245             cmd->opcode == MMC_GO_IDLE_STATE ||
 246             cmd->opcode == MMC_GO_INACTIVE_STATE ||
 247             (cmd->opcode == SD_IO_RW_DIRECT &&
 248              ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
 249                 cmdr |= SDMMC_CMD_STOP;
 250         else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
 251                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 252
 253         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
 254                 u32 clk_en_a;
 255
 256                 /* Special bit makes CMD11 not die */
 257                 cmdr |= SDMMC_CMD_VOLT_SWITCH;
 258
 259                 /* Change state to continue to handle CMD11 weirdness */
 260                 WARN_ON(slot->host->state != STATE_SENDING_CMD);
 261                 slot->host->state = STATE_SENDING_CMD11;
 262
 263                 /*
 264                  * We need to disable low power mode (automatic clock stop)
 265                  * while doing voltage switch so we don't confuse the card,
 266                  * since stopping the clock is a specific part of the UHS
 267                  * voltage change dance.
 268                  *
 269                  * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
 270                  * unconditionally turned back on in dw_mci_setup_bus() if it's
 271                  * ever called with a non-zero clock.  That shouldn't happen
 272                  * until the voltage change is all done.
 273                  */
 274                 clk_en_a = mci_readl(host, CLKENA);
 275                 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
 276                 mci_writel(host, CLKENA, clk_en_a);
 277                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
 278                              SDMMC_CMD_PRV_DAT_WAIT, 0);
 279         }
 280
 281         if (cmd->flags & MMC_RSP_PRESENT) {
 282                 /* We expect a response, so set this bit */
 283                 cmdr |= SDMMC_CMD_RESP_EXP;
 284                 if (cmd->flags & MMC_RSP_136)
 285                         cmdr |= SDMMC_CMD_RESP_LONG;
 286         }
 287
 288         if (cmd->flags & MMC_RSP_CRC)
 289                 cmdr |= SDMMC_CMD_RESP_CRC;
 290
 291         data = cmd->data;
 292         if (data) {
 293                 cmdr |= SDMMC_CMD_DAT_EXP;
 294                 if (data->flags & MMC_DATA_STREAM)
 295                         cmdr |= SDMMC_CMD_STRM_MODE;
 296                 if (data->flags & MMC_DATA_WRITE)
 297                         cmdr |= SDMMC_CMD_DAT_WR;
 298         }
 299
 300         if (drv_data && drv_data->prepare_command)
 301                 drv_data->prepare_command(slot->host, &cmdr);
 302
 303         return cmdr;
 304 }
 305
 306 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
 307 {
 308         struct mmc_command *stop;
 309         u32 cmdr;
 310
 311         if (!cmd->data)
 312                 return 0;
 313
 314         stop = &host->stop_abort;
 315         cmdr = cmd->opcode;
 316         memset(stop, 0, sizeof(struct mmc_command));
 317
 318         if (cmdr == MMC_READ_SINGLE_BLOCK ||
 319             cmdr == MMC_READ_MULTIPLE_BLOCK ||
 320             cmdr == MMC_WRITE_BLOCK ||
 321             cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
 322             cmdr == MMC_SEND_TUNING_BLOCK ||
 323             cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
 324                 stop->opcode = MMC_STOP_TRANSMISSION;
 325                 stop->arg = 0;
 326                 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
 327         } else if (cmdr == SD_IO_RW_EXTENDED) {
 328                 stop->opcode = SD_IO_RW_DIRECT;
 329                 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
 330                              ((cmd->arg >> 28) & 0x7);
 331                 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
 332         } else {
 333                 return 0;
 334         }
 335
 336         cmdr = stop->opcode | SDMMC_CMD_STOP |
 337                 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
 338
 339         return cmdr;
 340 }
 341
 342 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
 343 {
 344         unsigned long timeout = jiffies + msecs_to_jiffies(500);
 345
 346         /*
 347          * Databook says that before issuing a new data transfer command
 348          * we need to check to see if the card is busy.  Data transfer commands
 349          * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
 350          *
 351          * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
 352          * expected.
 353          */
 354         if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
 355             !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
 356                 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {
 357                         if (time_after(jiffies, timeout)) {
 358                                 /* Command will fail; we'll pass error then */
 359                                 dev_err(host->dev, "Busy; trying anyway\n");
 360                                 break;
 361                         }
 362                         udelay(10);
 363                 }
 364         }
 365 }
 366
 367 static void dw_mci_start_command(struct dw_mci *host,
 368                                  struct mmc_command *cmd, u32 cmd_flags)
 369 {
 370         host->cmd = cmd;
 371         dev_vdbg(host->dev,
 372                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
 373                  cmd->arg, cmd_flags);
 374
 375         mci_writel(host, CMDARG, cmd->arg);
 376         wmb(); /* drain writebuffer */
 377         dw_mci_wait_while_busy(host, cmd_flags);
 378
 379         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 380 }
 381
 382 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
 383 {
 384         struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
 385
 386         dw_mci_start_command(host, stop, host->stop_cmdr);
 387 }
 388
 389 /* DMA interface functions */
 390 static void dw_mci_stop_dma(struct dw_mci *host)
 391 {
 392         if (host->using_dma) {
 393                 host->dma_ops->stop(host);
 394                 host->dma_ops->cleanup(host);
 395         }
 396
 397         /* Data transfer was stopped by the interrupt handler */
 398         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 399 }
 400
 401 static int dw_mci_get_dma_dir(struct mmc_data *data)
 402 {
 403         if (data->flags & MMC_DATA_WRITE)
 404                 return DMA_TO_DEVICE;
 405         else
 406                 return DMA_FROM_DEVICE;
 407 }
 408
 409 static void dw_mci_dma_cleanup(struct dw_mci *host)
 410 {
 411         struct mmc_data *data = host->data;
 412
 413         if (data)
 414                 if (!data->host_cookie)
 415                         dma_unmap_sg(host->dev,
 416                                      data->sg,
 417                                      data->sg_len,
 418                                      dw_mci_get_dma_dir(data));
 419 }
 420
 421 static void dw_mci_idmac_reset(struct dw_mci *host)
 422 {
 423         u32 bmod = mci_readl(host, BMOD);
 424         /* Software reset of DMA */
 425         bmod |= SDMMC_IDMAC_SWRESET;
 426         mci_writel(host, BMOD, bmod);
 427 }
 428
 429 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 430 {
 431         u32 temp;
 432
 433         /* Disable and reset the IDMAC interface */
 434         temp = mci_readl(host, CTRL);
 435         temp &= ~SDMMC_CTRL_USE_IDMAC;
 436         temp |= SDMMC_CTRL_DMA_RESET;
 437         mci_writel(host, CTRL, temp);
 438
 439         /* Stop the IDMAC running */
 440         temp = mci_readl(host, BMOD);
 441         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 442         temp |= SDMMC_IDMAC_SWRESET;
 443         mci_writel(host, BMOD, temp);
 444 }
 445
 446 static void dw_mci_dmac_complete_dma(void *arg)
 447 {
 448         struct dw_mci *host = arg;
 449         struct mmc_data *data = host->data;
 450
 451         dev_vdbg(host->dev, "DMA complete\n");
 452
 453         if ((host->use_dma == TRANS_MODE_EDMAC) &&
 454             data && (data->flags & MMC_DATA_READ))
 455                 /* Invalidate cache after read */
 456                 dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc),
 457                                     data->sg,
 458                                     data->sg_len,
 459                                     DMA_FROM_DEVICE);
 460
 461         host->dma_ops->cleanup(host);
 462
 463         /*
 464          * If the card was removed, data will be NULL. No point in trying to
 465          * send the stop command or waiting for NBUSY in this case.
 466          */
 467         if (data) {
 468                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 469                 tasklet_schedule(&host->tasklet);
 470         }
 471 }
 472
 473 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
 474                                     unsigned int sg_len)
 475 {
 476         unsigned int desc_len;
 477         int i;
 478
 479         if (host->dma_64bit_address == 1) {
 480                 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
 481
 482                 desc_first = desc_last = desc = host->sg_cpu;
 483
 484                 for (i = 0; i < sg_len; i++) {
 485                         unsigned int length = sg_dma_len(&data->sg[i]);
 486
 487                         u64 mem_addr = sg_dma_address(&data->sg[i]);
 488
 489                         for ( ; length ; desc++) {
 490                                 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
 491                                            length : DW_MCI_DESC_DATA_LENGTH;
 492
 493                                 length -= desc_len;
 494
 495                                 /*
 496                                  * Set the OWN bit and disable interrupts
 497                                  * for this descriptor
 498                                  */
 499                                 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
 500                                                         IDMAC_DES0_CH;
 501
 502                                 /* Buffer length */
 503                                 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
 504
 505                                 /* Physical address to DMA to/from */
 506                                 desc->des4 = mem_addr & 0xffffffff;
 507                                 desc->des5 = mem_addr >> 32;
 508
 509                                 /* Update physical address for the next desc */
 510                                 mem_addr += desc_len;
 511
 512                                 /* Save pointer to the last descriptor */
 513                                 desc_last = desc;
 514                         }
 515                 }
 516
 517                 /* Set first descriptor */
 518                 desc_first->des0 |= IDMAC_DES0_FD;
 519
 520                 /* Set last descriptor */
 521                 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 522                 desc_last->des0 |= IDMAC_DES0_LD;
 523
 524         } else {
 525                 struct idmac_desc *desc_first, *desc_last, *desc;
 526
 527                 desc_first = desc_last = desc = host->sg_cpu;
 528
 529                 for (i = 0; i < sg_len; i++) {
 530                         unsigned int length = sg_dma_len(&data->sg[i]);
 531
 532                         u32 mem_addr = sg_dma_address(&data->sg[i]);
 533
 534                         for ( ; length ; desc++) {
 535                                 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
 536                                            length : DW_MCI_DESC_DATA_LENGTH;
 537
 538                                 length -= desc_len;
 539
 540                                 /*
 541                                  * Set the OWN bit and disable interrupts
 542                                  * for this descriptor
 543                                  */
 544                                 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
 545                                                          IDMAC_DES0_DIC |
 546                                                          IDMAC_DES0_CH);
 547
 548                                 /* Buffer length */
 549                                 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
 550
 551                                 /* Physical address to DMA to/from */
 552                                 desc->des2 = cpu_to_le32(mem_addr);
 553
 554                                 /* Update physical address for the next desc */
 555                                 mem_addr += desc_len;
 556
 557                                 /* Save pointer to the last descriptor */
 558                                 desc_last = desc;
 559                         }
 560                 }
 561
 562                 /* Set first descriptor */
 563                 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
 564
 565                 /* Set last descriptor */
 566                 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
 567                                                IDMAC_DES0_DIC));
 568                 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
 569         }
 570
 571         wmb(); /* drain writebuffer */
 572 }
 573
 574 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 575 {
 576         u32 temp;
 577
 578         dw_mci_translate_sglist(host, host->data, sg_len);
 579
 580         /* Make sure to reset DMA in case we did PIO before this */
 581         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
 582         dw_mci_idmac_reset(host);
 583
 584         /* Select IDMAC interface */
 585         temp = mci_readl(host, CTRL);
 586         temp |= SDMMC_CTRL_USE_IDMAC;
 587         mci_writel(host, CTRL, temp);
 588
 589         /* drain writebuffer */
 590         wmb();
 591
 592         /* Enable the IDMAC */
 593         temp = mci_readl(host, BMOD);
 594         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 595         mci_writel(host, BMOD, temp);
 596
 597         /* Start it running */
 598         mci_writel(host, PLDMND, 1);
 599
 600         return 0;
 601 }
 602
 603 static int dw_mci_idmac_init(struct dw_mci *host)
 604 {
 605         int i;
 606
 607         if (host->dma_64bit_address == 1) {
 608                 struct idmac_desc_64addr *p;
 609                 /* Number of descriptors in the ring buffer */
 610                 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr);
 611
 612                 /* Forward link the descriptor list */
 613                 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
 614                                                                 i++, p++) {
 615                         p->des6 = (host->sg_dma +
 616                                         (sizeof(struct idmac_desc_64addr) *
 617                                                         (i + 1))) & 0xffffffff;
 618
 619                         p->des7 = (u64)(host->sg_dma +
 620                                         (sizeof(struct idmac_desc_64addr) *
 621                                                         (i + 1))) >> 32;
 622                         /* Initialize reserved and buffer size fields to "0" */
 623                         p->des1 = 0;
 624                         p->des2 = 0;
 625                         p->des3 = 0;
 626                 }
 627
 628                 /* Set the last descriptor as the end-of-ring descriptor */
 629                 p->des6 = host->sg_dma & 0xffffffff;
 630                 p->des7 = (u64)host->sg_dma >> 32;
 631                 p->des0 = IDMAC_DES0_ER;
 632
 633         } else {
 634                 struct idmac_desc *p;
 635                 /* Number of descriptors in the ring buffer */
 636                 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
 637
 638                 /* Forward link the descriptor list */
 639                 for (i = 0, p = host->sg_cpu;
 640                      i < host->ring_size - 1;
 641                      i++, p++) {
 642                         p->des3 = cpu_to_le32(host->sg_dma +
 643                                         (sizeof(struct idmac_desc) * (i + 1)));
 644                         p->des1 = 0;
 645                 }
 646
 647                 /* Set the last descriptor as the end-of-ring descriptor */
 648                 p->des3 = cpu_to_le32(host->sg_dma);
 649                 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
 650         }
 651
 652         dw_mci_idmac_reset(host);
 653
 654         if (host->dma_64bit_address == 1) {
 655                 /* Mask out interrupts - get Tx & Rx complete only */
 656                 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
 657                 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
 658                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
 659
 660                 /* Set the descriptor base address */
 661                 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
 662                 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
 663
 664         } else {
 665                 /* Mask out interrupts - get Tx & Rx complete only */
 666                 mci_writel(host, IDSTS, IDMAC_INT_CLR);
 667                 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
 668                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
 669
 670                 /* Set the descriptor base address */
 671                 mci_writel(host, DBADDR, host->sg_dma);
 672         }
 673
 674         return 0;
 675 }
 676
 677 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
 678         .init = dw_mci_idmac_init,
 679         .start = dw_mci_idmac_start_dma,
 680         .stop = dw_mci_idmac_stop_dma,
 681         .complete = dw_mci_dmac_complete_dma,
 682         .cleanup = dw_mci_dma_cleanup,
 683 };
 684
 685 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
 686 {
 687         dmaengine_terminate_all(host->dms->ch);
 688 }
 689
 690 static int dw_mci_edmac_start_dma(struct dw_mci *host,
 691                                             unsigned int sg_len)
 692 {
 693         struct dma_slave_config cfg;
 694         struct dma_async_tx_descriptor *desc = NULL;
 695         struct scatterlist *sgl = host->data->sg;
 696         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 697         u32 sg_elems = host->data->sg_len;
 698         u32 fifoth_val;
 699         u32 fifo_offset = host->fifo_reg - host->regs;
 700         int ret = 0;
 701
 702         /* Set external dma config: burst size, burst width */
 703         cfg.dst_addr = (dma_addr_t)(host->phy_regs + fifo_offset);
 704         cfg.src_addr = cfg.dst_addr;
 705         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 706         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 707
 708         /* Match burst msize with external dma config */
 709         fifoth_val = mci_readl(host, FIFOTH);
 710         cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
 711         cfg.src_maxburst = cfg.dst_maxburst;
 712
 713         if (host->data->flags & MMC_DATA_WRITE)
 714                 cfg.direction = DMA_MEM_TO_DEV;
 715         else
 716                 cfg.direction = DMA_DEV_TO_MEM;
 717
 718         ret = dmaengine_slave_config(host->dms->ch, &cfg);
 719         if (ret) {
 720                 dev_err(host->dev, "Failed to config edmac.\n");
 721                 return -EBUSY;
 722         }
 723
 724         desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
 725                                        sg_len, cfg.direction,
 726                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 727         if (!desc) {
 728                 dev_err(host->dev, "Can't prepare slave sg.\n");
 729                 return -EBUSY;
 730         }
 731
 732         /* Set dw_mci_dmac_complete_dma as callback */
 733         desc->callback = dw_mci_dmac_complete_dma;
 734         desc->callback_param = (void *)host;
 735         dmaengine_submit(desc);
 736
 737         /* Flush cache before write */
 738         if (host->data->flags & MMC_DATA_WRITE)
 739                 dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl,
 740                                        sg_elems, DMA_TO_DEVICE);
 741
 742         dma_async_issue_pending(host->dms->ch);
 743
 744         return 0;
 745 }
 746
 747 static int dw_mci_edmac_init(struct dw_mci *host)
 748 {
 749         /* Request external dma channel */
 750         host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
 751         if (!host->dms)
 752                 return -ENOMEM;
 753
 754         host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
 755         if (!host->dms->ch) {
 756                 dev_err(host->dev, "Failed to get external DMA channel.\n");
 757                 kfree(host->dms);
 758                 host->dms = NULL;
 759                 return -ENXIO;
 760         }
 761
 762         return 0;
 763 }
 764
 765 static void dw_mci_edmac_exit(struct dw_mci *host)
 766 {
 767         if (host->dms) {
 768                 if (host->dms->ch) {
 769                         dma_release_channel(host->dms->ch);
 770                         host->dms->ch = NULL;
 771                 }
 772                 kfree(host->dms);
 773                 host->dms = NULL;
 774         }
 775 }
 776
 777 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
 778         .init = dw_mci_edmac_init,
 779         .exit = dw_mci_edmac_exit,
 780         .start = dw_mci_edmac_start_dma,
 781         .stop = dw_mci_edmac_stop_dma,
 782         .complete = dw_mci_dmac_complete_dma,
 783         .cleanup = dw_mci_dma_cleanup,
 784 };
 785
 786 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 787                                    struct mmc_data *data,
 788                                    bool next)
 789 {
 790         struct scatterlist *sg;
 791         unsigned int i, sg_len;
 792
 793         if (!next && data->host_cookie)
 794                 return data->host_cookie;
 795
 796         /*
 797          * We don't do DMA on "complex" transfers, i.e. with
 798          * non-word-aligned buffers or lengths. Also, we don't bother
 799          * with all the DMA setup overhead for short transfers.
 800          */
 801         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 802                 return -EINVAL;
 803
 804         if (data->blksz & 3)
 805                 return -EINVAL;
 806
 807         for_each_sg(data->sg, sg, data->sg_len, i) {
 808                 if (sg->offset & 3 || sg->length & 3)
 809                         return -EINVAL;
 810         }
 811
 812         sg_len = dma_map_sg(host->dev,
 813                             data->sg,
 814                             data->sg_len,
 815                             dw_mci_get_dma_dir(data));
 816         if (sg_len == 0)
 817                 return -EINVAL;
 818
 819         if (next)
 820                 data->host_cookie = sg_len;
 821
 822         return sg_len;
 823 }
 824
 825 static void dw_mci_pre_req(struct mmc_host *mmc,
 826                            struct mmc_request *mrq,
 827                            bool is_first_req)
 828 {
 829         struct dw_mci_slot *slot = mmc_priv(mmc);
 830         struct mmc_data *data = mrq->data;
 831
 832         if (!slot->host->use_dma || !data)
 833                 return;
 834
 835         if (data->host_cookie) {
 836                 data->host_cookie = 0;
 837                 return;
 838         }
 839
 840         if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
 841                 data->host_cookie = 0;
 842 }
 843
 844 static void dw_mci_post_req(struct mmc_host *mmc,
 845                             struct mmc_request *mrq,
 846                             int err)
 847 {
 848         struct dw_mci_slot *slot = mmc_priv(mmc);
 849         struct mmc_data *data = mrq->data;
 850
 851         if (!slot->host->use_dma || !data)
 852                 return;
 853
 854         if (data->host_cookie)
 855                 dma_unmap_sg(slot->host->dev,
 856                              data->sg,
 857                              data->sg_len,
 858                              dw_mci_get_dma_dir(data));
 859         data->host_cookie = 0;
 860 }
 861
 862 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
 863 {
 864         unsigned int blksz = data->blksz;
 865         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 866         u32 fifo_width = 1 << host->data_shift;
 867         u32 blksz_depth = blksz / fifo_width, fifoth_val;
 868         u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
 869         int idx = ARRAY_SIZE(mszs) - 1;
 870
 871         /* pio should ship this scenario */
 872         if (!host->use_dma)
 873                 return;
 874
 875         tx_wmark = (host->fifo_depth) / 2;
 876         tx_wmark_invers = host->fifo_depth - tx_wmark;
 877
 878         /*
 879          * MSIZE is '1',
 880          * if blksz is not a multiple of the FIFO width
 881          */
 882         if (blksz % fifo_width) {
 883                 msize = 0;
 884                 rx_wmark = 1;
 885                 goto done;
 886         }
 887
 888         do {
 889                 if (!((blksz_depth % mszs[idx]) ||
 890                      (tx_wmark_invers % mszs[idx]))) {
 891                         msize = idx;
 892                         rx_wmark = mszs[idx] - 1;
 893                         break;
 894                 }
 895         } while (--idx > 0);
 896         /*
 897          * If idx is '0', it won't be tried
 898          * Thus, initial values are uesed
 899          */
 900 done:
 901         fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
 902         mci_writel(host, FIFOTH, fifoth_val);
 903 }
 904
 905 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
 906 {
 907         unsigned int blksz = data->blksz;
 908         u32 blksz_depth, fifo_depth;
 909         u16 thld_size;
 910
 911         WARN_ON(!(data->flags & MMC_DATA_READ));
 912
 913         /*
 914          * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
 915          * in the FIFO region, so we really shouldn't access it).
 916          */
 917         if (host->verid < DW_MMC_240A)
 918                 return;
 919
 920         if (host->timing != MMC_TIMING_MMC_HS200 &&
 921             host->timing != MMC_TIMING_MMC_HS400 &&
 922             host->timing != MMC_TIMING_UHS_SDR104)
 923                 goto disable;
 924
 925         blksz_depth = blksz / (1 << host->data_shift);
 926         fifo_depth = host->fifo_depth;
 927
 928         if (blksz_depth > fifo_depth)
 929                 goto disable;
 930
 931         /*
 932          * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
 933          * If (blksz_depth) <  (fifo_depth >> 1), should be thld_size = blksz
 934          * Currently just choose blksz.
 935          */
 936         thld_size = blksz;
 937         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
 938         return;
 939
 940 disable:
 941         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
 942 }
 943
 944 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
 945 {
 946         unsigned long irqflags;
 947         int sg_len;
 948         u32 temp;
 949
 950         host->using_dma = 0;
 951
 952         /* If we don't have a channel, we can't do DMA */
 953         if (!host->use_dma)
 954                 return -ENODEV;
 955
 956         sg_len = dw_mci_pre_dma_transfer(host, data, 0);
 957         if (sg_len < 0) {
 958                 host->dma_ops->stop(host);
 959                 return sg_len;
 960         }
 961
 962         host->using_dma = 1;
 963
 964         if (host->use_dma == TRANS_MODE_IDMAC)
 965                 dev_vdbg(host->dev,
 966                          "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
 967                          (unsigned long)host->sg_cpu,
 968                          (unsigned long)host->sg_dma,
 969                          sg_len);
 970
 971         /*
 972          * Decide the MSIZE and RX/TX Watermark.
 973          * If current block size is same with previous size,
 974          * no need to update fifoth.
 975          */
 976         if (host->prev_blksz != data->blksz)
 977                 dw_mci_adjust_fifoth(host, data);
 978
 979         /* Enable the DMA interface */
 980         temp = mci_readl(host, CTRL);
 981         temp |= SDMMC_CTRL_DMA_ENABLE;
 982         mci_writel(host, CTRL, temp);
 983
 984         /* Disable RX/TX IRQs, let DMA handle it */
 985         spin_lock_irqsave(&host->irq_lock, irqflags);
 986         temp = mci_readl(host, INTMASK);
 987         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
 988         mci_writel(host, INTMASK, temp);
 989         spin_unlock_irqrestore(&host->irq_lock, irqflags);
 990
 991         if (host->dma_ops->start(host, sg_len)) {
 992                 /* We can't do DMA */
 993                 dev_err(host->dev, "%s: failed to start DMA.\n", __func__);
 994                 return -ENODEV;
 995         }
 996
 997         return 0;
 998 }
 999
1000 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1001 {
1002         unsigned long irqflags;
1003         int flags = SG_MITER_ATOMIC;
1004         u32 temp;
1005
1006         data->error = -EINPROGRESS;
1007
1008         WARN_ON(host->data);
1009         host->sg = NULL;
1010         host->data = data;
1011
1012         if (data->flags & MMC_DATA_READ) {
1013                 host->dir_status = DW_MCI_RECV_STATUS;
1014                 dw_mci_ctrl_rd_thld(host, data);
1015         } else {
1016                 host->dir_status = DW_MCI_SEND_STATUS;
1017         }
1018
1019         if (dw_mci_submit_data_dma(host, data)) {
1020                 if (host->data->flags & MMC_DATA_READ)
1021                         flags |= SG_MITER_TO_SG;
1022                 else
1023                         flags |= SG_MITER_FROM_SG;
1024
1025                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1026                 host->sg = data->sg;
1027                 host->part_buf_start = 0;
1028                 host->part_buf_count = 0;
1029
1030                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1031
1032                 spin_lock_irqsave(&host->irq_lock, irqflags);
1033                 temp = mci_readl(host, INTMASK);
1034                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1035                 mci_writel(host, INTMASK, temp);
1036                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1037
1038                 temp = mci_readl(host, CTRL);
1039                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1040                 mci_writel(host, CTRL, temp);
1041
1042                 /*
1043                  * Use the initial fifoth_val for PIO mode.
1044                  * If next issued data may be transfered by DMA mode,
1045                  * prev_blksz should be invalidated.
1046                  */
1047                 mci_writel(host, FIFOTH, host->fifoth_val);
1048                 host->prev_blksz = 0;
1049         } else {
1050                 /*
1051                  * Keep the current block size.
1052                  * It will be used to decide whether to update
1053                  * fifoth register next time.
1054                  */
1055                 host->prev_blksz = data->blksz;
1056         }
1057 }
1058
1059 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
1060 {
1061         struct dw_mci *host = slot->host;
1062         unsigned long timeout = jiffies + msecs_to_jiffies(500);
1063         unsigned int cmd_status = 0;
1064
1065         mci_writel(host, CMDARG, arg);
1066         wmb(); /* drain writebuffer */
1067         dw_mci_wait_while_busy(host, cmd);
1068         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
1069
1070         while (time_before(jiffies, timeout)) {
1071                 cmd_status = mci_readl(host, CMD);
1072                 if (!(cmd_status & SDMMC_CMD_START))
1073                         return;
1074         }
1075         dev_err(&slot->mmc->class_dev,
1076                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1077                 cmd, arg, cmd_status);
1078 }
1079
1080 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1081 {
1082         struct dw_mci *host = slot->host;
1083         unsigned int clock = slot->clock;
1084         u32 div;
1085         u32 clk_en_a;
1086         u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1087
1088         /* We must continue to set bit 28 in CMD until the change is complete */
1089         if (host->state == STATE_WAITING_CMD11_DONE)
1090                 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1091
1092         if (!clock) {
1093                 mci_writel(host, CLKENA, 0);
1094                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1095         } else if (clock != host->current_speed || force_clkinit) {
1096                 div = host->bus_hz / clock;
1097                 if (host->bus_hz % clock && host->bus_hz > clock)
1098                         /*
1099                          * move the + 1 after the divide to prevent
1100                          * over-clocking the card.
1101                          */
1102                         div += 1;
1103
1104                 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1105
1106                 if ((clock << div) != slot->__clk_old || force_clkinit)
1107                         dev_info(&slot->mmc->class_dev,
1108                                  "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1109                                  slot->id, host->bus_hz, clock,
1110                                  div ? ((host->bus_hz / div) >> 1) :
1111                                  host->bus_hz, div);
1112
1113                 /* disable clock */
1114                 mci_writel(host, CLKENA, 0);
1115                 mci_writel(host, CLKSRC, 0);
1116
1117                 /* inform CIU */
1118                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1119
1120                 /* set clock to desired speed */
1121                 mci_writel(host, CLKDIV, div);
1122
1123                 /* inform CIU */
1124                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1125
1126                 /* enable clock; only low power if no SDIO */
1127                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1128                 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1129                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1130                 mci_writel(host, CLKENA, clk_en_a);
1131
1132                 /* inform CIU */
1133                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1134
1135                 /* keep the clock with reflecting clock dividor */
1136                 slot->__clk_old = clock << div;
1137         }
1138
1139         host->current_speed = clock;
1140
1141         /* Set the current slot bus width */
1142         mci_writel(host, CTYPE, (slot->ctype << slot->id));
1143 }
1144
1145 static void __dw_mci_start_request(struct dw_mci *host,
1146                                    struct dw_mci_slot *slot,
1147                                    struct mmc_command *cmd)
1148 {
1149         struct mmc_request *mrq;
1150         struct mmc_data *data;
1151         u32 cmdflags;
1152
1153         mrq = slot->mrq;
1154
1155         host->cur_slot = slot;
1156         host->mrq = mrq;
1157
1158         host->pending_events = 0;
1159         host->completed_events = 0;
1160         host->cmd_status = 0;
1161         host->data_status = 0;
1162         host->dir_status = 0;
1163
1164         data = cmd->data;
1165         if (data) {
1166                 mci_writel(host, TMOUT, 0xFFFFFFFF);
1167                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1168                 mci_writel(host, BLKSIZ, data->blksz);
1169         }
1170
1171         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1172
1173         /* this is the first command, send the initialization clock */
1174         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1175                 cmdflags |= SDMMC_CMD_INIT;
1176
1177         if (data) {
1178                 dw_mci_submit_data(host, data);
1179                 wmb(); /* drain writebuffer */
1180         }
1181
1182         dw_mci_start_command(host, cmd, cmdflags);
1183
1184         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1185                 unsigned long irqflags;
1186
1187                 /*
1188                  * Databook says to fail after 2ms w/ no response, but evidence
1189                  * shows that sometimes the cmd11 interrupt takes over 130ms.
1190                  * We'll set to 500ms, plus an extra jiffy just in case jiffies
1191                  * is just about to roll over.
1192                  *
1193                  * We do this whole thing under spinlock and only if the
1194                  * command hasn't already completed (indicating the the irq
1195                  * already ran so we don't want the timeout).
1196                  */
1197                 spin_lock_irqsave(&host->irq_lock, irqflags);
1198                 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1199                         mod_timer(&host->cmd11_timer,
1200                                 jiffies + msecs_to_jiffies(500) + 1);
1201                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1202         }
1203
1204         if (mrq->stop)
1205                 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
1206         else
1207                 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1208 }
1209
1210 static void dw_mci_start_request(struct dw_mci *host,
1211                                  struct dw_mci_slot *slot)
1212 {
1213         struct mmc_request *mrq = slot->mrq;
1214         struct mmc_command *cmd;
1215
1216         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1217         __dw_mci_start_request(host, slot, cmd);
1218 }
1219
1220 /* must be called with host->lock held */
1221 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1222                                  struct mmc_request *mrq)
1223 {
1224         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1225                  host->state);
1226
1227         slot->mrq = mrq;
1228
1229         if (host->state == STATE_WAITING_CMD11_DONE) {
1230                 dev_warn(&slot->mmc->class_dev,
1231                          "Voltage change didn't complete\n");
1232                 /*
1233                  * this case isn't expected to happen, so we can
1234                  * either crash here or just try to continue on
1235                  * in the closest possible state
1236                  */
1237                 host->state = STATE_IDLE;
1238         }
1239
1240         if (host->state == STATE_IDLE) {
1241                 host->state = STATE_SENDING_CMD;
1242                 dw_mci_start_request(host, slot);
1243         } else {
1244                 list_add_tail(&slot->queue_node, &host->queue);
1245         }
1246 }
1247
1248 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1249 {
1250         struct dw_mci_slot *slot = mmc_priv(mmc);
1251         struct dw_mci *host = slot->host;
1252
1253         WARN_ON(slot->mrq);
1254
1255         /*
1256          * The check for card presence and queueing of the request must be
1257          * atomic, otherwise the card could be removed in between and the
1258          * request wouldn't fail until another card was inserted.
1259          */
1260
1261         if (!dw_mci_get_cd(mmc)) {
1262                 mrq->cmd->error = -ENOMEDIUM;
1263                 mmc_request_done(mmc, mrq);
1264                 return;
1265         }
1266
1267         spin_lock_bh(&host->lock);
1268
1269         dw_mci_queue_request(host, slot, mrq);
1270
1271         spin_unlock_bh(&host->lock);
1272 }
1273
1274 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1275 {
1276         struct dw_mci_slot *slot = mmc_priv(mmc);
1277         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1278         u32 regs;
1279         int ret;
1280
1281         switch (ios->bus_width) {
1282         case MMC_BUS_WIDTH_4:
1283                 slot->ctype = SDMMC_CTYPE_4BIT;
1284                 break;
1285         case MMC_BUS_WIDTH_8:
1286                 slot->ctype = SDMMC_CTYPE_8BIT;
1287                 break;
1288         default:
1289                 /* set default 1 bit mode */
1290                 slot->ctype = SDMMC_CTYPE_1BIT;
1291         }
1292
1293         regs = mci_readl(slot->host, UHS_REG);
1294
1295         /* DDR mode set */
1296         if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1297             ios->timing == MMC_TIMING_UHS_DDR50 ||
1298             ios->timing == MMC_TIMING_MMC_HS400)
1299                 regs |= ((0x1 << slot->id) << 16);
1300         else
1301                 regs &= ~((0x1 << slot->id) << 16);
1302
1303         mci_writel(slot->host, UHS_REG, regs);
1304         slot->host->timing = ios->timing;
1305
1306         /*
1307          * Use mirror of ios->clock to prevent race with mmc
1308          * core ios update when finding the minimum.
1309          */
1310         slot->clock = ios->clock;
1311
1312         if (drv_data && drv_data->set_ios)
1313                 drv_data->set_ios(slot->host, ios);
1314
1315         switch (ios->power_mode) {
1316         case MMC_POWER_UP:
1317                 if (!IS_ERR(mmc->supply.vmmc)) {
1318                         ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1319                                         ios->vdd);
1320                         if (ret) {
1321                                 dev_err(slot->host->dev,
1322                                         "failed to enable vmmc regulator\n");
1323                                 /*return, if failed turn on vmmc*/
1324                                 return;
1325                         }
1326                 }
1327                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1328                 regs = mci_readl(slot->host, PWREN);
1329                 regs |= (1 << slot->id);
1330                 mci_writel(slot->host, PWREN, regs);
1331                 break;
1332         case MMC_POWER_ON:
1333                 if (!slot->host->vqmmc_enabled) {
1334                         if (!IS_ERR(mmc->supply.vqmmc)) {
1335                                 ret = regulator_enable(mmc->supply.vqmmc);
1336                                 if (ret < 0)
1337                                         dev_err(slot->host->dev,
1338                                                 "failed to enable vqmmc\n");
1339                                 else
1340                                         slot->host->vqmmc_enabled = true;
1341
1342                         } else {
1343                                 /* Keep track so we don't reset again */
1344                                 slot->host->vqmmc_enabled = true;
1345                         }
1346
1347                         /* Reset our state machine after powering on */
1348                         dw_mci_ctrl_reset(slot->host,
1349                                           SDMMC_CTRL_ALL_RESET_FLAGS);
1350                 }
1351
1352                 /* Adjust clock / bus width after power is up */
1353                 dw_mci_setup_bus(slot, false);
1354
1355                 break;
1356         case MMC_POWER_OFF:
1357                 /* Turn clock off before power goes down */
1358                 dw_mci_setup_bus(slot, false);
1359
1360                 if (!IS_ERR(mmc->supply.vmmc))
1361                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1362
1363                 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1364                         regulator_disable(mmc->supply.vqmmc);
1365                 slot->host->vqmmc_enabled = false;
1366
1367                 regs = mci_readl(slot->host, PWREN);
1368                 regs &= ~(1 << slot->id);
1369                 mci_writel(slot->host, PWREN, regs);
1370                 break;
1371         default:
1372                 break;
1373         }
1374
1375         if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1376                 slot->host->state = STATE_IDLE;
1377 }
1378
1379 static int dw_mci_card_busy(struct mmc_host *mmc)
1380 {
1381         struct dw_mci_slot *slot = mmc_priv(mmc);
1382         u32 status;
1383
1384         /*
1385          * Check the busy bit which is low when DAT[3:0]
1386          * (the data lines) are 0000
1387          */
1388         status = mci_readl(slot->host, STATUS);
1389
1390         return !!(status & SDMMC_STATUS_BUSY);
1391 }
1392
1393 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1394 {
1395         struct dw_mci_slot *slot = mmc_priv(mmc);
1396         struct dw_mci *host = slot->host;
1397         const struct dw_mci_drv_data *drv_data = host->drv_data;
1398         u32 uhs;
1399         u32 v18 = SDMMC_UHS_18V << slot->id;
1400         int ret;
1401
1402         if (drv_data && drv_data->switch_voltage)
1403                 return drv_data->switch_voltage(mmc, ios);
1404
1405         /*
1406          * Program the voltage.  Note that some instances of dw_mmc may use
1407          * the UHS_REG for this.  For other instances (like exynos) the UHS_REG
1408          * does no harm but you need to set the regulator directly.  Try both.
1409          */
1410         uhs = mci_readl(host, UHS_REG);
1411         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1412                 uhs &= ~v18;
1413         else
1414                 uhs |= v18;
1415
1416         if (!IS_ERR(mmc->supply.vqmmc)) {
1417                 ret = mmc_regulator_set_vqmmc(mmc, ios);
1418
1419                 if (ret) {
1420                         dev_dbg(&mmc->class_dev,
1421                                          "Regulator set error %d - %s V\n",
1422                                          ret, uhs & v18 ? "1.8" : "3.3");
1423                         return ret;
1424                 }
1425         }
1426         mci_writel(host, UHS_REG, uhs);
1427
1428         return 0;
1429 }
1430
1431 static int dw_mci_get_ro(struct mmc_host *mmc)
1432 {
1433         int read_only;
1434         struct dw_mci_slot *slot = mmc_priv(mmc);
1435         int gpio_ro = mmc_gpio_get_ro(mmc);
1436
1437         /* Use platform get_ro function, else try on board write protect */
1438         if (!IS_ERR_VALUE(gpio_ro))
1439                 read_only = gpio_ro;
1440         else
1441                 read_only =
1442                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1443
1444         dev_dbg(&mmc->class_dev, "card is %s\n",
1445                 read_only ? "read-only" : "read-write");
1446
1447         return read_only;
1448 }
1449
1450 static int dw_mci_set_sdio_status(struct mmc_host *mmc, int val)
1451 {
1452         struct dw_mci_slot *slot = mmc_priv(mmc);
1453         struct dw_mci *host = slot->host;
1454
1455         if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
1456                 return 0;
1457
1458         spin_lock_bh(&host->lock);
1459
1460         if (val)
1461                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1462         else
1463                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1464
1465         spin_unlock_bh(&host->lock);
1466
1467         mmc_detect_change(slot->mmc, 20);
1468
1469         return 0;
1470 }
1471
1472 static int dw_mci_get_cd(struct mmc_host *mmc)
1473 {
1474         int present;
1475         struct dw_mci_slot *slot = mmc_priv(mmc);
1476         struct dw_mci_board *brd = slot->host->pdata;
1477         struct dw_mci *host = slot->host;
1478         int gpio_cd = mmc_gpio_get_cd(mmc);
1479
1480         /* Use platform get_cd function, else try onboard card detect */
1481         if ((brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) ||
1482             (mmc->caps & MMC_CAP_NONREMOVABLE))
1483                 present = 1;
1484         else if (!IS_ERR_VALUE(gpio_cd))
1485                 present = gpio_cd;
1486         else
1487                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1488                         == 0 ? 1 : 0;
1489
1490         spin_lock_bh(&host->lock);
1491         if (present) {
1492                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1493                 dev_dbg(&mmc->class_dev, "card is present\n");
1494         } else {
1495                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1496                 dev_dbg(&mmc->class_dev, "card is not present\n");
1497         }
1498         spin_unlock_bh(&host->lock);
1499
1500         return present;
1501 }
1502
1503 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1504 {
1505         struct dw_mci_slot *slot = mmc_priv(mmc);
1506         struct dw_mci *host = slot->host;
1507
1508         /*
1509          * Low power mode will stop the card clock when idle.  According to the
1510          * description of the CLKENA register we should disable low power mode
1511          * for SDIO cards if we need SDIO interrupts to work.
1512          */
1513         if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1514                 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1515                 u32 clk_en_a_old;
1516                 u32 clk_en_a;
1517
1518                 clk_en_a_old = mci_readl(host, CLKENA);
1519
1520                 if (card->type == MMC_TYPE_SDIO ||
1521                     card->type == MMC_TYPE_SD_COMBO) {
1522                         set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1523                         clk_en_a = clk_en_a_old & ~clken_low_pwr;
1524                 } else {
1525                         clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1526                         clk_en_a = clk_en_a_old | clken_low_pwr;
1527                 }
1528
1529                 if (clk_en_a != clk_en_a_old) {
1530                         mci_writel(host, CLKENA, clk_en_a);
1531                         mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1532                                      SDMMC_CMD_PRV_DAT_WAIT, 0);
1533                 }
1534         }
1535 }
1536
1537 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1538 {
1539         struct dw_mci_slot *slot = mmc_priv(mmc);
1540         struct dw_mci *host = slot->host;
1541         unsigned long irqflags;
1542         u32 int_mask;
1543
1544         spin_lock_irqsave(&host->irq_lock, irqflags);
1545
1546         /* Enable/disable Slot Specific SDIO interrupt */
1547         int_mask = mci_readl(host, INTMASK);
1548         if (enb)
1549                 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1550         else
1551                 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1552         mci_writel(host, INTMASK, int_mask);
1553
1554         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1555 }
1556
1557 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1558 {
1559         struct dw_mci_slot *slot = mmc_priv(mmc);
1560         struct dw_mci *host = slot->host;
1561         const struct dw_mci_drv_data *drv_data = host->drv_data;
1562         int err = -EINVAL;
1563
1564         if (drv_data && drv_data->execute_tuning)
1565                 err = drv_data->execute_tuning(slot, opcode);
1566         return err;
1567 }
1568
1569 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1570                                        struct mmc_ios *ios)
1571 {
1572         struct dw_mci_slot *slot = mmc_priv(mmc);
1573         struct dw_mci *host = slot->host;
1574         const struct dw_mci_drv_data *drv_data = host->drv_data;
1575
1576         if (drv_data && drv_data->prepare_hs400_tuning)
1577                 return drv_data->prepare_hs400_tuning(host, ios);
1578
1579         return 0;
1580 }
1581
1582 static const struct mmc_host_ops dw_mci_ops = {
1583         .request                = dw_mci_request,
1584         .pre_req                = dw_mci_pre_req,
1585         .post_req               = dw_mci_post_req,
1586         .set_ios                = dw_mci_set_ios,
1587         .set_sdio_status        = dw_mci_set_sdio_status,
1588         .get_ro                 = dw_mci_get_ro,
1589         .get_cd                 = dw_mci_get_cd,
1590         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
1591         .execute_tuning         = dw_mci_execute_tuning,
1592         .card_busy              = dw_mci_card_busy,
1593         .start_signal_voltage_switch = dw_mci_switch_voltage,
1594         .init_card              = dw_mci_init_card,
1595         .prepare_hs400_tuning   = dw_mci_prepare_hs400_tuning,
1596 };
1597
1598 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1599         __releases(&host->lock)
1600         __acquires(&host->lock)
1601 {
1602         struct dw_mci_slot *slot;
1603         struct mmc_host *prev_mmc = host->cur_slot->mmc;
1604
1605         WARN_ON(host->cmd || host->data);
1606
1607         host->cur_slot->mrq = NULL;
1608         host->mrq = NULL;
1609         if (!list_empty(&host->queue)) {
1610                 slot = list_entry(host->queue.next,
1611                                   struct dw_mci_slot, queue_node);
1612                 list_del(&slot->queue_node);
1613                 dev_vdbg(host->dev, "list not empty: %s is next\n",
1614                          mmc_hostname(slot->mmc));
1615                 host->state = STATE_SENDING_CMD;
1616                 dw_mci_start_request(host, slot);
1617         } else {
1618                 dev_vdbg(host->dev, "list empty\n");
1619
1620                 if (host->state == STATE_SENDING_CMD11)
1621                         host->state = STATE_WAITING_CMD11_DONE;
1622                 else
1623                         host->state = STATE_IDLE;
1624         }
1625
1626         spin_unlock(&host->lock);
1627         mmc_request_done(prev_mmc, mrq);
1628         spin_lock(&host->lock);
1629 }
1630
1631 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1632 {
1633         u32 status = host->cmd_status;
1634
1635         host->cmd_status = 0;
1636
1637         /* Read the response from the card (up to 16 bytes) */
1638         if (cmd->flags & MMC_RSP_PRESENT) {
1639                 if (cmd->flags & MMC_RSP_136) {
1640                         cmd->resp[3] = mci_readl(host, RESP0);
1641                         cmd->resp[2] = mci_readl(host, RESP1);
1642                         cmd->resp[1] = mci_readl(host, RESP2);
1643                         cmd->resp[0] = mci_readl(host, RESP3);
1644                 } else {
1645                         cmd->resp[0] = mci_readl(host, RESP0);
1646                         cmd->resp[1] = 0;
1647                         cmd->resp[2] = 0;
1648                         cmd->resp[3] = 0;
1649                 }
1650         }
1651
1652         if (status & SDMMC_INT_RTO)
1653                 cmd->error = -ETIMEDOUT;
1654         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1655                 cmd->error = -EILSEQ;
1656         else if (status & SDMMC_INT_RESP_ERR)
1657                 cmd->error = -EIO;
1658         else
1659                 cmd->error = 0;
1660
1661         if (cmd->error) {
1662                 /* newer ip versions need a delay between retries */
1663                 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
1664                         mdelay(20);
1665         }
1666
1667         return cmd->error;
1668 }
1669
1670 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1671 {
1672         u32 status = host->data_status;
1673
1674         if (status & DW_MCI_DATA_ERROR_FLAGS) {
1675                 if (status & SDMMC_INT_DRTO) {
1676                         data->error = -ETIMEDOUT;
1677                 } else if (status & SDMMC_INT_DCRC) {
1678                         data->error = -EILSEQ;
1679                 } else if (status & SDMMC_INT_EBE) {
1680                         if (host->dir_status ==
1681                                 DW_MCI_SEND_STATUS) {
1682                                 /*
1683                                  * No data CRC status was returned.
1684                                  * The number of bytes transferred
1685                                  * will be exaggerated in PIO mode.
1686                                  */
1687                                 data->bytes_xfered = 0;
1688                                 data->error = -ETIMEDOUT;
1689                         } else if (host->dir_status ==
1690                                         DW_MCI_RECV_STATUS) {
1691                                 data->error = -EIO;
1692                         }
1693                 } else {
1694                         /* SDMMC_INT_SBE is included */
1695                         data->error = -EIO;
1696                 }
1697
1698                 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1699
1700                 /*
1701                  * After an error, there may be data lingering
1702                  * in the FIFO
1703                  */
1704                 dw_mci_reset(host);
1705         } else {
1706                 data->bytes_xfered = data->blocks * data->blksz;
1707                 data->error = 0;
1708         }
1709
1710         return data->error;
1711 }
1712
1713 static void dw_mci_set_drto(struct dw_mci *host)
1714 {
1715         unsigned int drto_clks;
1716         unsigned int drto_ms;
1717
1718         drto_clks = mci_readl(host, TMOUT) >> 8;
1719         drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1720
1721         /* add a bit spare time */
1722         drto_ms += 10;
1723
1724         mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1725 }
1726
1727 static void dw_mci_tasklet_func(unsigned long priv)
1728 {
1729         struct dw_mci *host = (struct dw_mci *)priv;
1730         struct mmc_data *data;
1731         struct mmc_command *cmd;
1732         struct mmc_request *mrq;
1733         enum dw_mci_state state;
1734         enum dw_mci_state prev_state;
1735         unsigned int err;
1736
1737         spin_lock(&host->lock);
1738
1739         state = host->state;
1740         data = host->data;
1741         mrq = host->mrq;
1742
1743         do {
1744                 prev_state = state;
1745
1746                 switch (state) {
1747                 case STATE_IDLE:
1748                 case STATE_WAITING_CMD11_DONE:
1749                         break;
1750
1751                 case STATE_SENDING_CMD11:
1752                 case STATE_SENDING_CMD:
1753                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1754                                                 &host->pending_events))
1755                                 break;
1756
1757                         cmd = host->cmd;
1758                         host->cmd = NULL;
1759                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1760                         err = dw_mci_command_complete(host, cmd);
1761                         if (cmd == mrq->sbc && !err) {
1762                                 prev_state = state = STATE_SENDING_CMD;
1763                                 __dw_mci_start_request(host, host->cur_slot,
1764                                                        mrq->cmd);
1765                                 goto unlock;
1766                         }
1767
1768                         if (cmd->data && err) {
1769                                 dw_mci_stop_dma(host);
1770                                 send_stop_abort(host, data);
1771                                 state = STATE_SENDING_STOP;
1772                                 break;
1773                         }
1774
1775                         if (!cmd->data || err) {
1776                                 dw_mci_request_end(host, mrq);
1777                                 goto unlock;
1778                         }
1779
1780                         prev_state = state = STATE_SENDING_DATA;
1781                         /* fall through */
1782
1783                 case STATE_SENDING_DATA:
1784                         /*
1785                          * We could get a data error and never a transfer
1786                          * complete so we'd better check for it here.
1787                          *
1788                          * Note that we don't really care if we also got a
1789                          * transfer complete; stopping the DMA and sending an
1790                          * abort won't hurt.
1791                          */
1792                         if (test_and_clear_bit(EVENT_DATA_ERROR,
1793                                                &host->pending_events)) {
1794                                 dw_mci_stop_dma(host);
1795                                 if (data->stop ||
1796                                     !(host->data_status & (SDMMC_INT_DRTO |
1797                                                            SDMMC_INT_EBE)))
1798                                         send_stop_abort(host, data);
1799                                 state = STATE_DATA_ERROR;
1800                                 break;
1801                         }
1802
1803                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1804                                                 &host->pending_events)) {
1805                                 /*
1806                                  * If all data-related interrupts don't come
1807                                  * within the given time in reading data state.
1808                                  */
1809                                 if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) &&
1810                                     (host->dir_status == DW_MCI_RECV_STATUS))
1811                                         dw_mci_set_drto(host);
1812                                 break;
1813                         }
1814
1815                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1816
1817                         /*
1818                          * Handle an EVENT_DATA_ERROR that might have shown up
1819                          * before the transfer completed.  This might not have
1820                          * been caught by the check above because the interrupt
1821                          * could have gone off between the previous check and
1822                          * the check for transfer complete.
1823                          *
1824                          * Technically this ought not be needed assuming we
1825                          * get a DATA_COMPLETE eventually (we'll notice the
1826                          * error and end the request), but it shouldn't hurt.
1827                          *
1828                          * This has the advantage of sending the stop command.
1829                          */
1830                         if (test_and_clear_bit(EVENT_DATA_ERROR,
1831                                                &host->pending_events)) {
1832                                 dw_mci_stop_dma(host);
1833                                 if (data->stop ||
1834                                     !(host->data_status & (SDMMC_INT_DRTO |
1835                                                            SDMMC_INT_EBE)))
1836                                         send_stop_abort(host, data);
1837                                 state = STATE_DATA_ERROR;
1838                                 break;
1839                         }
1840                         prev_state = state = STATE_DATA_BUSY;
1841
1842                         /* fall through */
1843
1844                 case STATE_DATA_BUSY:
1845                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1846                                                 &host->pending_events)) {
1847                                 /*
1848                                  * If data error interrupt comes but data over
1849                                  * interrupt doesn't come within the given time.
1850                                  * in reading data state.
1851                                  */
1852                                 if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) &&
1853                                     (host->dir_status == DW_MCI_RECV_STATUS))
1854                                         dw_mci_set_drto(host);
1855                                 break;
1856                         }
1857
1858                         host->data = NULL;
1859                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1860                         err = dw_mci_data_complete(host, data);
1861
1862                         if (!err) {
1863                                 if (!data->stop || mrq->sbc) {
1864                                         if (mrq->sbc && data->stop)
1865                                                 data->stop->error = 0;
1866                                         dw_mci_request_end(host, mrq);
1867                                         goto unlock;
1868                                 }
1869
1870                                 /* stop command for open-ended transfer*/
1871                                 if (data->stop)
1872                                         send_stop_abort(host, data);
1873                         } else {
1874                                 /*
1875                                  * If we don't have a command complete now we'll
1876                                  * never get one since we just reset everything;
1877                                  * better end the request.
1878                                  *
1879                                  * If we do have a command complete we'll fall
1880                                  * through to the SENDING_STOP command and
1881                                  * everything will be peachy keen.
1882                                  */
1883                                 if (!test_bit(EVENT_CMD_COMPLETE,
1884                                               &host->pending_events)) {
1885                                         host->cmd = NULL;
1886                                         dw_mci_request_end(host, mrq);
1887                                         goto unlock;
1888                                 }
1889                         }
1890
1891                         /*
1892                          * If err has non-zero,
1893                          * stop-abort command has been already issued.
1894                          */
1895                         prev_state = state = STATE_SENDING_STOP;
1896
1897                         /* fall through */
1898
1899                 case STATE_SENDING_STOP:
1900                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1901                                                 &host->pending_events))
1902                                 break;
1903
1904                         /* CMD error in data command */
1905                         if (mrq->cmd->error && mrq->data)
1906                                 dw_mci_reset(host);
1907
1908                         host->cmd = NULL;
1909                         host->data = NULL;
1910
1911                         if (mrq->stop)
1912                                 dw_mci_command_complete(host, mrq->stop);
1913                         else
1914                                 host->cmd_status = 0;
1915
1916                         dw_mci_request_end(host, mrq);
1917                         goto unlock;
1918
1919                 case STATE_DATA_ERROR:
1920                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1921                                                 &host->pending_events))
1922                                 break;
1923
1924                         state = STATE_DATA_BUSY;
1925                         break;
1926                 }
1927         } while (state != prev_state);
1928
1929         host->state = state;
1930 unlock:
1931         spin_unlock(&host->lock);
1932
1933 }
1934
1935 /* push final bytes to part_buf, only use during push */
1936 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
1937 {
1938         memcpy((void *)&host->part_buf, buf, cnt);
1939         host->part_buf_count = cnt;
1940 }
1941
1942 /* append bytes to part_buf, only use during push */
1943 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1944 {
1945         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1946         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1947         host->part_buf_count += cnt;
1948         return cnt;
1949 }
1950
1951 /* pull first bytes from part_buf, only use during pull */
1952 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1953 {
1954         cnt = min_t(int, cnt, host->part_buf_count);
1955         if (cnt) {
1956                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1957                        cnt);
1958                 host->part_buf_count -= cnt;
1959                 host->part_buf_start += cnt;
1960         }
1961         return cnt;
1962 }
1963
1964 /* pull final bytes from the part_buf, assuming it's just been filled */
1965 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1966 {
1967         memcpy(buf, &host->part_buf, cnt);
1968         host->part_buf_start = cnt;
1969         host->part_buf_count = (1 << host->data_shift) - cnt;
1970 }
1971
1972 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1973 {
1974         struct mmc_data *data = host->data;
1975         int init_cnt = cnt;
1976
1977         /* try and push anything in the part_buf */
1978         if (unlikely(host->part_buf_count)) {
1979                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1980
1981                 buf += len;
1982                 cnt -= len;
1983                 if (host->part_buf_count == 2) {
1984                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
1985                         host->part_buf_count = 0;
1986                 }
1987         }
1988 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1989         if (unlikely((unsigned long)buf & 0x1)) {
1990                 while (cnt >= 2) {
1991                         u16 aligned_buf[64];
1992                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1993                         int items = len >> 1;
1994                         int i;
1995                         /* memcpy from input buffer into aligned buffer */
1996                         memcpy(aligned_buf, buf, len);
1997                         buf += len;
1998                         cnt -= len;
1999                         /* push data from aligned buffer into fifo */
2000                         for (i = 0; i < items; ++i)
2001                                 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2002                 }
2003         } else
2004 #endif
2005         {
2006                 u16 *pdata = buf;
2007
2008                 for (; cnt >= 2; cnt -= 2)
2009                         mci_fifo_writew(host->fifo_reg, *pdata++);
2010                 buf = pdata;
2011         }
2012         /* put anything remaining in the part_buf */
2013         if (cnt) {
2014                 dw_mci_set_part_bytes(host, buf, cnt);
2015                  /* Push data if we have reached the expected data length */
2016                 if ((data->bytes_xfered + init_cnt) ==
2017                     (data->blksz * data->blocks))
2018                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
2019         }
2020 }
2021
2022 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2023 {
2024 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2025         if (unlikely((unsigned long)buf & 0x1)) {
2026                 while (cnt >= 2) {
2027                         /* pull data from fifo into aligned buffer */
2028                         u16 aligned_buf[64];
2029                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2030                         int items = len >> 1;
2031                         int i;
2032
2033                         for (i = 0; i < items; ++i)
2034                                 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2035                         /* memcpy from aligned buffer into output buffer */
2036                         memcpy(buf, aligned_buf, len);
2037                         buf += len;
2038                         cnt -= len;
2039                 }
2040         } else
2041 #endif
2042         {
2043                 u16 *pdata = buf;
2044
2045                 for (; cnt >= 2; cnt -= 2)
2046                         *pdata++ = mci_fifo_readw(host->fifo_reg);
2047                 buf = pdata;
2048         }
2049         if (cnt) {
2050                 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2051                 dw_mci_pull_final_bytes(host, buf, cnt);
2052         }
2053 }
2054
2055 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2056 {
2057         struct mmc_data *data = host->data;
2058         int init_cnt = cnt;
2059
2060         /* try and push anything in the part_buf */
2061         if (unlikely(host->part_buf_count)) {
2062                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2063
2064                 buf += len;
2065                 cnt -= len;
2066                 if (host->part_buf_count == 4) {
2067                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2068                         host->part_buf_count = 0;
2069                 }
2070         }
2071 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2072         if (unlikely((unsigned long)buf & 0x3)) {
2073                 while (cnt >= 4) {
2074                         u32 aligned_buf[32];
2075                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2076                         int items = len >> 2;
2077                         int i;
2078                         /* memcpy from input buffer into aligned buffer */
2079                         memcpy(aligned_buf, buf, len);
2080                         buf += len;
2081                         cnt -= len;
2082                         /* push data from aligned buffer into fifo */
2083                         for (i = 0; i < items; ++i)
2084                                 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2085                 }
2086         } else
2087 #endif
2088         {
2089                 u32 *pdata = buf;
2090
2091                 for (; cnt >= 4; cnt -= 4)
2092                         mci_fifo_writel(host->fifo_reg, *pdata++);
2093                 buf = pdata;
2094         }
2095         /* put anything remaining in the part_buf */
2096         if (cnt) {
2097                 dw_mci_set_part_bytes(host, buf, cnt);
2098                  /* Push data if we have reached the expected data length */
2099                 if ((data->bytes_xfered + init_cnt) ==
2100                     (data->blksz * data->blocks))
2101                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2102         }
2103 }
2104
2105 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2106 {
2107 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2108         if (unlikely((unsigned long)buf & 0x3)) {
2109                 while (cnt >= 4) {
2110                         /* pull data from fifo into aligned buffer */
2111                         u32 aligned_buf[32];
2112                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2113                         int items = len >> 2;
2114                         int i;
2115
2116                         for (i = 0; i < items; ++i)
2117                                 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2118                         /* memcpy from aligned buffer into output buffer */
2119                         memcpy(buf, aligned_buf, len);
2120                         buf += len;
2121                         cnt -= len;
2122                 }
2123         } else
2124 #endif
2125         {
2126                 u32 *pdata = buf;
2127
2128                 for (; cnt >= 4; cnt -= 4)
2129                         *pdata++ = mci_fifo_readl(host->fifo_reg);
2130                 buf = pdata;
2131         }
2132         if (cnt) {
2133                 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2134                 dw_mci_pull_final_bytes(host, buf, cnt);
2135         }
2136 }
2137
2138 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2139 {
2140         struct mmc_data *data = host->data;
2141         int init_cnt = cnt;
2142
2143         /* try and push anything in the part_buf */
2144         if (unlikely(host->part_buf_count)) {
2145                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2146
2147                 buf += len;
2148                 cnt -= len;
2149
2150                 if (host->part_buf_count == 8) {
2151                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2152                         host->part_buf_count = 0;
2153                 }
2154         }
2155 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2156         if (unlikely((unsigned long)buf & 0x7)) {
2157                 while (cnt >= 8) {
2158                         u64 aligned_buf[16];
2159                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2160                         int items = len >> 3;
2161                         int i;
2162                         /* memcpy from input buffer into aligned buffer */
2163                         memcpy(aligned_buf, buf, len);
2164                         buf += len;
2165                         cnt -= len;
2166                         /* push data from aligned buffer into fifo */
2167                         for (i = 0; i < items; ++i)
2168                                 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2169                 }
2170         } else
2171 #endif
2172         {
2173                 u64 *pdata = buf;
2174
2175                 for (; cnt >= 8; cnt -= 8)
2176                         mci_fifo_writeq(host->fifo_reg, *pdata++);
2177                 buf = pdata;
2178         }
2179         /* put anything remaining in the part_buf */
2180         if (cnt) {
2181                 dw_mci_set_part_bytes(host, buf, cnt);
2182                 /* Push data if we have reached the expected data length */
2183                 if ((data->bytes_xfered + init_cnt) ==
2184                     (data->blksz * data->blocks))
2185                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2186         }
2187 }
2188
2189 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2190 {
2191 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2192         if (unlikely((unsigned long)buf & 0x7)) {
2193                 while (cnt >= 8) {
2194                         /* pull data from fifo into aligned buffer */
2195                         u64 aligned_buf[16];
2196                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2197                         int items = len >> 3;
2198                         int i;
2199
2200                         for (i = 0; i < items; ++i)
2201                                 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2202
2203                         /* memcpy from aligned buffer into output buffer */
2204                         memcpy(buf, aligned_buf, len);
2205                         buf += len;
2206                         cnt -= len;
2207                 }
2208         } else
2209 #endif
2210         {
2211                 u64 *pdata = buf;
2212
2213                 for (; cnt >= 8; cnt -= 8)
2214                         *pdata++ = mci_fifo_readq(host->fifo_reg);
2215                 buf = pdata;
2216         }
2217         if (cnt) {
2218                 host->part_buf = mci_fifo_readq(host->fifo_reg);
2219                 dw_mci_pull_final_bytes(host, buf, cnt);
2220         }
2221 }
2222
2223 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2224 {
2225         int len;
2226
2227         /* get remaining partial bytes */
2228         len = dw_mci_pull_part_bytes(host, buf, cnt);
2229         if (unlikely(len == cnt))
2230                 return;
2231         buf += len;
2232         cnt -= len;
2233
2234         /* get the rest of the data */
2235         host->pull_data(host, buf, cnt);
2236 }
2237
2238 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2239 {
2240         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2241         void *buf;
2242         unsigned int offset;
2243         struct mmc_data *data = host->data;
2244         int shift = host->data_shift;
2245         u32 status;
2246         unsigned int len;
2247         unsigned int remain, fcnt;
2248
2249         do {
2250                 if (!sg_miter_next(sg_miter))
2251                         goto done;
2252
2253                 host->sg = sg_miter->piter.sg;
2254                 buf = sg_miter->addr;
2255                 remain = sg_miter->length;
2256                 offset = 0;
2257
2258                 do {
2259                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2260                                         << shift) + host->part_buf_count;
2261                         len = min(remain, fcnt);
2262                         if (!len)
2263                                 break;
2264                         dw_mci_pull_data(host, (void *)(buf + offset), len);
2265                         data->bytes_xfered += len;
2266                         offset += len;
2267                         remain -= len;
2268                 } while (remain);
2269
2270                 sg_miter->consumed = offset;
2271                 status = mci_readl(host, MINTSTS);
2272                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2273         /* if the RXDR is ready read again */
2274         } while ((status & SDMMC_INT_RXDR) ||
2275                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2276
2277         if (!remain) {
2278                 if (!sg_miter_next(sg_miter))
2279                         goto done;
2280                 sg_miter->consumed = 0;
2281         }
2282         sg_miter_stop(sg_miter);
2283         return;
2284
2285 done:
2286         sg_miter_stop(sg_miter);
2287         host->sg = NULL;
2288         smp_wmb(); /* drain writebuffer */
2289         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2290 }
2291
2292 static void dw_mci_write_data_pio(struct dw_mci *host)
2293 {
2294         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2295         void *buf;
2296         unsigned int offset;
2297         struct mmc_data *data = host->data;
2298         int shift = host->data_shift;
2299         u32 status;
2300         unsigned int len;
2301         unsigned int fifo_depth = host->fifo_depth;
2302         unsigned int remain, fcnt;
2303
2304         do {
2305                 if (!sg_miter_next(sg_miter))
2306                         goto done;
2307
2308                 host->sg = sg_miter->piter.sg;
2309                 buf = sg_miter->addr;
2310                 remain = sg_miter->length;
2311                 offset = 0;
2312
2313                 do {
2314                         fcnt = ((fifo_depth -
2315                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2316                                         << shift) - host->part_buf_count;
2317                         len = min(remain, fcnt);
2318                         if (!len)
2319                                 break;
2320                         host->push_data(host, (void *)(buf + offset), len);
2321                         data->bytes_xfered += len;
2322                         offset += len;
2323                         remain -= len;
2324                 } while (remain);
2325
2326                 sg_miter->consumed = offset;
2327                 status = mci_readl(host, MINTSTS);
2328                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2329         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2330
2331         if (!remain) {
2332                 if (!sg_miter_next(sg_miter))
2333                         goto done;
2334                 sg_miter->consumed = 0;
2335         }
2336         sg_miter_stop(sg_miter);
2337         return;
2338
2339 done:
2340         sg_miter_stop(sg_miter);
2341         host->sg = NULL;
2342         smp_wmb(); /* drain writebuffer */
2343         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2344 }
2345
2346 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2347 {
2348         if (!host->cmd_status)
2349                 host->cmd_status = status;
2350
2351         smp_wmb(); /* drain writebuffer */
2352
2353         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2354         tasklet_schedule(&host->tasklet);
2355 }
2356
2357 static void dw_mci_handle_cd(struct dw_mci *host)
2358 {
2359         int i;
2360
2361         for (i = 0; i < host->num_slots; i++) {
2362                 struct dw_mci_slot *slot = host->slot[i];
2363
2364                 if (!slot)
2365                         continue;
2366
2367                 if (slot->mmc->ops->card_event)
2368                         slot->mmc->ops->card_event(slot->mmc);
2369                 mmc_detect_change(slot->mmc,
2370                         msecs_to_jiffies(host->pdata->detect_delay_ms));
2371         }
2372 }
2373
2374 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2375 {
2376         struct dw_mci *host = dev_id;
2377         u32 pending;
2378         int i;
2379
2380         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2381
2382         /*
2383          * DTO fix - version 2.10a and below, and only if internal DMA
2384          * is configured.
2385          */
2386         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
2387                 if (!pending &&
2388                     ((mci_readl(host, STATUS) >> 17) & 0x1fff))
2389                         pending |= SDMMC_INT_DATA_OVER;
2390         }
2391
2392         if (pending) {
2393                 /* Check volt switch first, since it can look like an error */
2394                 if ((host->state == STATE_SENDING_CMD11) &&
2395                     (pending & SDMMC_INT_VOLT_SWITCH)) {
2396                         unsigned long irqflags;
2397
2398                         mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2399                         pending &= ~SDMMC_INT_VOLT_SWITCH;
2400
2401                         /*
2402                          * Hold the lock; we know cmd11_timer can't be kicked
2403                          * off after the lock is released, so safe to delete.
2404                          */
2405                         spin_lock_irqsave(&host->irq_lock, irqflags);
2406                         dw_mci_cmd_interrupt(host, pending);
2407                         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2408
2409                         del_timer(&host->cmd11_timer);
2410                 }
2411
2412                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2413                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2414                         host->cmd_status = pending;
2415                         smp_wmb(); /* drain writebuffer */
2416                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2417                 }
2418
2419                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2420                         /* if there is an error report DATA_ERROR */
2421                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2422                         host->data_status = pending;
2423                         smp_wmb(); /* drain writebuffer */
2424                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
2425                         tasklet_schedule(&host->tasklet);
2426                 }
2427
2428                 if (pending & SDMMC_INT_DATA_OVER) {
2429                         if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO)
2430                                 del_timer(&host->dto_timer);
2431
2432                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2433                         if (!host->data_status)
2434                                 host->data_status = pending;
2435                         smp_wmb(); /* drain writebuffer */
2436                         if (host->dir_status == DW_MCI_RECV_STATUS) {
2437                                 if (host->sg != NULL)
2438                                         dw_mci_read_data_pio(host, true);
2439                         }
2440                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2441                         tasklet_schedule(&host->tasklet);
2442                 }
2443
2444                 if (pending & SDMMC_INT_RXDR) {
2445                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2446                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2447                                 dw_mci_read_data_pio(host, false);
2448                 }
2449
2450                 if (pending & SDMMC_INT_TXDR) {
2451                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2452                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2453                                 dw_mci_write_data_pio(host);
2454                 }
2455
2456                 if (pending & SDMMC_INT_CMD_DONE) {
2457                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2458                         dw_mci_cmd_interrupt(host, pending);
2459                 }
2460
2461                 if (pending & SDMMC_INT_CD) {
2462                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
2463                         dw_mci_handle_cd(host);
2464                 }
2465
2466                 /* Handle SDIO Interrupts */
2467                 for (i = 0; i < host->num_slots; i++) {
2468                         struct dw_mci_slot *slot = host->slot[i];
2469
2470                         if (!slot)
2471                                 continue;
2472
2473                         if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2474                                 mci_writel(host, RINTSTS,
2475                                            SDMMC_INT_SDIO(slot->sdio_id));
2476                                 mmc_signal_sdio_irq(slot->mmc);
2477                         }
2478                 }
2479
2480         }
2481
2482         if (host->use_dma != TRANS_MODE_IDMAC)
2483                 return IRQ_HANDLED;
2484
2485         /* Handle IDMA interrupts */
2486         if (host->dma_64bit_address == 1) {
2487                 pending = mci_readl(host, IDSTS64);
2488                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2489                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2490                                                         SDMMC_IDMAC_INT_RI);
2491                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2492                         host->dma_ops->complete((void *)host);
2493                 }
2494         } else {
2495                 pending = mci_readl(host, IDSTS);
2496                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2497                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2498                                                         SDMMC_IDMAC_INT_RI);
2499                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2500                         host->dma_ops->complete((void *)host);
2501                 }
2502         }
2503
2504         return IRQ_HANDLED;
2505 }
2506
2507 #ifdef CONFIG_OF
2508 /* given a slot, find out the device node representing that slot */
2509 static struct device_node *dw_mci_of_find_slot_node(struct dw_mci_slot *slot)
2510 {
2511         struct device *dev = slot->mmc->parent;
2512         struct device_node *np;
2513         const __be32 *addr;
2514         int len;
2515
2516         if (!dev || !dev->of_node)
2517                 return NULL;
2518
2519         for_each_child_of_node(dev->of_node, np) {
2520                 addr = of_get_property(np, "reg", &len);
2521                 if (!addr || (len < sizeof(int)))
2522                         continue;
2523                 if (be32_to_cpup(addr) == slot->id)
2524                         return np;
2525         }
2526         return NULL;
2527 }
2528
2529 static void dw_mci_slot_of_parse(struct dw_mci_slot *slot)
2530 {
2531         struct device_node *np = dw_mci_of_find_slot_node(slot);
2532
2533         if (!np)
2534                 return;
2535
2536         if (of_property_read_bool(np, "disable-wp")) {
2537                 slot->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
2538                 dev_warn(slot->mmc->parent,
2539                         "Slot quirk 'disable-wp' is deprecated\n");
2540         }
2541 }
2542 #else /* CONFIG_OF */
2543 static void dw_mci_slot_of_parse(struct dw_mci_slot *slot)
2544 {
2545 }
2546 #endif /* CONFIG_OF */
2547
2548 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2549 {
2550         struct mmc_host *mmc;
2551         struct dw_mci_slot *slot;
2552         const struct dw_mci_drv_data *drv_data = host->drv_data;
2553         int ctrl_id, ret;
2554         u32 freq[2];
2555
2556         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2557         if (!mmc)
2558                 return -ENOMEM;
2559
2560         slot = mmc_priv(mmc);
2561         slot->id = id;
2562         slot->sdio_id = host->sdio_id0 + id;
2563         slot->mmc = mmc;
2564         slot->host = host;
2565         host->slot[id] = slot;
2566
2567         mmc->ops = &dw_mci_ops;
2568         if (of_property_read_u32_array(host->dev->of_node,
2569                                        "clock-freq-min-max", freq, 2)) {
2570                 mmc->f_min = DW_MCI_FREQ_MIN;
2571                 mmc->f_max = DW_MCI_FREQ_MAX;
2572         } else {
2573                 mmc->f_min = freq[0];
2574                 mmc->f_max = freq[1];
2575         }
2576
2577         /*if there are external regulators, get them*/
2578         ret = mmc_regulator_get_supply(mmc);
2579         if (ret == -EPROBE_DEFER)
2580                 goto err_host_allocated;
2581
2582         if (!mmc->ocr_avail)
2583                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2584
2585         if (host->pdata->caps)
2586                 mmc->caps = host->pdata->caps;
2587
2588         if (host->pdata->pm_caps)
2589                 mmc->pm_caps = host->pdata->pm_caps;
2590
2591         if (host->dev->of_node) {
2592                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2593                 if (ctrl_id < 0)
2594                         ctrl_id = 0;
2595         } else {
2596                 ctrl_id = to_platform_device(host->dev)->id;
2597         }
2598         if (drv_data && drv_data->caps)
2599                 mmc->caps |= drv_data->caps[ctrl_id];
2600
2601         if (host->pdata->caps2)
2602                 mmc->caps2 = host->pdata->caps2;
2603
2604         dw_mci_slot_of_parse(slot);
2605
2606         ret = mmc_of_parse(mmc);
2607         if (ret)
2608                 goto err_host_allocated;
2609
2610         /* Useful defaults if platform data is unset. */
2611         if (host->use_dma == TRANS_MODE_IDMAC) {
2612                 mmc->max_segs = host->ring_size;
2613                 mmc->max_blk_size = 65536;
2614                 mmc->max_seg_size = 0x1000;
2615                 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2616                 mmc->max_blk_count = mmc->max_req_size / 512;
2617         } else if (host->use_dma == TRANS_MODE_EDMAC) {
2618                 mmc->max_segs = 64;
2619                 mmc->max_blk_size = 65536;
2620                 mmc->max_blk_count = 65535;
2621                 mmc->max_req_size =
2622                                 mmc->max_blk_size * mmc->max_blk_count;
2623                 mmc->max_seg_size = mmc->max_req_size;
2624         } else {
2625                 /* TRANS_MODE_PIO */
2626                 mmc->max_segs = 64;
2627                 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
2628                 mmc->max_blk_count = 512;
2629                 mmc->max_req_size = mmc->max_blk_size *
2630                                     mmc->max_blk_count;
2631                 mmc->max_seg_size = mmc->max_req_size;
2632         }
2633
2634         dw_mci_get_cd(mmc);
2635
2636         ret = mmc_add_host(mmc);
2637         if (ret)
2638                 goto err_host_allocated;
2639
2640 #if defined(CONFIG_DEBUG_FS)
2641         dw_mci_init_debugfs(slot);
2642 #endif
2643
2644         return 0;
2645
2646 err_host_allocated:
2647         mmc_free_host(mmc);
2648         return ret;
2649 }
2650
2651 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2652 {
2653         /* Debugfs stuff is cleaned up by mmc core */
2654         mmc_remove_host(slot->mmc);
2655         slot->host->slot[id] = NULL;
2656         mmc_free_host(slot->mmc);
2657 }
2658
2659 static void dw_mci_init_dma(struct dw_mci *host)
2660 {
2661         int addr_config;
2662         struct device *dev = host->dev;
2663         struct device_node *np = dev->of_node;
2664
2665         /*
2666         * Check tansfer mode from HCON[17:16]
2667         * Clear the ambiguous description of dw_mmc databook:
2668         * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2669         * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2670         * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2671         * 2b'11: Non DW DMA Interface -> pio only
2672         * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2673         * simpler request/acknowledge handshake mechanism and both of them
2674         * are regarded as external dma master for dw_mmc.
2675         */
2676         host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2677         if (host->use_dma == DMA_INTERFACE_IDMA) {
2678                 host->use_dma = TRANS_MODE_IDMAC;
2679         } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2680                    host->use_dma == DMA_INTERFACE_GDMA) {
2681                 host->use_dma = TRANS_MODE_EDMAC;
2682         } else {
2683                 goto no_dma;
2684         }
2685
2686         /* Determine which DMA interface to use */
2687         if (host->use_dma == TRANS_MODE_IDMAC) {
2688                 /*
2689                 * Check ADDR_CONFIG bit in HCON to find
2690                 * IDMAC address bus width
2691                 */
2692                 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2693
2694                 if (addr_config == 1) {
2695                         /* host supports IDMAC in 64-bit address mode */
2696                         host->dma_64bit_address = 1;
2697                         dev_info(host->dev,
2698                                  "IDMAC supports 64-bit address mode.\n");
2699                         if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2700                                 dma_set_coherent_mask(host->dev,
2701                                                       DMA_BIT_MASK(64));
2702                 } else {
2703                         /* host supports IDMAC in 32-bit address mode */
2704                         host->dma_64bit_address = 0;
2705                         dev_info(host->dev,
2706                                  "IDMAC supports 32-bit address mode.\n");
2707                 }
2708
2709                 /* Alloc memory for sg translation */
2710                 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
2711                                                    &host->sg_dma, GFP_KERNEL);
2712                 if (!host->sg_cpu) {
2713                         dev_err(host->dev,
2714                                 "%s: could not alloc DMA memory\n",
2715                                 __func__);
2716                         goto no_dma;
2717                 }
2718
2719                 host->dma_ops = &dw_mci_idmac_ops;
2720                 dev_info(host->dev, "Using internal DMA controller.\n");
2721         } else {
2722                 /* TRANS_MODE_EDMAC: check dma bindings again */
2723                 if ((of_property_count_strings(np, "dma-names") < 0) ||
2724                     (!of_find_property(np, "dmas", NULL))) {
2725                         goto no_dma;
2726                 }
2727                 host->dma_ops = &dw_mci_edmac_ops;
2728                 dev_info(host->dev, "Using external DMA controller.\n");
2729         }
2730
2731         if (host->dma_ops->init && host->dma_ops->start &&
2732             host->dma_ops->stop && host->dma_ops->cleanup) {
2733                 if (host->dma_ops->init(host)) {
2734                         dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2735                                 __func__);
2736                         goto no_dma;
2737                 }
2738         } else {
2739                 dev_err(host->dev, "DMA initialization not found.\n");
2740                 goto no_dma;
2741         }
2742
2743         return;
2744
2745 no_dma:
2746         dev_info(host->dev, "Using PIO mode.\n");
2747         host->use_dma = TRANS_MODE_PIO;
2748 }
2749
2750 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
2751 {
2752         unsigned long timeout = jiffies + msecs_to_jiffies(500);
2753         u32 ctrl;
2754
2755         ctrl = mci_readl(host, CTRL);
2756         ctrl |= reset;
2757         mci_writel(host, CTRL, ctrl);
2758
2759         /* wait till resets clear */
2760         do {
2761                 ctrl = mci_readl(host, CTRL);
2762                 if (!(ctrl & reset))
2763                         return true;
2764         } while (time_before(jiffies, timeout));
2765
2766         dev_err(host->dev,
2767                 "Timeout resetting block (ctrl reset %#x)\n",
2768                 ctrl & reset);
2769
2770         return false;
2771 }
2772
2773 static bool dw_mci_reset(struct dw_mci *host)
2774 {
2775         u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2776         bool ret = false;
2777
2778         /*
2779          * Reseting generates a block interrupt, hence setting
2780          * the scatter-gather pointer to NULL.
2781          */
2782         if (host->sg) {
2783                 sg_miter_stop(&host->sg_miter);
2784                 host->sg = NULL;
2785         }
2786
2787         if (host->use_dma)
2788                 flags |= SDMMC_CTRL_DMA_RESET;
2789
2790         if (dw_mci_ctrl_reset(host, flags)) {
2791                 /*
2792                  * In all cases we clear the RAWINTS register to clear any
2793                  * interrupts.
2794                  */
2795                 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2796
2797                 /* if using dma we wait for dma_req to clear */
2798                 if (host->use_dma) {
2799                         unsigned long timeout = jiffies + msecs_to_jiffies(500);
2800                         u32 status;
2801
2802                         do {
2803                                 status = mci_readl(host, STATUS);
2804                                 if (!(status & SDMMC_STATUS_DMA_REQ))
2805                                         break;
2806                                 cpu_relax();
2807                         } while (time_before(jiffies, timeout));
2808
2809                         if (status & SDMMC_STATUS_DMA_REQ) {
2810                                 dev_err(host->dev,
2811                                         "%s: Timeout waiting for dma_req to clear during reset\n",
2812                                         __func__);
2813                                 goto ciu_out;
2814                         }
2815
2816                         /* when using DMA next we reset the fifo again */
2817                         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2818                                 goto ciu_out;
2819                 }
2820         } else {
2821                 /* if the controller reset bit did clear, then set clock regs */
2822                 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2823                         dev_err(host->dev,
2824                                 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
2825                                 __func__);
2826                         goto ciu_out;
2827                 }
2828         }
2829
2830         if (host->use_dma == TRANS_MODE_IDMAC)
2831                 /* It is also recommended that we reset and reprogram idmac */
2832                 dw_mci_idmac_reset(host);
2833
2834         ret = true;
2835
2836 ciu_out:
2837         /* After a CTRL reset we need to have CIU set clock registers  */
2838         mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2839
2840         return ret;
2841 }
2842
2843 static void dw_mci_cmd11_timer(unsigned long arg)
2844 {
2845         struct dw_mci *host = (struct dw_mci *)arg;
2846
2847         if (host->state != STATE_SENDING_CMD11) {
2848                 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2849                 return;
2850         }
2851
2852         host->cmd_status = SDMMC_INT_RTO;
2853         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2854         tasklet_schedule(&host->tasklet);
2855 }
2856
2857 static void dw_mci_dto_timer(unsigned long arg)
2858 {
2859         struct dw_mci *host = (struct dw_mci *)arg;
2860
2861         switch (host->state) {
2862         case STATE_SENDING_DATA:
2863         case STATE_DATA_BUSY:
2864                 /*
2865                  * If DTO interrupt does NOT come in sending data state,
2866                  * we should notify the driver to terminate current transfer
2867                  * and report a data timeout to the core.
2868                  */
2869                 host->data_status = SDMMC_INT_DRTO;
2870                 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2871                 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2872                 tasklet_schedule(&host->tasklet);
2873                 break;
2874         default:
2875                 break;
2876         }
2877 }
2878
2879 #ifdef CONFIG_OF
2880 static struct dw_mci_of_quirks {
2881         char *quirk;
2882         int id;
2883 } of_quirks[] = {
2884         {
2885                 .quirk  = "broken-cd",
2886                 .id     = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
2887         },
2888 };
2889
2890 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2891 {
2892         struct dw_mci_board *pdata;
2893         struct device *dev = host->dev;
2894         struct device_node *np = dev->of_node;
2895         const struct dw_mci_drv_data *drv_data = host->drv_data;
2896         int idx, ret;
2897         u32 clock_frequency;
2898
2899         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2900         if (!pdata)
2901                 return ERR_PTR(-ENOMEM);
2902
2903         /* find out number of slots supported */
2904         if (of_property_read_u32(dev->of_node, "num-slots",
2905                                 &pdata->num_slots)) {
2906                 dev_info(dev,
2907                          "num-slots property not found, assuming 1 slot is available\n");
2908                 pdata->num_slots = 1;
2909         }
2910
2911         /* get quirks */
2912         for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
2913                 if (of_get_property(np, of_quirks[idx].quirk, NULL))
2914                         pdata->quirks |= of_quirks[idx].id;
2915
2916         if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2917                 dev_info(dev,
2918                          "fifo-depth property not found, using value of FIFOTH register as default\n");
2919
2920         of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2921
2922         if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2923                 pdata->bus_hz = clock_frequency;
2924
2925         if (drv_data && drv_data->parse_dt) {
2926                 ret = drv_data->parse_dt(host);
2927                 if (ret)
2928                         return ERR_PTR(ret);
2929         }
2930
2931         if (of_find_property(np, "supports-highspeed", NULL)) {
2932                 dev_info(dev, "supports-highspeed property is deprecated.\n");
2933                 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2934         }
2935
2936         return pdata;
2937 }
2938
2939 #else /* CONFIG_OF */
2940 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2941 {
2942         return ERR_PTR(-EINVAL);
2943 }
2944 #endif /* CONFIG_OF */
2945
2946 static void dw_mci_enable_cd(struct dw_mci *host)
2947 {
2948         struct dw_mci_board *brd = host->pdata;
2949         unsigned long irqflags;
2950         u32 temp;
2951         int i;
2952
2953         /* No need for CD if broken card detection */
2954         if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
2955                 return;
2956
2957         /* No need for CD if all slots have a non-error GPIO */
2958         for (i = 0; i < host->num_slots; i++) {
2959                 struct dw_mci_slot *slot = host->slot[i];
2960
2961                 if (IS_ERR_VALUE(mmc_gpio_get_cd(slot->mmc)))
2962                         break;
2963         }
2964         if (i == host->num_slots)
2965                 return;
2966
2967         spin_lock_irqsave(&host->irq_lock, irqflags);
2968         temp = mci_readl(host, INTMASK);
2969         temp  |= SDMMC_INT_CD;
2970         mci_writel(host, INTMASK, temp);
2971         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2972 }
2973
2974 int dw_mci_probe(struct dw_mci *host)
2975 {
2976         const struct dw_mci_drv_data *drv_data = host->drv_data;
2977         int width, i, ret = 0;
2978         u32 fifo_size;
2979         int init_slots = 0;
2980
2981         if (!host->pdata) {
2982                 host->pdata = dw_mci_parse_dt(host);
2983                 if (IS_ERR(host->pdata)) {
2984                         dev_err(host->dev, "platform data not available\n");
2985                         return -EINVAL;
2986                 }
2987         }
2988
2989         if (host->pdata->num_slots < 1) {
2990                 dev_err(host->dev,
2991                         "Platform data must supply num_slots.\n");
2992                 return -ENODEV;
2993         }
2994
2995         host->biu_clk = devm_clk_get(host->dev, "biu");
2996         if (IS_ERR(host->biu_clk)) {
2997                 dev_dbg(host->dev, "biu clock not available\n");
2998         } else {
2999                 ret = clk_prepare_enable(host->biu_clk);
3000                 if (ret) {
3001                         dev_err(host->dev, "failed to enable biu clock\n");
3002                         return ret;
3003                 }
3004         }
3005
3006         host->ciu_clk = devm_clk_get(host->dev, "ciu");
3007         if (IS_ERR(host->ciu_clk)) {
3008                 dev_dbg(host->dev, "ciu clock not available\n");
3009                 host->bus_hz = host->pdata->bus_hz;
3010         } else {
3011                 ret = clk_prepare_enable(host->ciu_clk);
3012                 if (ret) {
3013                         dev_err(host->dev, "failed to enable ciu clock\n");
3014                         goto err_clk_biu;
3015                 }
3016
3017                 if (host->pdata->bus_hz) {
3018                         ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3019                         if (ret)
3020                                 dev_warn(host->dev,
3021                                          "Unable to set bus rate to %uHz\n",
3022                                          host->pdata->bus_hz);
3023                 }
3024                 host->bus_hz = clk_get_rate(host->ciu_clk);
3025         }
3026
3027         if (!host->bus_hz) {
3028                 dev_err(host->dev,
3029                         "Platform data must supply bus speed\n");
3030                 ret = -ENODEV;
3031                 goto err_clk_ciu;
3032         }
3033
3034         if (drv_data && drv_data->init) {
3035                 ret = drv_data->init(host);
3036                 if (ret) {
3037                         dev_err(host->dev,
3038                                 "implementation specific init failed\n");
3039                         goto err_clk_ciu;
3040                 }
3041         }
3042
3043         if (drv_data && drv_data->setup_clock) {
3044                 ret = drv_data->setup_clock(host);
3045                 if (ret) {
3046                         dev_err(host->dev,
3047                                 "implementation specific clock setup failed\n");
3048                         goto err_clk_ciu;
3049                 }
3050         }
3051
3052         setup_timer(&host->cmd11_timer,
3053                     dw_mci_cmd11_timer, (unsigned long)host);
3054
3055         host->quirks = host->pdata->quirks;
3056
3057         if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO)
3058                 setup_timer(&host->dto_timer,
3059                             dw_mci_dto_timer, (unsigned long)host);
3060
3061         spin_lock_init(&host->lock);
3062         spin_lock_init(&host->irq_lock);
3063         INIT_LIST_HEAD(&host->queue);
3064
3065         /*
3066          * Get the host data width - this assumes that HCON has been set with
3067          * the correct values.
3068          */
3069         i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3070         if (!i) {
3071                 host->push_data = dw_mci_push_data16;
3072                 host->pull_data = dw_mci_pull_data16;
3073                 width = 16;
3074                 host->data_shift = 1;
3075         } else if (i == 2) {
3076                 host->push_data = dw_mci_push_data64;
3077                 host->pull_data = dw_mci_pull_data64;
3078                 width = 64;
3079                 host->data_shift = 3;
3080         } else {
3081                 /* Check for a reserved value, and warn if it is */
3082                 WARN((i != 1),
3083                      "HCON reports a reserved host data width!\n"
3084                      "Defaulting to 32-bit access.\n");
3085                 host->push_data = dw_mci_push_data32;
3086                 host->pull_data = dw_mci_pull_data32;
3087                 width = 32;
3088                 host->data_shift = 2;
3089         }
3090
3091         /* Reset all blocks */
3092         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS))
3093                 return -ENODEV;
3094
3095         host->dma_ops = host->pdata->dma_ops;
3096         dw_mci_init_dma(host);
3097
3098         /* Clear the interrupts for the host controller */
3099         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3100         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3101
3102         /* Put in max timeout */
3103         mci_writel(host, TMOUT, 0xFFFFFFFF);
3104
3105         /*
3106          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
3107          *                          Tx Mark = fifo_size / 2 DMA Size = 8
3108          */
3109         if (!host->pdata->fifo_depth) {
3110                 /*
3111                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3112                  * have been overwritten by the bootloader, just like we're
3113                  * about to do, so if you know the value for your hardware, you
3114                  * should put it in the platform data.
3115                  */
3116                 fifo_size = mci_readl(host, FIFOTH);
3117                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3118         } else {
3119                 fifo_size = host->pdata->fifo_depth;
3120         }
3121         host->fifo_depth = fifo_size;
3122         host->fifoth_val =
3123                 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3124         mci_writel(host, FIFOTH, host->fifoth_val);
3125
3126         /* disable clock to CIU */
3127         mci_writel(host, CLKENA, 0);
3128         mci_writel(host, CLKSRC, 0);
3129
3130         /*
3131          * In 2.40a spec, Data offset is changed.
3132          * Need to check the version-id and set data-offset for DATA register.
3133          */
3134         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3135         dev_info(host->dev, "Version ID is %04x\n", host->verid);
3136
3137         if (host->verid < DW_MMC_240A)
3138                 host->fifo_reg = host->regs + DATA_OFFSET;
3139         else
3140                 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3141
3142         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3143         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3144                                host->irq_flags, "dw-mci", host);
3145         if (ret)
3146                 goto err_dmaunmap;
3147
3148         if (host->pdata->num_slots)
3149                 host->num_slots = host->pdata->num_slots;
3150         else
3151                 host->num_slots = SDMMC_GET_SLOT_NUM(mci_readl(host, HCON));
3152
3153         /*
3154          * Enable interrupts for command done, data over, data empty,
3155          * receive ready and error such as transmit, receive timeout, crc error
3156          */
3157         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3158         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3159                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3160                    DW_MCI_ERROR_FLAGS);
3161         /* Enable mci interrupt */
3162         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3163
3164         dev_info(host->dev,
3165                  "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3166                  host->irq, width, fifo_size);
3167
3168         /* We need at least one slot to succeed */
3169         for (i = 0; i < host->num_slots; i++) {
3170                 ret = dw_mci_init_slot(host, i);
3171                 if (ret)
3172                         dev_dbg(host->dev, "slot %d init failed\n", i);
3173                 else
3174                         init_slots++;
3175         }
3176
3177         if (init_slots) {
3178                 dev_info(host->dev, "%d slots initialized\n", init_slots);
3179         } else {
3180                 dev_dbg(host->dev,
3181                         "attempted to initialize %d slots, but failed on all\n",
3182                         host->num_slots);
3183                 goto err_dmaunmap;
3184         }
3185
3186         /* Now that slots are all setup, we can enable card detect */
3187         dw_mci_enable_cd(host);
3188
3189         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
3190                 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
3191
3192         return 0;
3193
3194 err_dmaunmap:
3195         if (host->use_dma && host->dma_ops->exit)
3196                 host->dma_ops->exit(host);
3197
3198 err_clk_ciu:
3199         if (!IS_ERR(host->ciu_clk))
3200                 clk_disable_unprepare(host->ciu_clk);
3201
3202 err_clk_biu:
3203         if (!IS_ERR(host->biu_clk))
3204                 clk_disable_unprepare(host->biu_clk);
3205
3206         return ret;
3207 }
3208 EXPORT_SYMBOL(dw_mci_probe);
3209
3210 void dw_mci_remove(struct dw_mci *host)
3211 {
3212         int i;
3213
3214         for (i = 0; i < host->num_slots; i++) {
3215                 dev_dbg(host->dev, "remove slot %d\n", i);
3216                 if (host->slot[i])
3217                         dw_mci_cleanup_slot(host->slot[i], i);
3218         }
3219
3220         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3221         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3222
3223         /* disable clock to CIU */
3224         mci_writel(host, CLKENA, 0);
3225         mci_writel(host, CLKSRC, 0);
3226
3227         if (host->use_dma && host->dma_ops->exit)
3228                 host->dma_ops->exit(host);
3229
3230         if (!IS_ERR(host->ciu_clk))
3231                 clk_disable_unprepare(host->ciu_clk);
3232
3233         if (!IS_ERR(host->biu_clk))
3234                 clk_disable_unprepare(host->biu_clk);
3235 }
3236 EXPORT_SYMBOL(dw_mci_remove);
3237
3238
3239
3240 #ifdef CONFIG_PM_SLEEP
3241 /*
3242  * TODO: we should probably disable the clock to the card in the suspend path.
3243  */
3244 int dw_mci_suspend(struct dw_mci *host)
3245 {
3246         if (host->use_dma && host->dma_ops->exit)
3247                 host->dma_ops->exit(host);
3248
3249         return 0;
3250 }
3251 EXPORT_SYMBOL(dw_mci_suspend);
3252
3253 int dw_mci_resume(struct dw_mci *host)
3254 {
3255         int i, ret;
3256
3257         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3258                 ret = -ENODEV;
3259                 return ret;
3260         }
3261
3262         if (host->use_dma && host->dma_ops->init)
3263                 host->dma_ops->init(host);
3264
3265         /*
3266          * Restore the initial value at FIFOTH register
3267          * And Invalidate the prev_blksz with zero
3268          */
3269         mci_writel(host, FIFOTH, host->fifoth_val);
3270         host->prev_blksz = 0;
3271
3272         /* Put in max timeout */
3273         mci_writel(host, TMOUT, 0xFFFFFFFF);
3274
3275         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3276         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3277                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3278                    DW_MCI_ERROR_FLAGS);
3279         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3280
3281         for (i = 0; i < host->num_slots; i++) {
3282                 struct dw_mci_slot *slot = host->slot[i];
3283
3284                 if (!slot)
3285                         continue;
3286                 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
3287                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3288                         dw_mci_setup_bus(slot, true);
3289                 }
3290         }
3291
3292         /* Now that slots are all setup, we can enable card detect */
3293         dw_mci_enable_cd(host);
3294
3295         return 0;
3296 }
3297 EXPORT_SYMBOL(dw_mci_resume);
3298 #endif /* CONFIG_PM_SLEEP */
3299
3300 static int __init dw_mci_init(void)
3301 {
3302         pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3303         return 0;
3304 }
3305
3306 static void __exit dw_mci_exit(void)
3307 {
3308 }
3309
3310 module_init(dw_mci_init);
3311 module_exit(dw_mci_exit);
3312
3313 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3314 MODULE_AUTHOR("NXP Semiconductor VietNam");
3315 MODULE_AUTHOR("Imagination Technologies Ltd");
3316 MODULE_LICENSE("GPL v2");