drivers/mmc/host/dw_mmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/blkdev.h>
  15 #include <linux/clk.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/ioport.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/seq_file.h>
  26 #include <linux/slab.h>
  27 #include <linux/stat.h>
  28 #include <linux/delay.h>
  29 #include <linux/irq.h>
  30 #include <linux/mmc/card.h>
  31 #include <linux/mmc/host.h>
  32 #include <linux/mmc/mmc.h>
  33 #include <linux/mmc/sd.h>
  34 #include <linux/mmc/sdio.h>
  35 #include <linux/mmc/dw_mmc.h>
  36 #include <linux/bitops.h>
  37 #include <linux/regulator/consumer.h>
  38 #include <linux/of.h>
  39 #include <linux/of_gpio.h>
  40 #include <linux/mmc/slot-gpio.h>
  41
  42 #include "dw_mmc.h"
  43
  44 /* Common flag combinations */
  45 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
  46                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
  47                                  SDMMC_INT_EBE | SDMMC_INT_HLE)
  48 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  49                                  SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
  50 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  51                                  DW_MCI_CMD_ERROR_FLAGS)
  52 #define DW_MCI_SEND_STATUS      1
  53 #define DW_MCI_RECV_STATUS      2
  54 #define DW_MCI_DMA_THRESHOLD    16
  55
  56 #define DW_MCI_FREQ_MAX 200000000       /* unit: HZ */
  57 #define DW_MCI_FREQ_MIN 400000          /* unit: HZ */
  58
  59 #define IDMAC_INT_CLR           (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  60                                  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  61                                  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
  62                                  SDMMC_IDMAC_INT_TI)
  63
  64 struct idmac_desc_64addr {
  65         u32             des0;   /* Control Descriptor */
  66
  67         u32             des1;   /* Reserved */
  68
  69         u32             des2;   /*Buffer sizes */
  70 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
  71         ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
  72          ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
  73
  74         u32             des3;   /* Reserved */
  75
  76         u32             des4;   /* Lower 32-bits of Buffer Address Pointer 1*/
  77         u32             des5;   /* Upper 32-bits of Buffer Address Pointer 1*/
  78
  79         u32             des6;   /* Lower 32-bits of Next Descriptor Address */
  80         u32             des7;   /* Upper 32-bits of Next Descriptor Address */
  81 };
  82
  83 struct idmac_desc {
  84         __le32          des0;   /* Control Descriptor */
  85 #define IDMAC_DES0_DIC  BIT(1)
  86 #define IDMAC_DES0_LD   BIT(2)
  87 #define IDMAC_DES0_FD   BIT(3)
  88 #define IDMAC_DES0_CH   BIT(4)
  89 #define IDMAC_DES0_ER   BIT(5)
  90 #define IDMAC_DES0_CES  BIT(30)
  91 #define IDMAC_DES0_OWN  BIT(31)
  92
  93         __le32          des1;   /* Buffer sizes */
  94 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  95         ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
  96
  97         __le32          des2;   /* buffer 1 physical address */
  98
  99         __le32          des3;   /* buffer 2 physical address */
 100 };
 101
 102 /* Each descriptor can transfer up to 4KB of data in chained mode */
 103 #define DW_MCI_DESC_DATA_LENGTH 0x1000
 104
 105 static bool dw_mci_reset(struct dw_mci *host);
 106 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
 107 static int dw_mci_card_busy(struct mmc_host *mmc);
 108
 109 #if defined(CONFIG_DEBUG_FS)
 110 static int dw_mci_req_show(struct seq_file *s, void *v)
 111 {
 112         struct dw_mci_slot *slot = s->private;
 113         struct mmc_request *mrq;
 114         struct mmc_command *cmd;
 115         struct mmc_command *stop;
 116         struct mmc_data *data;
 117
 118         /* Make sure we get a consistent snapshot */
 119         spin_lock_bh(&slot->host->lock);
 120         mrq = slot->mrq;
 121
 122         if (mrq) {
 123                 cmd = mrq->cmd;
 124                 data = mrq->data;
 125                 stop = mrq->stop;
 126
 127                 if (cmd)
 128                         seq_printf(s,
 129                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 130                                    cmd->opcode, cmd->arg, cmd->flags,
 131                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 132                                    cmd->resp[2], cmd->error);
 133                 if (data)
 134                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 135                                    data->bytes_xfered, data->blocks,
 136                                    data->blksz, data->flags, data->error);
 137                 if (stop)
 138                         seq_printf(s,
 139                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 140                                    stop->opcode, stop->arg, stop->flags,
 141                                    stop->resp[0], stop->resp[1], stop->resp[2],
 142                                    stop->resp[2], stop->error);
 143         }
 144
 145         spin_unlock_bh(&slot->host->lock);
 146
 147         return 0;
 148 }
 149
 150 static int dw_mci_req_open(struct inode *inode, struct file *file)
 151 {
 152         return single_open(file, dw_mci_req_show, inode->i_private);
 153 }
 154
 155 static const struct file_operations dw_mci_req_fops = {
 156         .owner          = THIS_MODULE,
 157         .open           = dw_mci_req_open,
 158         .read           = seq_read,
 159         .llseek         = seq_lseek,
 160         .release        = single_release,
 161 };
 162
 163 static int dw_mci_regs_show(struct seq_file *s, void *v)
 164 {
 165         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
 166         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
 167         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
 168         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
 169         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
 170         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
 171
 172         return 0;
 173 }
 174
 175 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 176 {
 177         return single_open(file, dw_mci_regs_show, inode->i_private);
 178 }
 179
 180 static const struct file_operations dw_mci_regs_fops = {
 181         .owner          = THIS_MODULE,
 182         .open           = dw_mci_regs_open,
 183         .read           = seq_read,
 184         .llseek         = seq_lseek,
 185         .release        = single_release,
 186 };
 187
 188 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 189 {
 190         struct mmc_host *mmc = slot->mmc;
 191         struct dw_mci *host = slot->host;
 192         struct dentry *root;
 193         struct dentry *node;
 194
 195         root = mmc->debugfs_root;
 196         if (!root)
 197                 return;
 198
 199         node = debugfs_create_file("regs", S_IRUSR, root, host,
 200                                    &dw_mci_regs_fops);
 201         if (!node)
 202                 goto err;
 203
 204         node = debugfs_create_file("req", S_IRUSR, root, slot,
 205                                    &dw_mci_req_fops);
 206         if (!node)
 207                 goto err;
 208
 209         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 210         if (!node)
 211                 goto err;
 212
 213         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 214                                   (u32 *)&host->pending_events);
 215         if (!node)
 216                 goto err;
 217
 218         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 219                                   (u32 *)&host->completed_events);
 220         if (!node)
 221                 goto err;
 222
 223         return;
 224
 225 err:
 226         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 227 }
 228 #endif /* defined(CONFIG_DEBUG_FS) */
 229
 230 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
 231
 232 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 233 {
 234         struct mmc_data *data;
 235         struct dw_mci_slot *slot = mmc_priv(mmc);
 236         struct dw_mci *host = slot->host;
 237         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
 238         u32 cmdr;
 239
 240         cmd->error = -EINPROGRESS;
 241         cmdr = cmd->opcode;
 242
 243         if (cmd->opcode == MMC_STOP_TRANSMISSION ||
 244             cmd->opcode == MMC_GO_IDLE_STATE ||
 245             cmd->opcode == MMC_GO_INACTIVE_STATE ||
 246             (cmd->opcode == SD_IO_RW_DIRECT &&
 247              ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
 248                 cmdr |= SDMMC_CMD_STOP;
 249         else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
 250                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 251
 252         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
 253                 u32 clk_en_a;
 254
 255                 /* Special bit makes CMD11 not die */
 256                 cmdr |= SDMMC_CMD_VOLT_SWITCH;
 257
 258                 /* Change state to continue to handle CMD11 weirdness */
 259                 WARN_ON(slot->host->state != STATE_SENDING_CMD);
 260                 slot->host->state = STATE_SENDING_CMD11;
 261
 262                 /*
 263                  * We need to disable low power mode (automatic clock stop)
 264                  * while doing voltage switch so we don't confuse the card,
 265                  * since stopping the clock is a specific part of the UHS
 266                  * voltage change dance.
 267                  *
 268                  * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
 269                  * unconditionally turned back on in dw_mci_setup_bus() if it's
 270                  * ever called with a non-zero clock.  That shouldn't happen
 271                  * until the voltage change is all done.
 272                  */
 273                 clk_en_a = mci_readl(host, CLKENA);
 274                 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
 275                 mci_writel(host, CLKENA, clk_en_a);
 276                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
 277                              SDMMC_CMD_PRV_DAT_WAIT, 0);
 278         }
 279
 280         if (cmd->flags & MMC_RSP_PRESENT) {
 281                 /* We expect a response, so set this bit */
 282                 cmdr |= SDMMC_CMD_RESP_EXP;
 283                 if (cmd->flags & MMC_RSP_136)
 284                         cmdr |= SDMMC_CMD_RESP_LONG;
 285         }
 286
 287         if (cmd->flags & MMC_RSP_CRC)
 288                 cmdr |= SDMMC_CMD_RESP_CRC;
 289
 290         data = cmd->data;
 291         if (data) {
 292                 cmdr |= SDMMC_CMD_DAT_EXP;
 293                 if (data->flags & MMC_DATA_STREAM)
 294                         cmdr |= SDMMC_CMD_STRM_MODE;
 295                 if (data->flags & MMC_DATA_WRITE)
 296                         cmdr |= SDMMC_CMD_DAT_WR;
 297         }
 298
 299         if (drv_data && drv_data->prepare_command)
 300                 drv_data->prepare_command(slot->host, &cmdr);
 301
 302         return cmdr;
 303 }
 304
 305 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
 306 {
 307         struct mmc_command *stop;
 308         u32 cmdr;
 309
 310         if (!cmd->data)
 311                 return 0;
 312
 313         stop = &host->stop_abort;
 314         cmdr = cmd->opcode;
 315         memset(stop, 0, sizeof(struct mmc_command));
 316
 317         if (cmdr == MMC_READ_SINGLE_BLOCK ||
 318             cmdr == MMC_READ_MULTIPLE_BLOCK ||
 319             cmdr == MMC_WRITE_BLOCK ||
 320             cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
 321             cmdr == MMC_SEND_TUNING_BLOCK ||
 322             cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
 323                 stop->opcode = MMC_STOP_TRANSMISSION;
 324                 stop->arg = 0;
 325                 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
 326         } else if (cmdr == SD_IO_RW_EXTENDED) {
 327                 stop->opcode = SD_IO_RW_DIRECT;
 328                 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
 329                              ((cmd->arg >> 28) & 0x7);
 330                 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
 331         } else {
 332                 return 0;
 333         }
 334
 335         cmdr = stop->opcode | SDMMC_CMD_STOP |
 336                 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
 337
 338         return cmdr;
 339 }
 340
 341 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
 342 {
 343         unsigned long timeout = jiffies + msecs_to_jiffies(500);
 344
 345         /*
 346          * Databook says that before issuing a new data transfer command
 347          * we need to check to see if the card is busy.  Data transfer commands
 348          * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
 349          *
 350          * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
 351          * expected.
 352          */
 353         if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
 354             !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
 355                 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {
 356                         if (time_after(jiffies, timeout)) {
 357                                 /* Command will fail; we'll pass error then */
 358                                 dev_err(host->dev, "Busy; trying anyway\n");
 359                                 break;
 360                         }
 361                         udelay(10);
 362                 }
 363         }
 364 }
 365
 366 static void dw_mci_start_command(struct dw_mci *host,
 367                                  struct mmc_command *cmd, u32 cmd_flags)
 368 {
 369         host->cmd = cmd;
 370         dev_vdbg(host->dev,
 371                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
 372                  cmd->arg, cmd_flags);
 373
 374         mci_writel(host, CMDARG, cmd->arg);
 375         wmb(); /* drain writebuffer */
 376         dw_mci_wait_while_busy(host, cmd_flags);
 377
 378         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 379 }
 380
 381 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
 382 {
 383         struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
 384
 385         dw_mci_start_command(host, stop, host->stop_cmdr);
 386 }
 387
 388 /* DMA interface functions */
 389 static void dw_mci_stop_dma(struct dw_mci *host)
 390 {
 391         if (host->using_dma) {
 392                 host->dma_ops->stop(host);
 393                 host->dma_ops->cleanup(host);
 394         }
 395
 396         /* Data transfer was stopped by the interrupt handler */
 397         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 398 }
 399
 400 static int dw_mci_get_dma_dir(struct mmc_data *data)
 401 {
 402         if (data->flags & MMC_DATA_WRITE)
 403                 return DMA_TO_DEVICE;
 404         else
 405                 return DMA_FROM_DEVICE;
 406 }
 407
 408 static void dw_mci_dma_cleanup(struct dw_mci *host)
 409 {
 410         struct mmc_data *data = host->data;
 411
 412         if (data)
 413                 if (!data->host_cookie)
 414                         dma_unmap_sg(host->dev,
 415                                      data->sg,
 416                                      data->sg_len,
 417                                      dw_mci_get_dma_dir(data));
 418 }
 419
 420 static void dw_mci_idmac_reset(struct dw_mci *host)
 421 {
 422         u32 bmod = mci_readl(host, BMOD);
 423         /* Software reset of DMA */
 424         bmod |= SDMMC_IDMAC_SWRESET;
 425         mci_writel(host, BMOD, bmod);
 426 }
 427
 428 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 429 {
 430         u32 temp;
 431
 432         /* Disable and reset the IDMAC interface */
 433         temp = mci_readl(host, CTRL);
 434         temp &= ~SDMMC_CTRL_USE_IDMAC;
 435         temp |= SDMMC_CTRL_DMA_RESET;
 436         mci_writel(host, CTRL, temp);
 437
 438         /* Stop the IDMAC running */
 439         temp = mci_readl(host, BMOD);
 440         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 441         temp |= SDMMC_IDMAC_SWRESET;
 442         mci_writel(host, BMOD, temp);
 443 }
 444
 445 static void dw_mci_dmac_complete_dma(void *arg)
 446 {
 447         struct dw_mci *host = arg;
 448         struct mmc_data *data = host->data;
 449
 450         dev_vdbg(host->dev, "DMA complete\n");
 451
 452         if ((host->use_dma == TRANS_MODE_EDMAC) &&
 453             data && (data->flags & MMC_DATA_READ))
 454                 /* Invalidate cache after read */
 455                 dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc),
 456                                     data->sg,
 457                                     data->sg_len,
 458                                     DMA_FROM_DEVICE);
 459
 460         host->dma_ops->cleanup(host);
 461
 462         /*
 463          * If the card was removed, data will be NULL. No point in trying to
 464          * send the stop command or waiting for NBUSY in this case.
 465          */
 466         if (data) {
 467                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 468                 tasklet_schedule(&host->tasklet);
 469         }
 470 }
 471
 472 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
 473                                     unsigned int sg_len)
 474 {
 475         unsigned int desc_len;
 476         int i;
 477
 478         if (host->dma_64bit_address == 1) {
 479                 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
 480
 481                 desc_first = desc_last = desc = host->sg_cpu;
 482
 483                 for (i = 0; i < sg_len; i++) {
 484                         unsigned int length = sg_dma_len(&data->sg[i]);
 485
 486                         u64 mem_addr = sg_dma_address(&data->sg[i]);
 487
 488                         for ( ; length ; desc++) {
 489                                 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
 490                                            length : DW_MCI_DESC_DATA_LENGTH;
 491
 492                                 length -= desc_len;
 493
 494                                 /*
 495                                  * Set the OWN bit and disable interrupts
 496                                  * for this descriptor
 497                                  */
 498                                 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
 499                                                         IDMAC_DES0_CH;
 500
 501                                 /* Buffer length */
 502                                 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
 503
 504                                 /* Physical address to DMA to/from */
 505                                 desc->des4 = mem_addr & 0xffffffff;
 506                                 desc->des5 = mem_addr >> 32;
 507
 508                                 /* Update physical address for the next desc */
 509                                 mem_addr += desc_len;
 510
 511                                 /* Save pointer to the last descriptor */
 512                                 desc_last = desc;
 513                         }
 514                 }
 515
 516                 /* Set first descriptor */
 517                 desc_first->des0 |= IDMAC_DES0_FD;
 518
 519                 /* Set last descriptor */
 520                 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 521                 desc_last->des0 |= IDMAC_DES0_LD;
 522
 523         } else {
 524                 struct idmac_desc *desc_first, *desc_last, *desc;
 525
 526                 desc_first = desc_last = desc = host->sg_cpu;
 527
 528                 for (i = 0; i < sg_len; i++) {
 529                         unsigned int length = sg_dma_len(&data->sg[i]);
 530
 531                         u32 mem_addr = sg_dma_address(&data->sg[i]);
 532
 533                         for ( ; length ; desc++) {
 534                                 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
 535                                            length : DW_MCI_DESC_DATA_LENGTH;
 536
 537                                 length -= desc_len;
 538
 539                                 /*
 540                                  * Set the OWN bit and disable interrupts
 541                                  * for this descriptor
 542                                  */
 543                                 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
 544                                                          IDMAC_DES0_DIC |
 545                                                          IDMAC_DES0_CH);
 546
 547                                 /* Buffer length */
 548                                 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
 549
 550                                 /* Physical address to DMA to/from */
 551                                 desc->des2 = cpu_to_le32(mem_addr);
 552
 553                                 /* Update physical address for the next desc */
 554                                 mem_addr += desc_len;
 555
 556                                 /* Save pointer to the last descriptor */
 557                                 desc_last = desc;
 558                         }
 559                 }
 560
 561                 /* Set first descriptor */
 562                 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
 563
 564                 /* Set last descriptor */
 565                 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
 566                                                IDMAC_DES0_DIC));
 567                 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
 568         }
 569
 570         wmb(); /* drain writebuffer */
 571 }
 572
 573 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 574 {
 575         u32 temp;
 576
 577         dw_mci_translate_sglist(host, host->data, sg_len);
 578
 579         /* Make sure to reset DMA in case we did PIO before this */
 580         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
 581         dw_mci_idmac_reset(host);
 582
 583         /* Select IDMAC interface */
 584         temp = mci_readl(host, CTRL);
 585         temp |= SDMMC_CTRL_USE_IDMAC;
 586         mci_writel(host, CTRL, temp);
 587
 588         /* drain writebuffer */
 589         wmb();
 590
 591         /* Enable the IDMAC */
 592         temp = mci_readl(host, BMOD);
 593         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 594         mci_writel(host, BMOD, temp);
 595
 596         /* Start it running */
 597         mci_writel(host, PLDMND, 1);
 598
 599         return 0;
 600 }
 601
 602 static int dw_mci_idmac_init(struct dw_mci *host)
 603 {
 604         int i;
 605
 606         if (host->dma_64bit_address == 1) {
 607                 struct idmac_desc_64addr *p;
 608                 /* Number of descriptors in the ring buffer */
 609                 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr);
 610
 611                 /* Forward link the descriptor list */
 612                 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
 613                                                                 i++, p++) {
 614                         p->des6 = (host->sg_dma +
 615                                         (sizeof(struct idmac_desc_64addr) *
 616                                                         (i + 1))) & 0xffffffff;
 617
 618                         p->des7 = (u64)(host->sg_dma +
 619                                         (sizeof(struct idmac_desc_64addr) *
 620                                                         (i + 1))) >> 32;
 621                         /* Initialize reserved and buffer size fields to "0" */
 622                         p->des1 = 0;
 623                         p->des2 = 0;
 624                         p->des3 = 0;
 625                 }
 626
 627                 /* Set the last descriptor as the end-of-ring descriptor */
 628                 p->des6 = host->sg_dma & 0xffffffff;
 629                 p->des7 = (u64)host->sg_dma >> 32;
 630                 p->des0 = IDMAC_DES0_ER;
 631
 632         } else {
 633                 struct idmac_desc *p;
 634                 /* Number of descriptors in the ring buffer */
 635                 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
 636
 637                 /* Forward link the descriptor list */
 638                 for (i = 0, p = host->sg_cpu;
 639                      i < host->ring_size - 1;
 640                      i++, p++) {
 641                         p->des3 = cpu_to_le32(host->sg_dma +
 642                                         (sizeof(struct idmac_desc) * (i + 1)));
 643                         p->des1 = 0;
 644                 }
 645
 646                 /* Set the last descriptor as the end-of-ring descriptor */
 647                 p->des3 = cpu_to_le32(host->sg_dma);
 648                 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
 649         }
 650
 651         dw_mci_idmac_reset(host);
 652
 653         if (host->dma_64bit_address == 1) {
 654                 /* Mask out interrupts - get Tx & Rx complete only */
 655                 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
 656                 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
 657                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
 658
 659                 /* Set the descriptor base address */
 660                 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
 661                 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
 662
 663         } else {
 664                 /* Mask out interrupts - get Tx & Rx complete only */
 665                 mci_writel(host, IDSTS, IDMAC_INT_CLR);
 666                 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
 667                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
 668
 669                 /* Set the descriptor base address */
 670                 mci_writel(host, DBADDR, host->sg_dma);
 671         }
 672
 673         return 0;
 674 }
 675
 676 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
 677         .init = dw_mci_idmac_init,
 678         .start = dw_mci_idmac_start_dma,
 679         .stop = dw_mci_idmac_stop_dma,
 680         .complete = dw_mci_dmac_complete_dma,
 681         .cleanup = dw_mci_dma_cleanup,
 682 };
 683
 684 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
 685 {
 686         dmaengine_terminate_all(host->dms->ch);
 687 }
 688
 689 static int dw_mci_edmac_start_dma(struct dw_mci *host,
 690                                             unsigned int sg_len)
 691 {
 692         struct dma_slave_config cfg;
 693         struct dma_async_tx_descriptor *desc = NULL;
 694         struct scatterlist *sgl = host->data->sg;
 695         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 696         u32 sg_elems = host->data->sg_len;
 697         u32 fifoth_val;
 698         u32 fifo_offset = host->fifo_reg - host->regs;
 699         int ret = 0;
 700
 701         /* Set external dma config: burst size, burst width */
 702         cfg.dst_addr = (dma_addr_t)(host->phy_regs + fifo_offset);
 703         cfg.src_addr = cfg.dst_addr;
 704         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 705         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 706
 707         /* Match burst msize with external dma config */
 708         fifoth_val = mci_readl(host, FIFOTH);
 709         cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
 710         cfg.src_maxburst = cfg.dst_maxburst;
 711
 712         if (host->data->flags & MMC_DATA_WRITE)
 713                 cfg.direction = DMA_MEM_TO_DEV;
 714         else
 715                 cfg.direction = DMA_DEV_TO_MEM;
 716
 717         ret = dmaengine_slave_config(host->dms->ch, &cfg);
 718         if (ret) {
 719                 dev_err(host->dev, "Failed to config edmac.\n");
 720                 return -EBUSY;
 721         }
 722
 723         desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
 724                                        sg_len, cfg.direction,
 725                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 726         if (!desc) {
 727                 dev_err(host->dev, "Can't prepare slave sg.\n");
 728                 return -EBUSY;
 729         }
 730
 731         /* Set dw_mci_dmac_complete_dma as callback */
 732         desc->callback = dw_mci_dmac_complete_dma;
 733         desc->callback_param = (void *)host;
 734         dmaengine_submit(desc);
 735
 736         /* Flush cache before write */
 737         if (host->data->flags & MMC_DATA_WRITE)
 738                 dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl,
 739                                        sg_elems, DMA_TO_DEVICE);
 740
 741         dma_async_issue_pending(host->dms->ch);
 742
 743         return 0;
 744 }
 745
 746 static int dw_mci_edmac_init(struct dw_mci *host)
 747 {
 748         /* Request external dma channel */
 749         host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
 750         if (!host->dms)
 751                 return -ENOMEM;
 752
 753         host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
 754         if (!host->dms->ch) {
 755                 dev_err(host->dev, "Failed to get external DMA channel.\n");
 756                 kfree(host->dms);
 757                 host->dms = NULL;
 758                 return -ENXIO;
 759         }
 760
 761         return 0;
 762 }
 763
 764 static void dw_mci_edmac_exit(struct dw_mci *host)
 765 {
 766         if (host->dms) {
 767                 if (host->dms->ch) {
 768                         dma_release_channel(host->dms->ch);
 769                         host->dms->ch = NULL;
 770                 }
 771                 kfree(host->dms);
 772                 host->dms = NULL;
 773         }
 774 }
 775
 776 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
 777         .init = dw_mci_edmac_init,
 778         .exit = dw_mci_edmac_exit,
 779         .start = dw_mci_edmac_start_dma,
 780         .stop = dw_mci_edmac_stop_dma,
 781         .complete = dw_mci_dmac_complete_dma,
 782         .cleanup = dw_mci_dma_cleanup,
 783 };
 784
 785 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 786                                    struct mmc_data *data,
 787                                    bool next)
 788 {
 789         struct scatterlist *sg;
 790         unsigned int i, sg_len;
 791
 792         if (!next && data->host_cookie)
 793                 return data->host_cookie;
 794
 795         /*
 796          * We don't do DMA on "complex" transfers, i.e. with
 797          * non-word-aligned buffers or lengths. Also, we don't bother
 798          * with all the DMA setup overhead for short transfers.
 799          */
 800         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 801                 return -EINVAL;
 802
 803         if (data->blksz & 3)
 804                 return -EINVAL;
 805
 806         for_each_sg(data->sg, sg, data->sg_len, i) {
 807                 if (sg->offset & 3 || sg->length & 3)
 808                         return -EINVAL;
 809         }
 810
 811         sg_len = dma_map_sg(host->dev,
 812                             data->sg,
 813                             data->sg_len,
 814                             dw_mci_get_dma_dir(data));
 815         if (sg_len == 0)
 816                 return -EINVAL;
 817
 818         if (next)
 819                 data->host_cookie = sg_len;
 820
 821         return sg_len;
 822 }
 823
 824 static void dw_mci_pre_req(struct mmc_host *mmc,
 825                            struct mmc_request *mrq,
 826                            bool is_first_req)
 827 {
 828         struct dw_mci_slot *slot = mmc_priv(mmc);
 829         struct mmc_data *data = mrq->data;
 830
 831         if (!slot->host->use_dma || !data)
 832                 return;
 833
 834         if (data->host_cookie) {
 835                 data->host_cookie = 0;
 836                 return;
 837         }
 838
 839         if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
 840                 data->host_cookie = 0;
 841 }
 842
 843 static void dw_mci_post_req(struct mmc_host *mmc,
 844                             struct mmc_request *mrq,
 845                             int err)
 846 {
 847         struct dw_mci_slot *slot = mmc_priv(mmc);
 848         struct mmc_data *data = mrq->data;
 849
 850         if (!slot->host->use_dma || !data)
 851                 return;
 852
 853         if (data->host_cookie)
 854                 dma_unmap_sg(slot->host->dev,
 855                              data->sg,
 856                              data->sg_len,
 857                              dw_mci_get_dma_dir(data));
 858         data->host_cookie = 0;
 859 }
 860
 861 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
 862 {
 863         unsigned int blksz = data->blksz;
 864         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 865         u32 fifo_width = 1 << host->data_shift;
 866         u32 blksz_depth = blksz / fifo_width, fifoth_val;
 867         u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
 868         int idx = ARRAY_SIZE(mszs) - 1;
 869
 870         /* pio should ship this scenario */
 871         if (!host->use_dma)
 872                 return;
 873
 874         tx_wmark = (host->fifo_depth) / 2;
 875         tx_wmark_invers = host->fifo_depth - tx_wmark;
 876
 877         /*
 878          * MSIZE is '1',
 879          * if blksz is not a multiple of the FIFO width
 880          */
 881         if (blksz % fifo_width) {
 882                 msize = 0;
 883                 rx_wmark = 1;
 884                 goto done;
 885         }
 886
 887         do {
 888                 if (!((blksz_depth % mszs[idx]) ||
 889                      (tx_wmark_invers % mszs[idx]))) {
 890                         msize = idx;
 891                         rx_wmark = mszs[idx] - 1;
 892                         break;
 893                 }
 894         } while (--idx > 0);
 895         /*
 896          * If idx is '0', it won't be tried
 897          * Thus, initial values are uesed
 898          */
 899 done:
 900         fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
 901         mci_writel(host, FIFOTH, fifoth_val);
 902 }
 903
 904 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
 905 {
 906         unsigned int blksz = data->blksz;
 907         u32 blksz_depth, fifo_depth;
 908         u16 thld_size;
 909
 910         WARN_ON(!(data->flags & MMC_DATA_READ));
 911
 912         /*
 913          * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
 914          * in the FIFO region, so we really shouldn't access it).
 915          */
 916         if (host->verid < DW_MMC_240A)
 917                 return;
 918
 919         if (host->timing != MMC_TIMING_MMC_HS200 &&
 920             host->timing != MMC_TIMING_MMC_HS400 &&
 921             host->timing != MMC_TIMING_UHS_SDR104)
 922                 goto disable;
 923
 924         blksz_depth = blksz / (1 << host->data_shift);
 925         fifo_depth = host->fifo_depth;
 926
 927         if (blksz_depth > fifo_depth)
 928                 goto disable;
 929
 930         /*
 931          * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
 932          * If (blksz_depth) <  (fifo_depth >> 1), should be thld_size = blksz
 933          * Currently just choose blksz.
 934          */
 935         thld_size = blksz;
 936         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
 937         return;
 938
 939 disable:
 940         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
 941 }
 942
 943 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
 944 {
 945         unsigned long irqflags;
 946         int sg_len;
 947         u32 temp;
 948
 949         host->using_dma = 0;
 950
 951         /* If we don't have a channel, we can't do DMA */
 952         if (!host->use_dma)
 953                 return -ENODEV;
 954
 955         sg_len = dw_mci_pre_dma_transfer(host, data, 0);
 956         if (sg_len < 0) {
 957                 host->dma_ops->stop(host);
 958                 return sg_len;
 959         }
 960
 961         host->using_dma = 1;
 962
 963         if (host->use_dma == TRANS_MODE_IDMAC)
 964                 dev_vdbg(host->dev,
 965                          "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
 966                          (unsigned long)host->sg_cpu,
 967                          (unsigned long)host->sg_dma,
 968                          sg_len);
 969
 970         /*
 971          * Decide the MSIZE and RX/TX Watermark.
 972          * If current block size is same with previous size,
 973          * no need to update fifoth.
 974          */
 975         if (host->prev_blksz != data->blksz)
 976                 dw_mci_adjust_fifoth(host, data);
 977
 978         /* Enable the DMA interface */
 979         temp = mci_readl(host, CTRL);
 980         temp |= SDMMC_CTRL_DMA_ENABLE;
 981         mci_writel(host, CTRL, temp);
 982
 983         /* Disable RX/TX IRQs, let DMA handle it */
 984         spin_lock_irqsave(&host->irq_lock, irqflags);
 985         temp = mci_readl(host, INTMASK);
 986         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
 987         mci_writel(host, INTMASK, temp);
 988         spin_unlock_irqrestore(&host->irq_lock, irqflags);
 989
 990         if (host->dma_ops->start(host, sg_len)) {
 991                 /* We can't do DMA */
 992                 dev_err(host->dev, "%s: failed to start DMA.\n", __func__);
 993                 return -ENODEV;
 994         }
 995
 996         return 0;
 997 }
 998
 999 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1000 {
1001         unsigned long irqflags;
1002         int flags = SG_MITER_ATOMIC;
1003         u32 temp;
1004
1005         data->error = -EINPROGRESS;
1006
1007         WARN_ON(host->data);
1008         host->sg = NULL;
1009         host->data = data;
1010
1011         if (data->flags & MMC_DATA_READ) {
1012                 host->dir_status = DW_MCI_RECV_STATUS;
1013                 dw_mci_ctrl_rd_thld(host, data);
1014         } else {
1015                 host->dir_status = DW_MCI_SEND_STATUS;
1016         }
1017
1018         if (dw_mci_submit_data_dma(host, data)) {
1019                 if (host->data->flags & MMC_DATA_READ)
1020                         flags |= SG_MITER_TO_SG;
1021                 else
1022                         flags |= SG_MITER_FROM_SG;
1023
1024                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1025                 host->sg = data->sg;
1026                 host->part_buf_start = 0;
1027                 host->part_buf_count = 0;
1028
1029                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1030
1031                 spin_lock_irqsave(&host->irq_lock, irqflags);
1032                 temp = mci_readl(host, INTMASK);
1033                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1034                 mci_writel(host, INTMASK, temp);
1035                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1036
1037                 temp = mci_readl(host, CTRL);
1038                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1039                 mci_writel(host, CTRL, temp);
1040
1041                 /*
1042                  * Use the initial fifoth_val for PIO mode.
1043                  * If next issued data may be transfered by DMA mode,
1044                  * prev_blksz should be invalidated.
1045                  */
1046                 mci_writel(host, FIFOTH, host->fifoth_val);
1047                 host->prev_blksz = 0;
1048         } else {
1049                 /*
1050                  * Keep the current block size.
1051                  * It will be used to decide whether to update
1052                  * fifoth register next time.
1053                  */
1054                 host->prev_blksz = data->blksz;
1055         }
1056 }
1057
1058 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
1059 {
1060         struct dw_mci *host = slot->host;
1061         unsigned long timeout = jiffies + msecs_to_jiffies(500);
1062         unsigned int cmd_status = 0;
1063
1064         mci_writel(host, CMDARG, arg);
1065         wmb(); /* drain writebuffer */
1066         dw_mci_wait_while_busy(host, cmd);
1067         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
1068
1069         while (time_before(jiffies, timeout)) {
1070                 cmd_status = mci_readl(host, CMD);
1071                 if (!(cmd_status & SDMMC_CMD_START))
1072                         return;
1073         }
1074         dev_err(&slot->mmc->class_dev,
1075                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1076                 cmd, arg, cmd_status);
1077 }
1078
1079 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1080 {
1081         struct dw_mci *host = slot->host;
1082         unsigned int clock = slot->clock;
1083         u32 div;
1084         u32 clk_en_a;
1085         u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1086
1087         /* We must continue to set bit 28 in CMD until the change is complete */
1088         if (host->state == STATE_WAITING_CMD11_DONE)
1089                 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1090
1091         if (!clock) {
1092                 mci_writel(host, CLKENA, 0);
1093                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1094         } else if (clock != host->current_speed || force_clkinit) {
1095                 div = host->bus_hz / clock;
1096                 if (host->bus_hz % clock && host->bus_hz > clock)
1097                         /*
1098                          * move the + 1 after the divide to prevent
1099                          * over-clocking the card.
1100                          */
1101                         div += 1;
1102
1103                 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1104
1105                 if ((clock << div) != slot->__clk_old || force_clkinit)
1106                         dev_info(&slot->mmc->class_dev,
1107                                  "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1108                                  slot->id, host->bus_hz, clock,
1109                                  div ? ((host->bus_hz / div) >> 1) :
1110                                  host->bus_hz, div);
1111
1112                 /* disable clock */
1113                 mci_writel(host, CLKENA, 0);
1114                 mci_writel(host, CLKSRC, 0);
1115
1116                 /* inform CIU */
1117                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1118
1119                 /* set clock to desired speed */
1120                 mci_writel(host, CLKDIV, div);
1121
1122                 /* inform CIU */
1123                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1124
1125                 /* enable clock; only low power if no SDIO */
1126                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1127                 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1128                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1129                 mci_writel(host, CLKENA, clk_en_a);
1130
1131                 /* inform CIU */
1132                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1133
1134                 /* keep the clock with reflecting clock dividor */
1135                 slot->__clk_old = clock << div;
1136         }
1137
1138         host->current_speed = clock;
1139
1140         /* Set the current slot bus width */
1141         mci_writel(host, CTYPE, (slot->ctype << slot->id));
1142 }
1143
1144 static void __dw_mci_start_request(struct dw_mci *host,
1145                                    struct dw_mci_slot *slot,
1146                                    struct mmc_command *cmd)
1147 {
1148         struct mmc_request *mrq;
1149         struct mmc_data *data;
1150         u32 cmdflags;
1151
1152         mrq = slot->mrq;
1153
1154         host->cur_slot = slot;
1155         host->mrq = mrq;
1156
1157         host->pending_events = 0;
1158         host->completed_events = 0;
1159         host->cmd_status = 0;
1160         host->data_status = 0;
1161         host->dir_status = 0;
1162
1163         data = cmd->data;
1164         if (data) {
1165                 mci_writel(host, TMOUT, 0xFFFFFFFF);
1166                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1167                 mci_writel(host, BLKSIZ, data->blksz);
1168         }
1169
1170         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1171
1172         /* this is the first command, send the initialization clock */
1173         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1174                 cmdflags |= SDMMC_CMD_INIT;
1175
1176         if (data) {
1177                 dw_mci_submit_data(host, data);
1178                 wmb(); /* drain writebuffer */
1179         }
1180
1181         dw_mci_start_command(host, cmd, cmdflags);
1182
1183         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1184                 unsigned long irqflags;
1185
1186                 /*
1187                  * Databook says to fail after 2ms w/ no response, but evidence
1188                  * shows that sometimes the cmd11 interrupt takes over 130ms.
1189                  * We'll set to 500ms, plus an extra jiffy just in case jiffies
1190                  * is just about to roll over.
1191                  *
1192                  * We do this whole thing under spinlock and only if the
1193                  * command hasn't already completed (indicating the the irq
1194                  * already ran so we don't want the timeout).
1195                  */
1196                 spin_lock_irqsave(&host->irq_lock, irqflags);
1197                 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1198                         mod_timer(&host->cmd11_timer,
1199                                 jiffies + msecs_to_jiffies(500) + 1);
1200                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1201         }
1202
1203         if (mrq->stop)
1204                 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
1205         else
1206                 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1207 }
1208
1209 static void dw_mci_start_request(struct dw_mci *host,
1210                                  struct dw_mci_slot *slot)
1211 {
1212         struct mmc_request *mrq = slot->mrq;
1213         struct mmc_command *cmd;
1214
1215         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1216         __dw_mci_start_request(host, slot, cmd);
1217 }
1218
1219 /* must be called with host->lock held */
1220 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1221                                  struct mmc_request *mrq)
1222 {
1223         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1224                  host->state);
1225
1226         slot->mrq = mrq;
1227
1228         if (host->state == STATE_WAITING_CMD11_DONE) {
1229                 dev_warn(&slot->mmc->class_dev,
1230                          "Voltage change didn't complete\n");
1231                 /*
1232                  * this case isn't expected to happen, so we can
1233                  * either crash here or just try to continue on
1234                  * in the closest possible state
1235                  */
1236                 host->state = STATE_IDLE;
1237         }
1238
1239         if (host->state == STATE_IDLE) {
1240                 host->state = STATE_SENDING_CMD;
1241                 dw_mci_start_request(host, slot);
1242         } else {
1243                 list_add_tail(&slot->queue_node, &host->queue);
1244         }
1245 }
1246
1247 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1248 {
1249         struct dw_mci_slot *slot = mmc_priv(mmc);
1250         struct dw_mci *host = slot->host;
1251
1252         WARN_ON(slot->mrq);
1253
1254         /*
1255          * The check for card presence and queueing of the request must be
1256          * atomic, otherwise the card could be removed in between and the
1257          * request wouldn't fail until another card was inserted.
1258          */
1259         spin_lock_bh(&host->lock);
1260
1261         if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1262                 spin_unlock_bh(&host->lock);
1263                 mrq->cmd->error = -ENOMEDIUM;
1264                 mmc_request_done(mmc, mrq);
1265                 return;
1266         }
1267
1268         dw_mci_queue_request(host, slot, mrq);
1269
1270         spin_unlock_bh(&host->lock);
1271 }
1272
1273 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1274 {
1275         struct dw_mci_slot *slot = mmc_priv(mmc);
1276         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1277         u32 regs;
1278         int ret;
1279
1280         switch (ios->bus_width) {
1281         case MMC_BUS_WIDTH_4:
1282                 slot->ctype = SDMMC_CTYPE_4BIT;
1283                 break;
1284         case MMC_BUS_WIDTH_8:
1285                 slot->ctype = SDMMC_CTYPE_8BIT;
1286                 break;
1287         default:
1288                 /* set default 1 bit mode */
1289                 slot->ctype = SDMMC_CTYPE_1BIT;
1290         }
1291
1292         regs = mci_readl(slot->host, UHS_REG);
1293
1294         /* DDR mode set */
1295         if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1296             ios->timing == MMC_TIMING_UHS_DDR50 ||
1297             ios->timing == MMC_TIMING_MMC_HS400)
1298                 regs |= ((0x1 << slot->id) << 16);
1299         else
1300                 regs &= ~((0x1 << slot->id) << 16);
1301
1302         mci_writel(slot->host, UHS_REG, regs);
1303         slot->host->timing = ios->timing;
1304
1305         /*
1306          * Use mirror of ios->clock to prevent race with mmc
1307          * core ios update when finding the minimum.
1308          */
1309         slot->clock = ios->clock;
1310
1311         if (drv_data && drv_data->set_ios)
1312                 drv_data->set_ios(slot->host, ios);
1313
1314         switch (ios->power_mode) {
1315         case MMC_POWER_UP:
1316                 if (!IS_ERR(mmc->supply.vmmc)) {
1317                         ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1318                                         ios->vdd);
1319                         if (ret) {
1320                                 dev_err(slot->host->dev,
1321                                         "failed to enable vmmc regulator\n");
1322                                 /*return, if failed turn on vmmc*/
1323                                 return;
1324                         }
1325                 }
1326                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1327                 regs = mci_readl(slot->host, PWREN);
1328                 regs |= (1 << slot->id);
1329                 mci_writel(slot->host, PWREN, regs);
1330                 break;
1331         case MMC_POWER_ON:
1332                 if (!slot->host->vqmmc_enabled) {
1333                         if (!IS_ERR(mmc->supply.vqmmc)) {
1334                                 ret = regulator_enable(mmc->supply.vqmmc);
1335                                 if (ret < 0)
1336                                         dev_err(slot->host->dev,
1337                                                 "failed to enable vqmmc\n");
1338                                 else
1339                                         slot->host->vqmmc_enabled = true;
1340
1341                         } else {
1342                                 /* Keep track so we don't reset again */
1343                                 slot->host->vqmmc_enabled = true;
1344                         }
1345
1346                         /* Reset our state machine after powering on */
1347                         dw_mci_ctrl_reset(slot->host,
1348                                           SDMMC_CTRL_ALL_RESET_FLAGS);
1349                 }
1350
1351                 /* Adjust clock / bus width after power is up */
1352                 dw_mci_setup_bus(slot, false);
1353
1354                 break;
1355         case MMC_POWER_OFF:
1356                 /* Turn clock off before power goes down */
1357                 dw_mci_setup_bus(slot, false);
1358
1359                 if (!IS_ERR(mmc->supply.vmmc))
1360                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1361
1362                 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1363                         regulator_disable(mmc->supply.vqmmc);
1364                 slot->host->vqmmc_enabled = false;
1365
1366                 regs = mci_readl(slot->host, PWREN);
1367                 regs &= ~(1 << slot->id);
1368                 mci_writel(slot->host, PWREN, regs);
1369                 break;
1370         default:
1371                 break;
1372         }
1373
1374         if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1375                 slot->host->state = STATE_IDLE;
1376 }
1377
1378 static int dw_mci_card_busy(struct mmc_host *mmc)
1379 {
1380         struct dw_mci_slot *slot = mmc_priv(mmc);
1381         u32 status;
1382
1383         /*
1384          * Check the busy bit which is low when DAT[3:0]
1385          * (the data lines) are 0000
1386          */
1387         status = mci_readl(slot->host, STATUS);
1388
1389         return !!(status & SDMMC_STATUS_BUSY);
1390 }
1391
1392 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1393 {
1394         struct dw_mci_slot *slot = mmc_priv(mmc);
1395         struct dw_mci *host = slot->host;
1396         const struct dw_mci_drv_data *drv_data = host->drv_data;
1397         u32 uhs;
1398         u32 v18 = SDMMC_UHS_18V << slot->id;
1399         int ret;
1400
1401         if (drv_data && drv_data->switch_voltage)
1402                 return drv_data->switch_voltage(mmc, ios);
1403
1404         /*
1405          * Program the voltage.  Note that some instances of dw_mmc may use
1406          * the UHS_REG for this.  For other instances (like exynos) the UHS_REG
1407          * does no harm but you need to set the regulator directly.  Try both.
1408          */
1409         uhs = mci_readl(host, UHS_REG);
1410         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1411                 uhs &= ~v18;
1412         else
1413                 uhs |= v18;
1414
1415         if (!IS_ERR(mmc->supply.vqmmc)) {
1416                 ret = mmc_regulator_set_vqmmc(mmc, ios);
1417
1418                 if (ret) {
1419                         dev_dbg(&mmc->class_dev,
1420                                          "Regulator set error %d - %s V\n",
1421                                          ret, uhs & v18 ? "1.8" : "3.3");
1422                         return ret;
1423                 }
1424         }
1425         mci_writel(host, UHS_REG, uhs);
1426
1427         return 0;
1428 }
1429
1430 static int dw_mci_get_ro(struct mmc_host *mmc)
1431 {
1432         int read_only;
1433         struct dw_mci_slot *slot = mmc_priv(mmc);
1434         int gpio_ro = mmc_gpio_get_ro(mmc);
1435
1436         /* Use platform get_ro function, else try on board write protect */
1437         if (!IS_ERR_VALUE(gpio_ro))
1438                 read_only = gpio_ro;
1439         else
1440                 read_only =
1441                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1442
1443         dev_dbg(&mmc->class_dev, "card is %s\n",
1444                 read_only ? "read-only" : "read-write");
1445
1446         return read_only;
1447 }
1448
1449 static int dw_mci_set_sdio_status(struct mmc_host *mmc, int val)
1450 {
1451         struct dw_mci_slot *slot = mmc_priv(mmc);
1452         struct dw_mci *host = slot->host;
1453
1454         if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
1455                 return 0;
1456
1457         spin_lock_bh(&host->lock);
1458
1459         if (val)
1460                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1461         else
1462                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1463
1464         spin_unlock_bh(&host->lock);
1465
1466         mmc_detect_change(slot->mmc, 20);
1467
1468         return 0;
1469 }
1470
1471 static int dw_mci_get_cd(struct mmc_host *mmc)
1472 {
1473         int present;
1474         struct dw_mci_slot *slot = mmc_priv(mmc);
1475         struct dw_mci_board *brd = slot->host->pdata;
1476         struct dw_mci *host = slot->host;
1477         int gpio_cd = mmc_gpio_get_cd(mmc);
1478
1479         /* Use platform get_cd function, else try onboard card detect */
1480         if ((brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) ||
1481             (mmc->caps & MMC_CAP_NONREMOVABLE))
1482                 present = 1;
1483         else if (!IS_ERR_VALUE(gpio_cd))
1484                 present = gpio_cd;
1485         else
1486                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1487                         == 0 ? 1 : 0;
1488
1489         spin_lock_bh(&host->lock);
1490         if (present) {
1491                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1492                 dev_dbg(&mmc->class_dev, "card is present\n");
1493         } else {
1494                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1495                 dev_dbg(&mmc->class_dev, "card is not present\n");
1496         }
1497         spin_unlock_bh(&host->lock);
1498
1499         return present;
1500 }
1501
1502 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1503 {
1504         struct dw_mci_slot *slot = mmc_priv(mmc);
1505         struct dw_mci *host = slot->host;
1506
1507         /*
1508          * Low power mode will stop the card clock when idle.  According to the
1509          * description of the CLKENA register we should disable low power mode
1510          * for SDIO cards if we need SDIO interrupts to work.
1511          */
1512         if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1513                 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1514                 u32 clk_en_a_old;
1515                 u32 clk_en_a;
1516
1517                 clk_en_a_old = mci_readl(host, CLKENA);
1518
1519                 if (card->type == MMC_TYPE_SDIO ||
1520                     card->type == MMC_TYPE_SD_COMBO) {
1521                         set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1522                         clk_en_a = clk_en_a_old & ~clken_low_pwr;
1523                 } else {
1524                         clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1525                         clk_en_a = clk_en_a_old | clken_low_pwr;
1526                 }
1527
1528                 if (clk_en_a != clk_en_a_old) {
1529                         mci_writel(host, CLKENA, clk_en_a);
1530                         mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1531                                      SDMMC_CMD_PRV_DAT_WAIT, 0);
1532                 }
1533         }
1534 }
1535
1536 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1537 {
1538         struct dw_mci_slot *slot = mmc_priv(mmc);
1539         struct dw_mci *host = slot->host;
1540         unsigned long irqflags;
1541         u32 int_mask;
1542
1543         spin_lock_irqsave(&host->irq_lock, irqflags);
1544
1545         /* Enable/disable Slot Specific SDIO interrupt */
1546         int_mask = mci_readl(host, INTMASK);
1547         if (enb)
1548                 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1549         else
1550                 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1551         mci_writel(host, INTMASK, int_mask);
1552
1553         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1554 }
1555
1556 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1557 {
1558         struct dw_mci_slot *slot = mmc_priv(mmc);
1559         struct dw_mci *host = slot->host;
1560         const struct dw_mci_drv_data *drv_data = host->drv_data;
1561         int err = -EINVAL;
1562
1563         if (drv_data && drv_data->execute_tuning)
1564                 err = drv_data->execute_tuning(slot, opcode);
1565         return err;
1566 }
1567
1568 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1569                                        struct mmc_ios *ios)
1570 {
1571         struct dw_mci_slot *slot = mmc_priv(mmc);
1572         struct dw_mci *host = slot->host;
1573         const struct dw_mci_drv_data *drv_data = host->drv_data;
1574
1575         if (drv_data && drv_data->prepare_hs400_tuning)
1576                 return drv_data->prepare_hs400_tuning(host, ios);
1577
1578         return 0;
1579 }
1580
1581 static const struct mmc_host_ops dw_mci_ops = {
1582         .request                = dw_mci_request,
1583         .pre_req                = dw_mci_pre_req,
1584         .post_req               = dw_mci_post_req,
1585         .set_ios                = dw_mci_set_ios,
1586         .set_sdio_status        = dw_mci_set_sdio_status,
1587         .get_ro                 = dw_mci_get_ro,
1588         .get_cd                 = dw_mci_get_cd,
1589         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
1590         .execute_tuning         = dw_mci_execute_tuning,
1591         .card_busy              = dw_mci_card_busy,
1592         .start_signal_voltage_switch = dw_mci_switch_voltage,
1593         .init_card              = dw_mci_init_card,
1594         .prepare_hs400_tuning   = dw_mci_prepare_hs400_tuning,
1595 };
1596
1597 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1598         __releases(&host->lock)
1599         __acquires(&host->lock)
1600 {
1601         struct dw_mci_slot *slot;
1602         struct mmc_host *prev_mmc = host->cur_slot->mmc;
1603
1604         WARN_ON(host->cmd || host->data);
1605
1606         host->cur_slot->mrq = NULL;
1607         host->mrq = NULL;
1608         if (!list_empty(&host->queue)) {
1609                 slot = list_entry(host->queue.next,
1610                                   struct dw_mci_slot, queue_node);
1611                 list_del(&slot->queue_node);
1612                 dev_vdbg(host->dev, "list not empty: %s is next\n",
1613                          mmc_hostname(slot->mmc));
1614                 host->state = STATE_SENDING_CMD;
1615                 dw_mci_start_request(host, slot);
1616         } else {
1617                 dev_vdbg(host->dev, "list empty\n");
1618
1619                 if (host->state == STATE_SENDING_CMD11)
1620                         host->state = STATE_WAITING_CMD11_DONE;
1621                 else
1622                         host->state = STATE_IDLE;
1623         }
1624
1625         spin_unlock(&host->lock);
1626         mmc_request_done(prev_mmc, mrq);
1627         spin_lock(&host->lock);
1628 }
1629
1630 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1631 {
1632         u32 status = host->cmd_status;
1633
1634         host->cmd_status = 0;
1635
1636         /* Read the response from the card (up to 16 bytes) */
1637         if (cmd->flags & MMC_RSP_PRESENT) {
1638                 if (cmd->flags & MMC_RSP_136) {
1639                         cmd->resp[3] = mci_readl(host, RESP0);
1640                         cmd->resp[2] = mci_readl(host, RESP1);
1641                         cmd->resp[1] = mci_readl(host, RESP2);
1642                         cmd->resp[0] = mci_readl(host, RESP3);
1643                 } else {
1644                         cmd->resp[0] = mci_readl(host, RESP0);
1645                         cmd->resp[1] = 0;
1646                         cmd->resp[2] = 0;
1647                         cmd->resp[3] = 0;
1648                 }
1649         }
1650
1651         if (status & SDMMC_INT_RTO)
1652                 cmd->error = -ETIMEDOUT;
1653         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1654                 cmd->error = -EILSEQ;
1655         else if (status & SDMMC_INT_RESP_ERR)
1656                 cmd->error = -EIO;
1657         else
1658                 cmd->error = 0;
1659
1660         if (cmd->error) {
1661                 /* newer ip versions need a delay between retries */
1662                 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
1663                         mdelay(20);
1664         }
1665
1666         return cmd->error;
1667 }
1668
1669 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1670 {
1671         u32 status = host->data_status;
1672
1673         if (status & DW_MCI_DATA_ERROR_FLAGS) {
1674                 if (status & SDMMC_INT_DRTO) {
1675                         data->error = -ETIMEDOUT;
1676                 } else if (status & SDMMC_INT_DCRC) {
1677                         data->error = -EILSEQ;
1678                 } else if (status & SDMMC_INT_EBE) {
1679                         if (host->dir_status ==
1680                                 DW_MCI_SEND_STATUS) {
1681                                 /*
1682                                  * No data CRC status was returned.
1683                                  * The number of bytes transferred
1684                                  * will be exaggerated in PIO mode.
1685                                  */
1686                                 data->bytes_xfered = 0;
1687                                 data->error = -ETIMEDOUT;
1688                         } else if (host->dir_status ==
1689                                         DW_MCI_RECV_STATUS) {
1690                                 data->error = -EIO;
1691                         }
1692                 } else {
1693                         /* SDMMC_INT_SBE is included */
1694                         data->error = -EIO;
1695                 }
1696
1697                 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1698
1699                 /*
1700                  * After an error, there may be data lingering
1701                  * in the FIFO
1702                  */
1703                 dw_mci_reset(host);
1704         } else {
1705                 data->bytes_xfered = data->blocks * data->blksz;
1706                 data->error = 0;
1707         }
1708
1709         return data->error;
1710 }
1711
1712 static void dw_mci_set_drto(struct dw_mci *host)
1713 {
1714         unsigned int drto_clks;
1715         unsigned int drto_ms;
1716
1717         drto_clks = mci_readl(host, TMOUT) >> 8;
1718         drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1719
1720         /* add a bit spare time */
1721         drto_ms += 10;
1722
1723         mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1724 }
1725
1726 static void dw_mci_tasklet_func(unsigned long priv)
1727 {
1728         struct dw_mci *host = (struct dw_mci *)priv;
1729         struct mmc_data *data;
1730         struct mmc_command *cmd;
1731         struct mmc_request *mrq;
1732         enum dw_mci_state state;
1733         enum dw_mci_state prev_state;
1734         unsigned int err;
1735
1736         spin_lock(&host->lock);
1737
1738         state = host->state;
1739         data = host->data;
1740         mrq = host->mrq;
1741
1742         do {
1743                 prev_state = state;
1744
1745                 switch (state) {
1746                 case STATE_IDLE:
1747                 case STATE_WAITING_CMD11_DONE:
1748                         break;
1749
1750                 case STATE_SENDING_CMD11:
1751                 case STATE_SENDING_CMD:
1752                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1753                                                 &host->pending_events))
1754                                 break;
1755
1756                         cmd = host->cmd;
1757                         host->cmd = NULL;
1758                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1759                         err = dw_mci_command_complete(host, cmd);
1760                         if (cmd == mrq->sbc && !err) {
1761                                 prev_state = state = STATE_SENDING_CMD;
1762                                 __dw_mci_start_request(host, host->cur_slot,
1763                                                        mrq->cmd);
1764                                 goto unlock;
1765                         }
1766
1767                         if (cmd->data && err) {
1768                                 dw_mci_stop_dma(host);
1769                                 send_stop_abort(host, data);
1770                                 state = STATE_SENDING_STOP;
1771                                 break;
1772                         }
1773
1774                         if (!cmd->data || err) {
1775                                 dw_mci_request_end(host, mrq);
1776                                 goto unlock;
1777                         }
1778
1779                         prev_state = state = STATE_SENDING_DATA;
1780                         /* fall through */
1781
1782                 case STATE_SENDING_DATA:
1783                         /*
1784                          * We could get a data error and never a transfer
1785                          * complete so we'd better check for it here.
1786                          *
1787                          * Note that we don't really care if we also got a
1788                          * transfer complete; stopping the DMA and sending an
1789                          * abort won't hurt.
1790                          */
1791                         if (test_and_clear_bit(EVENT_DATA_ERROR,
1792                                                &host->pending_events)) {
1793                                 dw_mci_stop_dma(host);
1794                                 if (data->stop ||
1795                                     !(host->data_status & (SDMMC_INT_DRTO |
1796                                                            SDMMC_INT_EBE)))
1797                                         send_stop_abort(host, data);
1798                                 state = STATE_DATA_ERROR;
1799                                 break;
1800                         }
1801
1802                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1803                                                 &host->pending_events)) {
1804                                 /*
1805                                  * If all data-related interrupts don't come
1806                                  * within the given time in reading data state.
1807                                  */
1808                                 if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) &&
1809                                     (host->dir_status == DW_MCI_RECV_STATUS))
1810                                         dw_mci_set_drto(host);
1811                                 break;
1812                         }
1813
1814                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1815
1816                         /*
1817                          * Handle an EVENT_DATA_ERROR that might have shown up
1818                          * before the transfer completed.  This might not have
1819                          * been caught by the check above because the interrupt
1820                          * could have gone off between the previous check and
1821                          * the check for transfer complete.
1822                          *
1823                          * Technically this ought not be needed assuming we
1824                          * get a DATA_COMPLETE eventually (we'll notice the
1825                          * error and end the request), but it shouldn't hurt.
1826                          *
1827                          * This has the advantage of sending the stop command.
1828                          */
1829                         if (test_and_clear_bit(EVENT_DATA_ERROR,
1830                                                &host->pending_events)) {
1831                                 dw_mci_stop_dma(host);
1832                                 if (data->stop ||
1833                                     !(host->data_status & (SDMMC_INT_DRTO |
1834                                                            SDMMC_INT_EBE)))
1835                                         send_stop_abort(host, data);
1836                                 state = STATE_DATA_ERROR;
1837                                 break;
1838                         }
1839                         prev_state = state = STATE_DATA_BUSY;
1840
1841                         /* fall through */
1842
1843                 case STATE_DATA_BUSY:
1844                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1845                                                 &host->pending_events)) {
1846                                 /*
1847                                  * If data error interrupt comes but data over
1848                                  * interrupt doesn't come within the given time.
1849                                  * in reading data state.
1850                                  */
1851                                 if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) &&
1852                                     (host->dir_status == DW_MCI_RECV_STATUS))
1853                                         dw_mci_set_drto(host);
1854                                 break;
1855                         }
1856
1857                         host->data = NULL;
1858                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1859                         err = dw_mci_data_complete(host, data);
1860
1861                         if (!err) {
1862                                 if (!data->stop || mrq->sbc) {
1863                                         if (mrq->sbc && data->stop)
1864                                                 data->stop->error = 0;
1865                                         dw_mci_request_end(host, mrq);
1866                                         goto unlock;
1867                                 }
1868
1869                                 /* stop command for open-ended transfer*/
1870                                 if (data->stop)
1871                                         send_stop_abort(host, data);
1872                         } else {
1873                                 /*
1874                                  * If we don't have a command complete now we'll
1875                                  * never get one since we just reset everything;
1876                                  * better end the request.
1877                                  *
1878                                  * If we do have a command complete we'll fall
1879                                  * through to the SENDING_STOP command and
1880                                  * everything will be peachy keen.
1881                                  */
1882                                 if (!test_bit(EVENT_CMD_COMPLETE,
1883                                               &host->pending_events)) {
1884                                         host->cmd = NULL;
1885                                         dw_mci_request_end(host, mrq);
1886                                         goto unlock;
1887                                 }
1888                         }
1889
1890                         /*
1891                          * If err has non-zero,
1892                          * stop-abort command has been already issued.
1893                          */
1894                         prev_state = state = STATE_SENDING_STOP;
1895
1896                         /* fall through */
1897
1898                 case STATE_SENDING_STOP:
1899                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1900                                                 &host->pending_events))
1901                                 break;
1902
1903                         /* CMD error in data command */
1904                         if (mrq->cmd->error && mrq->data)
1905                                 dw_mci_reset(host);
1906
1907                         host->cmd = NULL;
1908                         host->data = NULL;
1909
1910                         if (mrq->stop)
1911                                 dw_mci_command_complete(host, mrq->stop);
1912                         else
1913                                 host->cmd_status = 0;
1914
1915                         dw_mci_request_end(host, mrq);
1916                         goto unlock;
1917
1918                 case STATE_DATA_ERROR:
1919                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1920                                                 &host->pending_events))
1921                                 break;
1922
1923                         state = STATE_DATA_BUSY;
1924                         break;
1925                 }
1926         } while (state != prev_state);
1927
1928         host->state = state;
1929 unlock:
1930         spin_unlock(&host->lock);
1931
1932 }
1933
1934 /* push final bytes to part_buf, only use during push */
1935 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
1936 {
1937         memcpy((void *)&host->part_buf, buf, cnt);
1938         host->part_buf_count = cnt;
1939 }
1940
1941 /* append bytes to part_buf, only use during push */
1942 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1943 {
1944         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1945         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1946         host->part_buf_count += cnt;
1947         return cnt;
1948 }
1949
1950 /* pull first bytes from part_buf, only use during pull */
1951 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1952 {
1953         cnt = min_t(int, cnt, host->part_buf_count);
1954         if (cnt) {
1955                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1956                        cnt);
1957                 host->part_buf_count -= cnt;
1958                 host->part_buf_start += cnt;
1959         }
1960         return cnt;
1961 }
1962
1963 /* pull final bytes from the part_buf, assuming it's just been filled */
1964 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1965 {
1966         memcpy(buf, &host->part_buf, cnt);
1967         host->part_buf_start = cnt;
1968         host->part_buf_count = (1 << host->data_shift) - cnt;
1969 }
1970
1971 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1972 {
1973         struct mmc_data *data = host->data;
1974         int init_cnt = cnt;
1975
1976         /* try and push anything in the part_buf */
1977         if (unlikely(host->part_buf_count)) {
1978                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1979
1980                 buf += len;
1981                 cnt -= len;
1982                 if (host->part_buf_count == 2) {
1983                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
1984                         host->part_buf_count = 0;
1985                 }
1986         }
1987 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1988         if (unlikely((unsigned long)buf & 0x1)) {
1989                 while (cnt >= 2) {
1990                         u16 aligned_buf[64];
1991                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1992                         int items = len >> 1;
1993                         int i;
1994                         /* memcpy from input buffer into aligned buffer */
1995                         memcpy(aligned_buf, buf, len);
1996                         buf += len;
1997                         cnt -= len;
1998                         /* push data from aligned buffer into fifo */
1999                         for (i = 0; i < items; ++i)
2000                                 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2001                 }
2002         } else
2003 #endif
2004         {
2005                 u16 *pdata = buf;
2006
2007                 for (; cnt >= 2; cnt -= 2)
2008                         mci_fifo_writew(host->fifo_reg, *pdata++);
2009                 buf = pdata;
2010         }
2011         /* put anything remaining in the part_buf */
2012         if (cnt) {
2013                 dw_mci_set_part_bytes(host, buf, cnt);
2014                  /* Push data if we have reached the expected data length */
2015                 if ((data->bytes_xfered + init_cnt) ==
2016                     (data->blksz * data->blocks))
2017                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
2018         }
2019 }
2020
2021 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2022 {
2023 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2024         if (unlikely((unsigned long)buf & 0x1)) {
2025                 while (cnt >= 2) {
2026                         /* pull data from fifo into aligned buffer */
2027                         u16 aligned_buf[64];
2028                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2029                         int items = len >> 1;
2030                         int i;
2031
2032                         for (i = 0; i < items; ++i)
2033                                 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2034                         /* memcpy from aligned buffer into output buffer */
2035                         memcpy(buf, aligned_buf, len);
2036                         buf += len;
2037                         cnt -= len;
2038                 }
2039         } else
2040 #endif
2041         {
2042                 u16 *pdata = buf;
2043
2044                 for (; cnt >= 2; cnt -= 2)
2045                         *pdata++ = mci_fifo_readw(host->fifo_reg);
2046                 buf = pdata;
2047         }
2048         if (cnt) {
2049                 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2050                 dw_mci_pull_final_bytes(host, buf, cnt);
2051         }
2052 }
2053
2054 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2055 {
2056         struct mmc_data *data = host->data;
2057         int init_cnt = cnt;
2058
2059         /* try and push anything in the part_buf */
2060         if (unlikely(host->part_buf_count)) {
2061                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2062
2063                 buf += len;
2064                 cnt -= len;
2065                 if (host->part_buf_count == 4) {
2066                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2067                         host->part_buf_count = 0;
2068                 }
2069         }
2070 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2071         if (unlikely((unsigned long)buf & 0x3)) {
2072                 while (cnt >= 4) {
2073                         u32 aligned_buf[32];
2074                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2075                         int items = len >> 2;
2076                         int i;
2077                         /* memcpy from input buffer into aligned buffer */
2078                         memcpy(aligned_buf, buf, len);
2079                         buf += len;
2080                         cnt -= len;
2081                         /* push data from aligned buffer into fifo */
2082                         for (i = 0; i < items; ++i)
2083                                 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2084                 }
2085         } else
2086 #endif
2087         {
2088                 u32 *pdata = buf;
2089
2090                 for (; cnt >= 4; cnt -= 4)
2091                         mci_fifo_writel(host->fifo_reg, *pdata++);
2092                 buf = pdata;
2093         }
2094         /* put anything remaining in the part_buf */
2095         if (cnt) {
2096                 dw_mci_set_part_bytes(host, buf, cnt);
2097                  /* Push data if we have reached the expected data length */
2098                 if ((data->bytes_xfered + init_cnt) ==
2099                     (data->blksz * data->blocks))
2100                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2101         }
2102 }
2103
2104 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2105 {
2106 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2107         if (unlikely((unsigned long)buf & 0x3)) {
2108                 while (cnt >= 4) {
2109                         /* pull data from fifo into aligned buffer */
2110                         u32 aligned_buf[32];
2111                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2112                         int items = len >> 2;
2113                         int i;
2114
2115                         for (i = 0; i < items; ++i)
2116                                 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2117                         /* memcpy from aligned buffer into output buffer */
2118                         memcpy(buf, aligned_buf, len);
2119                         buf += len;
2120                         cnt -= len;
2121                 }
2122         } else
2123 #endif
2124         {
2125                 u32 *pdata = buf;
2126
2127                 for (; cnt >= 4; cnt -= 4)
2128                         *pdata++ = mci_fifo_readl(host->fifo_reg);
2129                 buf = pdata;
2130         }
2131         if (cnt) {
2132                 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2133                 dw_mci_pull_final_bytes(host, buf, cnt);
2134         }
2135 }
2136
2137 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2138 {
2139         struct mmc_data *data = host->data;
2140         int init_cnt = cnt;
2141
2142         /* try and push anything in the part_buf */
2143         if (unlikely(host->part_buf_count)) {
2144                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2145
2146                 buf += len;
2147                 cnt -= len;
2148
2149                 if (host->part_buf_count == 8) {
2150                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2151                         host->part_buf_count = 0;
2152                 }
2153         }
2154 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2155         if (unlikely((unsigned long)buf & 0x7)) {
2156                 while (cnt >= 8) {
2157                         u64 aligned_buf[16];
2158                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2159                         int items = len >> 3;
2160                         int i;
2161                         /* memcpy from input buffer into aligned buffer */
2162                         memcpy(aligned_buf, buf, len);
2163                         buf += len;
2164                         cnt -= len;
2165                         /* push data from aligned buffer into fifo */
2166                         for (i = 0; i < items; ++i)
2167                                 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2168                 }
2169         } else
2170 #endif
2171         {
2172                 u64 *pdata = buf;
2173
2174                 for (; cnt >= 8; cnt -= 8)
2175                         mci_fifo_writeq(host->fifo_reg, *pdata++);
2176                 buf = pdata;
2177         }
2178         /* put anything remaining in the part_buf */
2179         if (cnt) {
2180                 dw_mci_set_part_bytes(host, buf, cnt);
2181                 /* Push data if we have reached the expected data length */
2182                 if ((data->bytes_xfered + init_cnt) ==
2183                     (data->blksz * data->blocks))
2184                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2185         }
2186 }
2187
2188 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2189 {
2190 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2191         if (unlikely((unsigned long)buf & 0x7)) {
2192                 while (cnt >= 8) {
2193                         /* pull data from fifo into aligned buffer */
2194                         u64 aligned_buf[16];
2195                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2196                         int items = len >> 3;
2197                         int i;
2198
2199                         for (i = 0; i < items; ++i)
2200                                 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2201
2202                         /* memcpy from aligned buffer into output buffer */
2203                         memcpy(buf, aligned_buf, len);
2204                         buf += len;
2205                         cnt -= len;
2206                 }
2207         } else
2208 #endif
2209         {
2210                 u64 *pdata = buf;
2211
2212                 for (; cnt >= 8; cnt -= 8)
2213                         *pdata++ = mci_fifo_readq(host->fifo_reg);
2214                 buf = pdata;
2215         }
2216         if (cnt) {
2217                 host->part_buf = mci_fifo_readq(host->fifo_reg);
2218                 dw_mci_pull_final_bytes(host, buf, cnt);
2219         }
2220 }
2221
2222 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2223 {
2224         int len;
2225
2226         /* get remaining partial bytes */
2227         len = dw_mci_pull_part_bytes(host, buf, cnt);
2228         if (unlikely(len == cnt))
2229                 return;
2230         buf += len;
2231         cnt -= len;
2232
2233         /* get the rest of the data */
2234         host->pull_data(host, buf, cnt);
2235 }
2236
2237 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2238 {
2239         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2240         void *buf;
2241         unsigned int offset;
2242         struct mmc_data *data = host->data;
2243         int shift = host->data_shift;
2244         u32 status;
2245         unsigned int len;
2246         unsigned int remain, fcnt;
2247
2248         do {
2249                 if (!sg_miter_next(sg_miter))
2250                         goto done;
2251
2252                 host->sg = sg_miter->piter.sg;
2253                 buf = sg_miter->addr;
2254                 remain = sg_miter->length;
2255                 offset = 0;
2256
2257                 do {
2258                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2259                                         << shift) + host->part_buf_count;
2260                         len = min(remain, fcnt);
2261                         if (!len)
2262                                 break;
2263                         dw_mci_pull_data(host, (void *)(buf + offset), len);
2264                         data->bytes_xfered += len;
2265                         offset += len;
2266                         remain -= len;
2267                 } while (remain);
2268
2269                 sg_miter->consumed = offset;
2270                 status = mci_readl(host, MINTSTS);
2271                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2272         /* if the RXDR is ready read again */
2273         } while ((status & SDMMC_INT_RXDR) ||
2274                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2275
2276         if (!remain) {
2277                 if (!sg_miter_next(sg_miter))
2278                         goto done;
2279                 sg_miter->consumed = 0;
2280         }
2281         sg_miter_stop(sg_miter);
2282         return;
2283
2284 done:
2285         sg_miter_stop(sg_miter);
2286         host->sg = NULL;
2287         smp_wmb(); /* drain writebuffer */
2288         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2289 }
2290
2291 static void dw_mci_write_data_pio(struct dw_mci *host)
2292 {
2293         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2294         void *buf;
2295         unsigned int offset;
2296         struct mmc_data *data = host->data;
2297         int shift = host->data_shift;
2298         u32 status;
2299         unsigned int len;
2300         unsigned int fifo_depth = host->fifo_depth;
2301         unsigned int remain, fcnt;
2302
2303         do {
2304                 if (!sg_miter_next(sg_miter))
2305                         goto done;
2306
2307                 host->sg = sg_miter->piter.sg;
2308                 buf = sg_miter->addr;
2309                 remain = sg_miter->length;
2310                 offset = 0;
2311
2312                 do {
2313                         fcnt = ((fifo_depth -
2314                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2315                                         << shift) - host->part_buf_count;
2316                         len = min(remain, fcnt);
2317                         if (!len)
2318                                 break;
2319                         host->push_data(host, (void *)(buf + offset), len);
2320                         data->bytes_xfered += len;
2321                         offset += len;
2322                         remain -= len;
2323                 } while (remain);
2324
2325                 sg_miter->consumed = offset;
2326                 status = mci_readl(host, MINTSTS);
2327                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2328         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2329
2330         if (!remain) {
2331                 if (!sg_miter_next(sg_miter))
2332                         goto done;
2333                 sg_miter->consumed = 0;
2334         }
2335         sg_miter_stop(sg_miter);
2336         return;
2337
2338 done:
2339         sg_miter_stop(sg_miter);
2340         host->sg = NULL;
2341         smp_wmb(); /* drain writebuffer */
2342         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2343 }
2344
2345 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2346 {
2347         if (!host->cmd_status)
2348                 host->cmd_status = status;
2349
2350         smp_wmb(); /* drain writebuffer */
2351
2352         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2353         tasklet_schedule(&host->tasklet);
2354 }
2355
2356 static void dw_mci_handle_cd(struct dw_mci *host)
2357 {
2358         int i;
2359
2360         for (i = 0; i < host->num_slots; i++) {
2361                 struct dw_mci_slot *slot = host->slot[i];
2362
2363                 if (!slot)
2364                         continue;
2365
2366                 if (slot->mmc->ops->card_event)
2367                         slot->mmc->ops->card_event(slot->mmc);
2368                 mmc_detect_change(slot->mmc,
2369                         msecs_to_jiffies(host->pdata->detect_delay_ms));
2370         }
2371 }
2372
2373 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2374 {
2375         struct dw_mci *host = dev_id;
2376         u32 pending;
2377         int i;
2378
2379         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2380
2381         /*
2382          * DTO fix - version 2.10a and below, and only if internal DMA
2383          * is configured.
2384          */
2385         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
2386                 if (!pending &&
2387                     ((mci_readl(host, STATUS) >> 17) & 0x1fff))
2388                         pending |= SDMMC_INT_DATA_OVER;
2389         }
2390
2391         if (pending) {
2392                 /* Check volt switch first, since it can look like an error */
2393                 if ((host->state == STATE_SENDING_CMD11) &&
2394                     (pending & SDMMC_INT_VOLT_SWITCH)) {
2395                         unsigned long irqflags;
2396
2397                         mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2398                         pending &= ~SDMMC_INT_VOLT_SWITCH;
2399
2400                         /*
2401                          * Hold the lock; we know cmd11_timer can't be kicked
2402                          * off after the lock is released, so safe to delete.
2403                          */
2404                         spin_lock_irqsave(&host->irq_lock, irqflags);
2405                         dw_mci_cmd_interrupt(host, pending);
2406                         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2407
2408                         del_timer(&host->cmd11_timer);
2409                 }
2410
2411                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2412                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2413                         host->cmd_status = pending;
2414                         smp_wmb(); /* drain writebuffer */
2415                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2416                 }
2417
2418                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2419                         /* if there is an error report DATA_ERROR */
2420                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2421                         host->data_status = pending;
2422                         smp_wmb(); /* drain writebuffer */
2423                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
2424                         tasklet_schedule(&host->tasklet);
2425                 }
2426
2427                 if (pending & SDMMC_INT_DATA_OVER) {
2428                         if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO)
2429                                 del_timer(&host->dto_timer);
2430
2431                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2432                         if (!host->data_status)
2433                                 host->data_status = pending;
2434                         smp_wmb(); /* drain writebuffer */
2435                         if (host->dir_status == DW_MCI_RECV_STATUS) {
2436                                 if (host->sg != NULL)
2437                                         dw_mci_read_data_pio(host, true);
2438                         }
2439                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2440                         tasklet_schedule(&host->tasklet);
2441                 }
2442
2443                 if (pending & SDMMC_INT_RXDR) {
2444                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2445                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2446                                 dw_mci_read_data_pio(host, false);
2447                 }
2448
2449                 if (pending & SDMMC_INT_TXDR) {
2450                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2451                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2452                                 dw_mci_write_data_pio(host);
2453                 }
2454
2455                 if (pending & SDMMC_INT_CMD_DONE) {
2456                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2457                         dw_mci_cmd_interrupt(host, pending);
2458                 }
2459
2460                 if (pending & SDMMC_INT_CD) {
2461                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
2462                         dw_mci_handle_cd(host);
2463                 }
2464
2465                 /* Handle SDIO Interrupts */
2466                 for (i = 0; i < host->num_slots; i++) {
2467                         struct dw_mci_slot *slot = host->slot[i];
2468
2469                         if (!slot)
2470                                 continue;
2471
2472                         if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2473                                 mci_writel(host, RINTSTS,
2474                                            SDMMC_INT_SDIO(slot->sdio_id));
2475                                 mmc_signal_sdio_irq(slot->mmc);
2476                         }
2477                 }
2478
2479         }
2480
2481         if (host->use_dma != TRANS_MODE_IDMAC)
2482                 return IRQ_HANDLED;
2483
2484         /* Handle IDMA interrupts */
2485         if (host->dma_64bit_address == 1) {
2486                 pending = mci_readl(host, IDSTS64);
2487                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2488                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2489                                                         SDMMC_IDMAC_INT_RI);
2490                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2491                         host->dma_ops->complete((void *)host);
2492                 }
2493         } else {
2494                 pending = mci_readl(host, IDSTS);
2495                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2496                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2497                                                         SDMMC_IDMAC_INT_RI);
2498                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2499                         host->dma_ops->complete((void *)host);
2500                 }
2501         }
2502
2503         return IRQ_HANDLED;
2504 }
2505
2506 #ifdef CONFIG_OF
2507 /* given a slot, find out the device node representing that slot */
2508 static struct device_node *dw_mci_of_find_slot_node(struct dw_mci_slot *slot)
2509 {
2510         struct device *dev = slot->mmc->parent;
2511         struct device_node *np;
2512         const __be32 *addr;
2513         int len;
2514
2515         if (!dev || !dev->of_node)
2516                 return NULL;
2517
2518         for_each_child_of_node(dev->of_node, np) {
2519                 addr = of_get_property(np, "reg", &len);
2520                 if (!addr || (len < sizeof(int)))
2521                         continue;
2522                 if (be32_to_cpup(addr) == slot->id)
2523                         return np;
2524         }
2525         return NULL;
2526 }
2527
2528 static void dw_mci_slot_of_parse(struct dw_mci_slot *slot)
2529 {
2530         struct device_node *np = dw_mci_of_find_slot_node(slot);
2531
2532         if (!np)
2533                 return;
2534
2535         if (of_property_read_bool(np, "disable-wp")) {
2536                 slot->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
2537                 dev_warn(slot->mmc->parent,
2538                         "Slot quirk 'disable-wp' is deprecated\n");
2539         }
2540 }
2541 #else /* CONFIG_OF */
2542 static void dw_mci_slot_of_parse(struct dw_mci_slot *slot)
2543 {
2544 }
2545 #endif /* CONFIG_OF */
2546
2547 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2548 {
2549         struct mmc_host *mmc;
2550         struct dw_mci_slot *slot;
2551         const struct dw_mci_drv_data *drv_data = host->drv_data;
2552         int ctrl_id, ret;
2553         u32 freq[2];
2554
2555         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2556         if (!mmc)
2557                 return -ENOMEM;
2558
2559         slot = mmc_priv(mmc);
2560         slot->id = id;
2561         slot->sdio_id = host->sdio_id0 + id;
2562         slot->mmc = mmc;
2563         slot->host = host;
2564         host->slot[id] = slot;
2565
2566         mmc->ops = &dw_mci_ops;
2567         if (of_property_read_u32_array(host->dev->of_node,
2568                                        "clock-freq-min-max", freq, 2)) {
2569                 mmc->f_min = DW_MCI_FREQ_MIN;
2570                 mmc->f_max = DW_MCI_FREQ_MAX;
2571         } else {
2572                 mmc->f_min = freq[0];
2573                 mmc->f_max = freq[1];
2574         }
2575
2576         /*if there are external regulators, get them*/
2577         ret = mmc_regulator_get_supply(mmc);
2578         if (ret == -EPROBE_DEFER)
2579                 goto err_host_allocated;
2580
2581         if (!mmc->ocr_avail)
2582                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2583
2584         if (host->pdata->caps)
2585                 mmc->caps = host->pdata->caps;
2586
2587         if (host->pdata->pm_caps)
2588                 mmc->pm_caps = host->pdata->pm_caps;
2589
2590         if (host->dev->of_node) {
2591                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2592                 if (ctrl_id < 0)
2593                         ctrl_id = 0;
2594         } else {
2595                 ctrl_id = to_platform_device(host->dev)->id;
2596         }
2597         if (drv_data && drv_data->caps)
2598                 mmc->caps |= drv_data->caps[ctrl_id];
2599
2600         if (host->pdata->caps2)
2601                 mmc->caps2 = host->pdata->caps2;
2602
2603         dw_mci_slot_of_parse(slot);
2604
2605         ret = mmc_of_parse(mmc);
2606         if (ret)
2607                 goto err_host_allocated;
2608
2609         /* Useful defaults if platform data is unset. */
2610         if (host->use_dma == TRANS_MODE_IDMAC) {
2611                 mmc->max_segs = host->ring_size;
2612                 mmc->max_blk_size = 65536;
2613                 mmc->max_seg_size = 0x1000;
2614                 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2615                 mmc->max_blk_count = mmc->max_req_size / 512;
2616         } else if (host->use_dma == TRANS_MODE_EDMAC) {
2617                 mmc->max_segs = 64;
2618                 mmc->max_blk_size = 65536;
2619                 mmc->max_blk_count = 65535;
2620                 mmc->max_req_size =
2621                                 mmc->max_blk_size * mmc->max_blk_count;
2622                 mmc->max_seg_size = mmc->max_req_size;
2623         } else {
2624                 /* TRANS_MODE_PIO */
2625                 mmc->max_segs = 64;
2626                 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
2627                 mmc->max_blk_count = 512;
2628                 mmc->max_req_size = mmc->max_blk_size *
2629                                     mmc->max_blk_count;
2630                 mmc->max_seg_size = mmc->max_req_size;
2631         }
2632
2633         if (dw_mci_get_cd(mmc))
2634                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2635         else
2636                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2637
2638         ret = mmc_add_host(mmc);
2639         if (ret)
2640                 goto err_host_allocated;
2641
2642 #if defined(CONFIG_DEBUG_FS)
2643         dw_mci_init_debugfs(slot);
2644 #endif
2645
2646         return 0;
2647
2648 err_host_allocated:
2649         mmc_free_host(mmc);
2650         return ret;
2651 }
2652
2653 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2654 {
2655         /* Debugfs stuff is cleaned up by mmc core */
2656         mmc_remove_host(slot->mmc);
2657         slot->host->slot[id] = NULL;
2658         mmc_free_host(slot->mmc);
2659 }
2660
2661 static void dw_mci_init_dma(struct dw_mci *host)
2662 {
2663         int addr_config;
2664         struct device *dev = host->dev;
2665         struct device_node *np = dev->of_node;
2666
2667         /*
2668         * Check tansfer mode from HCON[17:16]
2669         * Clear the ambiguous description of dw_mmc databook:
2670         * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2671         * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2672         * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2673         * 2b'11: Non DW DMA Interface -> pio only
2674         * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2675         * simpler request/acknowledge handshake mechanism and both of them
2676         * are regarded as external dma master for dw_mmc.
2677         */
2678         host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2679         if (host->use_dma == DMA_INTERFACE_IDMA) {
2680                 host->use_dma = TRANS_MODE_IDMAC;
2681         } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2682                    host->use_dma == DMA_INTERFACE_GDMA) {
2683                 host->use_dma = TRANS_MODE_EDMAC;
2684         } else {
2685                 goto no_dma;
2686         }
2687
2688         /* Determine which DMA interface to use */
2689         if (host->use_dma == TRANS_MODE_IDMAC) {
2690                 /*
2691                 * Check ADDR_CONFIG bit in HCON to find
2692                 * IDMAC address bus width
2693                 */
2694                 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2695
2696                 if (addr_config == 1) {
2697                         /* host supports IDMAC in 64-bit address mode */
2698                         host->dma_64bit_address = 1;
2699                         dev_info(host->dev,
2700                                  "IDMAC supports 64-bit address mode.\n");
2701                         if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2702                                 dma_set_coherent_mask(host->dev,
2703                                                       DMA_BIT_MASK(64));
2704                 } else {
2705                         /* host supports IDMAC in 32-bit address mode */
2706                         host->dma_64bit_address = 0;
2707                         dev_info(host->dev,
2708                                  "IDMAC supports 32-bit address mode.\n");
2709                 }
2710
2711                 /* Alloc memory for sg translation */
2712                 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
2713                                                    &host->sg_dma, GFP_KERNEL);
2714                 if (!host->sg_cpu) {
2715                         dev_err(host->dev,
2716                                 "%s: could not alloc DMA memory\n",
2717                                 __func__);
2718                         goto no_dma;
2719                 }
2720
2721                 host->dma_ops = &dw_mci_idmac_ops;
2722                 dev_info(host->dev, "Using internal DMA controller.\n");
2723         } else {
2724                 /* TRANS_MODE_EDMAC: check dma bindings again */
2725                 if ((of_property_count_strings(np, "dma-names") < 0) ||
2726                     (!of_find_property(np, "dmas", NULL))) {
2727                         goto no_dma;
2728                 }
2729                 host->dma_ops = &dw_mci_edmac_ops;
2730                 dev_info(host->dev, "Using external DMA controller.\n");
2731         }
2732
2733         if (host->dma_ops->init && host->dma_ops->start &&
2734             host->dma_ops->stop && host->dma_ops->cleanup) {
2735                 if (host->dma_ops->init(host)) {
2736                         dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2737                                 __func__);
2738                         goto no_dma;
2739                 }
2740         } else {
2741                 dev_err(host->dev, "DMA initialization not found.\n");
2742                 goto no_dma;
2743         }
2744
2745         return;
2746
2747 no_dma:
2748         dev_info(host->dev, "Using PIO mode.\n");
2749         host->use_dma = TRANS_MODE_PIO;
2750 }
2751
2752 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
2753 {
2754         unsigned long timeout = jiffies + msecs_to_jiffies(500);
2755         u32 ctrl;
2756
2757         ctrl = mci_readl(host, CTRL);
2758         ctrl |= reset;
2759         mci_writel(host, CTRL, ctrl);
2760
2761         /* wait till resets clear */
2762         do {
2763                 ctrl = mci_readl(host, CTRL);
2764                 if (!(ctrl & reset))
2765                         return true;
2766         } while (time_before(jiffies, timeout));
2767
2768         dev_err(host->dev,
2769                 "Timeout resetting block (ctrl reset %#x)\n",
2770                 ctrl & reset);
2771
2772         return false;
2773 }
2774
2775 static bool dw_mci_reset(struct dw_mci *host)
2776 {
2777         u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2778         bool ret = false;
2779
2780         /*
2781          * Reseting generates a block interrupt, hence setting
2782          * the scatter-gather pointer to NULL.
2783          */
2784         if (host->sg) {
2785                 sg_miter_stop(&host->sg_miter);
2786                 host->sg = NULL;
2787         }
2788
2789         if (host->use_dma)
2790                 flags |= SDMMC_CTRL_DMA_RESET;
2791
2792         if (dw_mci_ctrl_reset(host, flags)) {
2793                 /*
2794                  * In all cases we clear the RAWINTS register to clear any
2795                  * interrupts.
2796                  */
2797                 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2798
2799                 /* if using dma we wait for dma_req to clear */
2800                 if (host->use_dma) {
2801                         unsigned long timeout = jiffies + msecs_to_jiffies(500);
2802                         u32 status;
2803
2804                         do {
2805                                 status = mci_readl(host, STATUS);
2806                                 if (!(status & SDMMC_STATUS_DMA_REQ))
2807                                         break;
2808                                 cpu_relax();
2809                         } while (time_before(jiffies, timeout));
2810
2811                         if (status & SDMMC_STATUS_DMA_REQ) {
2812                                 dev_err(host->dev,
2813                                         "%s: Timeout waiting for dma_req to clear during reset\n",
2814                                         __func__);
2815                                 goto ciu_out;
2816                         }
2817
2818                         /* when using DMA next we reset the fifo again */
2819                         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2820                                 goto ciu_out;
2821                 }
2822         } else {
2823                 /* if the controller reset bit did clear, then set clock regs */
2824                 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2825                         dev_err(host->dev,
2826                                 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
2827                                 __func__);
2828                         goto ciu_out;
2829                 }
2830         }
2831
2832         if (host->use_dma == TRANS_MODE_IDMAC)
2833                 /* It is also recommended that we reset and reprogram idmac */
2834                 dw_mci_idmac_reset(host);
2835
2836         ret = true;
2837
2838 ciu_out:
2839         /* After a CTRL reset we need to have CIU set clock registers  */
2840         mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2841
2842         return ret;
2843 }
2844
2845 static void dw_mci_cmd11_timer(unsigned long arg)
2846 {
2847         struct dw_mci *host = (struct dw_mci *)arg;
2848
2849         if (host->state != STATE_SENDING_CMD11) {
2850                 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2851                 return;
2852         }
2853
2854         host->cmd_status = SDMMC_INT_RTO;
2855         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2856         tasklet_schedule(&host->tasklet);
2857 }
2858
2859 static void dw_mci_dto_timer(unsigned long arg)
2860 {
2861         struct dw_mci *host = (struct dw_mci *)arg;
2862
2863         switch (host->state) {
2864         case STATE_SENDING_DATA:
2865         case STATE_DATA_BUSY:
2866                 /*
2867                  * If DTO interrupt does NOT come in sending data state,
2868                  * we should notify the driver to terminate current transfer
2869                  * and report a data timeout to the core.
2870                  */
2871                 host->data_status = SDMMC_INT_DRTO;
2872                 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2873                 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2874                 tasklet_schedule(&host->tasklet);
2875                 break;
2876         default:
2877                 break;
2878         }
2879 }
2880
2881 #ifdef CONFIG_OF
2882 static struct dw_mci_of_quirks {
2883         char *quirk;
2884         int id;
2885 } of_quirks[] = {
2886         {
2887                 .quirk  = "broken-cd",
2888                 .id     = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
2889         },
2890 };
2891
2892 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2893 {
2894         struct dw_mci_board *pdata;
2895         struct device *dev = host->dev;
2896         struct device_node *np = dev->of_node;
2897         const struct dw_mci_drv_data *drv_data = host->drv_data;
2898         int idx, ret;
2899         u32 clock_frequency;
2900
2901         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2902         if (!pdata)
2903                 return ERR_PTR(-ENOMEM);
2904
2905         /* find out number of slots supported */
2906         if (of_property_read_u32(dev->of_node, "num-slots",
2907                                 &pdata->num_slots)) {
2908                 dev_info(dev,
2909                          "num-slots property not found, assuming 1 slot is available\n");
2910                 pdata->num_slots = 1;
2911         }
2912
2913         /* get quirks */
2914         for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
2915                 if (of_get_property(np, of_quirks[idx].quirk, NULL))
2916                         pdata->quirks |= of_quirks[idx].id;
2917
2918         if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2919                 dev_info(dev,
2920                          "fifo-depth property not found, using value of FIFOTH register as default\n");
2921
2922         of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2923
2924         if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2925                 pdata->bus_hz = clock_frequency;
2926
2927         if (drv_data && drv_data->parse_dt) {
2928                 ret = drv_data->parse_dt(host);
2929                 if (ret)
2930                         return ERR_PTR(ret);
2931         }
2932
2933         if (of_find_property(np, "supports-highspeed", NULL)) {
2934                 dev_info(dev, "supports-highspeed property is deprecated.\n");
2935                 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2936         }
2937
2938         return pdata;
2939 }
2940
2941 #else /* CONFIG_OF */
2942 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2943 {
2944         return ERR_PTR(-EINVAL);
2945 }
2946 #endif /* CONFIG_OF */
2947
2948 static void dw_mci_enable_cd(struct dw_mci *host)
2949 {
2950         struct dw_mci_board *brd = host->pdata;
2951         unsigned long irqflags;
2952         u32 temp;
2953         int i;
2954
2955         /* No need for CD if broken card detection */
2956         if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
2957                 return;
2958
2959         /* No need for CD if all slots have a non-error GPIO */
2960         for (i = 0; i < host->num_slots; i++) {
2961                 struct dw_mci_slot *slot = host->slot[i];
2962
2963                 if (IS_ERR_VALUE(mmc_gpio_get_cd(slot->mmc)))
2964                         break;
2965         }
2966         if (i == host->num_slots)
2967                 return;
2968
2969         spin_lock_irqsave(&host->irq_lock, irqflags);
2970         temp = mci_readl(host, INTMASK);
2971         temp  |= SDMMC_INT_CD;
2972         mci_writel(host, INTMASK, temp);
2973         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2974 }
2975
2976 int dw_mci_probe(struct dw_mci *host)
2977 {
2978         const struct dw_mci_drv_data *drv_data = host->drv_data;
2979         int width, i, ret = 0;
2980         u32 fifo_size;
2981         int init_slots = 0;
2982
2983         if (!host->pdata) {
2984                 host->pdata = dw_mci_parse_dt(host);
2985                 if (IS_ERR(host->pdata)) {
2986                         dev_err(host->dev, "platform data not available\n");
2987                         return -EINVAL;
2988                 }
2989         }
2990
2991         if (host->pdata->num_slots < 1) {
2992                 dev_err(host->dev,
2993                         "Platform data must supply num_slots.\n");
2994                 return -ENODEV;
2995         }
2996
2997         host->biu_clk = devm_clk_get(host->dev, "biu");
2998         if (IS_ERR(host->biu_clk)) {
2999                 dev_dbg(host->dev, "biu clock not available\n");
3000         } else {
3001                 ret = clk_prepare_enable(host->biu_clk);
3002                 if (ret) {
3003                         dev_err(host->dev, "failed to enable biu clock\n");
3004                         return ret;
3005                 }
3006         }
3007
3008         host->ciu_clk = devm_clk_get(host->dev, "ciu");
3009         if (IS_ERR(host->ciu_clk)) {
3010                 dev_dbg(host->dev, "ciu clock not available\n");
3011                 host->bus_hz = host->pdata->bus_hz;
3012         } else {
3013                 ret = clk_prepare_enable(host->ciu_clk);
3014                 if (ret) {
3015                         dev_err(host->dev, "failed to enable ciu clock\n");
3016                         goto err_clk_biu;
3017                 }
3018
3019                 if (host->pdata->bus_hz) {
3020                         ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3021                         if (ret)
3022                                 dev_warn(host->dev,
3023                                          "Unable to set bus rate to %uHz\n",
3024                                          host->pdata->bus_hz);
3025                 }
3026                 host->bus_hz = clk_get_rate(host->ciu_clk);
3027         }
3028
3029         if (!host->bus_hz) {
3030                 dev_err(host->dev,
3031                         "Platform data must supply bus speed\n");
3032                 ret = -ENODEV;
3033                 goto err_clk_ciu;
3034         }
3035
3036         if (drv_data && drv_data->init) {
3037                 ret = drv_data->init(host);
3038                 if (ret) {
3039                         dev_err(host->dev,
3040                                 "implementation specific init failed\n");
3041                         goto err_clk_ciu;
3042                 }
3043         }
3044
3045         if (drv_data && drv_data->setup_clock) {
3046                 ret = drv_data->setup_clock(host);
3047                 if (ret) {
3048                         dev_err(host->dev,
3049                                 "implementation specific clock setup failed\n");
3050                         goto err_clk_ciu;
3051                 }
3052         }
3053
3054         setup_timer(&host->cmd11_timer,
3055                     dw_mci_cmd11_timer, (unsigned long)host);
3056
3057         host->quirks = host->pdata->quirks;
3058
3059         if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO)
3060                 setup_timer(&host->dto_timer,
3061                             dw_mci_dto_timer, (unsigned long)host);
3062
3063         spin_lock_init(&host->lock);
3064         spin_lock_init(&host->irq_lock);
3065         INIT_LIST_HEAD(&host->queue);
3066
3067         /*
3068          * Get the host data width - this assumes that HCON has been set with
3069          * the correct values.
3070          */
3071         i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3072         if (!i) {
3073                 host->push_data = dw_mci_push_data16;
3074                 host->pull_data = dw_mci_pull_data16;
3075                 width = 16;
3076                 host->data_shift = 1;
3077         } else if (i == 2) {
3078                 host->push_data = dw_mci_push_data64;
3079                 host->pull_data = dw_mci_pull_data64;
3080                 width = 64;
3081                 host->data_shift = 3;
3082         } else {
3083                 /* Check for a reserved value, and warn if it is */
3084                 WARN((i != 1),
3085                      "HCON reports a reserved host data width!\n"
3086                      "Defaulting to 32-bit access.\n");
3087                 host->push_data = dw_mci_push_data32;
3088                 host->pull_data = dw_mci_pull_data32;
3089                 width = 32;
3090                 host->data_shift = 2;
3091         }
3092
3093         /* Reset all blocks */
3094         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS))
3095                 return -ENODEV;
3096
3097         host->dma_ops = host->pdata->dma_ops;
3098         dw_mci_init_dma(host);
3099
3100         /* Clear the interrupts for the host controller */
3101         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3102         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3103
3104         /* Put in max timeout */
3105         mci_writel(host, TMOUT, 0xFFFFFFFF);
3106
3107         /*
3108          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
3109          *                          Tx Mark = fifo_size / 2 DMA Size = 8
3110          */
3111         if (!host->pdata->fifo_depth) {
3112                 /*
3113                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3114                  * have been overwritten by the bootloader, just like we're
3115                  * about to do, so if you know the value for your hardware, you
3116                  * should put it in the platform data.
3117                  */
3118                 fifo_size = mci_readl(host, FIFOTH);
3119                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3120         } else {
3121                 fifo_size = host->pdata->fifo_depth;
3122         }
3123         host->fifo_depth = fifo_size;
3124         host->fifoth_val =
3125                 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3126         mci_writel(host, FIFOTH, host->fifoth_val);
3127
3128         /* disable clock to CIU */
3129         mci_writel(host, CLKENA, 0);
3130         mci_writel(host, CLKSRC, 0);
3131
3132         /*
3133          * In 2.40a spec, Data offset is changed.
3134          * Need to check the version-id and set data-offset for DATA register.
3135          */
3136         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3137         dev_info(host->dev, "Version ID is %04x\n", host->verid);
3138
3139         if (host->verid < DW_MMC_240A)
3140                 host->fifo_reg = host->regs + DATA_OFFSET;
3141         else
3142                 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3143
3144         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3145         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3146                                host->irq_flags, "dw-mci", host);
3147         if (ret)
3148                 goto err_dmaunmap;
3149
3150         if (host->pdata->num_slots)
3151                 host->num_slots = host->pdata->num_slots;
3152         else
3153                 host->num_slots = SDMMC_GET_SLOT_NUM(mci_readl(host, HCON));
3154
3155         /*
3156          * Enable interrupts for command done, data over, data empty,
3157          * receive ready and error such as transmit, receive timeout, crc error
3158          */
3159         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3160         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3161                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3162                    DW_MCI_ERROR_FLAGS);
3163         /* Enable mci interrupt */
3164         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3165
3166         dev_info(host->dev,
3167                  "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3168                  host->irq, width, fifo_size);
3169
3170         /* We need at least one slot to succeed */
3171         for (i = 0; i < host->num_slots; i++) {
3172                 ret = dw_mci_init_slot(host, i);
3173                 if (ret)
3174                         dev_dbg(host->dev, "slot %d init failed\n", i);
3175                 else
3176                         init_slots++;
3177         }
3178
3179         if (init_slots) {
3180                 dev_info(host->dev, "%d slots initialized\n", init_slots);
3181         } else {
3182                 dev_dbg(host->dev,
3183                         "attempted to initialize %d slots, but failed on all\n",
3184                         host->num_slots);
3185                 goto err_dmaunmap;
3186         }
3187
3188         /* Now that slots are all setup, we can enable card detect */
3189         dw_mci_enable_cd(host);
3190
3191         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
3192                 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
3193
3194         return 0;
3195
3196 err_dmaunmap:
3197         if (host->use_dma && host->dma_ops->exit)
3198                 host->dma_ops->exit(host);
3199
3200 err_clk_ciu:
3201         if (!IS_ERR(host->ciu_clk))
3202                 clk_disable_unprepare(host->ciu_clk);
3203
3204 err_clk_biu:
3205         if (!IS_ERR(host->biu_clk))
3206                 clk_disable_unprepare(host->biu_clk);
3207
3208         return ret;
3209 }
3210 EXPORT_SYMBOL(dw_mci_probe);
3211
3212 void dw_mci_remove(struct dw_mci *host)
3213 {
3214         int i;
3215
3216         for (i = 0; i < host->num_slots; i++) {
3217                 dev_dbg(host->dev, "remove slot %d\n", i);
3218                 if (host->slot[i])
3219                         dw_mci_cleanup_slot(host->slot[i], i);
3220         }
3221
3222         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3223         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3224
3225         /* disable clock to CIU */
3226         mci_writel(host, CLKENA, 0);
3227         mci_writel(host, CLKSRC, 0);
3228
3229         if (host->use_dma && host->dma_ops->exit)
3230                 host->dma_ops->exit(host);
3231
3232         if (!IS_ERR(host->ciu_clk))
3233                 clk_disable_unprepare(host->ciu_clk);
3234
3235         if (!IS_ERR(host->biu_clk))
3236                 clk_disable_unprepare(host->biu_clk);
3237 }
3238 EXPORT_SYMBOL(dw_mci_remove);
3239
3240
3241
3242 #ifdef CONFIG_PM_SLEEP
3243 /*
3244  * TODO: we should probably disable the clock to the card in the suspend path.
3245  */
3246 int dw_mci_suspend(struct dw_mci *host)
3247 {
3248         if (host->use_dma && host->dma_ops->exit)
3249                 host->dma_ops->exit(host);
3250
3251         return 0;
3252 }
3253 EXPORT_SYMBOL(dw_mci_suspend);
3254
3255 int dw_mci_resume(struct dw_mci *host)
3256 {
3257         int i, ret;
3258
3259         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3260                 ret = -ENODEV;
3261                 return ret;
3262         }
3263
3264         if (host->use_dma && host->dma_ops->init)
3265                 host->dma_ops->init(host);
3266
3267         /*
3268          * Restore the initial value at FIFOTH register
3269          * And Invalidate the prev_blksz with zero
3270          */
3271         mci_writel(host, FIFOTH, host->fifoth_val);
3272         host->prev_blksz = 0;
3273
3274         /* Put in max timeout */
3275         mci_writel(host, TMOUT, 0xFFFFFFFF);
3276
3277         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3278         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3279                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3280                    DW_MCI_ERROR_FLAGS);
3281         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3282
3283         for (i = 0; i < host->num_slots; i++) {
3284                 struct dw_mci_slot *slot = host->slot[i];
3285
3286                 if (!slot)
3287                         continue;
3288                 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
3289                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3290                         dw_mci_setup_bus(slot, true);
3291                 }
3292         }
3293
3294         /* Now that slots are all setup, we can enable card detect */
3295         dw_mci_enable_cd(host);
3296
3297         return 0;
3298 }
3299 EXPORT_SYMBOL(dw_mci_resume);
3300 #endif /* CONFIG_PM_SLEEP */
3301
3302 static int __init dw_mci_init(void)
3303 {
3304         pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3305         return 0;
3306 }
3307
3308 static void __exit dw_mci_exit(void)
3309 {
3310 }
3311
3312 module_init(dw_mci_init);
3313 module_exit(dw_mci_exit);
3314
3315 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3316 MODULE_AUTHOR("NXP Semiconductor VietNam");
3317 MODULE_AUTHOR("Imagination Technologies Ltd");
3318 MODULE_LICENSE("GPL v2");