drivers/mfd/lpc_ich.c

   1 /*
   2  *  lpc_ich.c - LPC interface for Intel ICH
   3  *
   4  *  LPC bridge function of the Intel ICH contains many other
   5  *  functional units, such as Interrupt controllers, Timers,
   6  *  Power Management, System Management, GPIO, RTC, and LPC
   7  *  Configuration Registers.
   8  *
   9  *  This driver is derived from lpc_sch.
  10
  11  *  Copyright (c) 2011 Extreme Engineering Solution, Inc.
  12  *  Author: Aaron Sierra <asierra@xes-inc.com>
  13  *
  14  *  This program is free software; you can redistribute it and/or modify
  15  *  it under the terms of the GNU General Public License 2 as published
  16  *  by the Free Software Foundation.
  17  *
  18  *  This program is distributed in the hope that it will be useful,
  19  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *  GNU General Public License for more details.
  22  *
  23  *  You should have received a copy of the GNU General Public License
  24  *  along with this program; see the file COPYING.  If not, write to
  25  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  26  *
  27  *  This driver supports the following I/O Controller hubs:
  28  *      (See the intel documentation on http://developer.intel.com.)
  29  *      document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
  30  *      document number 290687-002, 298242-027: 82801BA (ICH2)
  31  *      document number 290733-003, 290739-013: 82801CA (ICH3-S)
  32  *      document number 290716-001, 290718-007: 82801CAM (ICH3-M)
  33  *      document number 290744-001, 290745-025: 82801DB (ICH4)
  34  *      document number 252337-001, 252663-008: 82801DBM (ICH4-M)
  35  *      document number 273599-001, 273645-002: 82801E (C-ICH)
  36  *      document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
  37  *      document number 300641-004, 300884-013: 6300ESB
  38  *      document number 301473-002, 301474-026: 82801F (ICH6)
  39  *      document number 313082-001, 313075-006: 631xESB, 632xESB
  40  *      document number 307013-003, 307014-024: 82801G (ICH7)
  41  *      document number 322896-001, 322897-001: NM10
  42  *      document number 313056-003, 313057-017: 82801H (ICH8)
  43  *      document number 316972-004, 316973-012: 82801I (ICH9)
  44  *      document number 319973-002, 319974-002: 82801J (ICH10)
  45  *      document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
  46  *      document number 320066-003, 320257-008: EP80597 (IICH)
  47  *      document number 324645-001, 324646-001: Cougar Point (CPT)
  48  *      document number TBD : Patsburg (PBG)
  49  *      document number TBD : DH89xxCC
  50  *      document number TBD : Panther Point
  51  *      document number TBD : Lynx Point
  52  *      document number TBD : Lynx Point-LP
  53  *      document number TBD : Wellsburg
  54  *      document number TBD : Avoton SoC
  55  *      document number TBD : Coleto Creek
  56  */
  57
  58 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  59
  60 #include <linux/init.h>
  61 #include <linux/kernel.h>
  62 #include <linux/module.h>
  63 #include <linux/errno.h>
  64 #include <linux/acpi.h>
  65 #include <linux/pci.h>
  66 #include <linux/mfd/core.h>
  67 #include <linux/mfd/lpc_ich.h>
  68
  69 #define ACPIBASE                0x40
  70 #define ACPIBASE_GPE_OFF        0x28
  71 #define ACPIBASE_GPE_END        0x2f
  72 #define ACPIBASE_SMI_OFF        0x30
  73 #define ACPIBASE_SMI_END        0x33
  74 #define ACPIBASE_TCO_OFF        0x60
  75 #define ACPIBASE_TCO_END        0x7f
  76 #define ACPICTRL                0x44
  77
  78 #define ACPIBASE_GCS_OFF        0x3410
  79 #define ACPIBASE_GCS_END        0x3414
  80
  81 #define GPIOBASE_ICH0           0x58
  82 #define GPIOCTRL_ICH0           0x5C
  83 #define GPIOBASE_ICH6           0x48
  84 #define GPIOCTRL_ICH6           0x4C
  85
  86 #define RCBABASE                0xf0
  87
  88 #define wdt_io_res(i) wdt_res(0, i)
  89 #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i)
  90 #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)])
  91
  92 struct lpc_ich_cfg {
  93         int base;
  94         int ctrl;
  95         int save;
  96 };
  97
  98 struct lpc_ich_priv {
  99         int chipset;
 100         struct lpc_ich_cfg acpi;
 101         struct lpc_ich_cfg gpio;
 102 };
 103
 104 static struct resource wdt_ich_res[] = {
 105         /* ACPI - TCO */
 106         {
 107                 .flags = IORESOURCE_IO,
 108         },
 109         /* ACPI - SMI */
 110         {
 111                 .flags = IORESOURCE_IO,
 112         },
 113         /* GCS */
 114         {
 115                 .flags = IORESOURCE_MEM,
 116         },
 117 };
 118
 119 static struct resource gpio_ich_res[] = {
 120         /* GPIO */
 121         {
 122                 .flags = IORESOURCE_IO,
 123         },
 124         /* ACPI - GPE0 */
 125         {
 126                 .flags = IORESOURCE_IO,
 127         },
 128 };
 129
 130 enum lpc_cells {
 131         LPC_WDT = 0,
 132         LPC_GPIO,
 133 };
 134
 135 static struct mfd_cell lpc_ich_cells[] = {
 136         [LPC_WDT] = {
 137                 .name = "iTCO_wdt",
 138                 .num_resources = ARRAY_SIZE(wdt_ich_res),
 139                 .resources = wdt_ich_res,
 140                 .ignore_resource_conflicts = true,
 141         },
 142         [LPC_GPIO] = {
 143                 .name = "gpio_ich",
 144                 .num_resources = ARRAY_SIZE(gpio_ich_res),
 145                 .resources = gpio_ich_res,
 146                 .ignore_resource_conflicts = true,
 147         },
 148 };
 149
 150 /* chipset related info */
 151 enum lpc_chipsets {
 152         LPC_ICH = 0,    /* ICH */
 153         LPC_ICH0,       /* ICH0 */
 154         LPC_ICH2,       /* ICH2 */
 155         LPC_ICH2M,      /* ICH2-M */
 156         LPC_ICH3,       /* ICH3-S */
 157         LPC_ICH3M,      /* ICH3-M */
 158         LPC_ICH4,       /* ICH4 */
 159         LPC_ICH4M,      /* ICH4-M */
 160         LPC_CICH,       /* C-ICH */
 161         LPC_ICH5,       /* ICH5 & ICH5R */
 162         LPC_6300ESB,    /* 6300ESB */
 163         LPC_ICH6,       /* ICH6 & ICH6R */
 164         LPC_ICH6M,      /* ICH6-M */
 165         LPC_ICH6W,      /* ICH6W & ICH6RW */
 166         LPC_631XESB,    /* 631xESB/632xESB */
 167         LPC_ICH7,       /* ICH7 & ICH7R */
 168         LPC_ICH7DH,     /* ICH7DH */
 169         LPC_ICH7M,      /* ICH7-M & ICH7-U */
 170         LPC_ICH7MDH,    /* ICH7-M DH */
 171         LPC_NM10,       /* NM10 */
 172         LPC_ICH8,       /* ICH8 & ICH8R */
 173         LPC_ICH8DH,     /* ICH8DH */
 174         LPC_ICH8DO,     /* ICH8DO */
 175         LPC_ICH8M,      /* ICH8M */
 176         LPC_ICH8ME,     /* ICH8M-E */
 177         LPC_ICH9,       /* ICH9 */
 178         LPC_ICH9R,      /* ICH9R */
 179         LPC_ICH9DH,     /* ICH9DH */
 180         LPC_ICH9DO,     /* ICH9DO */
 181         LPC_ICH9M,      /* ICH9M */
 182         LPC_ICH9ME,     /* ICH9M-E */
 183         LPC_ICH10,      /* ICH10 */
 184         LPC_ICH10R,     /* ICH10R */
 185         LPC_ICH10D,     /* ICH10D */
 186         LPC_ICH10DO,    /* ICH10DO */
 187         LPC_PCH,        /* PCH Desktop Full Featured */
 188         LPC_PCHM,       /* PCH Mobile Full Featured */
 189         LPC_P55,        /* P55 */
 190         LPC_PM55,       /* PM55 */
 191         LPC_H55,        /* H55 */
 192         LPC_QM57,       /* QM57 */
 193         LPC_H57,        /* H57 */
 194         LPC_HM55,       /* HM55 */
 195         LPC_Q57,        /* Q57 */
 196         LPC_HM57,       /* HM57 */
 197         LPC_PCHMSFF,    /* PCH Mobile SFF Full Featured */
 198         LPC_QS57,       /* QS57 */
 199         LPC_3400,       /* 3400 */
 200         LPC_3420,       /* 3420 */
 201         LPC_3450,       /* 3450 */
 202         LPC_EP80579,    /* EP80579 */
 203         LPC_CPT,        /* Cougar Point */
 204         LPC_CPTD,       /* Cougar Point Desktop */
 205         LPC_CPTM,       /* Cougar Point Mobile */
 206         LPC_PBG,        /* Patsburg */
 207         LPC_DH89XXCC,   /* DH89xxCC */
 208         LPC_PPT,        /* Panther Point */
 209         LPC_LPT,        /* Lynx Point */
 210         LPC_LPT_LP,     /* Lynx Point-LP */
 211         LPC_WBG,        /* Wellsburg */
 212         LPC_AVN,        /* Avoton SoC */
 213         LPC_COLETO,     /* Coleto Creek */
 214 };
 215
 216 struct lpc_ich_info lpc_chipset_info[] = {
 217         [LPC_ICH] = {
 218                 .name = "ICH",
 219                 .iTCO_version = 1,
 220         },
 221         [LPC_ICH0] = {
 222                 .name = "ICH0",
 223                 .iTCO_version = 1,
 224         },
 225         [LPC_ICH2] = {
 226                 .name = "ICH2",
 227                 .iTCO_version = 1,
 228         },
 229         [LPC_ICH2M] = {
 230                 .name = "ICH2-M",
 231                 .iTCO_version = 1,
 232         },
 233         [LPC_ICH3] = {
 234                 .name = "ICH3-S",
 235                 .iTCO_version = 1,
 236         },
 237         [LPC_ICH3M] = {
 238                 .name = "ICH3-M",
 239                 .iTCO_version = 1,
 240         },
 241         [LPC_ICH4] = {
 242                 .name = "ICH4",
 243                 .iTCO_version = 1,
 244         },
 245         [LPC_ICH4M] = {
 246                 .name = "ICH4-M",
 247                 .iTCO_version = 1,
 248         },
 249         [LPC_CICH] = {
 250                 .name = "C-ICH",
 251                 .iTCO_version = 1,
 252         },
 253         [LPC_ICH5] = {
 254                 .name = "ICH5 or ICH5R",
 255                 .iTCO_version = 1,
 256         },
 257         [LPC_6300ESB] = {
 258                 .name = "6300ESB",
 259                 .iTCO_version = 1,
 260         },
 261         [LPC_ICH6] = {
 262                 .name = "ICH6 or ICH6R",
 263                 .iTCO_version = 2,
 264                 .gpio_version = ICH_V6_GPIO,
 265         },
 266         [LPC_ICH6M] = {
 267                 .name = "ICH6-M",
 268                 .iTCO_version = 2,
 269                 .gpio_version = ICH_V6_GPIO,
 270         },
 271         [LPC_ICH6W] = {
 272                 .name = "ICH6W or ICH6RW",
 273                 .iTCO_version = 2,
 274                 .gpio_version = ICH_V6_GPIO,
 275         },
 276         [LPC_631XESB] = {
 277                 .name = "631xESB/632xESB",
 278                 .iTCO_version = 2,
 279                 .gpio_version = ICH_V6_GPIO,
 280         },
 281         [LPC_ICH7] = {
 282                 .name = "ICH7 or ICH7R",
 283                 .iTCO_version = 2,
 284                 .gpio_version = ICH_V7_GPIO,
 285         },
 286         [LPC_ICH7DH] = {
 287                 .name = "ICH7DH",
 288                 .iTCO_version = 2,
 289                 .gpio_version = ICH_V7_GPIO,
 290         },
 291         [LPC_ICH7M] = {
 292                 .name = "ICH7-M or ICH7-U",
 293                 .iTCO_version = 2,
 294                 .gpio_version = ICH_V7_GPIO,
 295         },
 296         [LPC_ICH7MDH] = {
 297                 .name = "ICH7-M DH",
 298                 .iTCO_version = 2,
 299                 .gpio_version = ICH_V7_GPIO,
 300         },
 301         [LPC_NM10] = {
 302                 .name = "NM10",
 303                 .iTCO_version = 2,
 304         },
 305         [LPC_ICH8] = {
 306                 .name = "ICH8 or ICH8R",
 307                 .iTCO_version = 2,
 308                 .gpio_version = ICH_V7_GPIO,
 309         },
 310         [LPC_ICH8DH] = {
 311                 .name = "ICH8DH",
 312                 .iTCO_version = 2,
 313                 .gpio_version = ICH_V7_GPIO,
 314         },
 315         [LPC_ICH8DO] = {
 316                 .name = "ICH8DO",
 317                 .iTCO_version = 2,
 318                 .gpio_version = ICH_V7_GPIO,
 319         },
 320         [LPC_ICH8M] = {
 321                 .name = "ICH8M",
 322                 .iTCO_version = 2,
 323                 .gpio_version = ICH_V7_GPIO,
 324         },
 325         [LPC_ICH8ME] = {
 326                 .name = "ICH8M-E",
 327                 .iTCO_version = 2,
 328                 .gpio_version = ICH_V7_GPIO,
 329         },
 330         [LPC_ICH9] = {
 331                 .name = "ICH9",
 332                 .iTCO_version = 2,
 333                 .gpio_version = ICH_V9_GPIO,
 334         },
 335         [LPC_ICH9R] = {
 336                 .name = "ICH9R",
 337                 .iTCO_version = 2,
 338                 .gpio_version = ICH_V9_GPIO,
 339         },
 340         [LPC_ICH9DH] = {
 341                 .name = "ICH9DH",
 342                 .iTCO_version = 2,
 343                 .gpio_version = ICH_V9_GPIO,
 344         },
 345         [LPC_ICH9DO] = {
 346                 .name = "ICH9DO",
 347                 .iTCO_version = 2,
 348                 .gpio_version = ICH_V9_GPIO,
 349         },
 350         [LPC_ICH9M] = {
 351                 .name = "ICH9M",
 352                 .iTCO_version = 2,
 353                 .gpio_version = ICH_V9_GPIO,
 354         },
 355         [LPC_ICH9ME] = {
 356                 .name = "ICH9M-E",
 357                 .iTCO_version = 2,
 358                 .gpio_version = ICH_V9_GPIO,
 359         },
 360         [LPC_ICH10] = {
 361                 .name = "ICH10",
 362                 .iTCO_version = 2,
 363                 .gpio_version = ICH_V10CONS_GPIO,
 364         },
 365         [LPC_ICH10R] = {
 366                 .name = "ICH10R",
 367                 .iTCO_version = 2,
 368                 .gpio_version = ICH_V10CONS_GPIO,
 369         },
 370         [LPC_ICH10D] = {
 371                 .name = "ICH10D",
 372                 .iTCO_version = 2,
 373                 .gpio_version = ICH_V10CORP_GPIO,
 374         },
 375         [LPC_ICH10DO] = {
 376                 .name = "ICH10DO",
 377                 .iTCO_version = 2,
 378                 .gpio_version = ICH_V10CORP_GPIO,
 379         },
 380         [LPC_PCH] = {
 381                 .name = "PCH Desktop Full Featured",
 382                 .iTCO_version = 2,
 383                 .gpio_version = ICH_V5_GPIO,
 384         },
 385         [LPC_PCHM] = {
 386                 .name = "PCH Mobile Full Featured",
 387                 .iTCO_version = 2,
 388                 .gpio_version = ICH_V5_GPIO,
 389         },
 390         [LPC_P55] = {
 391                 .name = "P55",
 392                 .iTCO_version = 2,
 393                 .gpio_version = ICH_V5_GPIO,
 394         },
 395         [LPC_PM55] = {
 396                 .name = "PM55",
 397                 .iTCO_version = 2,
 398                 .gpio_version = ICH_V5_GPIO,
 399         },
 400         [LPC_H55] = {
 401                 .name = "H55",
 402                 .iTCO_version = 2,
 403                 .gpio_version = ICH_V5_GPIO,
 404         },
 405         [LPC_QM57] = {
 406                 .name = "QM57",
 407                 .iTCO_version = 2,
 408                 .gpio_version = ICH_V5_GPIO,
 409         },
 410         [LPC_H57] = {
 411                 .name = "H57",
 412                 .iTCO_version = 2,
 413                 .gpio_version = ICH_V5_GPIO,
 414         },
 415         [LPC_HM55] = {
 416                 .name = "HM55",
 417                 .iTCO_version = 2,
 418                 .gpio_version = ICH_V5_GPIO,
 419         },
 420         [LPC_Q57] = {
 421                 .name = "Q57",
 422                 .iTCO_version = 2,
 423                 .gpio_version = ICH_V5_GPIO,
 424         },
 425         [LPC_HM57] = {
 426                 .name = "HM57",
 427                 .iTCO_version = 2,
 428                 .gpio_version = ICH_V5_GPIO,
 429         },
 430         [LPC_PCHMSFF] = {
 431                 .name = "PCH Mobile SFF Full Featured",
 432                 .iTCO_version = 2,
 433                 .gpio_version = ICH_V5_GPIO,
 434         },
 435         [LPC_QS57] = {
 436                 .name = "QS57",
 437                 .iTCO_version = 2,
 438                 .gpio_version = ICH_V5_GPIO,
 439         },
 440         [LPC_3400] = {
 441                 .name = "3400",
 442                 .iTCO_version = 2,
 443                 .gpio_version = ICH_V5_GPIO,
 444         },
 445         [LPC_3420] = {
 446                 .name = "3420",
 447                 .iTCO_version = 2,
 448                 .gpio_version = ICH_V5_GPIO,
 449         },
 450         [LPC_3450] = {
 451                 .name = "3450",
 452                 .iTCO_version = 2,
 453                 .gpio_version = ICH_V5_GPIO,
 454         },
 455         [LPC_EP80579] = {
 456                 .name = "EP80579",
 457                 .iTCO_version = 2,
 458         },
 459         [LPC_CPT] = {
 460                 .name = "Cougar Point",
 461                 .iTCO_version = 2,
 462                 .gpio_version = ICH_V5_GPIO,
 463         },
 464         [LPC_CPTD] = {
 465                 .name = "Cougar Point Desktop",
 466                 .iTCO_version = 2,
 467                 .gpio_version = ICH_V5_GPIO,
 468         },
 469         [LPC_CPTM] = {
 470                 .name = "Cougar Point Mobile",
 471                 .iTCO_version = 2,
 472                 .gpio_version = ICH_V5_GPIO,
 473         },
 474         [LPC_PBG] = {
 475                 .name = "Patsburg",
 476                 .iTCO_version = 2,
 477         },
 478         [LPC_DH89XXCC] = {
 479                 .name = "DH89xxCC",
 480                 .iTCO_version = 2,
 481         },
 482         [LPC_PPT] = {
 483                 .name = "Panther Point",
 484                 .iTCO_version = 2,
 485         },
 486         [LPC_LPT] = {
 487                 .name = "Lynx Point",
 488                 .iTCO_version = 2,
 489         },
 490         [LPC_LPT_LP] = {
 491                 .name = "Lynx Point_LP",
 492                 .iTCO_version = 2,
 493         },
 494         [LPC_WBG] = {
 495                 .name = "Wellsburg",
 496                 .iTCO_version = 2,
 497         },
 498         [LPC_AVN] = {
 499                 .name = "Avoton SoC",
 500                 .iTCO_version = 1,
 501         },
 502         [LPC_COLETO] = {
 503                 .name = "Coleto Creek",
 504                 .iTCO_version = 2,
 505         },
 506 };
 507
 508 /*
 509  * This data only exists for exporting the supported PCI ids
 510  * via MODULE_DEVICE_TABLE.  We do not actually register a
 511  * pci_driver, because the I/O Controller Hub has also other
 512  * functions that probably will be registered by other drivers.
 513  */
 514 static DEFINE_PCI_DEVICE_TABLE(lpc_ich_ids) = {
 515         { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH},
 516         { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0},
 517         { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2},
 518         { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M},
 519         { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3},
 520         { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M},
 521         { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4},
 522         { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M},
 523         { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH},
 524         { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5},
 525         { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB},
 526         { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6},
 527         { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M},
 528         { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W},
 529         { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB},
 530         { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB},
 531         { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB},
 532         { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB},
 533         { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB},
 534         { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB},
 535         { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB},
 536         { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB},
 537         { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB},
 538         { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB},
 539         { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB},
 540         { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB},
 541         { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB},
 542         { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB},
 543         { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB},
 544         { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB},
 545         { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7},
 546         { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH},
 547         { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M},
 548         { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH},
 549         { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10},
 550         { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8},
 551         { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH},
 552         { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO},
 553         { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M},
 554         { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME},
 555         { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9},
 556         { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R},
 557         { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH},
 558         { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO},
 559         { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M},
 560         { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME},
 561         { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10},
 562         { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R},
 563         { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D},
 564         { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO},
 565         { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH},
 566         { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM},
 567         { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55},
 568         { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55},
 569         { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55},
 570         { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57},
 571         { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57},
 572         { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55},
 573         { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57},
 574         { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57},
 575         { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF},
 576         { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57},
 577         { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400},
 578         { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
 579         { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
 580         { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
 581         { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT},
 582         { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD},
 583         { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM},
 584         { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT},
 585         { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT},
 586         { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT},
 587         { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT},
 588         { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT},
 589         { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT},
 590         { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT},
 591         { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT},
 592         { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT},
 593         { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT},
 594         { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT},
 595         { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT},
 596         { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT},
 597         { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT},
 598         { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT},
 599         { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT},
 600         { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT},
 601         { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT},
 602         { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT},
 603         { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT},
 604         { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT},
 605         { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT},
 606         { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT},
 607         { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT},
 608         { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT},
 609         { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT},
 610         { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT},
 611         { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT},
 612         { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG},
 613         { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG},
 614         { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC},
 615         { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT},
 616         { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT},
 617         { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT},
 618         { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT},
 619         { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT},
 620         { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT},
 621         { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT},
 622         { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT},
 623         { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT},
 624         { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT},
 625         { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT},
 626         { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT},
 627         { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT},
 628         { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT},
 629         { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT},
 630         { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT},
 631         { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT},
 632         { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT},
 633         { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT},
 634         { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT},
 635         { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT},
 636         { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT},
 637         { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT},
 638         { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT},
 639         { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT},
 640         { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT},
 641         { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT},
 642         { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT},
 643         { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT},
 644         { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT},
 645         { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT},
 646         { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT},
 647         { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
 648         { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
 649         { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
 650         { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT},
 651         { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT},
 652         { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT},
 653         { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT},
 654         { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT},
 655         { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT},
 656         { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT},
 657         { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT},
 658         { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT},
 659         { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT},
 660         { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT},
 661         { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT},
 662         { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT},
 663         { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT},
 664         { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT},
 665         { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT},
 666         { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT},
 667         { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT},
 668         { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT},
 669         { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT},
 670         { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT},
 671         { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT},
 672         { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT},
 673         { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT},
 674         { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT},
 675         { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT},
 676         { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT},
 677         { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT},
 678         { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT},
 679         { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP},
 680         { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP},
 681         { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP},
 682         { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP},
 683         { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP},
 684         { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP},
 685         { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP},
 686         { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP},
 687         { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG},
 688         { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG},
 689         { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG},
 690         { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG},
 691         { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG},
 692         { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG},
 693         { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG},
 694         { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG},
 695         { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG},
 696         { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG},
 697         { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG},
 698         { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG},
 699         { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG},
 700         { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG},
 701         { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG},
 702         { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG},
 703         { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG},
 704         { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG},
 705         { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG},
 706         { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG},
 707         { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG},
 708         { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG},
 709         { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG},
 710         { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG},
 711         { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG},
 712         { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG},
 713         { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG},
 714         { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG},
 715         { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG},
 716         { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG},
 717         { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG},
 718         { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG},
 719         { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN},
 720         { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN},
 721         { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN},
 722         { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN},
 723         { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO},
 724         { 0, },                 /* End of list */
 725 };
 726 MODULE_DEVICE_TABLE(pci, lpc_ich_ids);
 727
 728 static void lpc_ich_restore_config_space(struct pci_dev *dev)
 729 {
 730         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
 731
 732         if (priv->acpi.save >= 0) {
 733                 pci_write_config_byte(dev, priv->acpi.ctrl, priv->acpi.save);
 734                 priv->acpi.save = -1;
 735         }
 736
 737         if (priv->gpio.save >= 0) {
 738                 pci_write_config_byte(dev, priv->gpio.ctrl, priv->gpio.save);
 739                 priv->gpio.save = -1;
 740         }
 741 }
 742
 743 static void lpc_ich_enable_acpi_space(struct pci_dev *dev)
 744 {
 745         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
 746         u8 reg_save;
 747
 748         pci_read_config_byte(dev, priv->acpi.ctrl, &reg_save);
 749         pci_write_config_byte(dev, priv->acpi.ctrl, reg_save | 0x10);
 750         priv->acpi.save = reg_save;
 751 }
 752
 753 static void lpc_ich_enable_gpio_space(struct pci_dev *dev)
 754 {
 755         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
 756         u8 reg_save;
 757
 758         pci_read_config_byte(dev, priv->gpio.ctrl, &reg_save);
 759         pci_write_config_byte(dev, priv->gpio.ctrl, reg_save | 0x10);
 760         priv->gpio.save = reg_save;
 761 }
 762
 763 static void lpc_ich_finalize_cell(struct pci_dev *dev, struct mfd_cell *cell)
 764 {
 765         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
 766
 767         cell->platform_data = &lpc_chipset_info[priv->chipset];
 768         cell->pdata_size = sizeof(struct lpc_ich_info);
 769 }
 770
 771 /*
 772  * We don't check for resource conflict globally. There are 2 or 3 independent
 773  * GPIO groups and it's enough to have access to one of these to instantiate
 774  * the device.
 775  */
 776 static int lpc_ich_check_conflict_gpio(struct resource *res)
 777 {
 778         int ret;
 779         u8 use_gpio = 0;
 780
 781         if (resource_size(res) >= 0x50 &&
 782             !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3"))
 783                 use_gpio |= 1 << 2;
 784
 785         if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2"))
 786                 use_gpio |= 1 << 1;
 787
 788         ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1");
 789         if (!ret)
 790                 use_gpio |= 1 << 0;
 791
 792         return use_gpio ? use_gpio : ret;
 793 }
 794
 795 static int lpc_ich_init_gpio(struct pci_dev *dev)
 796 {
 797         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
 798         u32 base_addr_cfg;
 799         u32 base_addr;
 800         int ret;
 801         bool acpi_conflict = false;
 802         struct resource *res;
 803
 804         /* Setup power management base register */
 805         pci_read_config_dword(dev, priv->acpi.base, &base_addr_cfg);
 806         base_addr = base_addr_cfg & 0x0000ff80;
 807         if (!base_addr) {
 808                 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
 809                 lpc_ich_cells[LPC_GPIO].num_resources--;
 810                 goto gpe0_done;
 811         }
 812
 813         res = &gpio_ich_res[ICH_RES_GPE0];
 814         res->start = base_addr + ACPIBASE_GPE_OFF;
 815         res->end = base_addr + ACPIBASE_GPE_END;
 816         ret = acpi_check_resource_conflict(res);
 817         if (ret) {
 818                 /*
 819                  * This isn't fatal for the GPIO, but we have to make sure that
 820                  * the platform_device subsystem doesn't see this resource
 821                  * or it will register an invalid region.
 822                  */
 823                 lpc_ich_cells[LPC_GPIO].num_resources--;
 824                 acpi_conflict = true;
 825         } else {
 826                 lpc_ich_enable_acpi_space(dev);
 827         }
 828
 829 gpe0_done:
 830         /* Setup GPIO base register */
 831         pci_read_config_dword(dev, priv->gpio.base, &base_addr_cfg);
 832         base_addr = base_addr_cfg & 0x0000ff80;
 833         if (!base_addr) {
 834                 dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n");
 835                 ret = -ENODEV;
 836                 goto gpio_done;
 837         }
 838
 839         /* Older devices provide fewer GPIO and have a smaller resource size. */
 840         res = &gpio_ich_res[ICH_RES_GPIO];
 841         res->start = base_addr;
 842         switch (lpc_chipset_info[priv->chipset].gpio_version) {
 843         case ICH_V5_GPIO:
 844         case ICH_V10CORP_GPIO:
 845                 res->end = res->start + 128 - 1;
 846                 break;
 847         default:
 848                 res->end = res->start + 64 - 1;
 849                 break;
 850         }
 851
 852         ret = lpc_ich_check_conflict_gpio(res);
 853         if (ret < 0) {
 854                 /* this isn't necessarily fatal for the GPIO */
 855                 acpi_conflict = true;
 856                 goto gpio_done;
 857         }
 858         lpc_chipset_info[priv->chipset].use_gpio = ret;
 859         lpc_ich_enable_gpio_space(dev);
 860
 861         lpc_ich_finalize_cell(dev, &lpc_ich_cells[LPC_GPIO]);
 862         ret = mfd_add_devices(&dev->dev, -1, &lpc_ich_cells[LPC_GPIO],
 863                               1, NULL, 0, NULL);
 864
 865 gpio_done:
 866         if (acpi_conflict)
 867                 pr_warn("Resource conflict(s) found affecting %s\n",
 868                                 lpc_ich_cells[LPC_GPIO].name);
 869         return ret;
 870 }
 871
 872 static int lpc_ich_init_wdt(struct pci_dev *dev)
 873 {
 874         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
 875         u32 base_addr_cfg;
 876         u32 base_addr;
 877         int ret;
 878         struct resource *res;
 879
 880         /* Setup power management base register */
 881         pci_read_config_dword(dev, priv->acpi.base, &base_addr_cfg);
 882         base_addr = base_addr_cfg & 0x0000ff80;
 883         if (!base_addr) {
 884                 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
 885                 ret = -ENODEV;
 886                 goto wdt_done;
 887         }
 888
 889         res = wdt_io_res(ICH_RES_IO_TCO);
 890         res->start = base_addr + ACPIBASE_TCO_OFF;
 891         res->end = base_addr + ACPIBASE_TCO_END;
 892
 893         res = wdt_io_res(ICH_RES_IO_SMI);
 894         res->start = base_addr + ACPIBASE_SMI_OFF;
 895         res->end = base_addr + ACPIBASE_SMI_END;
 896
 897         lpc_ich_enable_acpi_space(dev);
 898
 899         /*
 900          * Get the Memory-Mapped GCS register. To get access to it
 901          * we have to read RCBA from PCI Config space 0xf0 and use
 902          * it as base. GCS = RCBA + ICH6_GCS(0x3410).
 903          */
 904         if (lpc_chipset_info[priv->chipset].iTCO_version == 1) {
 905                 /* Don't register iomem for TCO ver 1 */
 906                 lpc_ich_cells[LPC_WDT].num_resources--;
 907         } else {
 908                 pci_read_config_dword(dev, RCBABASE, &base_addr_cfg);
 909                 base_addr = base_addr_cfg & 0xffffc000;
 910                 if (!(base_addr_cfg & 1)) {
 911                         dev_notice(&dev->dev, "RCBA is disabled by "
 912                                         "hardware/BIOS, device disabled\n");
 913                         ret = -ENODEV;
 914                         goto wdt_done;
 915                 }
 916                 res = wdt_mem_res(ICH_RES_MEM_GCS);
 917                 res->start = base_addr + ACPIBASE_GCS_OFF;
 918                 res->end = base_addr + ACPIBASE_GCS_END;
 919         }
 920
 921         lpc_ich_finalize_cell(dev, &lpc_ich_cells[LPC_WDT]);
 922         ret = mfd_add_devices(&dev->dev, -1, &lpc_ich_cells[LPC_WDT],
 923                               1, NULL, 0, NULL);
 924
 925 wdt_done:
 926         return ret;
 927 }
 928
 929 static int lpc_ich_probe(struct pci_dev *dev,
 930                                 const struct pci_device_id *id)
 931 {
 932         struct lpc_ich_priv *priv;
 933         int ret;
 934         bool cell_added = false;
 935
 936         priv = devm_kzalloc(&dev->dev,
 937                             sizeof(struct lpc_ich_priv), GFP_KERNEL);
 938         if (!priv)
 939                 return -ENOMEM;
 940
 941         priv->chipset = id->driver_data;
 942         priv->acpi.save = -1;
 943         priv->acpi.base = ACPIBASE;
 944         priv->acpi.ctrl = ACPICTRL;
 945
 946         priv->gpio.save = -1;
 947         if (priv->chipset <= LPC_ICH5) {
 948                 priv->gpio.base = GPIOBASE_ICH0;
 949                 priv->gpio.ctrl = GPIOCTRL_ICH0;
 950         } else {
 951                 priv->gpio.base = GPIOBASE_ICH6;
 952                 priv->gpio.ctrl = GPIOCTRL_ICH6;
 953         }
 954
 955         pci_set_drvdata(dev, priv);
 956
 957         ret = lpc_ich_init_wdt(dev);
 958         if (!ret)
 959                 cell_added = true;
 960
 961         ret = lpc_ich_init_gpio(dev);
 962         if (!ret)
 963                 cell_added = true;
 964
 965         /*
 966          * We only care if at least one or none of the cells registered
 967          * successfully.
 968          */
 969         if (!cell_added) {
 970                 dev_warn(&dev->dev, "No MFD cells added\n");
 971                 lpc_ich_restore_config_space(dev);
 972                 pci_set_drvdata(dev, NULL);
 973                 return -ENODEV;
 974         }
 975
 976         return 0;
 977 }
 978
 979 static void lpc_ich_remove(struct pci_dev *dev)
 980 {
 981         mfd_remove_devices(&dev->dev);
 982         lpc_ich_restore_config_space(dev);
 983         pci_set_drvdata(dev, NULL);
 984 }
 985
 986 static struct pci_driver lpc_ich_driver = {
 987         .name           = "lpc_ich",
 988         .id_table       = lpc_ich_ids,
 989         .probe          = lpc_ich_probe,
 990         .remove         = lpc_ich_remove,
 991 };
 992
 993 static int __init lpc_ich_init(void)
 994 {
 995         return pci_register_driver(&lpc_ich_driver);
 996 }
 997
 998 static void __exit lpc_ich_exit(void)
 999 {
1000         pci_unregister_driver(&lpc_ich_driver);
1001 }
1002
1003 module_init(lpc_ich_init);
1004 module_exit(lpc_ich_exit);
1005
1006 MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>");
1007 MODULE_DESCRIPTION("LPC interface for Intel ICH");
1008 MODULE_LICENSE("GPL");