2 * Intel Sunrisepoint LPSS core support.
4 * Copyright (C) 2015, Intel Corporation
6 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 * Heikki Krogerus <heikki.krogerus@linux.intel.com>
9 * Jarkko Nikula <jarkko.nikula@linux.intel.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/clk.h>
17 #include <linux/clkdev.h>
18 #include <linux/clk-provider.h>
19 #include <linux/debugfs.h>
20 #include <linux/idr.h>
21 #include <linux/ioport.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/mfd/core.h>
25 #include <linux/pm_qos.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/seq_file.h>
29 #include <asm-generic/io-64-nonatomic-lo-hi.h>
31 #include "intel-lpss.h"
33 #define LPSS_DEV_OFFSET 0x000
34 #define LPSS_DEV_SIZE 0x200
35 #define LPSS_PRIV_OFFSET 0x200
36 #define LPSS_PRIV_SIZE 0x100
37 #define LPSS_IDMA64_OFFSET 0x800
38 #define LPSS_IDMA64_SIZE 0x800
40 /* Offsets from lpss->priv */
41 #define LPSS_PRIV_RESETS 0x04
42 #define LPSS_PRIV_RESETS_FUNC BIT(2)
43 #define LPSS_PRIV_RESETS_IDMA 0x3
45 #define LPSS_PRIV_ACTIVELTR 0x10
46 #define LPSS_PRIV_IDLELTR 0x14
48 #define LPSS_PRIV_LTR_REQ BIT(15)
49 #define LPSS_PRIV_LTR_SCALE_MASK 0xc00
50 #define LPSS_PRIV_LTR_SCALE_1US 0x800
51 #define LPSS_PRIV_LTR_SCALE_32US 0xc00
52 #define LPSS_PRIV_LTR_VALUE_MASK 0x3ff
54 #define LPSS_PRIV_SSP_REG 0x20
55 #define LPSS_PRIV_SSP_REG_DIS_DMA_FIN BIT(0)
57 #define LPSS_PRIV_REMAP_ADDR 0x40
59 #define LPSS_PRIV_CAPS 0xfc
60 #define LPSS_PRIV_CAPS_NO_IDMA BIT(8)
61 #define LPSS_PRIV_CAPS_TYPE_SHIFT 4
62 #define LPSS_PRIV_CAPS_TYPE_MASK (0xf << LPSS_PRIV_CAPS_TYPE_SHIFT)
64 /* This matches the type field in CAPS register */
65 enum intel_lpss_dev_type {
72 const struct intel_lpss_platform_info *info;
73 enum intel_lpss_dev_type type;
75 struct clk_lookup *clock;
76 const struct mfd_cell *cell;
83 struct dentry *debugfs;
86 static const struct resource intel_lpss_dev_resources[] = {
87 DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET, LPSS_DEV_SIZE, "lpss_dev"),
88 DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET, LPSS_PRIV_SIZE, "lpss_priv"),
92 static const struct resource intel_lpss_idma64_resources[] = {
93 DEFINE_RES_MEM(LPSS_IDMA64_OFFSET, LPSS_IDMA64_SIZE),
97 #define LPSS_IDMA64_DRIVER_NAME "idma64"
100 * Cells needs to be ordered so that the iDMA is created first. This is
101 * because we need to be sure the DMA is available when the host controller
104 static const struct mfd_cell intel_lpss_idma64_cell = {
105 .name = LPSS_IDMA64_DRIVER_NAME,
106 .num_resources = ARRAY_SIZE(intel_lpss_idma64_resources),
107 .resources = intel_lpss_idma64_resources,
110 static const struct mfd_cell intel_lpss_i2c_cell = {
111 .name = "i2c_designware",
112 .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
113 .resources = intel_lpss_dev_resources,
116 static const struct mfd_cell intel_lpss_uart_cell = {
117 .name = "dw-apb-uart",
118 .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
119 .resources = intel_lpss_dev_resources,
122 static const struct mfd_cell intel_lpss_spi_cell = {
123 .name = "pxa2xx-spi",
124 .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
125 .resources = intel_lpss_dev_resources,
128 static DEFINE_IDA(intel_lpss_devid_ida);
129 static struct dentry *intel_lpss_debugfs;
131 static int intel_lpss_request_dma_module(const char *name)
133 static bool intel_lpss_dma_requested;
135 if (intel_lpss_dma_requested)
138 intel_lpss_dma_requested = true;
139 return request_module("%s", name);
142 static void intel_lpss_cache_ltr(struct intel_lpss *lpss)
144 lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
145 lpss->idle_ltr = readl(lpss->priv + LPSS_PRIV_IDLELTR);
148 static int intel_lpss_debugfs_add(struct intel_lpss *lpss)
152 dir = debugfs_create_dir(dev_name(lpss->dev), intel_lpss_debugfs);
156 /* Cache the values into lpss structure */
157 intel_lpss_cache_ltr(lpss);
159 debugfs_create_x32("capabilities", S_IRUGO, dir, &lpss->caps);
160 debugfs_create_x32("active_ltr", S_IRUGO, dir, &lpss->active_ltr);
161 debugfs_create_x32("idle_ltr", S_IRUGO, dir, &lpss->idle_ltr);
167 static void intel_lpss_debugfs_remove(struct intel_lpss *lpss)
169 debugfs_remove_recursive(lpss->debugfs);
172 static void intel_lpss_ltr_set(struct device *dev, s32 val)
174 struct intel_lpss *lpss = dev_get_drvdata(dev);
178 * Program latency tolerance (LTR) accordingly what has been asked
179 * by the PM QoS layer or disable it in case we were passed
180 * negative value or PM_QOS_LATENCY_ANY.
182 ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
184 if (val == PM_QOS_LATENCY_ANY || val < 0) {
185 ltr &= ~LPSS_PRIV_LTR_REQ;
187 ltr |= LPSS_PRIV_LTR_REQ;
188 ltr &= ~LPSS_PRIV_LTR_SCALE_MASK;
189 ltr &= ~LPSS_PRIV_LTR_VALUE_MASK;
191 if (val > LPSS_PRIV_LTR_VALUE_MASK)
192 ltr |= LPSS_PRIV_LTR_SCALE_32US | val >> 5;
194 ltr |= LPSS_PRIV_LTR_SCALE_1US | val;
197 if (ltr == lpss->active_ltr)
200 writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR);
201 writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR);
203 /* Cache the values into lpss structure */
204 intel_lpss_cache_ltr(lpss);
207 static void intel_lpss_ltr_expose(struct intel_lpss *lpss)
209 lpss->dev->power.set_latency_tolerance = intel_lpss_ltr_set;
210 dev_pm_qos_expose_latency_tolerance(lpss->dev);
213 static void intel_lpss_ltr_hide(struct intel_lpss *lpss)
215 dev_pm_qos_hide_latency_tolerance(lpss->dev);
216 lpss->dev->power.set_latency_tolerance = NULL;
219 static int intel_lpss_assign_devs(struct intel_lpss *lpss)
223 type = lpss->caps & LPSS_PRIV_CAPS_TYPE_MASK;
224 type >>= LPSS_PRIV_CAPS_TYPE_SHIFT;
228 lpss->cell = &intel_lpss_i2c_cell;
231 lpss->cell = &intel_lpss_uart_cell;
234 lpss->cell = &intel_lpss_spi_cell;
245 static bool intel_lpss_has_idma(const struct intel_lpss *lpss)
247 return (lpss->caps & LPSS_PRIV_CAPS_NO_IDMA) == 0;
250 static void intel_lpss_set_remap_addr(const struct intel_lpss *lpss)
252 resource_size_t addr = lpss->info->mem->start;
254 lo_hi_writeq(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR);
257 static void intel_lpss_deassert_reset(const struct intel_lpss *lpss)
259 u32 value = LPSS_PRIV_RESETS_FUNC | LPSS_PRIV_RESETS_IDMA;
261 /* Bring out the device from reset */
262 writel(value, lpss->priv + LPSS_PRIV_RESETS);
265 static void intel_lpss_init_dev(const struct intel_lpss *lpss)
267 u32 value = LPSS_PRIV_SSP_REG_DIS_DMA_FIN;
269 intel_lpss_deassert_reset(lpss);
271 if (!intel_lpss_has_idma(lpss))
274 intel_lpss_set_remap_addr(lpss);
276 /* Make sure that SPI multiblock DMA transfers are re-enabled */
277 if (lpss->type == LPSS_DEV_SPI)
278 writel(value, lpss->priv + LPSS_PRIV_SSP_REG);
281 static void intel_lpss_unregister_clock_tree(struct clk *clk)
286 parent = clk_get_parent(clk);
292 static int intel_lpss_register_clock_divider(struct intel_lpss *lpss,
297 struct clk *tmp = *clk;
299 snprintf(name, sizeof(name), "%s-enable", devname);
300 tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0,
301 lpss->priv, 0, 0, NULL);
305 snprintf(name, sizeof(name), "%s-div", devname);
306 tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp),
307 0, lpss->priv, 1, 15, 16, 15, 0,
313 snprintf(name, sizeof(name), "%s-update", devname);
314 tmp = clk_register_gate(NULL, name, __clk_get_name(tmp),
315 CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL);
323 static int intel_lpss_register_clock(struct intel_lpss *lpss)
325 const struct mfd_cell *cell = lpss->cell;
330 if (!lpss->info->clk_rate)
334 clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL,
335 CLK_IS_ROOT, lpss->info->clk_rate);
339 snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid);
342 * Support for clock divider only if it has some preset value.
343 * Otherwise we assume that the divider is not used.
345 if (lpss->type != LPSS_DEV_I2C) {
346 ret = intel_lpss_register_clock_divider(lpss, devname, &clk);
348 goto err_clk_register;
353 /* Clock for the host controller */
354 lpss->clock = clkdev_create(clk, lpss->info->clk_con_id, "%s", devname);
356 goto err_clk_register;
363 intel_lpss_unregister_clock_tree(clk);
368 static void intel_lpss_unregister_clock(struct intel_lpss *lpss)
370 if (IS_ERR_OR_NULL(lpss->clk))
373 clkdev_drop(lpss->clock);
374 intel_lpss_unregister_clock_tree(lpss->clk);
377 int intel_lpss_probe(struct device *dev,
378 const struct intel_lpss_platform_info *info)
380 struct intel_lpss *lpss;
383 if (!info || !info->mem || info->irq <= 0)
386 lpss = devm_kzalloc(dev, sizeof(*lpss), GFP_KERNEL);
390 lpss->priv = devm_ioremap(dev, info->mem->start + LPSS_PRIV_OFFSET,
397 lpss->caps = readl(lpss->priv + LPSS_PRIV_CAPS);
399 dev_set_drvdata(dev, lpss);
401 ret = intel_lpss_assign_devs(lpss);
405 intel_lpss_init_dev(lpss);
407 lpss->devid = ida_simple_get(&intel_lpss_devid_ida, 0, 0, GFP_KERNEL);
411 ret = intel_lpss_register_clock(lpss);
413 goto err_clk_register;
415 intel_lpss_ltr_expose(lpss);
417 ret = intel_lpss_debugfs_add(lpss);
419 dev_warn(dev, "Failed to create debugfs entries\n");
421 if (intel_lpss_has_idma(lpss)) {
423 * Ensure the DMA driver is loaded before the host
424 * controller device appears, so that the host controller
425 * driver can request its DMA channels as early as
428 * If the DMA module is not there that's OK as well.
430 intel_lpss_request_dma_module(LPSS_IDMA64_DRIVER_NAME);
432 ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell,
433 1, info->mem, info->irq, NULL);
435 dev_warn(dev, "Failed to add %s, fallback to PIO\n",
436 LPSS_IDMA64_DRIVER_NAME);
439 ret = mfd_add_devices(dev, lpss->devid, lpss->cell,
440 1, info->mem, info->irq, NULL);
447 intel_lpss_debugfs_remove(lpss);
448 intel_lpss_ltr_hide(lpss);
451 ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
455 EXPORT_SYMBOL_GPL(intel_lpss_probe);
457 void intel_lpss_remove(struct device *dev)
459 struct intel_lpss *lpss = dev_get_drvdata(dev);
461 mfd_remove_devices(dev);
462 intel_lpss_debugfs_remove(lpss);
463 intel_lpss_ltr_hide(lpss);
464 intel_lpss_unregister_clock(lpss);
465 ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
467 EXPORT_SYMBOL_GPL(intel_lpss_remove);
469 static int resume_lpss_device(struct device *dev, void *data)
471 pm_runtime_resume(dev);
475 int intel_lpss_prepare(struct device *dev)
478 * Resume both child devices before entering system sleep. This
479 * ensures that they are in proper state before they get suspended.
481 device_for_each_child_reverse(dev, NULL, resume_lpss_device);
484 EXPORT_SYMBOL_GPL(intel_lpss_prepare);
486 int intel_lpss_suspend(struct device *dev)
490 EXPORT_SYMBOL_GPL(intel_lpss_suspend);
492 int intel_lpss_resume(struct device *dev)
494 struct intel_lpss *lpss = dev_get_drvdata(dev);
496 intel_lpss_init_dev(lpss);
500 EXPORT_SYMBOL_GPL(intel_lpss_resume);
502 static int __init intel_lpss_init(void)
504 intel_lpss_debugfs = debugfs_create_dir("intel_lpss", NULL);
507 module_init(intel_lpss_init);
509 static void __exit intel_lpss_exit(void)
511 debugfs_remove(intel_lpss_debugfs);
513 module_exit(intel_lpss_exit);
515 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
516 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
517 MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>");
518 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
519 MODULE_DESCRIPTION("Intel LPSS core driver");
520 MODULE_LICENSE("GPL v2");