drivers/media/video/s5k6aa.h

   1 #ifndef __S5K6AA_H__
   2 #define __S5K6AA_H__
   3
   4 struct reginfo
   5 {
   6     u16 reg;
   7     u16 val;
   8 };
   9
  10 /* General purpose section */
  11 #define REG_TC_GP_SpecialEffects                0x01EE
  12 #define REG_TC_GP_EnablePreview                 0x01F0
  13 #define REG_TC_GP_EnablePreviewChanged          0x01F2
  14 #define REG_TC_GP_EnableCapture                 0x01F4
  15 #define REG_TC_GP_EnableCaptureChanged          0x01F6
  16 #define REG_TC_GP_NewConfigSync                 0x01F8
  17 #define REG_TC_GP_PrevReqInputWidth             0x01FA
  18 #define REG_TC_GP_PrevReqInputHeight            0x01FC
  19 #define REG_TC_GP_PrevInputWidthOfs             0x01FE
  20 #define REG_TC_GP_PrevInputHeightOfs            0x0200
  21 #define REG_TC_GP_CapReqInputWidth              0x0202
  22 #define REG_TC_GP_CapReqInputHeight             0x0204
  23 #define REG_TC_GP_CapInputWidthOfs              0x0206
  24 #define REG_TC_GP_CapInputHeightOfs             0x0208
  25 #define REG_TC_GP_PrevZoomReqInputWidth         0x020A
  26 #define REG_TC_GP_PrevZoomReqInputHeight        0x020C
  27 #define REG_TC_GP_PrevZoomReqInputWidthOfs      0x020E
  28 #define REG_TC_GP_PrevZoomReqInputHeightOfs     0x0210
  29 #define REG_TC_GP_CapZoomReqInputWidth          0x0212
  30 #define REG_TC_GP_CapZoomReqInputHeight         0x0214
  31 #define REG_TC_GP_CapZoomReqInputWidthOfs       0x0216
  32 #define REG_TC_GP_CapZoomReqInputHeightOfs      0x0218
  33 #define REG_TC_GP_InputsChangeRequest           0x021A
  34 #define REG_TC_GP_ActivePrevConfig              0x021C
  35 #define REG_TC_GP_PrevConfigChanged             0x021E
  36 #define REG_TC_GP_PrevOpenAfterChange           0x0220
  37 #define REG_TC_GP_ErrorPrevConfig               0x0222
  38 #define REG_TC_GP_ActiveCapConfig               0x0224
  39 #define REG_TC_GP_CapConfigChanged              0x0226
  40 #define REG_TC_GP_ErrorCapConfig                0x0228
  41 #define REG_TC_GP_PrevConfigBypassChanged       0x022A
  42 #define REG_TC_GP_CapConfigBypassChanged        0x022C
  43 #define REG_TC_GP_SleepMode                     0x022E
  44 #define REG_TC_GP_SleepModeChanged              0x0230
  45 #define REG_TC_GP_SRA_AddLow                    0x0232
  46 #define REG_TC_GP_SRA_AddHigh                   0x0234
  47 #define REG_TC_GP_SRA_AccessType                0x0236
  48 #define REG_TC_GP_SRA_Changed                   0x0238
  49 #define REG_TC_GP_PrevMinFrTimeMsecMult10       0x023A
  50 #define REG_TC_GP_PrevOutKHzRate                0x023C
  51 #define REG_TC_GP_CapMinFrTimeMsecMult10        0x023E
  52 #define REG_TC_GP_CapOutKHzRate                 0x0240
  53
  54 /* Image property control section */
  55 #define REG_TC_UserBrightness                   0x01E4
  56 #define REG_TC_UserContrast                     0x01E6
  57 #define REG_TC_UserSaturation                   0x01E8
  58 #define REG_TC_UserSharpBlur                    0x01EA
  59 #define REG_TC_UserGlamour                      0x01EC
  60
  61 /* Flash control section */
  62 #define REG_TC_FLS_Mode                         0x03B6
  63 #define REG_TC_FLS_Threshold                    0x03B8
  64 #define REG_TC_FLS_Polarity                     0x03BA
  65 #define REG_TC_FLS_XenonMode                    0x03BC
  66 #define REG_TC_FLS_XenonPreFlashCnt             0x03BE
  67
  68 /* Extended image property control section */
  69 #define REG_SF_USER_LeiLow                      0x03C0
  70 #define REG_SF_USER_LeiHigh                     0x03C2
  71 #define REG_SF_USER_LeiChanged                  0x03C4
  72 #define REG_SF_USER_Exposure                    0x03C6
  73 #define REG_SF_USER_ExposureChanged             0x03CA
  74 #define REG_SF_USER_TotalGain                   0x03CC
  75 #define REG_SF_USER_TotalGainChanged            0x03CE
  76 #define REG_SF_USER_Rgain                       0x03D0
  77 #define REG_SF_USER_RgainChanged                0x03D2
  78 #define REG_SF_USER_Ggain                       0x03D4
  79 #define REG_SF_USER_GgainChanged                0x03D6
  80 #define REG_SF_USER_Bgain                       0x03D8
  81 #define REG_SF_USER_BgainChanged                0x03DA
  82 #define REG_SF_USER_FlickerQuant                0x03DC
  83 #define REG_SF_USER_FlickerQuantChanged         0x03DE
  84 #define REG_SF_USER_GASRAlphaVal                0x03E0
  85 #define REG_SF_USER_GASRAlphaChanged            0x03E2
  86 #define REG_SF_USER_GASGAlphaVal                0x03E4
  87 #define REG_SF_USER_GASGAlphaChanged            0x03E6
  88 #define REG_SF_USER_GASBAlphaVal                0x03E8
  89 #define REG_SF_USER_GASBAlphaChanged            0x03EA
  90 #define REG_SF_USER_DbgIdx                      0x03EC
  91 #define REG_SF_USER_DbgVal                      0x03EE
  92 #define REG_SF_USER_DbgChanged                  0x03F0
  93 #define REG_SF_USER_aGain                       0x03F2
  94 #define REG_SF_USER_aGainChanged                0x03F4
  95 #define REG_SF_USER_dGain                       0x03F6
  96 #define REG_SF_USER_dGainChanged                0x03F8
  97
  98 /* Output interface control section */
  99 #define REG_TC_OIF_EnMipiLanes                  0x03FA
 100 #define REG_TC_OIF_EnPackets                    0x03FC
 101 #define REG_TC_OIF_CfgChanged                   0x03FE
 102
 103 /* Debug control section */
 104 #define REG_TC_DBG_AutoAlgEnBits                0x0400
 105 #define REG_TC_DBG_IspBypass                    0x0402
 106 #define REG_TC_DBG_ReInitCmd                    0x0404
 107
 108 /* Version information section */
 109 #define REG_FWdate                              0x012C
 110 #define REG_FWapiVer                            0x012E
 111 #define REG_FWrevision                          0x0130
 112 #define REG_FWpid                               0x0132
 113 #define REG_FWprjName                           0x0134
 114 #define REG_FWcompDate                          0x0140
 115 #define REG_FWSFC_VER                           0x014C
 116 #define REG_FWTC_VER                            0x014E
 117 #define REG_FWrealImageLine                     0x0150
 118 #define REG_FWsenId                             0x0152
 119 #define REG_FWusDevIdQaVersion                  0x0154
 120 #define REG_FWusFwCompilationBits               0x0156
 121 #define REG_ulSVNrevision                       0x0158
 122 #define REG_SVNpathRomAddress                   0x015C
 123 #define REG_TRAP_N_PATCH_START_ADD              0x1B00
 124
 125 #define setot_usForceClocksSettings             0x0AEA
 126 #define setot_usConfigClocksSettings            0x0AEC
 127
 128 #define REG_0TC_CCFG_uCaptureMode  0x030C
 129 #define REG_0TC_CCFG_usWidth       0x030E
 130 #define REG_0TC_CCFG_usHeight      0x0310
 131 #define REG_0TC_CCFG_Format        0x0312
 132 #define REG_0TC_CCFG_usMaxOut4KHzRate 0x0314
 133 #define REG_0TC_CCFG_usMinOut4KHzRate 0x0316
 134 #define REG_0TC_CCFG_PVIMask    0x0318
 135 #define REG_0TC_CCFG_uClockInd  0x031A
 136 #define REG_0TC_CCFG_usFrTimeType  0x031C
 137 #define REG_0TC_CCFG_FrRateQualityType 0x031E
 138 #define REG_0TC_CCFG_usMaxFrTimeMsecMult10 0x0320
 139 #define REG_0TC_CCFG_usMinFrTimeMsecMult10 0x0322
 140 #define lt_uMaxAnGain2                0x049A
 141 #define REG_TC_GP_ActivePrevConfig    0x021C
 142 #define REG_TC_GP_PrevOpenAfterChange 0x0220
 143 #define REG_TC_GP_NewConfigSync       0x01F8
 144 #define REG_TC_GP_PrevConfigChanged   0x021E
 145 #define REG_TC_GP_ActiveCapConfig   0x0224
 146 #define REG_TC_GP_CapConfigChanged  0x0226
 147 #define REG_TC_GP_EnableCapture      0x01F4
 148 #define REG_TC_GP_EnableCaptureChanged  0x01F6
 149
 150 #define lt_uMaxExp1                                                                     0x0488  // 0x9C40
 151 #define lt_uMaxExp2                                                                     0x048C  // 0xE848
 152 #define lt_uCapMaxExp1                                                          0x0490  // 0x9C40
 153 #define lt_uCapMaxExp2                                                          0x0494  // 0xE848
 154 #define lt_uMaxDigGain                                                          0x049C  // 0x0200
 155 #define lt_uMaxAnGain1                                                          0x0498  // 0x0200
 156 #define lt_uMaxAnGain2                                                          0x049A  // 0x0500
 157
 158
 159 #define REG_1TC_CCFG_uCaptureMode                                       0x032E  // 0x0000
 160 #define REG_1TC_CCFG_Cfg                                                        0x0330  // 0x0500
 161 #define REG_1TC_CCFG_usWidth                                            0x0330  // 0x0500
 162 #define REG_1TC_CCFG_usHeight                                           0x0332  // 0x03C0
 163 #define REG_1TC_CCFG_Format                                                     0x0334  // 0x0009
 164 #define REG_1TC_CCFG_usMaxOut4KHzRate                           0x0336  // 0x1770
 165 #define REG_1TC_CCFG_usMinOut4KHzRate                           0x0338  // 0x05DC
 166 #define REG_1TC_CCFG_PVIMask                                            0x033A  // 0x0042
 167 #define REG_1TC_CCFG_uClockInd                                          0x033C  // 0x0000
 168 #define REG_1TC_CCFG_usFrTimeType                                       0x033E  // 0x0000
 169 #define REG_1TC_CCFG_FrRateQualityType                          0x0340  // 0x0002
 170 #define REG_1TC_CCFG_usMaxFrTimeMsecMult10                      0x0342  // 0x1964
 171 #define REG_1TC_CCFG_usMinFrTimeMsecMult10                      0x0344  // 0x0000
 172 #define REG_1TC_CCFG_sSaturation                                        0x0346  // 0x0000
 173 #define REG_1TC_CCFG_sSharpBlur                                         0x0348  // 0x0000
 174 #define REG_1TC_CCFG_sGlamour                                           0x034A  // 0x0000
 175 #define REG_1TC_CCFG_sColorTemp                                         0x034C  // 0x0000
 176 #define REG_1TC_CCFG_uDeviceGammaIndex                          0x034E  // 0x0000
 177 #define REG_CapConfigControls_2_                                        0x0350  // 0x0000
 178
 179
 180 #define REG_1TC_PCFG_usWidth    0x0268
 181 #define REG_1TC_PCFG_usHeight   0x026A
 182 #define REG_1TC_PCFG_Format     0x026C
 183 #define REG_1TC_PCFG_usMaxOut4KHzRate 0x026E
 184 #define REG_1TC_PCFG_usMinOut4KHzRate 0x0270
 185 #define REG_1TC_PCFG_PVIMask    0x0272
 186 #define REG_1TC_PCFG_uClockInd  0x0274
 187 #define REG_1TC_PCFG_usFrTimeType  0x0276
 188 #define REG_1TC_PCFG_FrRateQualityType 0x0278
 189 #define REG_1TC_PCFG_usMaxFrTimeMsecMult10 0x027A
 190 #define REG_1TC_PCFG_usMinFrTimeMsecMult10 0x027C
 191
 192 #define AFC_Default60Hz    0x0B2A
 193 #define REG_TC_DBG_AutoAlgEnBits  0x0400
 194 #define REG_SF_USER_FlickerQuant  0x03DC
 195 #define REG_SF_USER_FlickerQuantChanged  0x03DE
 196
 197
 198 #define REG_2TC_PCFG_usWidth    0x028E
 199 #define REG_2TC_PCFG_usHeight   0x0290
 200 #define REG_2TC_PCFG_Format     0x0292
 201 #define REG_2TC_PCFG_usMaxOut4KHzRate 0x0294
 202 #define REG_2TC_PCFG_usMinOut4KHzRate 0x0296
 203 #define REG_2TC_PCFG_PVIMask    0x0298
 204 #define REG_2TC_PCFG_uClockInd  0x029A
 205 #define REG_2TC_PCFG_usFrTimeType  0x029C
 206 #define REG_2TC_PCFG_FrRateQualityType 0x029E
 207 #define REG_2TC_PCFG_usMaxFrTimeMsecMult10 0x02A0
 208 #define REG_2TC_PCFG_usMinFrTimeMsecMult10 0x02A2
 209
 210 #define REG_3TC_PCFG_usWidth    0x02B4
 211 #define REG_3TC_PCFG_usHeight   0x02B6
 212 #define REG_3TC_PCFG_Format     0x02B8
 213 #define REG_3TC_PCFG_usMaxOut4KHzRate 0x02BA
 214 #define REG_3TC_PCFG_usMinOut4KHzRate 0x02BC
 215 #define REG_3TC_PCFG_PVIMask    0x02BE
 216 #define REG_3TC_PCFG_uClockInd  0x02C0
 217 #define REG_3TC_PCFG_usFrTimeType  0x02C2
 218 #define REG_3TC_PCFG_FrRateQualityType 0x02C4
 219 #define REG_3TC_PCFG_usMaxFrTimeMsecMult10 0x02C6
 220 #define REG_3TC_PCFG_usMinFrTimeMsecMult10 0x02C8
 221
 222 #define SEQUENCE_INIT        0x00
 223 #define SEQUENCE_NORMAL      0x01
 224 #define SEQUENCE_CAPTURE     0x02
 225 #define SEQUENCE_PREVIEW     0x03
 226
 227 #define SEQUENCE_PROPERTY    0xFFF9
 228 #define SEQUENCE_WAIT_MS     0xFFFA
 229 #define SEQUENCE_WAIT_US     0xFFFB
 230 #define SEQUENCE_END                    (0xFFFF)
 231 #define SEQUENCE_FAST_SETMODE_START     (0xFFFD)
 232 #define SEQUENCE_FAST_SETMODE_END       (0xFFFC)
 233
 234
 235 /*configure register for flipe and mirror during initial*/
 236 #define CONFIG_SENSOR_FLIPE     0
 237 #define CONFIG_SENSOR_MIRROR    1
 238 #define CONFIG_SENSOR_MIRROR_AND_FLIPE  0
 239 #define CONFIG_SENSOR_NONE_FLIP_MIRROR  0
 240 /**configure to indicate android cts****/
 241 #define CONFIG_SENSOR_FOR_CTS     1
 242 #endif