drivers/media/video/rk30_camera.c

   1 \r
   2 #include <mach/iomux.h>\r
   3 #include <media/soc_camera.h>\r
   4 #include <linux/android_pmem.h>\r
   5 #include <mach/rk30_camera.h>\r
   6 #ifndef PMEM_CAM_SIZE\r
   7 #include "../../../arch/arm/plat-rk/rk_camera.c"\r
   8 #else\r
   9 /*****************************************************************************************\r
  10  * camera  devices\r
  11  * author: ddl@rock-chips.com\r
  12  *****************************************************************************************/\r
  13 #ifdef CONFIG_VIDEO_RK29 \r
  14 \r
  15 static int rk_sensor_iomux(int pin)\r
  16 {    \r
  17 #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)\r
  18     iomux_set_gpio_mode(pin);\r
  19 #elif defined(CONFIG_ARCH_RK30)\r
  20     switch (pin)\r
  21     {\r
  22         case RK30_PIN0_PA0: \r
  23                 {\r
  24                          rk30_mux_api_set(GPIO0A0_HDMIHOTPLUGIN_NAME,0);\r
  25                         break;  \r
  26                 }\r
  27         case RK30_PIN0_PA1: \r
  28                 {\r
  29                          rk30_mux_api_set(GPIO0A1_HDMII2CSCL_NAME,0);\r
  30                         break;  \r
  31                 }\r
  32         case RK30_PIN0_PA2:\r
  33                 {\r
  34                          rk30_mux_api_set(GPIO0A2_HDMII2CSDA_NAME,0);\r
  35                         break;  \r
  36                 }\r
  37         case RK30_PIN0_PA3:\r
  38                 {\r
  39                          rk30_mux_api_set(GPIO0A3_PWM0_NAME,0);\r
  40                         break;  \r
  41                 }\r
  42         case RK30_PIN0_PA4:\r
  43                 {\r
  44                          rk30_mux_api_set(GPIO0A4_PWM1_NAME,0);\r
  45                         break;  \r
  46                 }\r
  47         case RK30_PIN0_PA5:\r
  48                 {\r
  49                          rk30_mux_api_set(GPIO0A5_OTGDRVVBUS_NAME,0);\r
  50                         break;  \r
  51                 }\r
  52         case RK30_PIN0_PA6:\r
  53         {\r
  54              rk30_mux_api_set(GPIO0A6_HOSTDRVVBUS_NAME,0);\r
  55             break;      \r
  56         }\r
  57         case RK30_PIN0_PA7:\r
  58         {\r
  59              rk30_mux_api_set(GPIO0A7_I2S8CHSDI_NAME,0);\r
  60             break;      \r
  61         }\r
  62         case RK30_PIN0_PB0:\r
  63         {\r
  64              rk30_mux_api_set(GPIO0B0_I2S8CHCLK_NAME,0);\r
  65             break;      \r
  66         }\r
  67         case RK30_PIN0_PB1:\r
  68         {\r
  69              rk30_mux_api_set(GPIO0B1_I2S8CHSCLK_NAME,0);\r
  70             break;      \r
  71         }\r
  72         case RK30_PIN0_PB2:\r
  73         {\r
  74              rk30_mux_api_set(GPIO0B2_I2S8CHLRCKRX_NAME,0);\r
  75             break;      \r
  76         }\r
  77         case RK30_PIN0_PB3:\r
  78         {\r
  79              rk30_mux_api_set(GPIO0B3_I2S8CHLRCKTX_NAME,0);\r
  80             break;      \r
  81         }\r
  82         case RK30_PIN0_PB4:\r
  83         {\r
  84              rk30_mux_api_set(GPIO0B4_I2S8CHSDO0_NAME,0);\r
  85             break;      \r
  86         }\r
  87         case RK30_PIN0_PB5:\r
  88         {\r
  89              rk30_mux_api_set(GPIO0B5_I2S8CHSDO1_NAME,0);\r
  90             break;      \r
  91         }\r
  92         case RK30_PIN0_PB6:\r
  93         {\r
  94              rk30_mux_api_set(GPIO0B6_I2S8CHSDO2_NAME,0);\r
  95             break;      \r
  96         }\r
  97         case RK30_PIN0_PB7:\r
  98         {\r
  99              rk30_mux_api_set(GPIO0B7_I2S8CHSDO3_NAME,0);\r
 100             break;      \r
 101         }\r
 102         case RK30_PIN0_PC0:\r
 103         {\r
 104              rk30_mux_api_set(GPIO0C0_I2S12CHCLK_NAME,0);\r
 105             break;      \r
 106         }\r
 107         case RK30_PIN0_PC1:\r
 108         {\r
 109              rk30_mux_api_set(GPIO0C1_I2S12CHSCLK_NAME,0);\r
 110             break;      \r
 111         }\r
 112         case RK30_PIN0_PC2:\r
 113         {\r
 114              rk30_mux_api_set(GPIO0C2_I2S12CHLRCKRX_NAME,0);\r
 115             break;      \r
 116         }\r
 117         case RK30_PIN0_PC3:\r
 118         {\r
 119              rk30_mux_api_set(GPIO0C3_I2S12CHLRCKTX_NAME,0);\r
 120             break;      \r
 121         }\r
 122         case RK30_PIN0_PC4:\r
 123         {\r
 124              rk30_mux_api_set(GPIO0C4_I2S12CHSDI_NAME,0);\r
 125             break;      \r
 126         }\r
 127         case RK30_PIN0_PC5:\r
 128         {\r
 129              rk30_mux_api_set(GPIO0C5_I2S12CHSDO_NAME,0);\r
 130             break;      \r
 131         }\r
 132         case RK30_PIN0_PC6:\r
 133         {\r
 134              rk30_mux_api_set(GPIO0C6_TRACECLK_SMCADDR2_NAME,0);\r
 135             break;      \r
 136         }\r
 137         case RK30_PIN0_PC7:\r
 138         {\r
 139              rk30_mux_api_set(GPIO0C7_TRACECTL_SMCADDR3_NAME,0);\r
 140             break;      \r
 141         }\r
 142         case RK30_PIN0_PD0:\r
 143         {\r
 144              rk30_mux_api_set(GPIO0D0_I2S22CHCLK_SMCCSN0_NAME,0);\r
 145             break;      \r
 146         }\r
 147         case RK30_PIN0_PD1:\r
 148         {\r
 149              rk30_mux_api_set(GPIO0D1_I2S22CHSCLK_SMCWEN_NAME,0);\r
 150             break;      \r
 151         }\r
 152         case RK30_PIN0_PD2:\r
 153         {\r
 154              rk30_mux_api_set(GPIO0D2_I2S22CHLRCKRX_SMCOEN_NAME,0);\r
 155             break;      \r
 156         }\r
 157         case RK30_PIN0_PD3:\r
 158         {\r
 159              rk30_mux_api_set(GPIO0D3_I2S22CHLRCKTX_SMCADVN_NAME,0);\r
 160             break;      \r
 161         }\r
 162         case RK30_PIN0_PD4:\r
 163         {\r
 164              rk30_mux_api_set(GPIO0D4_I2S22CHSDI_SMCADDR0_NAME,0);\r
 165             break;      \r
 166         }\r
 167         case RK30_PIN0_PD5:\r
 168         {\r
 169              rk30_mux_api_set(GPIO0D5_I2S22CHSDO_SMCADDR1_NAME,0);\r
 170             break;      \r
 171         }\r
 172         case RK30_PIN0_PD6:\r
 173         {\r
 174              rk30_mux_api_set(GPIO0D6_PWM2_NAME,0);\r
 175             break;      \r
 176         }\r
 177         case RK30_PIN0_PD7:\r
 178         {\r
 179              rk30_mux_api_set(GPIO0D7_PWM3_NAME,0);\r
 180             break;      \r
 181         }\r
 182         case RK30_PIN1_PA0:\r
 183         {\r
 184              rk30_mux_api_set(GPIO1A0_UART0SIN_NAME,0);\r
 185             break;      \r
 186         }\r
 187         case RK30_PIN1_PA1:\r
 188         {\r
 189              rk30_mux_api_set(GPIO1A1_UART0SOUT_NAME,0);\r
 190             break;      \r
 191         }\r
 192         case RK30_PIN1_PA2:\r
 193         {\r
 194              rk30_mux_api_set(GPIO1A2_UART0CTSN_NAME,0);\r
 195             break;      \r
 196         }\r
 197         case RK30_PIN1_PA3:\r
 198         {\r
 199              rk30_mux_api_set(GPIO1A3_UART0RTSN_NAME,0);\r
 200             break;      \r
 201         }\r
 202         case RK30_PIN1_PA4:\r
 203         {\r
 204              rk30_mux_api_set(GPIO1A4_UART1SIN_SPI0CSN0_NAME,0);\r
 205             break;      \r
 206         }\r
 207         case RK30_PIN1_PA5:\r
 208         {\r
 209              rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0CLK_NAME,0);\r
 210             break;      \r
 211         }\r
 212         case RK30_PIN1_PA6:\r
 213         {\r
 214              rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0RXD_NAME,0);\r
 215             break;      \r
 216         }\r
 217         case RK30_PIN1_PA7:\r
 218         {\r
 219              rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0TXD_NAME,0);\r
 220             break;      \r
 221         }\r
 222         case RK30_PIN1_PB0:\r
 223         {\r
 224              rk30_mux_api_set(GPIO1B0_UART2SIN_NAME,0);\r
 225             break;      \r
 226         }\r
 227         case RK30_PIN1_PB1:\r
 228         {\r
 229              rk30_mux_api_set(GPIO1B1_UART2SOUT_NAME,0);\r
 230             break;      \r
 231         }\r
 232         case RK30_PIN1_PB2:\r
 233         {\r
 234              rk30_mux_api_set(GPIO1B2_SPDIFTX_NAME,0);\r
 235             break;      \r
 236         }\r
 237         case RK30_PIN1_PB3:\r
 238         {\r
 239              rk30_mux_api_set(GPIO1B3_CIF0CLKOUT_NAME,0);\r
 240             break;      \r
 241         }\r
 242         case RK30_PIN1_PB4:\r
 243         {\r
 244              rk30_mux_api_set(GPIO1B4_CIF0DATA0_NAME,0);\r
 245             break;      \r
 246         }\r
 247         case RK30_PIN1_PB5:\r
 248         {\r
 249              rk30_mux_api_set(GPIO1B5_CIF0DATA1_NAME,0);\r
 250             break;      \r
 251         }\r
 252         case RK30_PIN1_PB6:\r
 253         {\r
 254              rk30_mux_api_set(GPIO1B6_CIFDATA10_NAME,0);\r
 255             break;      \r
 256         }\r
 257         case RK30_PIN1_PB7:\r
 258         {\r
 259              rk30_mux_api_set(GPIO1B7_CIFDATA11_NAME,0);\r
 260             break;      \r
 261         }\r
 262         case RK30_PIN1_PC0:\r
 263         {\r
 264              rk30_mux_api_set(GPIO1C0_CIF1DATA2_RMIICLKOUT_RMIICLKIN_NAME,0);\r
 265             break;      \r
 266         }\r
 267         case RK30_PIN1_PC1:\r
 268         {\r
 269              rk30_mux_api_set(GPIO1C1_CIFDATA3_RMIITXEN_NAME,0);\r
 270             break;      \r
 271         }\r
 272         case RK30_PIN1_PC2:\r
 273         {\r
 274              rk30_mux_api_set(GPIO1C2_CIF1DATA4_RMIITXD1_NAME,0);\r
 275             break;      \r
 276         }\r
 277         case RK30_PIN1_PC3:\r
 278         {\r
 279              rk30_mux_api_set(GPIO1C3_CIFDATA5_RMIITXD0_NAME,0);\r
 280             break;      \r
 281         }\r
 282         case RK30_PIN1_PC4:\r
 283         {\r
 284              rk30_mux_api_set(GPIO1C4_CIFDATA6_RMIIRXERR_NAME,0);\r
 285             break;      \r
 286         }\r
 287         case RK30_PIN1_PC5:\r
 288         {\r
 289              rk29_mux_api_set(GPIO1C5_CIFDATA7_RMIICRSDVALID_NAME,0);\r
 290             break;      \r
 291         }\r
 292         case RK30_PIN1_PC6:\r
 293         {\r
 294              rk30_mux_api_set(GPIO1C6_CIFDATA8_RMIIRXD1_NAME,0);\r
 295             break;      \r
 296         }\r
 297         case RK30_PIN1_PC7:\r
 298         {\r
 299              rk30_mux_api_set(GPIO1C7_CIFDATA9_RMIIRXD0_NAME,0);\r
 300             break;      \r
 301         }\r
 302         case RK30_PIN1_PD0:\r
 303         {\r
 304              rk30_mux_api_set(GPIO1D0_CIF1VSYNC_MIIMD_NAME,0);\r
 305             break;      \r
 306         }\r
 307         case RK30_PIN1_PD1:\r
 308         {\r
 309              rk30_mux_api_set(GPIO1D1_CIF1HREF_MIIMDCLK_NAME,0);\r
 310             break;      \r
 311         }\r
 312         case RK30_PIN1_PD2:\r
 313         {\r
 314              rk30_mux_api_set(GPIO1D2_CIF1CLKIN_NAME,0);\r
 315             break;      \r
 316         }\r
 317         case RK30_PIN1_PD3:\r
 318         {\r
 319              rk30_mux_api_set(GPIO1D3_CIF1DATA0_NAME,0);\r
 320             break;      \r
 321         }\r
 322         case RK30_PIN1_PD4:\r
 323         {\r
 324              rk30_mux_api_set(GPIO1D4_CIF1DATA1_NAME,0);\r
 325             break;      \r
 326         }\r
 327         case RK30_PIN1_PD5:\r
 328         {\r
 329              rk30_mux_api_set(GPIO1D5_CIF1DATA10_NAME,0);\r
 330             break;      \r
 331         }\r
 332         case RK30_PIN1_PD6:\r
 333         {\r
 334              rk30_mux_api_set(GPIO1D6_CIF1DATA11_NAME,0);\r
 335             break;      \r
 336         }\r
 337         case RK30_PIN1_PD7:\r
 338         {\r
 339              rk30_mux_api_set(GPIO1D7_CIF1CLKOUT_NAME,0);\r
 340             break;      \r
 341         }\r
 342         case RK30_PIN2_PA0:\r
 343         {\r
 344              rk30_mux_api_set(GPIO2A0_LCDC1DATA0_SMCADDR4_NAME,0);\r
 345             break;      \r
 346         }\r
 347         case RK30_PIN2_PA1:\r
 348         {\r
 349              rk30_mux_api_set(GPIO2A1_LCDC1DATA1_SMCADDR5_NAME,0);\r
 350             break;      \r
 351         }\r
 352         case RK30_PIN2_PA2:\r
 353         {\r
 354              rk30_mux_api_set(GPIO2A2_LCDCDATA2_SMCADDR6_NAME,0);\r
 355             break;      \r
 356         }\r
 357         case RK30_PIN2_PA3:\r
 358         {\r
 359              rk30_mux_api_set(GPIO2A3_LCDCDATA3_SMCADDR7_NAME,0);\r
 360             break;      \r
 361         }\r
 362         case RK30_PIN2_PA4:\r
 363         {\r
 364              rk30_mux_api_set(GPIO2A4_LCDC1DATA4_SMCADDR8_NAME,0);\r
 365             break;      \r
 366         }\r
 367         case RK30_PIN2_PA5:\r
 368         {\r
 369              rk30_mux_api_set(GPIO2A5_LCDC1DATA5_SMCADDR9_NAME,0);\r
 370             break;      \r
 371         }\r
 372         case RK30_PIN2_PA6:\r
 373         {\r
 374              rk30_mux_api_set(GPIO2A6_LCDC1DATA6_SMCADDR10_NAME,0);\r
 375             break;      \r
 376         }\r
 377         case RK30_PIN2_PA7:\r
 378         {\r
 379              rk30_mux_api_set(GPIO2A7_LCDC1DATA7_SMCADDR11_NAME,0);\r
 380             break;      \r
 381         }\r
 382         case RK30_PIN2_PB0:\r
 383         {\r
 384              rk30_mux_api_set(GPIO2B0_LCDC1DATA8_SMCADDR12_NAME,0);\r
 385             break;      \r
 386         }\r
 387         case RK30_PIN2_PB1:\r
 388         {\r
 389              rk30_mux_api_set(GPIO2B1_LCDC1DATA9_SMCADDR13_NAME,0);\r
 390             break;      \r
 391         }\r
 392         case RK30_PIN2_PB2:\r
 393         {\r
 394              rk30_mux_api_set(GPIO2B2_LCDC1DATA10_SMCADDR14_NAME,0);\r
 395             break;      \r
 396         }\r
 397         case RK30_PIN2_PB3:\r
 398         {\r
 399              rk30_mux_api_set(GPIO2B3_LCDC1DATA11_SMCADDR15_NAME,0);\r
 400             break;      \r
 401         }\r
 402         case RK30_PIN2_PB4:\r
 403         {\r
 404              rk30_mux_api_set(GPIO2B4_LCDC1DATA12_SMCADDR16_HSADCDATA9_NAME,0);\r
 405             break;      \r
 406         }\r
 407         case RK30_PIN2_PB5:\r
 408         {\r
 409              rk30_mux_api_set(GPIO2B5_LCDC1DATA13_SMCADDR17_HSADCDATA8_NAME,0);\r
 410             break;      \r
 411         }\r
 412         case RK30_PIN2_PB6:\r
 413         {\r
 414              rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME,0);\r
 415             break;      \r
 416         }\r
 417         case RK30_PIN2_PB7:\r
 418         {\r
 419              rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME,0);\r
 420             break;      \r
 421         }\r
 422         case RK30_PIN2_PC0:\r
 423         {\r
 424              rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME,0);\r
 425             break;      \r
 426         }\r
 427         case RK30_PIN2_PC1:\r
 428         {\r
 429              rk30_mux_api_set(GPIO2C1_LCDC1DATA17_SMCBLSN0_HSADCDATA6_NAME,0);\r
 430             break;      \r
 431         }\r
 432         case RK30_PIN2_PC2:\r
 433         {\r
 434              rk30_mux_api_set(GPIO2C2_LCDC1DATA18_SMCBLSN1_HSADCDATA5_NAME,0);\r
 435             break;      \r
 436         }\r
 437         case RK30_PIN2_PC3:\r
 438         {\r
 439              rk29_mux_api_set(GPIO2C3_LCDC1DATA19_SPI1CLK_HSADCDATA0_NAME,0);\r
 440             break;      \r
 441         }\r
 442         case RK30_PIN2_PC4:\r
 443         {\r
 444              rk30_mux_api_set(GPIO2C4_LCDC1DATA20_SPI1CSN0_HSADCDATA1_NAME,0);\r
 445             break;      \r
 446         }\r
 447         case RK30_PIN2_PC5:\r
 448         {\r
 449              rk30_mux_api_set(GPIO2C5_LCDC1DATA21_SPI1TXD_HSADCDATA2_NAME,0);\r
 450             break;      \r
 451         }\r
 452         case RK30_PIN2_PC6:\r
 453         {\r
 454              rk30_mux_api_set(GPIO2C6_LCDC1DATA22_SPI1RXD_HSADCDATA3_NAME,0);\r
 455             break;      \r
 456         }\r
 457         case RK30_PIN2_PC7:\r
 458         {\r
 459              rk30_mux_api_set(GPIO2C7_LCDC1DATA23_SPI1CSN1_HSADCDATA4_NAME,0);\r
 460             break;      \r
 461         }\r
 462         case RK30_PIN2_PD0:\r
 463         {\r
 464              rk30_mux_api_set(GPIO2D0_LCDC1DCLK_NAME,0);\r
 465             break;      \r
 466         }\r
 467         case RK30_PIN2_PD1:\r
 468         {\r
 469              rk30_mux_api_set(GPIO2D1_LCDC1DEN_SMCCSN1_NAME,0);\r
 470             break;      \r
 471         }\r
 472         case RK30_PIN2_PD2:\r
 473         {\r
 474              rk30_mux_api_set(GPIO2D2_LCDC1HSYNC_NAME,0);\r
 475             break;      \r
 476         }\r
 477         case RK30_PIN2_PD3:\r
 478         {\r
 479              rk30_mux_api_set(GPIO2D3_LCDC1VSYNC_NAME,0);\r
 480             break;      \r
 481         }\r
 482         case RK30_PIN2_PD4:\r
 483         {\r
 484              rk30_mux_api_set(GPIO2D4_I2C0SDA_NAME,0);\r
 485             break;      \r
 486         }\r
 487         case RK30_PIN2_PD5:\r
 488         {\r
 489              rk30_mux_api_set(GPIO2D5_I2C0SCL_NAME,0);\r
 490             break;      \r
 491         }\r
 492         case RK30_PIN2_PD6:\r
 493         {\r
 494              rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME,0);\r
 495             break;      \r
 496         }\r
 497         case RK30_PIN2_PD7:\r
 498         {\r
 499              rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME,0);\r
 500             break;      \r
 501         }\r
 502         case RK30_PIN3_PA0:\r
 503         {\r
 504              rk30_mux_api_set(GPIO3A0_I2C2SDA_NAME,0);\r
 505             break;      \r
 506         }\r
 507         case RK30_PIN3_PA1:\r
 508         {\r
 509              rk30_mux_api_set(GPIO3A1_I2C2SCL_NAME,0);\r
 510             break;      \r
 511         }\r
 512         case RK30_PIN3_PA2:\r
 513         {\r
 514              rk30_mux_api_set(GPIO3A2_I2C3SDA_NAME,0);\r
 515             break;      \r
 516         }\r
 517         case RK30_PIN3_PA3:\r
 518         {\r
 519              rk30_mux_api_set(GPIO3A3_I2C3SCL_NAME,0);\r
 520             break;      \r
 521         }\r
 522         case RK30_PIN3_PA4:\r
 523         {\r
 524              rk30_mux_api_set(GPIO3A4_I2C4SDA_NAME,0);\r
 525             break;      \r
 526         }\r
 527         case RK30_PIN3_PA5:\r
 528         {\r
 529              rk30_mux_api_set(GPIO3A5_I2C4SCL_NAME,0);\r
 530             break;      \r
 531         }\r
 532         case RK30_PIN3_PA6:\r
 533         {\r
 534              rk30_mux_api_set(GPIO3A6_SDMMC0RSTNOUT_NAME,0);\r
 535             break;      \r
 536         }\r
 537         case RK30_PIN3_PA7:\r
 538         {\r
 539              rk30_mux_api_set(GPIO3A7_SDMMC0PWREN_NAME,0);\r
 540             break;      \r
 541         }\r
 542         case RK30_PIN3_PB0:\r
 543         {\r
 544              rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME,0);\r
 545             break;      \r
 546         }\r
 547         case RK30_PIN3_PB1:\r
 548         {\r
 549              rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME,0);\r
 550             break;      \r
 551         }\r
 552         case RK30_PIN3_PB2:\r
 553         {\r
 554              rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME,0);\r
 555             break;      \r
 556         }\r
 557         case RK30_PIN3_PB3:\r
 558         {\r
 559              rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME,0);\r
 560             break;      \r
 561         }\r
 562         case RK30_PIN3_PB4:\r
 563         {\r
 564              rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME,0);\r
 565             break;      \r
 566         }\r
 567         case RK30_PIN3_PB5:\r
 568         {\r
 569              rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME,0);\r
 570             break;      \r
 571         }\r
 572         case RK30_PIN3_PB6:\r
 573         {\r
 574              rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME,0);\r
 575             break;      \r
 576         }\r
 577         case RK30_PIN3_PB7:\r
 578         {\r
 579              rk30_mux_api_set(GPIO3B7_SDMMC0WRITEPRT_NAME,0);\r
 580             break;      \r
 581         }\r
 582         case RK30_PIN3_PC0:\r
 583         {\r
 584              rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME,0);\r
 585             break;      \r
 586         }\r
 587         case RK30_PIN3_PC1:\r
 588         {\r
 589              rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME,0);\r
 590             break;      \r
 591         }\r
 592         case RK30_PIN3_PC2:\r
 593         {\r
 594              rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME,0);\r
 595             break;      \r
 596         }\r
 597         case RK30_PIN3_PC3:\r
 598         {\r
 599              rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME,0);\r
 600             break;      \r
 601         }\r
 602         case RK30_PIN3_PC4:\r
 603         {\r
 604              rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME,0);\r
 605             break;      \r
 606         }\r
 607         case RK30_PIN3_PC5:\r
 608         {\r
 609              rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME,0);\r
 610             break;      \r
 611         }\r
 612         case RK30_PIN3_PC6:\r
 613         {\r
 614              rk30_mux_api_set(GPIO3C6_SDMMC1DETECTN_NAME,0);\r
 615             break;      \r
 616         }\r
 617         case RK30_PIN3_PC7:\r
 618         {\r
 619              rk30_mux_api_set(GPIO3C7_SDMMC1WRITEPRT_NAME,0);\r
 620             break;      \r
 621         }\r
 622         case RK30_PIN3_PD0:\r
 623         {\r
 624              rk30_mux_api_set(GPIO3D0_SDMMC1PWREN_NAME,0);\r
 625             break;      \r
 626         }\r
 627         case RK30_PIN3_PD1:\r
 628         {\r
 629              rk30_mux_api_set(GPIO3D1_SDMMC1BACKENDPWR_NAME,0);\r
 630             break;      \r
 631         }\r
 632         case RK30_PIN3_PD2:\r
 633         {\r
 634              rk30_mux_api_set(GPIO3D2_SDMMC1INTN_NAME,0);\r
 635             break;      \r
 636         }\r
 637         case RK30_PIN3_PD3:\r
 638         {\r
 639              rk30_mux_api_set(GPIO3D3_UART3SIN_NAME,0);\r
 640             break;      \r
 641         }\r
 642         case RK30_PIN3_PD4:\r
 643         {\r
 644              rk30_mux_api_set(GPIO3D4_UART3SOUT_NAME,0);\r
 645             break;      \r
 646         }\r
 647         case RK30_PIN3_PD5:\r
 648         {\r
 649              rk30_mux_api_set(GPIO3D5_UART3CTSN_NAME,0);\r
 650             break;      \r
 651         }\r
 652         case RK30_PIN3_PD6:\r
 653         {\r
 654              rk30_mux_api_set(GPIO3D6_UART3RTSN_NAME,0);\r
 655             break;      \r
 656         }\r
 657         case RK30_PIN3_PD7:\r
 658         {\r
 659              rk30_mux_api_set(GPIO3D7_FLASHDQS_EMMCCLKOUT_NAME,0);\r
 660             break;      \r
 661         }\r
 662         case RK30_PIN4_PA0:\r
 663         {\r
 664                  rk30_mux_api_set(GPIO4A0_FLASHDATA8_NAME,0);\r
 665                 break;  \r
 666         }\r
 667         case RK30_PIN4_PA1:\r
 668         {\r
 669                  rk30_mux_api_set(GPIO4A1_FLASHDATA9_NAME,0);\r
 670                 break;  \r
 671         }\r
 672         case RK30_PIN4_PA2:\r
 673         {\r
 674                  rk30_mux_api_set(GPIO4A2_FLASHDATA10_NAME,0);\r
 675                 break;  \r
 676         }\r
 677                         \r
 678         case RK30_PIN4_PA3:\r
 679         {\r
 680                  rk30_mux_api_set(GPIO4A3_FLASHDATA11_NAME,0);\r
 681                 break;  \r
 682         }\r
 683         case RK30_PIN4_PA4:\r
 684         {\r
 685                  rk30_mux_api_set(GPIO4A4_FLASHDATA12_NAME,0);\r
 686                 break;  \r
 687         }\r
 688         case RK30_PIN4_PA5:\r
 689         {\r
 690              rk30_mux_api_set(GPIO4A5_FLASHDATA13_NAME,0);\r
 691             break;      \r
 692         }\r
 693         case RK30_PIN4_PA6:\r
 694         {\r
 695              rk30_mux_api_set(GPIO4A6_FLASHDATA14_NAME,0);\r
 696             break;      \r
 697         }\r
 698         case RK30_PIN4_PA7:\r
 699         {\r
 700              rk30_mux_api_set(GPIO4A7_FLASHDATA15_NAME,0);\r
 701             break;      \r
 702         }\r
 703         case RK30_PIN4_PB0:\r
 704         {\r
 705              rk30_mux_api_set(GPIO4B0_FLASHCSN1_NAME,0);\r
 706             break;      \r
 707         }\r
 708         case RK30_PIN4_PB1:\r
 709         {\r
 710              rk30_mux_api_set(GPIO4B1_FLASHCSN2_EMMCCMD_NAME,0);\r
 711             break;      \r
 712         }\r
 713         case RK30_PIN4_PB2:\r
 714         {\r
 715              rk30_mux_api_set(GPIO4B2_FLASHCSN3_EMMCRSTNOUT_NAME,0);\r
 716             break;      \r
 717         }\r
 718         case RK30_PIN4_PB3:\r
 719         {\r
 720              rk30_mux_api_set(GPIO4B3_FLASHCSN4_NAME,0);\r
 721             break;      \r
 722         }\r
 723         case RK30_PIN4_PB4:\r
 724         {\r
 725              rk30_mux_api_set(GPIO4B4_FLASHCSN5_NAME,0);\r
 726             break;      \r
 727         }\r
 728         case RK30_PIN4_PB5:\r
 729         {\r
 730              rk30_mux_api_set(GPIO4B5_FLASHCSN6_NAME,0);\r
 731             break;      \r
 732         }\r
 733         case RK30_PIN4_PB6:\r
 734         {\r
 735              rk30_mux_api_set(GPIO4B6_FLASHCSN7_NAME ,0);\r
 736             break;      \r
 737         }\r
 738         case RK30_PIN4_PB7:\r
 739         {\r
 740              rk30_mux_api_set(GPIO4B7_SPI0CSN1_NAME,0);\r
 741             break;      \r
 742         }\r
 743         case RK30_PIN4_PC0:\r
 744         {\r
 745              rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME,0);\r
 746             break;      \r
 747         }\r
 748         case RK30_PIN4_PC1:\r
 749         {\r
 750              rk30_mux_api_set(GPIO4C1_SMCDATA1_TRACEDATA1_NAME,0);\r
 751             break;      \r
 752         }\r
 753         case RK30_PIN4_PC2:\r
 754         {\r
 755              rk30_mux_api_set(GPIO4C2_SMCDATA2_TRACEDATA2_NAME,0);\r
 756             break;      \r
 757         }\r
 758         case RK30_PIN4_PC3:\r
 759         {\r
 760              rk30_mux_api_set(GPIO4C3_SMCDATA3_TRACEDATA3_NAME,0);\r
 761             break;      \r
 762         }\r
 763         case RK30_PIN4_PC4:\r
 764         {\r
 765              rk30_mux_api_set(GPIO4C4_SMCDATA4_TRACEDATA4_NAME,0);\r
 766             break;      \r
 767         }\r
 768         case RK30_PIN4_PC5:\r
 769         {\r
 770              rk30_mux_api_set(GPIO4C5_SMCDATA5_TRACEDATA5_NAME,0);\r
 771             break;      \r
 772         }\r
 773         case RK30_PIN4_PC6:\r
 774         {\r
 775              rk30_mux_api_set(GPIO4C6_SMCDATA6_TRACEDATA6_NAME,0);\r
 776             break;      \r
 777         }\r
 778 \r
 779 \r
 780         case RK30_PIN4_PC7:\r
 781         {\r
 782              rk30_mux_api_set(GPIO4C7_SMCDATA7_TRACEDATA7_NAME,0);\r
 783             break;      \r
 784         }\r
 785         case RK30_PIN4_PD0:\r
 786             {\r
 787                      rk30_mux_api_set(GPIO4D0_SMCDATA8_TRACEDATA8_NAME,0);                         \r
 788                      break;     \r
 789             }\r
 790         case RK30_PIN4_PD1:\r
 791         {\r
 792              rk30_mux_api_set(GPIO4D1_SMCDATA9_TRACEDATA9_NAME,0);             \r
 793              break;     \r
 794         }\r
 795         case RK30_PIN4_PD2:\r
 796             {\r
 797                      rk30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME,0);                                \r
 798                      break;     \r
 799             }\r
 800         case RK30_PIN4_PD3:\r
 801         {\r
 802              rk30_mux_api_set(GPIO4D3_SMCDATA11_TRACEDATA11_NAME,0);           \r
 803              break;     \r
 804         }\r
 805         case RK30_PIN4_PD4:\r
 806         {\r
 807              rk30_mux_api_set(GPIO4D4_SMCDATA12_TRACEDATA12_NAME,0);\r
 808             break;      \r
 809         }\r
 810         case RK30_PIN4_PD5:\r
 811         {\r
 812              rk30_mux_api_set(GPIO4D5_SMCDATA13_TRACEDATA13_NAME,0);\r
 813             break;      \r
 814         }\r
 815         case RK30_PIN4_PD6:\r
 816         {\r
 817              rk30_mux_api_set(GPIO4D6_SMCDATA14_TRACEDATA14_NAME,0);\r
 818             break;      \r
 819         }\r
 820         case RK30_PIN4_PD7:\r
 821         {\r
 822              rk30_mux_api_set(GPIO4D7_SMCDATA15_TRACEDATA15_NAME,0);\r
 823             break;      \r
 824         } \r
 825         case RK30_PIN6_PA0:\r
 826         case RK30_PIN6_PA1:\r
 827         case RK30_PIN6_PA2:\r
 828         case RK30_PIN6_PA3:\r
 829         case RK30_PIN6_PA4:\r
 830         case RK30_PIN6_PA5:\r
 831         case RK30_PIN6_PA6:\r
 832         case RK30_PIN6_PA7:\r
 833         case RK30_PIN6_PB0:\r
 834         case RK30_PIN6_PB1:\r
 835         case RK30_PIN6_PB2:\r
 836         case RK30_PIN6_PB3:\r
 837         case RK30_PIN6_PB4:\r
 838         case RK30_PIN6_PB5:\r
 839         case RK30_PIN6_PB6:\r
 840                         break;\r
 841         case RK30_PIN6_PB7:\r
 842                 {\r
 843                          rk30_mux_api_set(GPIO6B7_TESTCLOCKOUT_NAME,0);\r
 844                         break;  \r
 845                 } \r
 846         default:\r
 847         {\r
 848             printk("Pin=%d isn't RK GPIO, Please init it's iomux yourself!",pin);\r
 849             break;\r
 850         }\r
 851     }\r
 852 #endif\r
 853     return 0;\r
 854 }\r
 855 #define PMEM_CAM_BASE 0 //just for compile ,no meaning\r
 856 #include "../../../arch/arm/plat-rk/rk_camera.c"\r
 857 \r
 858 \r
 859 \r
 860 static u64 rockchip_device_camera_dmamask = 0xffffffffUL;\r
 861 #if RK_SUPPORT_CIF0\r
 862 static struct resource rk_camera_resource_host_0[] = {\r
 863         [0] = {\r
 864                 .start = RK30_CIF0_PHYS,\r
 865                 .end   = RK30_CIF0_PHYS + RK30_CIF0_SIZE - 1,\r
 866                 .flags = IORESOURCE_MEM,\r
 867         },\r
 868         [1] = {\r
 869                 .start = IRQ_CIF0,\r
 870                 .end   = IRQ_CIF0,\r
 871                 .flags = IORESOURCE_IRQ,\r
 872         }\r
 873 };\r
 874 #endif\r
 875 #if RK_SUPPORT_CIF1\r
 876 static struct resource rk_camera_resource_host_1[] = {\r
 877         [0] = {\r
 878                 .start = RK30_CIF1_PHYS,\r
 879                 .end   = RK30_CIF1_PHYS + RK30_CIF1_SIZE - 1,\r
 880                 .flags = IORESOURCE_MEM,\r
 881         },\r
 882         [1] = {\r
 883                 .start = IRQ_CIF1,\r
 884                 .end   = IRQ_CIF1,\r
 885                 .flags = IORESOURCE_IRQ,\r
 886         }\r
 887 };\r
 888 #endif\r
 889 \r
 890 /*platform_device : */\r
 891 #if RK_SUPPORT_CIF0\r
 892  struct platform_device rk_device_camera_host_0 = {\r
 893         .name             = RK29_CAM_DRV_NAME,\r
 894         .id       = RK_CAM_PLATFORM_DEV_ID_0,                           /* This is used to put cameras on this interface */\r
 895         .num_resources    = ARRAY_SIZE(rk_camera_resource_host_0),\r
 896         .resource         = rk_camera_resource_host_0,\r
 897         .dev                    = {\r
 898                 .dma_mask = &rockchip_device_camera_dmamask,\r
 899                 .coherent_dma_mask = 0xffffffffUL,\r
 900                 .platform_data  = &rk_camera_platform_data,\r
 901         }\r
 902 };\r
 903 #endif\r
 904 \r
 905 #if RK_SUPPORT_CIF1\r
 906 /*platform_device : */\r
 907  struct platform_device rk_device_camera_host_1 = {\r
 908         .name             = RK29_CAM_DRV_NAME,\r
 909         .id       = RK_CAM_PLATFORM_DEV_ID_1,                           /* This is used to put cameras on this interface */\r
 910         .num_resources    = ARRAY_SIZE(rk_camera_resource_host_1),\r
 911         .resource         = rk_camera_resource_host_1,\r
 912         .dev                    = {\r
 913                 .dma_mask = &rockchip_device_camera_dmamask,\r
 914                 .coherent_dma_mask = 0xffffffffUL,\r
 915                 .platform_data  = &rk_camera_platform_data,\r
 916         }\r
 917 };\r
 918 #endif\r
 919 \r
 920 static void rk_init_camera_plateform_data(void)\r
 921 {\r
 922     int i,dev_idx;\r
 923     \r
 924     dev_idx = 0;\r
 925     for (i=0; i<RK_CAM_NUM; i++) {\r
 926         rk_camera_platform_data.sensor_init_data[i] = &rk_init_data_sensor[i];\r
 927         if (rk_camera_platform_data.register_dev[i].device_info.name) {            \r
 928             rk_camera_platform_data.register_dev[i].link_info.board_info = \r
 929                 &rk_camera_platform_data.register_dev[i].i2c_cam_info;\r
 930             rk_camera_platform_data.register_dev[i].device_info.id = dev_idx;\r
 931             rk_camera_platform_data.register_dev[i].device_info.dev.platform_data = \r
 932                 &rk_camera_platform_data.register_dev[i].link_info;\r
 933             dev_idx++;\r
 934         }\r
 935     }\r
 936 }\r
 937 \r
 938 static void rk30_camera_request_reserve_mem(void)\r
 939 {\r
 940     int i,max_resolution;\r
 941     int cam_ipp_mem=PMEM_CAMIPP_NECESSARY, cam_pmem=PMEM_CAM_NECESSARY;\r
 942 \r
 943     i =0;\r
 944     max_resolution = 0x00;\r
 945     while (strstr(new_camera[i].dev.device_info.dev.init_name,"end")==NULL) {\r
 946         if (new_camera[i].resolution > max_resolution)\r
 947             max_resolution = new_camera[i].resolution;\r
 948         i++;\r
 949     }\r
 950 \r
 951     if (max_resolution < PMEM_SENSOR_FULL_RESOLUTION_CIF_1)\r
 952         max_resolution = PMEM_SENSOR_FULL_RESOLUTION_CIF_1;\r
 953     if (max_resolution < PMEM_SENSOR_FULL_RESOLUTION_CIF_0)\r
 954         max_resolution = PMEM_SENSOR_FULL_RESOLUTION_CIF_0;\r
 955 \r
 956     switch (max_resolution)\r
 957     {\r
 958         case 0x800000:\r
 959         default:\r
 960         {\r
 961             cam_ipp_mem = 0xC00000;\r
 962             cam_pmem = 0x1900000;\r
 963             break;\r
 964         }\r
 965 \r
 966         case 0x500000:\r
 967         {\r
 968             cam_ipp_mem = 0x800000;\r
 969             cam_pmem = 0x1400000;\r
 970             break;\r
 971         }\r
 972 \r
 973         case 0x300000:\r
 974         {\r
 975             cam_ipp_mem = 0x600000;\r
 976             cam_pmem = 0xf00000;\r
 977             break;\r
 978         }\r
 979 \r
 980         case 0x200000:\r
 981         {\r
 982             cam_ipp_mem = 0x600000;\r
 983             cam_pmem = 0xc00000;\r
 984             break;\r
 985         }\r
 986         case 0x210000:\r
 987         {\r
 988             cam_ipp_mem = 0xc00000;\r
 989             cam_pmem = 0xc00000;\r
 990             break;\r
 991         }\r
 992         case 0x100000:\r
 993         {\r
 994             cam_ipp_mem = 0x600000;\r
 995             cam_pmem = 0xa00000;\r
 996             break;\r
 997         }\r
 998 \r
 999         case 0x30000:\r
1000         {\r
1001             cam_ipp_mem = 0x600000;\r
1002             cam_pmem = 0x600000;\r
1003             break;\r
1004         }\r
1005     }\r
1006 \r
1007     \r
1008 \r
1009 #ifdef CONFIG_VIDEO_RK29_WORK_IPP\r
1010         rk_camera_platform_data.meminfo.vbase = rk_camera_platform_data.meminfo_cif1.vbase = NULL;\r
1011     #if defined(CONFIG_VIDEO_RKCIF_WORK_SIMUL_OFF) || ((RK_SUPPORT_CIF0 && RK_SUPPORT_CIF1) == 0)\r
1012         rk_camera_platform_data.meminfo.name = "camera_ipp_mem";\r
1013         rk_camera_platform_data.meminfo.start = board_mem_reserve_add("camera_ipp_mem",cam_ipp_mem);\r
1014         rk_camera_platform_data.meminfo.size= cam_ipp_mem;\r
1015 \r
1016         memcpy(&rk_camera_platform_data.meminfo_cif1,&rk_camera_platform_data.meminfo,sizeof(struct rk29camera_mem_res));\r
1017     #else\r
1018         rk_camera_platform_data.meminfo.name = "camera_ipp_mem_0";\r
1019         rk_camera_platform_data.meminfo.start = board_mem_reserve_add("camera_ipp_mem_0",PMEM_CAMIPP_NECESSARY_CIF_0);\r
1020         rk_camera_platform_data.meminfo.size= PMEM_CAMIPP_NECESSARY_CIF_0;\r
1021         \r
1022         rk_camera_platform_data.meminfo_cif1.name = "camera_ipp_mem_1";\r
1023         rk_camera_platform_data.meminfo_cif1.start =board_mem_reserve_add("camera_ipp_mem_1",PMEM_CAMIPP_NECESSARY_CIF_1);\r
1024         rk_camera_platform_data.meminfo_cif1.size= PMEM_CAMIPP_NECESSARY_CIF_1;\r
1025     #endif\r
1026  #endif\r
1027  #if PMEM_CAM_NECESSARY\r
1028         android_pmem_cam_pdata.start = board_mem_reserve_add((char*)(android_pmem_cam_pdata.name),cam_pmem);\r
1029         android_pmem_cam_pdata.size= cam_pmem;\r
1030  #endif\r
1031 \r
1032 }\r
1033 static int rk_register_camera_devices(void)\r
1034 {\r
1035     int i;\r
1036     int host_registered_0,host_registered_1;\r
1037     struct rkcamera_platform_data *new_camera;\r
1038     \r
1039         rk_init_camera_plateform_data();\r
1040 \r
1041     host_registered_0 = 0;\r
1042     host_registered_1 = 0;\r
1043     \r
1044     for (i=0; i<RK_CAM_NUM; i++) {\r
1045         if (rk_camera_platform_data.register_dev[i].device_info.name) {\r
1046             \r
1047             if (rk_camera_platform_data.register_dev[i].link_info.bus_id == RK_CAM_PLATFORM_DEV_ID_0) {\r
1048             #if RK_SUPPORT_CIF0                \r
1049                 host_registered_0 = 1;\r
1050             #else\r
1051                 printk(KERN_ERR "%s(%d) : This chip isn't support CIF0, Please user check ...\n",__FUNCTION__,__LINE__);\r
1052             #endif\r
1053             } \r
1054 \r
1055             if (rk_camera_platform_data.register_dev[i].link_info.bus_id == RK_CAM_PLATFORM_DEV_ID_1) {\r
1056             #if RK_SUPPORT_CIF1\r
1057                 host_registered_1 = 1;\r
1058             #else\r
1059                 printk(KERN_ERR "%s(%d) : This chip isn't support CIF1, Please user check ...\n",__FUNCTION__,__LINE__);\r
1060             #endif\r
1061             } \r
1062         }\r
1063     }\r
1064 \r
1065     \r
1066     i=0;\r
1067     new_camera = rk_camera_platform_data.register_dev_new;\r
1068     if (new_camera != NULL) {\r
1069         while (strstr(new_camera->dev.device_info.dev.init_name,"end")==NULL) {\r
1070             if (new_camera->dev.link_info.bus_id == RK_CAM_PLATFORM_DEV_ID_1) {\r
1071                 host_registered_1 = 1;\r
1072             } else if (new_camera->dev.link_info.bus_id == RK_CAM_PLATFORM_DEV_ID_0) {\r
1073                 host_registered_0 = 1;\r
1074             }\r
1075             new_camera++;\r
1076         }\r
1077     }\r
1078     #if RK_SUPPORT_CIF0\r
1079     if (host_registered_0) {\r
1080         platform_device_register(&rk_device_camera_host_0);\r
1081     }\r
1082     #endif\r
1083     #if RK_SUPPORT_CIF1\r
1084     if (host_registered_1) {\r
1085         platform_device_register(&rk_device_camera_host_1);\r
1086     }  \r
1087     #endif\r
1088 \r
1089     for (i=0; i<RK_CAM_NUM; i++) {\r
1090         if (rk_camera_platform_data.register_dev[i].device_info.name) {\r
1091             platform_device_register(&rk_camera_platform_data.register_dev[i].device_info);\r
1092         }\r
1093     }\r
1094 \r
1095     if (rk_camera_platform_data.sensor_register)\r
1096        (rk_camera_platform_data.sensor_register)(); \r
1097     \r
1098  #if PMEM_CAM_NECESSARY\r
1099     platform_device_register(&android_pmem_cam_device);\r
1100  #endif\r
1101         return 0;\r
1102 }\r
1103 \r
1104 module_init(rk_register_camera_devices);\r
1105 #endif\r
1106 \r
1107 #endif //#ifdef CONFIG_VIDEO_RK\r