2 em28xx-core.c - driver for Empia EM2800/EM2820/2840 USB video capture devices
4 Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it>
5 Markus Rechberger <mrechberger@gmail.com>
6 Mauro Carvalho Chehab <mchehab@infradead.org>
7 Sascha Sommer <saschasommer@freenet.de>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/init.h>
25 #include <linux/list.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
28 #include <linux/usb.h>
29 #include <linux/vmalloc.h>
30 #include <media/v4l2-common.h>
34 /* #define ENABLE_DEBUG_ISOC_FRAMES */
36 static unsigned int core_debug;
37 module_param(core_debug, int, 0644);
38 MODULE_PARM_DESC(core_debug, "enable debug messages [core]");
40 #define em28xx_coredbg(fmt, arg...) do {\
42 printk(KERN_INFO "%s %s :"fmt, \
43 dev->name, __func__ , ##arg); } while (0)
45 static unsigned int reg_debug;
46 module_param(reg_debug, int, 0644);
47 MODULE_PARM_DESC(reg_debug, "enable debug messages [URB reg]");
49 #define em28xx_regdbg(fmt, arg...) do {\
51 printk(KERN_INFO "%s %s :"fmt, \
52 dev->name, __func__ , ##arg); } while (0)
55 module_param(alt, int, 0644);
56 MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
58 static unsigned int disable_vbi;
59 module_param(disable_vbi, int, 0644);
60 MODULE_PARM_DESC(disable_vbi, "disable vbi support");
63 #define em28xx_isocdbg(fmt, arg...) do {\
65 printk(KERN_INFO "%s %s :"fmt, \
66 dev->name, __func__ , ##arg); } while (0)
69 * em28xx_read_reg_req()
70 * reads data from the usb device specifying bRequest
72 int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg,
76 int pipe = usb_rcvctrlpipe(dev->udev, 0);
78 if (dev->state & DEV_DISCONNECTED)
81 if (len > URB_MAX_CTRL_SIZE)
85 printk(KERN_DEBUG "(pipe 0x%08x): "
86 "IN: %02x %02x %02x %02x %02x %02x %02x %02x ",
88 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
91 len & 0xff, len >> 8);
94 mutex_lock(&dev->ctrl_urb_lock);
95 ret = usb_control_msg(dev->udev, pipe, req,
96 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
97 0x0000, reg, dev->urb_buf, len, HZ);
100 printk(" failed!\n");
101 mutex_unlock(&dev->ctrl_urb_lock);
106 memcpy(buf, dev->urb_buf, len);
108 mutex_unlock(&dev->ctrl_urb_lock);
114 for (byte = 0; byte < len; byte++)
115 printk(" %02x", (unsigned char)buf[byte]);
123 * em28xx_read_reg_req()
124 * reads data from the usb device specifying bRequest
126 int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg)
131 ret = em28xx_read_reg_req_len(dev, req, reg, &val, 1);
138 int em28xx_read_reg(struct em28xx *dev, u16 reg)
140 return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg);
142 EXPORT_SYMBOL_GPL(em28xx_read_reg);
145 * em28xx_write_regs_req()
146 * sends data to the usb device, specifying bRequest
148 int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf,
152 int pipe = usb_sndctrlpipe(dev->udev, 0);
154 if (dev->state & DEV_DISCONNECTED)
157 if ((len < 1) || (len > URB_MAX_CTRL_SIZE))
163 printk(KERN_DEBUG "(pipe 0x%08x): "
164 "OUT: %02x %02x %02x %02x %02x %02x %02x %02x >>>",
166 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
168 reg & 0xff, reg >> 8,
169 len & 0xff, len >> 8);
171 for (byte = 0; byte < len; byte++)
172 printk(" %02x", (unsigned char)buf[byte]);
176 mutex_lock(&dev->ctrl_urb_lock);
177 memcpy(dev->urb_buf, buf, len);
178 ret = usb_control_msg(dev->udev, pipe, req,
179 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
180 0x0000, reg, dev->urb_buf, len, HZ);
181 mutex_unlock(&dev->ctrl_urb_lock);
183 if (dev->wait_after_write)
184 msleep(dev->wait_after_write);
189 int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len)
193 rc = em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len);
195 /* Stores GPO/GPIO values at the cache, if changed
196 Only write values should be stored, since input on a GPIO
197 register will return the input bits.
198 Not sure what happens on reading GPO register.
201 if (reg == dev->reg_gpo_num)
202 dev->reg_gpo = buf[0];
203 else if (reg == dev->reg_gpio_num)
204 dev->reg_gpio = buf[0];
209 EXPORT_SYMBOL_GPL(em28xx_write_regs);
211 /* Write a single register */
212 int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val)
214 return em28xx_write_regs(dev, reg, &val, 1);
216 EXPORT_SYMBOL_GPL(em28xx_write_reg);
219 * em28xx_write_reg_bits()
220 * sets only some bits (specified by bitmask) of a register, by first reading
223 int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
229 /* Uses cache for gpo/gpio registers */
230 if (reg == dev->reg_gpo_num)
231 oldval = dev->reg_gpo;
232 else if (reg == dev->reg_gpio_num)
233 oldval = dev->reg_gpio;
235 oldval = em28xx_read_reg(dev, reg);
240 newval = (((u8) oldval) & ~bitmask) | (val & bitmask);
242 return em28xx_write_regs(dev, reg, &newval, 1);
244 EXPORT_SYMBOL_GPL(em28xx_write_reg_bits);
247 * em28xx_is_ac97_ready()
248 * Checks if ac97 is ready
250 static int em28xx_is_ac97_ready(struct em28xx *dev)
254 /* Wait up to 50 ms for AC97 command to complete */
255 for (i = 0; i < 10; i++, msleep(5)) {
256 ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY);
264 em28xx_warn("AC97 command still being executed: not handled properly!\n");
270 * write a 16 bit value to the specified AC97 address (LSB first!)
272 int em28xx_read_ac97(struct em28xx *dev, u8 reg)
275 u8 addr = (reg & 0x7f) | 0x80;
278 ret = em28xx_is_ac97_ready(dev);
282 ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
286 ret = dev->em28xx_read_reg_req_len(dev, 0, EM28XX_R40_AC97LSB,
287 (u8 *)&val, sizeof(val));
291 return le16_to_cpu(val);
293 EXPORT_SYMBOL_GPL(em28xx_read_ac97);
296 * em28xx_write_ac97()
297 * write a 16 bit value to the specified AC97 address (LSB first!)
299 int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val)
302 u8 addr = reg & 0x7f;
305 value = cpu_to_le16(val);
307 ret = em28xx_is_ac97_ready(dev);
311 ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, (u8 *) &value, 2);
315 ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
321 EXPORT_SYMBOL_GPL(em28xx_write_ac97);
323 struct em28xx_vol_itable {
324 enum em28xx_amux mux;
328 static struct em28xx_vol_itable inputs[] = {
329 { EM28XX_AMUX_VIDEO, AC97_VIDEO_VOL },
330 { EM28XX_AMUX_LINE_IN, AC97_LINEIN_VOL },
331 { EM28XX_AMUX_PHONE, AC97_PHONE_VOL },
332 { EM28XX_AMUX_MIC, AC97_MIC_VOL },
333 { EM28XX_AMUX_CD, AC97_CD_VOL },
334 { EM28XX_AMUX_AUX, AC97_AUX_VOL },
335 { EM28XX_AMUX_PCM_OUT, AC97_PCM_OUT_VOL },
338 static int set_ac97_input(struct em28xx *dev)
341 enum em28xx_amux amux = dev->ctl_ainput;
343 /* EM28XX_AMUX_VIDEO2 is a special case used to indicate that
344 em28xx should point to LINE IN, while AC97 should use VIDEO
346 if (amux == EM28XX_AMUX_VIDEO2)
347 amux = EM28XX_AMUX_VIDEO;
349 /* Mute all entres but the one that were selected */
350 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
351 if (amux == inputs[i].mux)
352 ret = em28xx_write_ac97(dev, inputs[i].reg, 0x0808);
354 ret = em28xx_write_ac97(dev, inputs[i].reg, 0x8000);
357 em28xx_warn("couldn't setup AC97 register %d\n",
363 static int em28xx_set_audio_source(struct em28xx *dev)
368 if (dev->board.is_em2800) {
369 if (dev->ctl_ainput == EM28XX_AMUX_VIDEO)
370 input = EM2800_AUDIO_SRC_TUNER;
372 input = EM2800_AUDIO_SRC_LINE;
374 ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1);
379 if (dev->board.has_msp34xx)
380 input = EM28XX_AUDIO_SRC_TUNER;
382 switch (dev->ctl_ainput) {
383 case EM28XX_AMUX_VIDEO:
384 input = EM28XX_AUDIO_SRC_TUNER;
387 input = EM28XX_AUDIO_SRC_LINE;
392 if (dev->board.mute_gpio && dev->mute)
393 em28xx_gpio_set(dev, dev->board.mute_gpio);
395 em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
397 ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0);
402 switch (dev->audio_mode.ac97) {
406 ret = set_ac97_input(dev);
412 struct em28xx_vol_otable {
413 enum em28xx_aout mux;
417 static const struct em28xx_vol_otable outputs[] = {
418 { EM28XX_AOUT_MASTER, AC97_MASTER_VOL },
419 { EM28XX_AOUT_LINE, AC97_LINE_LEVEL_VOL },
420 { EM28XX_AOUT_MONO, AC97_MASTER_MONO_VOL },
421 { EM28XX_AOUT_LFE, AC97_LFE_MASTER_VOL },
422 { EM28XX_AOUT_SURR, AC97_SURR_MASTER_VOL },
425 int em28xx_audio_analog_set(struct em28xx *dev)
430 if (!dev->audio_mode.has_audio)
433 /* It is assumed that all devices use master volume for output.
434 It would be possible to use also line output.
436 if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
437 /* Mute all outputs */
438 for (i = 0; i < ARRAY_SIZE(outputs); i++) {
439 ret = em28xx_write_ac97(dev, outputs[i].reg, 0x8000);
441 em28xx_warn("couldn't setup AC97 register %d\n",
446 xclk = dev->board.xclk & 0x7f;
448 xclk |= EM28XX_XCLK_AUDIO_UNMUTE;
450 ret = em28xx_write_reg(dev, EM28XX_R0F_XCLK, xclk);
455 /* Selects the proper audio input */
456 ret = em28xx_set_audio_source(dev);
459 if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
462 em28xx_write_ac97(dev, AC97_POWER_DOWN_CTRL, 0x4200);
463 em28xx_write_ac97(dev, AC97_EXT_AUD_CTRL, 0x0031);
464 em28xx_write_ac97(dev, AC97_PCM_IN_SRATE, 0xbb80);
466 /* LSB: left channel - both channels with the same level */
467 vol = (0x1f - dev->volume) | ((0x1f - dev->volume) << 8);
469 /* Mute device, if needed */
474 for (i = 0; i < ARRAY_SIZE(outputs); i++) {
475 if (dev->ctl_aoutput & outputs[i].mux)
476 ret = em28xx_write_ac97(dev, outputs[i].reg,
479 em28xx_warn("couldn't setup AC97 register %d\n",
483 if (dev->ctl_aoutput & EM28XX_AOUT_PCM_IN) {
484 int sel = ac97_return_record_select(dev->ctl_aoutput);
486 /* Use the same input for both left and right
490 em28xx_write_ac97(dev, AC97_RECORD_SELECT, sel);
496 EXPORT_SYMBOL_GPL(em28xx_audio_analog_set);
498 int em28xx_audio_setup(struct em28xx *dev)
500 int vid1, vid2, feat, cfg;
503 if (dev->chip_id == CHIP_ID_EM2870 || dev->chip_id == CHIP_ID_EM2874
504 || dev->chip_id == CHIP_ID_EM28174) {
505 /* Digital only device - don't load any alsa module */
506 dev->audio_mode.has_audio = false;
507 dev->has_audio_class = false;
508 dev->has_alsa_audio = false;
512 dev->audio_mode.has_audio = true;
514 /* See how this device is configured */
515 cfg = em28xx_read_reg(dev, EM28XX_R00_CHIPCFG);
516 em28xx_info("Config register raw data: 0x%02x\n", cfg);
518 /* Register read error? */
519 cfg = EM28XX_CHIPCFG_AC97; /* Be conservative */
520 } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) == 0x00) {
521 /* The device doesn't have vendor audio at all */
522 dev->has_alsa_audio = false;
523 dev->audio_mode.has_audio = false;
525 } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
526 EM28XX_CHIPCFG_I2S_3_SAMPRATES) {
527 em28xx_info("I2S Audio (3 sample rates)\n");
528 dev->audio_mode.i2s_3rates = 1;
529 } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
530 EM28XX_CHIPCFG_I2S_5_SAMPRATES) {
531 em28xx_info("I2S Audio (5 sample rates)\n");
532 dev->audio_mode.i2s_5rates = 1;
535 if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) != EM28XX_CHIPCFG_AC97) {
536 /* Skip the code that does AC97 vendor detection */
537 dev->audio_mode.ac97 = EM28XX_NO_AC97;
541 dev->audio_mode.ac97 = EM28XX_AC97_OTHER;
543 vid1 = em28xx_read_ac97(dev, AC97_VENDOR_ID1);
546 * Device likely doesn't support AC97
547 * Note: (some) em2800 devices without eeprom reports 0x91 on
548 * CHIPCFG register, even not having an AC97 chip
550 em28xx_warn("AC97 chip type couldn't be determined\n");
551 dev->audio_mode.ac97 = EM28XX_NO_AC97;
552 dev->has_alsa_audio = false;
553 dev->audio_mode.has_audio = false;
557 vid2 = em28xx_read_ac97(dev, AC97_VENDOR_ID2);
561 vid = vid1 << 16 | vid2;
563 dev->audio_mode.ac97_vendor_id = vid;
564 em28xx_warn("AC97 vendor ID = 0x%08x\n", vid);
566 feat = em28xx_read_ac97(dev, AC97_RESET);
570 dev->audio_mode.ac97_feat = feat;
571 em28xx_warn("AC97 features = 0x%04x\n", feat);
573 /* Try to identify what audio processor we have */
574 if (((vid == 0xffffffff) || (vid == 0x83847650)) && (feat == 0x6a90))
575 dev->audio_mode.ac97 = EM28XX_AC97_EM202;
576 else if ((vid >> 8) == 0x838476)
577 dev->audio_mode.ac97 = EM28XX_AC97_SIGMATEL;
580 /* Reports detected AC97 processor */
581 switch (dev->audio_mode.ac97) {
583 em28xx_info("No AC97 audio processor\n");
585 case EM28XX_AC97_EM202:
586 em28xx_info("Empia 202 AC97 audio processor detected\n");
588 case EM28XX_AC97_SIGMATEL:
589 em28xx_info("Sigmatel audio processor detected(stac 97%02x)\n",
590 dev->audio_mode.ac97_vendor_id & 0xff);
592 case EM28XX_AC97_OTHER:
593 em28xx_warn("Unknown AC97 audio processor detected!\n");
599 return em28xx_audio_analog_set(dev);
601 EXPORT_SYMBOL_GPL(em28xx_audio_setup);
603 int em28xx_colorlevels_set_default(struct em28xx *dev)
605 em28xx_write_reg(dev, EM28XX_R20_YGAIN, 0x10); /* contrast */
606 em28xx_write_reg(dev, EM28XX_R21_YOFFSET, 0x00); /* brightness */
607 em28xx_write_reg(dev, EM28XX_R22_UVGAIN, 0x10); /* saturation */
608 em28xx_write_reg(dev, EM28XX_R23_UOFFSET, 0x00);
609 em28xx_write_reg(dev, EM28XX_R24_VOFFSET, 0x00);
610 em28xx_write_reg(dev, EM28XX_R25_SHARPNESS, 0x00);
612 em28xx_write_reg(dev, EM28XX_R14_GAMMA, 0x20);
613 em28xx_write_reg(dev, EM28XX_R15_RGAIN, 0x20);
614 em28xx_write_reg(dev, EM28XX_R16_GGAIN, 0x20);
615 em28xx_write_reg(dev, EM28XX_R17_BGAIN, 0x20);
616 em28xx_write_reg(dev, EM28XX_R18_ROFFSET, 0x00);
617 em28xx_write_reg(dev, EM28XX_R19_GOFFSET, 0x00);
618 return em28xx_write_reg(dev, EM28XX_R1A_BOFFSET, 0x00);
621 int em28xx_capture_start(struct em28xx *dev, int start)
625 if (dev->chip_id == CHIP_ID_EM2874 ||
626 dev->chip_id == CHIP_ID_EM2884 ||
627 dev->chip_id == CHIP_ID_EM28174) {
628 /* The Transport Stream Enable Register moved in em2874 */
630 rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
632 EM2874_TS1_CAPTURE_ENABLE);
636 /* Enable Transport Stream */
637 rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
638 EM2874_TS1_CAPTURE_ENABLE,
639 EM2874_TS1_CAPTURE_ENABLE);
644 /* FIXME: which is the best order? */
645 /* video registers are sampled by VREF */
646 rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP,
647 start ? 0x10 : 0x00, 0x10);
652 /* disable video capture */
653 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x27);
657 if (dev->board.is_webcam)
658 rc = em28xx_write_reg(dev, 0x13, 0x0c);
660 /* enable video capture */
661 rc = em28xx_write_reg(dev, 0x48, 0x00);
663 if (dev->mode == EM28XX_ANALOG_MODE)
664 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
666 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
673 int em28xx_vbi_supported(struct em28xx *dev)
675 /* Modprobe option to manually disable */
676 if (disable_vbi == 1)
679 if (dev->chip_id == CHIP_ID_EM2860 ||
680 dev->chip_id == CHIP_ID_EM2883)
683 /* Version of em28xx that does not support VBI */
687 int em28xx_set_outfmt(struct em28xx *dev)
692 ret = em28xx_write_reg_bits(dev, EM28XX_R27_OUTFMT,
693 dev->format->reg | 0x20, 0xff);
697 ret = em28xx_write_reg(dev, EM28XX_R10_VINMODE, dev->vinmode);
701 vinctrl = dev->vinctl;
702 if (em28xx_vbi_supported(dev) == 1) {
703 vinctrl |= EM28XX_VINCTRL_VBI_RAW;
704 em28xx_write_reg(dev, EM28XX_R34_VBI_START_H, 0x00);
705 em28xx_write_reg(dev, EM28XX_R36_VBI_WIDTH, dev->vbi_width/4);
706 em28xx_write_reg(dev, EM28XX_R37_VBI_HEIGHT, dev->vbi_height);
707 if (dev->norm & V4L2_STD_525_60) {
709 em28xx_write_reg(dev, EM28XX_R35_VBI_START_V, 0x09);
710 } else if (dev->norm & V4L2_STD_625_50) {
712 em28xx_write_reg(dev, EM28XX_R35_VBI_START_V, 0x07);
716 return em28xx_write_reg(dev, EM28XX_R11_VINCTRL, vinctrl);
719 static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax,
722 em28xx_coredbg("em28xx Scale: (%d,%d)-(%d,%d)\n",
723 xmin, ymin, xmax, ymax);
725 em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1);
726 em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1);
727 em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1);
728 return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1);
731 static int em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart,
732 u16 width, u16 height)
736 u8 overflow = (height >> 7 & 0x02) | (width >> 8 & 0x01);
738 em28xx_coredbg("em28xx Area Set: (%d,%d)\n",
739 (width | (overflow & 2) << 7),
740 (height | (overflow & 1) << 8));
742 em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1);
743 em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1);
744 em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1);
745 em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1);
746 return em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1);
749 static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v)
752 /* the em2800 scaler only supports scaling down to 50% */
754 if (dev->board.is_em2800) {
755 mode = (v ? 0x20 : 0x00) | (h ? 0x10 : 0x00);
761 em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2);
765 em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2);
766 /* it seems that both H and V scalers must be active
768 mode = (h || v) ? 0x30 : 0x00;
770 return em28xx_write_reg_bits(dev, EM28XX_R26_COMPR, mode, 0x30);
773 /* FIXME: this only function read values from dev */
774 int em28xx_resolution_set(struct em28xx *dev)
777 width = norm_maxw(dev);
778 height = norm_maxh(dev);
780 /* Properly setup VBI */
781 dev->vbi_width = 720;
782 if (dev->norm & V4L2_STD_525_60)
783 dev->vbi_height = 12;
785 dev->vbi_height = 18;
787 if (!dev->progressive)
788 height >>= norm_maxh(dev);
790 em28xx_set_outfmt(dev);
793 em28xx_accumulator_set(dev, 1, (width - 4) >> 2, 1, (height - 4) >> 2);
795 /* If we don't set the start position to 2 in VBI mode, we end up
796 with line 20/21 being YUYV encoded instead of being in 8-bit
797 greyscale. The core of the issue is that line 21 (and line 23 for
798 PAL WSS) are inside of active video region, and as a result they
799 get the pixelformatting associated with that area. So by cropping
800 it out, we end up with the same format as the rest of the VBI
802 if (em28xx_vbi_supported(dev) == 1)
803 em28xx_capture_area_set(dev, 0, 2, width >> 2, height >> 2);
805 em28xx_capture_area_set(dev, 0, 0, width >> 2, height >> 2);
807 return em28xx_scaler_set(dev, dev->hscale, dev->vscale);
810 int em28xx_set_alternate(struct em28xx *dev)
812 int errCode, prev_alt = dev->alt;
814 unsigned int min_pkt_size = dev->width * 2 + 4;
817 * alt = 0 is used only for control messages, so, only values
818 * greater than 0 can be used for streaming.
820 if (alt && alt < dev->num_alt) {
821 em28xx_coredbg("alternate forced to %d\n", dev->alt);
826 /* When image size is bigger than a certain value,
827 the frame size should be increased, otherwise, only
828 green screen will be received.
830 if (dev->width * 2 * dev->height > 720 * 240 * 2)
833 for (i = 0; i < dev->num_alt; i++) {
834 /* stop when the selected alt setting offers enough bandwidth */
835 if (dev->alt_max_pkt_size[i] >= min_pkt_size) {
838 /* otherwise make sure that we end up with the maximum bandwidth
839 because the min_pkt_size equation might be wrong...
841 } else if (dev->alt_max_pkt_size[i] >
842 dev->alt_max_pkt_size[dev->alt])
847 if (dev->alt != prev_alt) {
848 em28xx_coredbg("minimum isoc packet size: %u (alt=%d)\n",
849 min_pkt_size, dev->alt);
850 dev->max_pkt_size = dev->alt_max_pkt_size[dev->alt];
851 em28xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n",
852 dev->alt, dev->max_pkt_size);
853 errCode = usb_set_interface(dev->udev, 0, dev->alt);
855 em28xx_errdev("cannot change alternate number to %d (error=%i)\n",
863 int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio)
870 if (dev->mode != EM28XX_SUSPEND) {
871 em28xx_write_reg(dev, 0x48, 0x00);
872 if (dev->mode == EM28XX_ANALOG_MODE)
873 em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
875 em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
879 /* Send GPIO reset sequences specified at board entry */
880 while (gpio->sleep >= 0) {
881 if (gpio->reg >= 0) {
882 rc = em28xx_write_reg_bits(dev,
896 EXPORT_SYMBOL_GPL(em28xx_gpio_set);
898 int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode)
900 if (dev->mode == set_mode)
903 if (set_mode == EM28XX_SUSPEND) {
904 dev->mode = set_mode;
906 /* FIXME: add suspend support for ac97 */
908 return em28xx_gpio_set(dev, dev->board.suspend_gpio);
911 dev->mode = set_mode;
913 if (dev->mode == EM28XX_DIGITAL_MODE)
914 return em28xx_gpio_set(dev, dev->board.dvb_gpio);
916 return em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
918 EXPORT_SYMBOL_GPL(em28xx_set_mode);
920 /* ------------------------------------------------------------------
922 ------------------------------------------------------------------*/
925 * IRQ callback, called by URB callback
927 static void em28xx_irq_callback(struct urb *urb)
929 struct em28xx *dev = urb->context;
932 switch (urb->status) {
933 case 0: /* success */
934 case -ETIMEDOUT: /* NAK */
936 case -ECONNRESET: /* kill */
941 em28xx_isocdbg("urb completition error %d.\n", urb->status);
945 /* Copy data from URB */
946 spin_lock(&dev->slock);
947 dev->isoc_ctl.isoc_copy(dev, urb);
948 spin_unlock(&dev->slock);
950 /* Reset urb buffers */
951 for (i = 0; i < urb->number_of_packets; i++) {
952 urb->iso_frame_desc[i].status = 0;
953 urb->iso_frame_desc[i].actual_length = 0;
957 urb->status = usb_submit_urb(urb, GFP_ATOMIC);
959 em28xx_isocdbg("urb resubmit failed (error=%i)\n",
965 * Stop and Deallocate URBs
967 void em28xx_uninit_isoc(struct em28xx *dev, enum em28xx_mode mode)
970 struct em28xx_usb_isoc_bufs *isoc_bufs;
973 em28xx_isocdbg("em28xx: called em28xx_uninit_isoc in mode %d\n", mode);
975 if (mode == EM28XX_DIGITAL_MODE)
976 isoc_bufs = &dev->isoc_ctl.digital_bufs;
978 isoc_bufs = &dev->isoc_ctl.analog_bufs;
980 for (i = 0; i < isoc_bufs->num_bufs; i++) {
981 urb = isoc_bufs->urb[i];
983 if (!irqs_disabled())
988 if (isoc_bufs->transfer_buffer[i]) {
989 usb_free_coherent(dev->udev,
990 urb->transfer_buffer_length,
991 isoc_bufs->transfer_buffer[i],
995 isoc_bufs->urb[i] = NULL;
997 isoc_bufs->transfer_buffer[i] = NULL;
1000 kfree(isoc_bufs->urb);
1001 kfree(isoc_bufs->transfer_buffer);
1003 isoc_bufs->urb = NULL;
1004 isoc_bufs->transfer_buffer = NULL;
1005 isoc_bufs->num_bufs = 0;
1007 em28xx_capture_start(dev, 0);
1009 EXPORT_SYMBOL_GPL(em28xx_uninit_isoc);
1014 void em28xx_stop_urbs(struct em28xx *dev)
1018 struct em28xx_usb_isoc_bufs *isoc_bufs = &dev->isoc_ctl.digital_bufs;
1020 em28xx_isocdbg("em28xx: called em28xx_stop_urbs\n");
1022 for (i = 0; i < isoc_bufs->num_bufs; i++) {
1023 urb = isoc_bufs->urb[i];
1025 if (!irqs_disabled())
1028 usb_unlink_urb(urb);
1032 em28xx_capture_start(dev, 0);
1034 EXPORT_SYMBOL_GPL(em28xx_stop_urbs);
1039 int em28xx_alloc_isoc(struct em28xx *dev, enum em28xx_mode mode,
1040 int max_packets, int num_bufs, int max_pkt_size)
1042 struct em28xx_usb_isoc_bufs *isoc_bufs;
1048 em28xx_isocdbg("em28xx: called em28xx_alloc_isoc in mode %d\n", mode);
1050 if (mode == EM28XX_DIGITAL_MODE)
1051 isoc_bufs = &dev->isoc_ctl.digital_bufs;
1053 isoc_bufs = &dev->isoc_ctl.analog_bufs;
1055 /* De-allocates all pending stuff */
1056 em28xx_uninit_isoc(dev, mode);
1058 isoc_bufs->num_bufs = num_bufs;
1060 isoc_bufs->urb = kzalloc(sizeof(void *)*num_bufs, GFP_KERNEL);
1061 if (!isoc_bufs->urb) {
1062 em28xx_errdev("cannot alloc memory for usb buffers\n");
1066 isoc_bufs->transfer_buffer = kzalloc(sizeof(void *)*num_bufs,
1068 if (!isoc_bufs->transfer_buffer) {
1069 em28xx_errdev("cannot allocate memory for usb transfer\n");
1070 kfree(isoc_bufs->urb);
1074 isoc_bufs->max_pkt_size = max_pkt_size;
1075 isoc_bufs->num_packets = max_packets;
1076 dev->isoc_ctl.vid_buf = NULL;
1077 dev->isoc_ctl.vbi_buf = NULL;
1079 sb_size = isoc_bufs->num_packets * isoc_bufs->max_pkt_size;
1081 /* allocate urbs and transfer buffers */
1082 for (i = 0; i < isoc_bufs->num_bufs; i++) {
1083 urb = usb_alloc_urb(isoc_bufs->num_packets, GFP_KERNEL);
1085 em28xx_err("cannot alloc isoc_ctl.urb %i\n", i);
1086 em28xx_uninit_isoc(dev, mode);
1089 isoc_bufs->urb[i] = urb;
1091 isoc_bufs->transfer_buffer[i] = usb_alloc_coherent(dev->udev,
1092 sb_size, GFP_KERNEL, &urb->transfer_dma);
1093 if (!isoc_bufs->transfer_buffer[i]) {
1094 em28xx_err("unable to allocate %i bytes for transfer"
1097 in_interrupt() ? " while in int" : "");
1098 em28xx_uninit_isoc(dev, mode);
1101 memset(isoc_bufs->transfer_buffer[i], 0, sb_size);
1103 /* FIXME: this is a hack - should be
1104 'desc.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK'
1105 should also be using 'desc.bInterval'
1107 pipe = usb_rcvisocpipe(dev->udev,
1108 mode == EM28XX_ANALOG_MODE ?
1109 EM28XX_EP_ANALOG : EM28XX_EP_DIGITAL);
1111 usb_fill_int_urb(urb, dev->udev, pipe,
1112 isoc_bufs->transfer_buffer[i], sb_size,
1113 em28xx_irq_callback, dev, 1);
1115 urb->number_of_packets = isoc_bufs->num_packets;
1116 urb->transfer_flags = URB_ISO_ASAP | URB_NO_TRANSFER_DMA_MAP;
1119 for (j = 0; j < isoc_bufs->num_packets; j++) {
1120 urb->iso_frame_desc[j].offset = k;
1121 urb->iso_frame_desc[j].length =
1122 isoc_bufs->max_pkt_size;
1123 k += isoc_bufs->max_pkt_size;
1129 EXPORT_SYMBOL_GPL(em28xx_alloc_isoc);
1132 * Allocate URBs and start IRQ
1134 int em28xx_init_isoc(struct em28xx *dev, enum em28xx_mode mode,
1135 int max_packets, int num_bufs, int max_pkt_size,
1136 int (*isoc_copy) (struct em28xx *dev, struct urb *urb))
1138 struct em28xx_dmaqueue *dma_q = &dev->vidq;
1139 struct em28xx_dmaqueue *vbi_dma_q = &dev->vbiq;
1140 struct em28xx_usb_isoc_bufs *isoc_bufs;
1145 em28xx_isocdbg("em28xx: called em28xx_init_isoc in mode %d\n", mode);
1147 dev->isoc_ctl.isoc_copy = isoc_copy;
1149 if (mode == EM28XX_DIGITAL_MODE) {
1150 isoc_bufs = &dev->isoc_ctl.digital_bufs;
1151 /* no need to free/alloc isoc buffers in digital mode */
1154 isoc_bufs = &dev->isoc_ctl.analog_bufs;
1159 rc = em28xx_alloc_isoc(dev, mode, max_packets,
1160 num_bufs, max_pkt_size);
1165 init_waitqueue_head(&dma_q->wq);
1166 init_waitqueue_head(&vbi_dma_q->wq);
1168 em28xx_capture_start(dev, 1);
1170 /* submit urbs and enables IRQ */
1171 for (i = 0; i < isoc_bufs->num_bufs; i++) {
1172 rc = usb_submit_urb(isoc_bufs->urb[i], GFP_ATOMIC);
1174 em28xx_err("submit of urb %i failed (error=%i)\n", i,
1176 em28xx_uninit_isoc(dev, mode);
1183 EXPORT_SYMBOL_GPL(em28xx_init_isoc);
1187 * configure i2c attached devices
1189 void em28xx_wake_i2c(struct em28xx *dev)
1191 v4l2_device_call_all(&dev->v4l2_dev, 0, core, reset, 0);
1192 v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_routing,
1193 INPUT(dev->ctl_input)->vmux, 0, 0);
1194 v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_stream, 0);
1198 * Device control list
1201 static LIST_HEAD(em28xx_devlist);
1202 static DEFINE_MUTEX(em28xx_devlist_mutex);
1205 * Extension interface
1208 static LIST_HEAD(em28xx_extension_devlist);
1210 int em28xx_register_extension(struct em28xx_ops *ops)
1212 struct em28xx *dev = NULL;
1214 mutex_lock(&em28xx_devlist_mutex);
1215 list_add_tail(&ops->next, &em28xx_extension_devlist);
1216 list_for_each_entry(dev, &em28xx_devlist, devlist) {
1219 mutex_unlock(&em28xx_devlist_mutex);
1220 printk(KERN_INFO "Em28xx: Initialized (%s) extension\n", ops->name);
1223 EXPORT_SYMBOL(em28xx_register_extension);
1225 void em28xx_unregister_extension(struct em28xx_ops *ops)
1227 struct em28xx *dev = NULL;
1229 mutex_lock(&em28xx_devlist_mutex);
1230 list_for_each_entry(dev, &em28xx_devlist, devlist) {
1233 list_del(&ops->next);
1234 mutex_unlock(&em28xx_devlist_mutex);
1235 printk(KERN_INFO "Em28xx: Removed (%s) extension\n", ops->name);
1237 EXPORT_SYMBOL(em28xx_unregister_extension);
1239 void em28xx_init_extension(struct em28xx *dev)
1241 const struct em28xx_ops *ops = NULL;
1243 mutex_lock(&em28xx_devlist_mutex);
1244 list_add_tail(&dev->devlist, &em28xx_devlist);
1245 list_for_each_entry(ops, &em28xx_extension_devlist, next) {
1249 mutex_unlock(&em28xx_devlist_mutex);
1252 void em28xx_close_extension(struct em28xx *dev)
1254 const struct em28xx_ops *ops = NULL;
1256 mutex_lock(&em28xx_devlist_mutex);
1257 list_for_each_entry(ops, &em28xx_extension_devlist, next) {
1261 list_del(&dev->devlist);
1262 mutex_unlock(&em28xx_devlist_mutex);